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* cpu.c,model.c,sem-switch.c,sem.c: Regenerated. Mostly comment
[deliverable/binutils-gdb.git] / sim / m32r / cpux.h
CommitLineData
8e420152
DE		 1/* CPU family header for m32rx.
2
b8a9943d
DE		 3This file is machine generated with CGEN.
4
8e420152
DE		 5Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
6
7This file is part of the GNU Simulators.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#ifndef CPU_M32RX_H
26#define CPU_M32RX_H
27
28/* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30#define MAX_LIW_INSNS 2
31
32/* Maximum number of instructions that can be executed in parallel. */
33#define MAX_PARALLEL_INSNS 2
34
35/* CPU state information. */
36typedef struct {
37 /* Hardware elements. */
38 struct {
39 /* program counter */
40 USI h_pc;
41#define GET_H_PC() CPU (h_pc)
42#define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
44 SI h_gr[16];
45#define GET_H_GR(a1) CPU (h_gr)[a1]
46#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
cab58155 48 USI h_cr[7];
8e420152
DE		 49#define GET_H_CR(a1) CPU (h_cr)[a1]
50#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
51 /* accumulator */
52 DI h_accum;
53#define GET_H_ACCUM() CPU (h_accum)
54#define SET_H_ACCUM(x) (CPU (h_accum) = (x))
b8a9943d 55/* start-sanitize-m32rx */
8e420152
DE		 56 /* accumulators */
57 DI h_accums[2];
b8a9943d 58/* end-sanitize-m32rx */
8e420152
DE		 59#define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
60#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
b8a9943d 61/* start-sanitize-m32rx */
8e420152
DE		 62 /* abort flag */
63 UBI h_abort;
b8a9943d 64/* end-sanitize-m32rx */
8e420152
DE		 65#define GET_H_ABORT() CPU (h_abort)
66#define SET_H_ABORT(x) (CPU (h_abort) = (x))
67 /* condition bit */
68 UBI h_cond;
69#define GET_H_COND() CPU (h_cond)
70#define SET_H_COND(x) (CPU (h_cond) = (x))
71 /* sm */
72 UBI h_sm;
73#define GET_H_SM() CPU (h_sm)
74#define SET_H_SM(x) (CPU (h_sm) = (x))
75 /* bsm */
76 UBI h_bsm;
77#define GET_H_BSM() CPU (h_bsm)
78#define SET_H_BSM(x) (CPU (h_bsm) = (x))
79 /* ie */
80 UBI h_ie;
81#define GET_H_IE() CPU (h_ie)
82#define SET_H_IE(x) (CPU (h_ie) = (x))
83 /* bie */
84 UBI h_bie;
85#define GET_H_BIE() CPU (h_bie)
86#define SET_H_BIE(x) (CPU (h_bie) = (x))
87 /* bcond */
88 UBI h_bcond;
89#define GET_H_BCOND() CPU (h_bcond)
90#define SET_H_BCOND(x) (CPU (h_bcond) = (x))
91 /* bpc */
92 SI h_bpc;
93#define GET_H_BPC() CPU (h_bpc)
94#define SET_H_BPC(x) (CPU (h_bpc) = (x))
cab58155
DE		 95 /* lock */
96 UBI h_lock;
97#define GET_H_LOCK() CPU (h_lock)
98#define SET_H_LOCK(x) (CPU (h_lock) = (x))
8e420152
DE		 99 } hardware;
100#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
101 /* CPU profiling state information. */
102 struct {
103 /* general registers */
104 unsigned long h_gr;
105 } profile;
106#define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
107} M32RX_CPU_DATA;
108
cab58155
DE		 109USI m32rx_h_pc_get (SIM_CPU *);
110void m32rx_h_pc_set (SIM_CPU *, USI);
111SI m32rx_h_gr_get (SIM_CPU *, UINT);
112void m32rx_h_gr_set (SIM_CPU *, UINT, SI);
113USI m32rx_h_cr_get (SIM_CPU *, UINT);
114void m32rx_h_cr_set (SIM_CPU *, UINT, USI);
115DI m32rx_h_accum_get (SIM_CPU *);
116void m32rx_h_accum_set (SIM_CPU *, DI);
117DI m32rx_h_accums_get (SIM_CPU *, UINT);
118void m32rx_h_accums_set (SIM_CPU *, UINT, DI);
119UBI m32rx_h_abort_get (SIM_CPU *);
120void m32rx_h_abort_set (SIM_CPU *, UBI);
121UBI m32rx_h_cond_get (SIM_CPU *);
122void m32rx_h_cond_set (SIM_CPU *, UBI);
123UBI m32rx_h_sm_get (SIM_CPU *);
124void m32rx_h_sm_set (SIM_CPU *, UBI);
125UBI m32rx_h_bsm_get (SIM_CPU *);
126void m32rx_h_bsm_set (SIM_CPU *, UBI);
127UBI m32rx_h_ie_get (SIM_CPU *);
128void m32rx_h_ie_set (SIM_CPU *, UBI);
129UBI m32rx_h_bie_get (SIM_CPU *);
130void m32rx_h_bie_set (SIM_CPU *, UBI);
131UBI m32rx_h_bcond_get (SIM_CPU *);
132void m32rx_h_bcond_set (SIM_CPU *, UBI);
133SI m32rx_h_bpc_get (SIM_CPU *);
134void m32rx_h_bpc_set (SIM_CPU *, SI);
135UBI m32rx_h_lock_get (SIM_CPU *);
136void m32rx_h_lock_set (SIM_CPU *, UBI);
b8a9943d 137extern DECODE *m32rx_decode (SIM_CPU *, PCADDR, insn_t);
8e420152
DE		 138
139/* The ARGBUF struct. */
140struct argbuf {
141 /* These are the baseclass definitions. */
142 unsigned int length;
143 PCADDR addr;
144 const struct cgen_insn *opcode;
b8a9943d
DE		 145#if ! defined (SCACHE_P)
146 insn_t insn;
147#endif
8e420152
DE		 148 /* cpu specific data follows */
149 union {
150 struct { /* e.g. add $dr,$sr */
151 UINT f_r1;
152 UINT f_r2;
153 } fmt_0_add;
154 struct { /* e.g. add3 $dr,$sr,#$slo16 */
155 UINT f_r1;
156 UINT f_r2;
157 HI f_simm16;
158 } fmt_1_add3;
159 struct { /* e.g. and3 $dr,$sr,#$uimm16 */
160 UINT f_r1;
161 UINT f_r2;
162 USI f_uimm16;
163 } fmt_2_and3;
164 struct { /* e.g. or3 $dr,$sr,#$ulo16 */
165 UINT f_r1;
166 UINT f_r2;
167 UHI f_uimm16;
168 } fmt_3_or3;
169 struct { /* e.g. addi $dr,#$simm8 */
170 UINT f_r1;
171 SI f_simm8;
172 } fmt_4_addi;
cab58155
DE		 173 struct { /* e.g. addv $dr,$sr */
174 UINT f_r1;
175 UINT f_r2;
176 } fmt_5_addv;
8e420152
DE		 177 struct { /* e.g. addv3 $dr,$sr,#$simm16 */
178 UINT f_r1;
179 UINT f_r2;
180 SI f_simm16;
cab58155 181 } fmt_6_addv3;
8e420152
DE		 182 struct { /* e.g. addx $dr,$sr */
183 UINT f_r1;
184 UINT f_r2;
cab58155 185 } fmt_7_addx;
8e420152
DE		 186 struct { /* e.g. bc $disp8 */
187 IADDR f_disp8;
cab58155 188 } fmt_8_bc8;
8e420152
DE		 189 struct { /* e.g. bc $disp24 */
190 IADDR f_disp24;
cab58155 191 } fmt_9_bc24;
8e420152
DE		 192 struct { /* e.g. beq $src1,$src2,$disp16 */
193 UINT f_r1;
194 UINT f_r2;
195 IADDR f_disp16;
cab58155 196 } fmt_10_beq;
8e420152
DE		 197 struct { /* e.g. beqz $src2,$disp16 */
198 UINT f_r2;
199 IADDR f_disp16;
cab58155 200 } fmt_11_beqz;
8e420152
DE		 201 struct { /* e.g. bl $disp8 */
202 IADDR f_disp8;
cab58155 203 } fmt_12_bl8;
8e420152
DE		 204 struct { /* e.g. bl $disp24 */
205 IADDR f_disp24;
cab58155 206 } fmt_13_bl24;
8e420152
DE		 207 struct { /* e.g. bcl $disp8 */
208 IADDR f_disp8;
cab58155 209 } fmt_14_bcl8;
8e420152
DE		 210 struct { /* e.g. bcl $disp24 */
211 IADDR f_disp24;
cab58155 212 } fmt_15_bcl24;
8e420152
DE		 213 struct { /* e.g. bra $disp8 */
214 IADDR f_disp8;
cab58155 215 } fmt_16_bra8;
8e420152
DE		 216 struct { /* e.g. bra $disp24 */
217 IADDR f_disp24;
cab58155 218 } fmt_17_bra24;
8e420152
DE		 219 struct { /* e.g. cmp $src1,$src2 */
220 UINT f_r1;
221 UINT f_r2;
cab58155 222 } fmt_18_cmp;
8e420152
DE		 223 struct { /* e.g. cmpi $src2,#$simm16 */
224 UINT f_r2;
225 SI f_simm16;
cab58155 226 } fmt_19_cmpi;
8e420152
DE		 227 struct { /* e.g. cmpui $src2,#$uimm16 */
228 UINT f_r2;
229 USI f_uimm16;
cab58155 230 } fmt_20_cmpui;
8e420152
DE		 231 struct { /* e.g. cmpz $src2 */
232 UINT f_r2;
cab58155 233 } fmt_21_cmpz;
8e420152
DE		 234 struct { /* e.g. div $dr,$sr */
235 UINT f_r1;
236 UINT f_r2;
cab58155 237 } fmt_22_div;
8e420152
DE		 238 struct { /* e.g. jc $sr */
239 UINT f_r2;
cab58155 240 } fmt_23_jc;
8e420152
DE		 241 struct { /* e.g. jl $sr */
242 UINT f_r2;
cab58155 243 } fmt_24_jl;
8e420152
DE		 244 struct { /* e.g. jmp $sr */
245 UINT f_r2;
cab58155 246 } fmt_25_jmp;
8e420152
DE		 247 struct { /* e.g. ld $dr,@$sr */
248 UINT f_r1;
249 UINT f_r2;
cab58155 250 } fmt_26_ld;
8e420152
DE		 251 struct { /* e.g. ld $dr,@($slo16,$sr) */
252 UINT f_r1;
253 UINT f_r2;
254 HI f_simm16;
cab58155 255 } fmt_27_ld_d;
8e420152
DE		 256 struct { /* e.g. ldb $dr,@$sr */
257 UINT f_r1;
258 UINT f_r2;
cab58155 259 } fmt_28_ldb;
8e420152
DE		 260 struct { /* e.g. ldb $dr,@($slo16,$sr) */
261 UINT f_r1;
262 UINT f_r2;
263 HI f_simm16;
cab58155 264 } fmt_29_ldb_d;
8e420152
DE		 265 struct { /* e.g. ldh $dr,@$sr */
266 UINT f_r1;
267 UINT f_r2;
cab58155 268 } fmt_30_ldh;
8e420152
DE		 269 struct { /* e.g. ldh $dr,@($slo16,$sr) */
270 UINT f_r1;
271 UINT f_r2;
272 HI f_simm16;
cab58155
DE		 273 } fmt_31_ldh_d;
274 struct { /* e.g. ld $dr,@$sr+ */
275 UINT f_r1;
276 UINT f_r2;
277 } fmt_32_ld_plus;
8e420152
DE		 278 struct { /* e.g. ld24 $dr,#$uimm24 */
279 UINT f_r1;
280 ADDR f_uimm24;
cab58155 281 } fmt_33_ld24;
8e420152
DE		 282 struct { /* e.g. ldi $dr,#$simm8 */
283 UINT f_r1;
284 SI f_simm8;
cab58155 285 } fmt_34_ldi8;
8e420152
DE		 286 struct { /* e.g. ldi $dr,$slo16 */
287 UINT f_r1;
288 HI f_simm16;
cab58155
DE		 289 } fmt_35_ldi16;
290 struct { /* e.g. lock $dr,@$sr */
291 UINT f_r1;
292 UINT f_r2;
293 } fmt_36_lock;
8e420152
DE		 294 struct { /* e.g. machi $src1,$src2,$acc */
295 UINT f_r1;
296 UINT f_acc;
297 UINT f_r2;
cab58155 298 } fmt_37_machi_a;
8e420152
DE		 299 struct { /* e.g. mulhi $src1,$src2,$acc */
300 UINT f_r1;
301 UINT f_acc;
302 UINT f_r2;
cab58155 303 } fmt_38_mulhi_a;
8e420152
DE		 304 struct { /* e.g. mv $dr,$sr */
305 UINT f_r1;
306 UINT f_r2;
cab58155 307 } fmt_39_mv;
8e420152
DE		 308 struct { /* e.g. mvfachi $dr,$accs */
309 UINT f_r1;
310 UINT f_accs;
cab58155 311 } fmt_40_mvfachi_a;
8e420152
DE		 312 struct { /* e.g. mvfc $dr,$scr */
313 UINT f_r1;
314 UINT f_r2;
cab58155 315 } fmt_41_mvfc;
8e420152
DE		 316 struct { /* e.g. mvtachi $src1,$accs */
317 UINT f_r1;
318 UINT f_accs;
cab58155 319 } fmt_42_mvtachi_a;
8e420152
DE		 320 struct { /* e.g. mvtc $sr,$dcr */
321 UINT f_r1;
322 UINT f_r2;
cab58155 323 } fmt_43_mvtc;
8e420152
DE		 324 struct { /* e.g. nop */
325 int empty;
cab58155 326 } fmt_44_nop;
e0bd6e18
DE		 327 struct { /* e.g. rac $accd,$accs,#$imm1 */
328 UINT f_accd;
329 UINT f_accs;
330 USI f_imm1;
cab58155 331 } fmt_45_rac_dsi;
b8a9943d
DE		 332 struct { /* e.g. rte */
333 int empty;
cab58155 334 } fmt_46_rte;
b8a9943d 335 struct { /* e.g. seth $dr,#$hi16 */
8e420152
DE		 336 UINT f_r1;
337 UHI f_hi16;
cab58155
DE		 338 } fmt_47_seth;
339 struct { /* e.g. sll3 $dr,$sr,#$simm16 */
340 UINT f_r1;
341 UINT f_r2;
342 SI f_simm16;
343 } fmt_48_sll3;
8e420152
DE		 344 struct { /* e.g. slli $dr,#$uimm5 */
345 UINT f_r1;
346 USI f_uimm5;
cab58155
DE		 347 } fmt_49_slli;
348 struct { /* e.g. st $src1,@$src2 */
349 UINT f_r1;
350 UINT f_r2;
351 } fmt_50_st;
8e420152
DE		 352 struct { /* e.g. st $src1,@($slo16,$src2) */
353 UINT f_r1;
354 UINT f_r2;
355 HI f_simm16;
cab58155
DE		 356 } fmt_51_st_d;
357 struct { /* e.g. stb $src1,@$src2 */
358 UINT f_r1;
359 UINT f_r2;
360 } fmt_52_stb;
361 struct { /* e.g. stb $src1,@($slo16,$src2) */
362 UINT f_r1;
363 UINT f_r2;
364 HI f_simm16;
365 } fmt_53_stb_d;
366 struct { /* e.g. sth $src1,@$src2 */
367 UINT f_r1;
368 UINT f_r2;
369 } fmt_54_sth;
370 struct { /* e.g. sth $src1,@($slo16,$src2) */
371 UINT f_r1;
372 UINT f_r2;
373 HI f_simm16;
374 } fmt_55_sth_d;
375 struct { /* e.g. st $src1,@+$src2 */
376 UINT f_r1;
377 UINT f_r2;
378 } fmt_56_st_plus;
8e420152
DE		 379 struct { /* e.g. trap #$uimm4 */
380 USI f_uimm4;
cab58155
DE		 381 } fmt_57_trap;
382 struct { /* e.g. unlock $src1,@$src2 */
8e420152
DE		 383 UINT f_r1;
384 UINT f_r2;
cab58155
DE		 385 } fmt_58_unlock;
386 struct { /* e.g. satb $dr,$sr */
b8a9943d 387 UINT f_r1;
8e420152 388 UINT f_r2;
cab58155
DE		 389 } fmt_59_satb;
390 struct { /* e.g. sat $dr,$sr */
391 UINT f_r1;
392 UINT f_r2;
393 } fmt_60_sat;
8e420152
DE		 394 struct { /* e.g. sadd */
395 int empty;
cab58155 396 } fmt_61_sadd;
8e420152
DE		 397 struct { /* e.g. macwu1 $src1,$src2 */
398 UINT f_r1;
399 UINT f_r2;
cab58155 400 } fmt_62_macwu1;
b8a9943d
DE		 401 struct { /* e.g. msblo $src1,$src2 */
402 UINT f_r1;
403 UINT f_r2;
cab58155
DE		 404 } fmt_63_msblo;
405 struct { /* e.g. mulwu1 $src1,$src2 */
406 UINT f_r1;
407 UINT f_r2;
408 } fmt_64_mulwu1;
8e420152
DE		 409 struct { /* e.g. sc */
410 int empty;
cab58155 411 } fmt_65_sc;
8e420152
DE		 412 } fields;
413#if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
414 unsigned long h_gr_get;
415 unsigned long h_gr_set;
416#endif
417};
418
419/* A cached insn.
cab58155
DE		 420 This is currently also used in the non-scache case. In this situation we
421 assume the cache size is 1, and do a few things a little differently. */
422/* FIXME: non-scache version to be redone. */
8e420152
DE		 423
424struct scache {
425 IADDR next;
426 union {
427#if ! WITH_SEM_SWITCH_FULL
428 SEMANTIC_FN *sem_fn;
429#endif
430#if ! WITH_SEM_SWITCH_FAST
8e420152
DE		 431 SEMANTIC_FN *sem_fast_fn;
432#endif
8e420152
DE		 433#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
434#ifdef __GNUC__
435 void *sem_case;
436#else
437 int sem_case;
438#endif
439#endif
440 } semantic;
441 struct argbuf argbuf;
442};
443
444/* Macros to simplify extraction, reading and semantic code.
445 These define and assign the local vars that contain the insn's fields. */
446
447#define EXTRACT_FMT_0_ADD_VARS \
448 /* Instruction fields. */ \
449 UINT f_op1; \
450 UINT f_r1; \
451 UINT f_op2; \
452 UINT f_r2; \
453 unsigned int length;
454#define EXTRACT_FMT_0_ADD_CODE \
455 length = 2; \
456 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
457 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
458 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
459 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
460
461#define EXTRACT_FMT_1_ADD3_VARS \
462 /* Instruction fields. */ \
463 UINT f_op1; \
464 UINT f_r1; \
465 UINT f_op2; \
466 UINT f_r2; \
467 int f_simm16; \
468 unsigned int length;
469#define EXTRACT_FMT_1_ADD3_CODE \
470 length = 4; \
471 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
472 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
473 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
474 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
475 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
476
477#define EXTRACT_FMT_2_AND3_VARS \
478 /* Instruction fields. */ \
479 UINT f_op1; \
480 UINT f_r1; \
481 UINT f_op2; \
482 UINT f_r2; \
483 UINT f_uimm16; \
484 unsigned int length;
485#define EXTRACT_FMT_2_AND3_CODE \
486 length = 4; \
487 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
488 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
489 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
490 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
491 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
492
493#define EXTRACT_FMT_3_OR3_VARS \
494 /* Instruction fields. */ \
495 UINT f_op1; \
496 UINT f_r1; \
497 UINT f_op2; \
498 UINT f_r2; \
499 UINT f_uimm16; \
500 unsigned int length;
501#define EXTRACT_FMT_3_OR3_CODE \
502 length = 4; \
503 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
504 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
505 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
506 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
507 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
508
509#define EXTRACT_FMT_4_ADDI_VARS \
510 /* Instruction fields. */ \
511 UINT f_op1; \
512 UINT f_r1; \
513 int f_simm8; \
514 unsigned int length;
515#define EXTRACT_FMT_4_ADDI_CODE \
516 length = 2; \
517 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
518 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
519 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
520
cab58155
DE		 521#define EXTRACT_FMT_5_ADDV_VARS \
522 /* Instruction fields. */ \
523 UINT f_op1; \
524 UINT f_r1; \
525 UINT f_op2; \
526 UINT f_r2; \
527 unsigned int length;
528#define EXTRACT_FMT_5_ADDV_CODE \
529 length = 2; \
530 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
531 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
532 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
533 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
534
535#define EXTRACT_FMT_6_ADDV3_VARS \
8e420152
DE		 536 /* Instruction fields. */ \
537 UINT f_op1; \
538 UINT f_r1; \
539 UINT f_op2; \
540 UINT f_r2; \
541 int f_simm16; \
542 unsigned int length;
cab58155 543#define EXTRACT_FMT_6_ADDV3_CODE \
8e420152
DE		 544 length = 4; \
545 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
546 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
547 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
548 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
549 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
550
cab58155 551#define EXTRACT_FMT_7_ADDX_VARS \
8e420152
DE		 552 /* Instruction fields. */ \
553 UINT f_op1; \
554 UINT f_r1; \
555 UINT f_op2; \
556 UINT f_r2; \
557 unsigned int length;
cab58155 558#define EXTRACT_FMT_7_ADDX_CODE \
8e420152
DE		 559 length = 2; \
560 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
561 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
562 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
563 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
564
cab58155 565#define EXTRACT_FMT_8_BC8_VARS \
8e420152
DE		 566 /* Instruction fields. */ \
567 UINT f_op1; \
568 UINT f_r1; \
569 int f_disp8; \
570 unsigned int length;
cab58155 571#define EXTRACT_FMT_8_BC8_CODE \
8e420152
DE		 572 length = 2; \
573 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
574 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
cab58155 575 f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
8e420152 576
cab58155 577#define EXTRACT_FMT_9_BC24_VARS \
8e420152
DE		 578 /* Instruction fields. */ \
579 UINT f_op1; \
580 UINT f_r1; \
581 int f_disp24; \
582 unsigned int length;
cab58155 583#define EXTRACT_FMT_9_BC24_CODE \
8e420152
DE		 584 length = 4; \
585 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
586 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
cab58155 587 f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
8e420152 588
cab58155 589#define EXTRACT_FMT_10_BEQ_VARS \
8e420152
DE		 590 /* Instruction fields. */ \
591 UINT f_op1; \
592 UINT f_r1; \
593 UINT f_op2; \
594 UINT f_r2; \
595 int f_disp16; \
596 unsigned int length;
cab58155 597#define EXTRACT_FMT_10_BEQ_CODE \
8e420152
DE		 598 length = 4; \
599 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
600 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
601 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
602 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
cab58155 603 f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \
8e420152 604
cab58155 605#define EXTRACT_FMT_11_BEQZ_VARS \
8e420152
DE		 606 /* Instruction fields. */ \
607 UINT f_op1; \
608 UINT f_r1; \
609 UINT f_op2; \
610 UINT f_r2; \
611 int f_disp16; \
612 unsigned int length;
cab58155 613#define EXTRACT_FMT_11_BEQZ_CODE \
8e420152
DE		 614 length = 4; \
615 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
616 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
617 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
618 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
cab58155 619 f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \
8e420152 620
cab58155 621#define EXTRACT_FMT_12_BL8_VARS \
8e420152
DE		 622 /* Instruction fields. */ \
623 UINT f_op1; \
624 UINT f_r1; \
625 int f_disp8; \
626 unsigned int length;
cab58155 627#define EXTRACT_FMT_12_BL8_CODE \
8e420152
DE		 628 length = 2; \
629 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
630 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
cab58155 631 f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
8e420152 632
cab58155 633#define EXTRACT_FMT_13_BL24_VARS \
8e420152
DE		 634 /* Instruction fields. */ \
635 UINT f_op1; \
636 UINT f_r1; \
637 int f_disp24; \
638 unsigned int length;
cab58155 639#define EXTRACT_FMT_13_BL24_CODE \
8e420152
DE		 640 length = 4; \
641 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
642 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
cab58155 643 f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
8e420152 644
cab58155 645#define EXTRACT_FMT_14_BCL8_VARS \
8e420152
DE		 646 /* Instruction fields. */ \
647 UINT f_op1; \
648 UINT f_r1; \
649 int f_disp8; \
650 unsigned int length;
cab58155 651#define EXTRACT_FMT_14_BCL8_CODE \
8e420152
DE		 652 length = 2; \
653 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
654 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
cab58155 655 f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
8e420152 656
cab58155 657#define EXTRACT_FMT_15_BCL24_VARS \
8e420152
DE		 658 /* Instruction fields. */ \
659 UINT f_op1; \
660 UINT f_r1; \
661 int f_disp24; \
662 unsigned int length;
cab58155 663#define EXTRACT_FMT_15_BCL24_CODE \
8e420152
DE		 664 length = 4; \
665 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
666 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
cab58155 667 f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
8e420152 668
cab58155 669#define EXTRACT_FMT_16_BRA8_VARS \
8e420152
DE		 670 /* Instruction fields. */ \
671 UINT f_op1; \
672 UINT f_r1; \
673 int f_disp8; \
674 unsigned int length;
cab58155 675#define EXTRACT_FMT_16_BRA8_CODE \
8e420152
DE		 676 length = 2; \
677 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
678 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
cab58155 679 f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
8e420152 680
cab58155 681#define EXTRACT_FMT_17_BRA24_VARS \
8e420152
DE		 682 /* Instruction fields. */ \
683 UINT f_op1; \
684 UINT f_r1; \
685 int f_disp24; \
686 unsigned int length;
cab58155 687#define EXTRACT_FMT_17_BRA24_CODE \
8e420152
DE		 688 length = 4; \
689 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
690 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
cab58155 691 f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
8e420152 692
cab58155 693#define EXTRACT_FMT_18_CMP_VARS \
8e420152
DE		 694 /* Instruction fields. */ \
695 UINT f_op1; \
696 UINT f_r1; \
697 UINT f_op2; \
698 UINT f_r2; \
699 unsigned int length;
cab58155 700#define EXTRACT_FMT_18_CMP_CODE \
8e420152
DE		 701 length = 2; \
702 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
703 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
704 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
705 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
706
cab58155 707#define EXTRACT_FMT_19_CMPI_VARS \
8e420152
DE		 708 /* Instruction fields. */ \
709 UINT f_op1; \
710 UINT f_r1; \
711 UINT f_op2; \
712 UINT f_r2; \
713 int f_simm16; \
714 unsigned int length;
cab58155 715#define EXTRACT_FMT_19_CMPI_CODE \
8e420152
DE		 716 length = 4; \
717 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
718 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
719 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
720 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
721 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
722
cab58155 723#define EXTRACT_FMT_20_CMPUI_VARS \
8e420152
DE		 724 /* Instruction fields. */ \
725 UINT f_op1; \
726 UINT f_r1; \
727 UINT f_op2; \
728 UINT f_r2; \
729 UINT f_uimm16; \
730 unsigned int length;
cab58155 731#define EXTRACT_FMT_20_CMPUI_CODE \
8e420152
DE		 732 length = 4; \
733 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
734 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
735 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
736 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
737 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
738
cab58155 739#define EXTRACT_FMT_21_CMPZ_VARS \
8e420152
DE		 740 /* Instruction fields. */ \
741 UINT f_op1; \
742 UINT f_r1; \
743 UINT f_op2; \
744 UINT f_r2; \
745 unsigned int length;
cab58155 746#define EXTRACT_FMT_21_CMPZ_CODE \
8e420152
DE		 747 length = 2; \
748 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
749 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
750 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
751 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
752
cab58155 753#define EXTRACT_FMT_22_DIV_VARS \
8e420152
DE		 754 /* Instruction fields. */ \
755 UINT f_op1; \
756 UINT f_r1; \
757 UINT f_op2; \
758 UINT f_r2; \
759 int f_simm16; \
760 unsigned int length;
cab58155 761#define EXTRACT_FMT_22_DIV_CODE \
8e420152
DE		 762 length = 4; \
763 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
764 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
765 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
766 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
767 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
768
cab58155 769#define EXTRACT_FMT_23_JC_VARS \
8e420152
DE		 770 /* Instruction fields. */ \
771 UINT f_op1; \
772 UINT f_r1; \
773 UINT f_op2; \
774 UINT f_r2; \
775 unsigned int length;
cab58155 776#define EXTRACT_FMT_23_JC_CODE \
8e420152
DE		 777 length = 2; \
778 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
779 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
780 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
781 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
782
cab58155 783#define EXTRACT_FMT_24_JL_VARS \
8e420152
DE		 784 /* Instruction fields. */ \
785 UINT f_op1; \
786 UINT f_r1; \
787 UINT f_op2; \
788 UINT f_r2; \
789 unsigned int length;
cab58155 790#define EXTRACT_FMT_24_JL_CODE \
8e420152
DE		 791 length = 2; \
792 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
793 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
794 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
795 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
796
cab58155 797#define EXTRACT_FMT_25_JMP_VARS \
8e420152
DE		 798 /* Instruction fields. */ \
799 UINT f_op1; \
800 UINT f_r1; \
801 UINT f_op2; \
802 UINT f_r2; \
803 unsigned int length;
cab58155 804#define EXTRACT_FMT_25_JMP_CODE \
8e420152
DE		 805 length = 2; \
806 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
807 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
808 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
809 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
810
cab58155 811#define EXTRACT_FMT_26_LD_VARS \
8e420152
DE		 812 /* Instruction fields. */ \
813 UINT f_op1; \
814 UINT f_r1; \
815 UINT f_op2; \
816 UINT f_r2; \
817 unsigned int length;
cab58155 818#define EXTRACT_FMT_26_LD_CODE \
8e420152
DE		 819 length = 2; \
820 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
821 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
822 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
823 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
824
cab58155 825#define EXTRACT_FMT_27_LD_D_VARS \
8e420152
DE		 826 /* Instruction fields. */ \
827 UINT f_op1; \
828 UINT f_r1; \
829 UINT f_op2; \
830 UINT f_r2; \
831 int f_simm16; \
832 unsigned int length;
cab58155 833#define EXTRACT_FMT_27_LD_D_CODE \
8e420152
DE		 834 length = 4; \
835 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
836 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
837 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
838 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
839 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
840
cab58155 841#define EXTRACT_FMT_28_LDB_VARS \
8e420152
DE		 842 /* Instruction fields. */ \
843 UINT f_op1; \
844 UINT f_r1; \
845 UINT f_op2; \
846 UINT f_r2; \
847 unsigned int length;
cab58155 848#define EXTRACT_FMT_28_LDB_CODE \
8e420152
DE		 849 length = 2; \
850 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
851 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
852 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
853 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
854
cab58155 855#define EXTRACT_FMT_29_LDB_D_VARS \
8e420152
DE		 856 /* Instruction fields. */ \
857 UINT f_op1; \
858 UINT f_r1; \
859 UINT f_op2; \
860 UINT f_r2; \
861 int f_simm16; \
862 unsigned int length;
cab58155 863#define EXTRACT_FMT_29_LDB_D_CODE \
8e420152
DE		 864 length = 4; \
865 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
866 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
867 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
868 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
869 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
870
cab58155 871#define EXTRACT_FMT_30_LDH_VARS \
8e420152
DE		 872 /* Instruction fields. */ \
873 UINT f_op1; \
874 UINT f_r1; \
875 UINT f_op2; \
876 UINT f_r2; \
877 unsigned int length;
cab58155 878#define EXTRACT_FMT_30_LDH_CODE \
8e420152
DE		 879 length = 2; \
880 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
881 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
882 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
883 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
884
cab58155 885#define EXTRACT_FMT_31_LDH_D_VARS \
8e420152
DE		 886 /* Instruction fields. */ \
887 UINT f_op1; \
888 UINT f_r1; \
889 UINT f_op2; \
890 UINT f_r2; \
891 int f_simm16; \
892 unsigned int length;
cab58155 893#define EXTRACT_FMT_31_LDH_D_CODE \
8e420152
DE		 894 length = 4; \
895 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
896 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
897 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
898 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
899 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
900
cab58155
DE		 901#define EXTRACT_FMT_32_LD_PLUS_VARS \
902 /* Instruction fields. */ \
903 UINT f_op1; \
904 UINT f_r1; \
905 UINT f_op2; \
906 UINT f_r2; \
907 unsigned int length;
908#define EXTRACT_FMT_32_LD_PLUS_CODE \
909 length = 2; \
910 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
911 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
912 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
913 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
914
915#define EXTRACT_FMT_33_LD24_VARS \
8e420152
DE		 916 /* Instruction fields. */ \
917 UINT f_op1; \
918 UINT f_r1; \
919 UINT f_uimm24; \
920 unsigned int length;
cab58155 921#define EXTRACT_FMT_33_LD24_CODE \
8e420152
DE		 922 length = 4; \
923 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
924 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
925 f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
926
cab58155 927#define EXTRACT_FMT_34_LDI8_VARS \
8e420152
DE		 928 /* Instruction fields. */ \
929 UINT f_op1; \
930 UINT f_r1; \
931 int f_simm8; \
932 unsigned int length;
cab58155 933#define EXTRACT_FMT_34_LDI8_CODE \
8e420152
DE		 934 length = 2; \
935 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
936 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
937 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
938
cab58155 939#define EXTRACT_FMT_35_LDI16_VARS \
8e420152
DE		 940 /* Instruction fields. */ \
941 UINT f_op1; \
942 UINT f_r1; \
943 UINT f_op2; \
944 UINT f_r2; \
945 int f_simm16; \
946 unsigned int length;
cab58155 947#define EXTRACT_FMT_35_LDI16_CODE \
8e420152
DE		 948 length = 4; \
949 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
950 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
951 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
952 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
953 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
954
cab58155
DE		 955#define EXTRACT_FMT_36_LOCK_VARS \
956 /* Instruction fields. */ \
957 UINT f_op1; \
958 UINT f_r1; \
959 UINT f_op2; \
960 UINT f_r2; \
961 unsigned int length;
962#define EXTRACT_FMT_36_LOCK_CODE \
963 length = 2; \
964 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
965 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
966 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
967 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
968
969#define EXTRACT_FMT_37_MACHI_A_VARS \
8e420152
DE		 970 /* Instruction fields. */ \
971 UINT f_op1; \
972 UINT f_r1; \
973 UINT f_acc; \
974 UINT f_op23; \
975 UINT f_r2; \
976 unsigned int length;
cab58155 977#define EXTRACT_FMT_37_MACHI_A_CODE \
8e420152
DE		 978 length = 2; \
979 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
980 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
981 f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
982 f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
983 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
984
cab58155 985#define EXTRACT_FMT_38_MULHI_A_VARS \
8e420152
DE		 986 /* Instruction fields. */ \
987 UINT f_op1; \
988 UINT f_r1; \
989 UINT f_acc; \
990 UINT f_op23; \
991 UINT f_r2; \
992 unsigned int length;
cab58155 993#define EXTRACT_FMT_38_MULHI_A_CODE \
8e420152
DE		 994 length = 2; \
995 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
996 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
997 f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
998 f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
999 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1000
cab58155 1001#define EXTRACT_FMT_39_MV_VARS \
8e420152
DE		 1002 /* Instruction fields. */ \
1003 UINT f_op1; \
1004 UINT f_r1; \
1005 UINT f_op2; \
1006 UINT f_r2; \
1007 unsigned int length;
cab58155 1008#define EXTRACT_FMT_39_MV_CODE \
8e420152
DE		 1009 length = 2; \
1010 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1011 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1012 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1013 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1014
cab58155 1015#define EXTRACT_FMT_40_MVFACHI_A_VARS \
8e420152
DE		 1016 /* Instruction fields. */ \
1017 UINT f_op1; \
1018 UINT f_r1; \
1019 UINT f_op2; \
1020 UINT f_accs; \
1021 UINT f_op3; \
1022 unsigned int length;
cab58155 1023#define EXTRACT_FMT_40_MVFACHI_A_CODE \
8e420152
DE		 1024 length = 2; \
1025 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1026 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1027 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1028 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1029 f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
1030
cab58155 1031#define EXTRACT_FMT_41_MVFC_VARS \
8e420152
DE		 1032 /* Instruction fields. */ \
1033 UINT f_op1; \
1034 UINT f_r1; \
1035 UINT f_op2; \
1036 UINT f_r2; \
1037 unsigned int length;
cab58155 1038#define EXTRACT_FMT_41_MVFC_CODE \
8e420152
DE		 1039 length = 2; \
1040 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1041 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1042 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1043 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1044
cab58155 1045#define EXTRACT_FMT_42_MVTACHI_A_VARS \
8e420152
DE		 1046 /* Instruction fields. */ \
1047 UINT f_op1; \
1048 UINT f_r1; \
1049 UINT f_op2; \
1050 UINT f_accs; \
1051 UINT f_op3; \
1052 unsigned int length;
cab58155 1053#define EXTRACT_FMT_42_MVTACHI_A_CODE \
8e420152
DE		 1054 length = 2; \
1055 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1056 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1057 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1058 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1059 f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
1060
cab58155 1061#define EXTRACT_FMT_43_MVTC_VARS \
8e420152
DE		 1062 /* Instruction fields. */ \
1063 UINT f_op1; \
1064 UINT f_r1; \
1065 UINT f_op2; \
1066 UINT f_r2; \
1067 unsigned int length;
cab58155 1068#define EXTRACT_FMT_43_MVTC_CODE \
8e420152
DE		 1069 length = 2; \
1070 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1071 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1072 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1073 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1074
cab58155 1075#define EXTRACT_FMT_44_NOP_VARS \
8e420152
DE		 1076 /* Instruction fields. */ \
1077 UINT f_op1; \
1078 UINT f_r1; \
1079 UINT f_op2; \
1080 UINT f_r2; \
1081 unsigned int length;
cab58155 1082#define EXTRACT_FMT_44_NOP_CODE \
8e420152
DE		 1083 length = 2; \
1084 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1085 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1086 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1087 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1088
cab58155 1089#define EXTRACT_FMT_45_RAC_DSI_VARS \
8e420152
DE		 1090 /* Instruction fields. */ \
1091 UINT f_op1; \
e0bd6e18
DE		 1092 UINT f_accd; \
1093 UINT f_bits67; \
8e420152 1094 UINT f_op2; \
b8a9943d 1095 UINT f_accs; \
e0bd6e18
DE		 1096 UINT f_bit14; \
1097 UINT f_imm1; \
8e420152 1098 unsigned int length;
cab58155 1099#define EXTRACT_FMT_45_RAC_DSI_CODE \
8e420152
DE		 1100 length = 2; \
1101 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
e0bd6e18
DE		 1102 f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
1103 f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
8e420152 1104 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
b8a9943d 1105 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
e0bd6e18 1106 f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
cab58155 1107 f_imm1 = ((EXTRACT_UNSIGNED (insn, 16, 15, 1)) + (1)); \
8e420152 1108
cab58155 1109#define EXTRACT_FMT_46_RTE_VARS \
e0bd6e18
DE		 1110 /* Instruction fields. */ \
1111 UINT f_op1; \
cab58155 1112 UINT f_r1; \
e0bd6e18 1113 UINT f_op2; \
cab58155 1114 UINT f_r2; \
e0bd6e18 1115 unsigned int length;
cab58155 1116#define EXTRACT_FMT_46_RTE_CODE \
e0bd6e18
DE		 1117 length = 2; \
1118 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
cab58155 1119 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
e0bd6e18 1120 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
cab58155 1121 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
e0bd6e18 1122
cab58155 1123#define EXTRACT_FMT_47_SETH_VARS \
e0bd6e18
DE		 1124 /* Instruction fields. */ \
1125 UINT f_op1; \
cab58155 1126 UINT f_r1; \
e0bd6e18 1127 UINT f_op2; \
cab58155
DE		 1128 UINT f_r2; \
1129 UINT f_hi16; \
1130 unsigned int length;
1131#define EXTRACT_FMT_47_SETH_CODE \
1132 length = 4; \
1133 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1134 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1135 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1136 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1137 f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1138
1139#define EXTRACT_FMT_48_SLL3_VARS \
1140 /* Instruction fields. */ \
1141 UINT f_op1; \
1142 UINT f_r1; \
1143 UINT f_op2; \
1144 UINT f_r2; \
1145 int f_simm16; \
e0bd6e18 1146 unsigned int length;
cab58155
DE		 1147#define EXTRACT_FMT_48_SLL3_CODE \
1148 length = 4; \
1149 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1150 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1151 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1152 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1153 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1154
1155#define EXTRACT_FMT_49_SLLI_VARS \
1156 /* Instruction fields. */ \
1157 UINT f_op1; \
1158 UINT f_r1; \
1159 UINT f_shift_op2; \
1160 UINT f_uimm5; \
1161 unsigned int length;
1162#define EXTRACT_FMT_49_SLLI_CODE \
e0bd6e18
DE		 1163 length = 2; \
1164 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
cab58155
DE		 1165 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1166 f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
1167 f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
1168
1169#define EXTRACT_FMT_50_ST_VARS \
1170 /* Instruction fields. */ \
1171 UINT f_op1; \
1172 UINT f_r1; \
1173 UINT f_op2; \
1174 UINT f_r2; \
1175 unsigned int length;
1176#define EXTRACT_FMT_50_ST_CODE \
1177 length = 2; \
1178 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1179 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
e0bd6e18 1180 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
cab58155 1181 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
e0bd6e18 1182
cab58155 1183#define EXTRACT_FMT_51_ST_D_VARS \
8e420152
DE		 1184 /* Instruction fields. */ \
1185 UINT f_op1; \
1186 UINT f_r1; \
1187 UINT f_op2; \
b8a9943d 1188 UINT f_r2; \
cab58155 1189 int f_simm16; \
8e420152 1190 unsigned int length;
cab58155
DE		 1191#define EXTRACT_FMT_51_ST_D_CODE \
1192 length = 4; \
1193 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1194 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1195 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1196 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1197 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1198
1199#define EXTRACT_FMT_52_STB_VARS \
1200 /* Instruction fields. */ \
1201 UINT f_op1; \
1202 UINT f_r1; \
1203 UINT f_op2; \
1204 UINT f_r2; \
1205 unsigned int length;
1206#define EXTRACT_FMT_52_STB_CODE \
8e420152
DE		 1207 length = 2; \
1208 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1209 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1210 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
b8a9943d 1211 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
8e420152 1212
cab58155 1213#define EXTRACT_FMT_53_STB_D_VARS \
8e420152
DE		 1214 /* Instruction fields. */ \
1215 UINT f_op1; \
1216 UINT f_r1; \
1217 UINT f_op2; \
1218 UINT f_r2; \
cab58155 1219 int f_simm16; \
8e420152 1220 unsigned int length;
cab58155 1221#define EXTRACT_FMT_53_STB_D_CODE \
8e420152
DE		 1222 length = 4; \
1223 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1224 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1225 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1226 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
cab58155 1227 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
8e420152 1228
cab58155 1229#define EXTRACT_FMT_54_STH_VARS \
8e420152
DE		 1230 /* Instruction fields. */ \
1231 UINT f_op1; \
1232 UINT f_r1; \
cab58155
DE		 1233 UINT f_op2; \
1234 UINT f_r2; \
8e420152 1235 unsigned int length;
cab58155 1236#define EXTRACT_FMT_54_STH_CODE \
8e420152
DE		 1237 length = 2; \
1238 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1239 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
cab58155
DE		 1240 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1241 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
8e420152 1242
cab58155 1243#define EXTRACT_FMT_55_STH_D_VARS \
8e420152
DE		 1244 /* Instruction fields. */ \
1245 UINT f_op1; \
1246 UINT f_r1; \
1247 UINT f_op2; \
1248 UINT f_r2; \
1249 int f_simm16; \
1250 unsigned int length;
cab58155 1251#define EXTRACT_FMT_55_STH_D_CODE \
8e420152
DE		 1252 length = 4; \
1253 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1254 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1255 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1256 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1257 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1258
cab58155
DE		 1259#define EXTRACT_FMT_56_ST_PLUS_VARS \
1260 /* Instruction fields. */ \
1261 UINT f_op1; \
1262 UINT f_r1; \
1263 UINT f_op2; \
1264 UINT f_r2; \
1265 unsigned int length;
1266#define EXTRACT_FMT_56_ST_PLUS_CODE \
1267 length = 2; \
1268 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1269 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1270 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1271 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1272
1273#define EXTRACT_FMT_57_TRAP_VARS \
8e420152
DE		 1274 /* Instruction fields. */ \
1275 UINT f_op1; \
1276 UINT f_r1; \
1277 UINT f_op2; \
1278 UINT f_uimm4; \
1279 unsigned int length;
cab58155 1280#define EXTRACT_FMT_57_TRAP_CODE \
8e420152
DE		 1281 length = 2; \
1282 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1283 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1284 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1285 f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1286
cab58155
DE		 1287#define EXTRACT_FMT_58_UNLOCK_VARS \
1288 /* Instruction fields. */ \
1289 UINT f_op1; \
1290 UINT f_r1; \
1291 UINT f_op2; \
1292 UINT f_r2; \
1293 unsigned int length;
1294#define EXTRACT_FMT_58_UNLOCK_CODE \
1295 length = 2; \
1296 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1297 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1298 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1299 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1300
1301#define EXTRACT_FMT_59_SATB_VARS \
b8a9943d
DE		 1302 /* Instruction fields. */ \
1303 UINT f_op1; \
1304 UINT f_r1; \
1305 UINT f_op2; \
1306 UINT f_r2; \
1307 UINT f_uimm16; \
1308 unsigned int length;
cab58155 1309#define EXTRACT_FMT_59_SATB_CODE \
b8a9943d
DE		 1310 length = 4; \
1311 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1312 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1313 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1314 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1315 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1316
cab58155 1317#define EXTRACT_FMT_60_SAT_VARS \
8e420152
DE		 1318 /* Instruction fields. */ \
1319 UINT f_op1; \
1320 UINT f_r1; \
1321 UINT f_op2; \
1322 UINT f_r2; \
1323 UINT f_uimm16; \
1324 unsigned int length;
cab58155 1325#define EXTRACT_FMT_60_SAT_CODE \
8e420152
DE		 1326 length = 4; \
1327 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1328 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1329 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1330 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1331 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1332
cab58155
DE		 1333#define EXTRACT_FMT_61_SADD_VARS \
1334 /* Instruction fields. */ \
1335 UINT f_op1; \
1336 UINT f_r1; \
1337 UINT f_op2; \
1338 UINT f_r2; \
1339 unsigned int length;
1340#define EXTRACT_FMT_61_SADD_CODE \
1341 length = 2; \
1342 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1343 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1344 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1345 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1346
1347#define EXTRACT_FMT_62_MACWU1_VARS \
8e420152
DE		 1348 /* Instruction fields. */ \
1349 UINT f_op1; \
1350 UINT f_r1; \
1351 UINT f_op2; \
1352 UINT f_r2; \
1353 unsigned int length;
cab58155 1354#define EXTRACT_FMT_62_MACWU1_CODE \
8e420152
DE		 1355 length = 2; \
1356 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1357 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1358 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1359 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1360
cab58155 1361#define EXTRACT_FMT_63_MSBLO_VARS \
8e420152
DE		 1362 /* Instruction fields. */ \
1363 UINT f_op1; \
1364 UINT f_r1; \
1365 UINT f_op2; \
1366 UINT f_r2; \
1367 unsigned int length;
cab58155 1368#define EXTRACT_FMT_63_MSBLO_CODE \
8e420152
DE		 1369 length = 2; \
1370 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1371 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1372 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1373 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1374
cab58155 1375#define EXTRACT_FMT_64_MULWU1_VARS \
8e420152
DE		 1376 /* Instruction fields. */ \
1377 UINT f_op1; \
1378 UINT f_r1; \
1379 UINT f_op2; \
1380 UINT f_r2; \
1381 unsigned int length;
cab58155 1382#define EXTRACT_FMT_64_MULWU1_CODE \
8e420152
DE		 1383 length = 2; \
1384 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1385 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1386 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1387 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1388
cab58155 1389#define EXTRACT_FMT_65_SC_VARS \
8e420152
DE		 1390 /* Instruction fields. */ \
1391 UINT f_op1; \
1392 UINT f_r1; \
1393 UINT f_op2; \
1394 UINT f_r2; \
1395 unsigned int length;
cab58155 1396#define EXTRACT_FMT_65_SC_CODE \
8e420152
DE		 1397 length = 2; \
1398 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1399 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1400 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1401 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1402
1403/* Fetched input values of an instruction. */
1404
e0bd6e18 1405struct parexec {
8e420152
DE		 1406 union {
1407 struct { /* e.g. add $dr,$sr */
1408 SI dr;
1409 SI sr;
1410 } fmt_0_add;
1411 struct { /* e.g. add3 $dr,$sr,#$slo16 */
1412 HI slo16;
1413 SI sr;
1414 } fmt_1_add3;
1415 struct { /* e.g. and3 $dr,$sr,#$uimm16 */
1416 SI sr;
1417 USI uimm16;
1418 } fmt_2_and3;
1419 struct { /* e.g. or3 $dr,$sr,#$ulo16 */
1420 SI sr;
1421 UHI ulo16;
1422 } fmt_3_or3;
1423 struct { /* e.g. addi $dr,#$simm8 */
1424 SI dr;
1425 SI simm8;
1426 } fmt_4_addi;
cab58155
DE		 1427 struct { /* e.g. addv $dr,$sr */
1428 SI dr;
1429 SI sr;
1430 } fmt_5_addv;
8e420152
DE		 1431 struct { /* e.g. addv3 $dr,$sr,#$simm16 */
1432 SI simm16;
1433 SI sr;
cab58155 1434 } fmt_6_addv3;
8e420152
DE		 1435 struct { /* e.g. addx $dr,$sr */
1436 UBI condbit;
1437 SI dr;
1438 SI sr;
cab58155 1439 } fmt_7_addx;
8e420152
DE		 1440 struct { /* e.g. bc $disp8 */
1441 UBI condbit;
1442 IADDR disp8;
cab58155 1443 } fmt_8_bc8;
8e420152
DE		 1444 struct { /* e.g. bc $disp24 */
1445 UBI condbit;
1446 IADDR disp24;
cab58155 1447 } fmt_9_bc24;
8e420152
DE		 1448 struct { /* e.g. beq $src1,$src2,$disp16 */
1449 IADDR disp16;
1450 SI src1;
1451 SI src2;
cab58155 1452 } fmt_10_beq;
8e420152
DE		 1453 struct { /* e.g. beqz $src2,$disp16 */
1454 IADDR disp16;
1455 SI src2;
cab58155 1456 } fmt_11_beqz;
8e420152
DE		 1457 struct { /* e.g. bl $disp8 */
1458 IADDR disp8;
1459 USI pc;
cab58155 1460 } fmt_12_bl8;
8e420152
DE		 1461 struct { /* e.g. bl $disp24 */
1462 IADDR disp24;
1463 USI pc;
cab58155 1464 } fmt_13_bl24;
8e420152
DE		 1465 struct { /* e.g. bcl $disp8 */
1466 UBI condbit;
1467 IADDR disp8;
1468 USI pc;
cab58155 1469 } fmt_14_bcl8;
8e420152
DE		 1470 struct { /* e.g. bcl $disp24 */
1471 UBI condbit;
1472 IADDR disp24;
1473 USI pc;
cab58155 1474 } fmt_15_bcl24;
8e420152
DE		 1475 struct { /* e.g. bra $disp8 */
1476 IADDR disp8;
cab58155 1477 } fmt_16_bra8;
8e420152
DE		 1478 struct { /* e.g. bra $disp24 */
1479 IADDR disp24;
cab58155 1480 } fmt_17_bra24;
8e420152
DE		 1481 struct { /* e.g. cmp $src1,$src2 */
1482 SI src1;
1483 SI src2;
cab58155 1484 } fmt_18_cmp;
8e420152
DE		 1485 struct { /* e.g. cmpi $src2,#$simm16 */
1486 SI simm16;
1487 SI src2;
cab58155 1488 } fmt_19_cmpi;
8e420152
DE		 1489 struct { /* e.g. cmpui $src2,#$uimm16 */
1490 SI src2;
1491 USI uimm16;
cab58155 1492 } fmt_20_cmpui;
8e420152
DE		 1493 struct { /* e.g. cmpz $src2 */
1494 SI src2;
cab58155 1495 } fmt_21_cmpz;
8e420152
DE		 1496 struct { /* e.g. div $dr,$sr */
1497 SI dr;
1498 SI sr;
cab58155 1499 } fmt_22_div;
8e420152
DE		 1500 struct { /* e.g. jc $sr */
1501 UBI condbit;
1502 SI sr;
cab58155 1503 } fmt_23_jc;
8e420152
DE		 1504 struct { /* e.g. jl $sr */
1505 USI pc;
1506 SI sr;
cab58155 1507 } fmt_24_jl;
8e420152
DE		 1508 struct { /* e.g. jmp $sr */
1509 SI sr;
cab58155 1510 } fmt_25_jmp;
8e420152 1511 struct { /* e.g. ld $dr,@$sr */
02310b01 1512 SI h_memory_sr;
8e420152 1513 SI sr;
cab58155 1514 } fmt_26_ld;
8e420152 1515 struct { /* e.g. ld $dr,@($slo16,$sr) */
02310b01 1516 SI h_memory_add_WI_sr_slo16;
8e420152
DE		 1517 HI slo16;
1518 SI sr;
cab58155 1519 } fmt_27_ld_d;
8e420152 1520 struct { /* e.g. ldb $dr,@$sr */
02310b01 1521 QI h_memory_sr;
8e420152 1522 SI sr;
cab58155 1523 } fmt_28_ldb;
8e420152 1524 struct { /* e.g. ldb $dr,@($slo16,$sr) */
02310b01 1525 QI h_memory_add_WI_sr_slo16;
8e420152
DE		 1526 HI slo16;
1527 SI sr;
cab58155 1528 } fmt_29_ldb_d;
8e420152 1529 struct { /* e.g. ldh $dr,@$sr */
02310b01 1530 HI h_memory_sr;
8e420152 1531 SI sr;
cab58155 1532 } fmt_30_ldh;
8e420152 1533 struct { /* e.g. ldh $dr,@($slo16,$sr) */
02310b01 1534 HI h_memory_add_WI_sr_slo16;
8e420152
DE		 1535 HI slo16;
1536 SI sr;
cab58155
DE		 1537 } fmt_31_ldh_d;
1538 struct { /* e.g. ld $dr,@$sr+ */
02310b01 1539 SI h_memory_sr;
cab58155
DE		 1540 SI sr;
1541 } fmt_32_ld_plus;
8e420152
DE		 1542 struct { /* e.g. ld24 $dr,#$uimm24 */
1543 ADDR uimm24;
cab58155 1544 } fmt_33_ld24;
8e420152
DE		 1545 struct { /* e.g. ldi $dr,#$simm8 */
1546 SI simm8;
cab58155 1547 } fmt_34_ldi8;
8e420152
DE		 1548 struct { /* e.g. ldi $dr,$slo16 */
1549 HI slo16;
cab58155
DE		 1550 } fmt_35_ldi16;
1551 struct { /* e.g. lock $dr,@$sr */
02310b01 1552 SI h_memory_sr;
cab58155
DE		 1553 SI sr;
1554 } fmt_36_lock;
8e420152
DE		 1555 struct { /* e.g. machi $src1,$src2,$acc */
1556 DI acc;
1557 SI src1;
1558 SI src2;
cab58155 1559 } fmt_37_machi_a;
8e420152
DE		 1560 struct { /* e.g. mulhi $src1,$src2,$acc */
1561 SI src1;
1562 SI src2;
cab58155 1563 } fmt_38_mulhi_a;
8e420152
DE		 1564 struct { /* e.g. mv $dr,$sr */
1565 SI sr;
cab58155 1566 } fmt_39_mv;
8e420152
DE		 1567 struct { /* e.g. mvfachi $dr,$accs */
1568 DI accs;
cab58155 1569 } fmt_40_mvfachi_a;
8e420152 1570 struct { /* e.g. mvfc $dr,$scr */
cab58155
DE		 1571 USI scr;
1572 } fmt_41_mvfc;
8e420152
DE		 1573 struct { /* e.g. mvtachi $src1,$accs */
1574 DI accs;
1575 SI src1;
cab58155 1576 } fmt_42_mvtachi_a;
8e420152
DE		 1577 struct { /* e.g. mvtc $sr,$dcr */
1578 SI sr;
cab58155 1579 } fmt_43_mvtc;
8e420152
DE		 1580 struct { /* e.g. nop */
1581 int empty;
cab58155 1582 } fmt_44_nop;
e0bd6e18 1583 struct { /* e.g. rac $accd,$accs,#$imm1 */
8e420152 1584 DI accs;
e0bd6e18 1585 USI imm1;
cab58155 1586 } fmt_45_rac_dsi;
b8a9943d
DE		 1587 struct { /* e.g. rte */
1588 UBI h_bcond_0;
1589 UBI h_bie_0;
1590 SI h_bpc_0;
1591 UBI h_bsm_0;
cab58155 1592 } fmt_46_rte;
b8a9943d 1593 struct { /* e.g. seth $dr,#$hi16 */
8e420152 1594 UHI hi16;
cab58155
DE		 1595 } fmt_47_seth;
1596 struct { /* e.g. sll3 $dr,$sr,#$simm16 */
1597 SI simm16;
1598 SI sr;
1599 } fmt_48_sll3;
8e420152
DE		 1600 struct { /* e.g. slli $dr,#$uimm5 */
1601 SI dr;
1602 USI uimm5;
cab58155
DE		 1603 } fmt_49_slli;
1604 struct { /* e.g. st $src1,@$src2 */
1605 SI src1;
1606 SI src2;
1607 } fmt_50_st;
8e420152
DE		 1608 struct { /* e.g. st $src1,@($slo16,$src2) */
1609 HI slo16;
1610 SI src1;
1611 SI src2;
cab58155
DE		 1612 } fmt_51_st_d;
1613 struct { /* e.g. stb $src1,@$src2 */
1614 SI src1;
1615 SI src2;
1616 } fmt_52_stb;
1617 struct { /* e.g. stb $src1,@($slo16,$src2) */
1618 HI slo16;
1619 SI src1;
1620 SI src2;
1621 } fmt_53_stb_d;
1622 struct { /* e.g. sth $src1,@$src2 */
1623 SI src1;
1624 SI src2;
1625 } fmt_54_sth;
1626 struct { /* e.g. sth $src1,@($slo16,$src2) */
1627 HI slo16;
1628 SI src1;
1629 SI src2;
1630 } fmt_55_sth_d;
1631 struct { /* e.g. st $src1,@+$src2 */
1632 SI src1;
1633 SI src2;
1634 } fmt_56_st_plus;
8e420152 1635 struct { /* e.g. trap #$uimm4 */
cab58155 1636 USI pc;
02310b01 1637 SI h_cr_0;
8e420152 1638 USI uimm4;
cab58155
DE		 1639 } fmt_57_trap;
1640 struct { /* e.g. unlock $src1,@$src2 */
1641 UBI h_lock_0;
1642 SI src1;
b8a9943d 1643 SI src2;
cab58155
DE		 1644 } fmt_58_unlock;
1645 struct { /* e.g. satb $dr,$sr */
1646 SI sr;
1647 } fmt_59_satb;
1648 struct { /* e.g. sat $dr,$sr */
b8a9943d 1649 UBI condbit;
cab58155
DE		 1650 SI sr;
1651 } fmt_60_sat;
8e420152 1652 struct { /* e.g. sadd */
b8a9943d
DE		 1653 DI h_accums_0;
1654 DI h_accums_1;
cab58155 1655 } fmt_61_sadd;
8e420152 1656 struct { /* e.g. macwu1 $src1,$src2 */
b8a9943d
DE		 1657 DI h_accums_1;
1658 SI src1;
1659 SI src2;
cab58155 1660 } fmt_62_macwu1;
b8a9943d
DE		 1661 struct { /* e.g. msblo $src1,$src2 */
1662 DI accum;
8e420152
DE		 1663 SI src1;
1664 SI src2;
cab58155
DE		 1665 } fmt_63_msblo;
1666 struct { /* e.g. mulwu1 $src1,$src2 */
1667 SI src1;
1668 SI src2;
1669 } fmt_64_mulwu1;
8e420152
DE		 1670 struct { /* e.g. sc */
1671 UBI condbit;
cab58155 1672 } fmt_65_sc;
8e420152
DE		 1673 } operands;
1674};
1675
1676#endif /* CPU_M32RX_H */
GDB Binutils - Deliverables
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