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* cgen.h (CGEN_FIELDS): Define here.
[deliverable/binutils-gdb.git] / sim / m32r / cpux.h
CommitLineData
8e420152
DE		 1/* CPU family header for m32rx.
2
b8a9943d
DE		 3This file is machine generated with CGEN.
4
8e420152
DE		 5Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
6
7This file is part of the GNU Simulators.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#ifndef CPU_M32RX_H
26#define CPU_M32RX_H
27
28/* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30#define MAX_LIW_INSNS 2
31
32/* Maximum number of instructions that can be executed in parallel. */
33#define MAX_PARALLEL_INSNS 2
34
35/* CPU state information. */
36typedef struct {
37 /* Hardware elements. */
38 struct {
39 /* program counter */
40 USI h_pc;
41#define GET_H_PC() CPU (h_pc)
42#define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
44 SI h_gr[16];
45#define GET_H_GR(a1) CPU (h_gr)[a1]
46#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
48 SI h_cr[7];
49#define GET_H_CR(a1) CPU (h_cr)[a1]
50#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
51 /* accumulator */
52 DI h_accum;
53#define GET_H_ACCUM() CPU (h_accum)
54#define SET_H_ACCUM(x) (CPU (h_accum) = (x))
b8a9943d 55/* start-sanitize-m32rx */
8e420152
DE		 56 /* accumulators */
57 DI h_accums[2];
b8a9943d 58/* end-sanitize-m32rx */
8e420152
DE		 59#define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
60#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
b8a9943d 61/* start-sanitize-m32rx */
8e420152
DE		 62 /* abort flag */
63 UBI h_abort;
b8a9943d 64/* end-sanitize-m32rx */
8e420152
DE		 65#define GET_H_ABORT() CPU (h_abort)
66#define SET_H_ABORT(x) (CPU (h_abort) = (x))
67 /* condition bit */
68 UBI h_cond;
69#define GET_H_COND() CPU (h_cond)
70#define SET_H_COND(x) (CPU (h_cond) = (x))
71 /* sm */
72 UBI h_sm;
73#define GET_H_SM() CPU (h_sm)
74#define SET_H_SM(x) (CPU (h_sm) = (x))
75 /* bsm */
76 UBI h_bsm;
77#define GET_H_BSM() CPU (h_bsm)
78#define SET_H_BSM(x) (CPU (h_bsm) = (x))
79 /* ie */
80 UBI h_ie;
81#define GET_H_IE() CPU (h_ie)
82#define SET_H_IE(x) (CPU (h_ie) = (x))
83 /* bie */
84 UBI h_bie;
85#define GET_H_BIE() CPU (h_bie)
86#define SET_H_BIE(x) (CPU (h_bie) = (x))
87 /* bcond */
88 UBI h_bcond;
89#define GET_H_BCOND() CPU (h_bcond)
90#define SET_H_BCOND(x) (CPU (h_bcond) = (x))
91 /* bpc */
92 SI h_bpc;
93#define GET_H_BPC() CPU (h_bpc)
94#define SET_H_BPC(x) (CPU (h_bpc) = (x))
95 } hardware;
96#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
97 /* CPU profiling state information. */
98 struct {
99 /* general registers */
100 unsigned long h_gr;
101 } profile;
102#define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
103} M32RX_CPU_DATA;
104
b8a9943d 105extern DECODE *m32rx_decode (SIM_CPU *, PCADDR, insn_t);
8e420152
DE		 106
107/* The ARGBUF struct. */
108struct argbuf {
109 /* These are the baseclass definitions. */
110 unsigned int length;
111 PCADDR addr;
112 const struct cgen_insn *opcode;
b8a9943d
DE		 113#if ! defined (SCACHE_P)
114 insn_t insn;
115#endif
8e420152
DE		 116 /* cpu specific data follows */
117 union {
118 struct { /* e.g. add $dr,$sr */
119 UINT f_r1;
120 UINT f_r2;
121 } fmt_0_add;
122 struct { /* e.g. add3 $dr,$sr,#$slo16 */
123 UINT f_r1;
124 UINT f_r2;
125 HI f_simm16;
126 } fmt_1_add3;
127 struct { /* e.g. and3 $dr,$sr,#$uimm16 */
128 UINT f_r1;
129 UINT f_r2;
130 USI f_uimm16;
131 } fmt_2_and3;
132 struct { /* e.g. or3 $dr,$sr,#$ulo16 */
133 UINT f_r1;
134 UINT f_r2;
135 UHI f_uimm16;
136 } fmt_3_or3;
137 struct { /* e.g. addi $dr,#$simm8 */
138 UINT f_r1;
139 SI f_simm8;
140 } fmt_4_addi;
141 struct { /* e.g. addv3 $dr,$sr,#$simm16 */
142 UINT f_r1;
143 UINT f_r2;
144 SI f_simm16;
145 } fmt_5_addv3;
146 struct { /* e.g. addx $dr,$sr */
147 UINT f_r1;
148 UINT f_r2;
149 } fmt_6_addx;
150 struct { /* e.g. bc $disp8 */
151 IADDR f_disp8;
152 } fmt_7_bc8;
153 struct { /* e.g. bc $disp24 */
154 IADDR f_disp24;
155 } fmt_8_bc24;
156 struct { /* e.g. beq $src1,$src2,$disp16 */
157 UINT f_r1;
158 UINT f_r2;
159 IADDR f_disp16;
160 } fmt_9_beq;
161 struct { /* e.g. beqz $src2,$disp16 */
162 UINT f_r2;
163 IADDR f_disp16;
164 } fmt_10_beqz;
165 struct { /* e.g. bl $disp8 */
166 IADDR f_disp8;
167 } fmt_11_bl8;
168 struct { /* e.g. bl $disp24 */
169 IADDR f_disp24;
170 } fmt_12_bl24;
171 struct { /* e.g. bcl $disp8 */
172 IADDR f_disp8;
173 } fmt_13_bcl8;
174 struct { /* e.g. bcl $disp24 */
175 IADDR f_disp24;
176 } fmt_14_bcl24;
177 struct { /* e.g. bra $disp8 */
178 IADDR f_disp8;
179 } fmt_15_bra8;
180 struct { /* e.g. bra $disp24 */
181 IADDR f_disp24;
182 } fmt_16_bra24;
183 struct { /* e.g. cmp $src1,$src2 */
184 UINT f_r1;
185 UINT f_r2;
186 } fmt_17_cmp;
187 struct { /* e.g. cmpi $src2,#$simm16 */
188 UINT f_r2;
189 SI f_simm16;
190 } fmt_18_cmpi;
191 struct { /* e.g. cmpui $src2,#$uimm16 */
192 UINT f_r2;
193 USI f_uimm16;
194 } fmt_19_cmpui;
195 struct { /* e.g. cmpz $src2 */
196 UINT f_r2;
197 } fmt_20_cmpz;
198 struct { /* e.g. div $dr,$sr */
199 UINT f_r1;
200 UINT f_r2;
201 } fmt_21_div;
202 struct { /* e.g. jc $sr */
203 UINT f_r2;
204 } fmt_22_jc;
205 struct { /* e.g. jl $sr */
206 UINT f_r2;
207 } fmt_23_jl;
208 struct { /* e.g. jmp $sr */
209 UINT f_r2;
210 } fmt_24_jmp;
211 struct { /* e.g. ld $dr,@$sr */
212 UINT f_r1;
213 UINT f_r2;
214 } fmt_25_ld;
215 struct { /* e.g. ld $dr,@($slo16,$sr) */
216 UINT f_r1;
217 UINT f_r2;
218 HI f_simm16;
219 } fmt_26_ld_d;
220 struct { /* e.g. ldb $dr,@$sr */
221 UINT f_r1;
222 UINT f_r2;
223 } fmt_27_ldb;
224 struct { /* e.g. ldb $dr,@($slo16,$sr) */
225 UINT f_r1;
226 UINT f_r2;
227 HI f_simm16;
228 } fmt_28_ldb_d;
229 struct { /* e.g. ldh $dr,@$sr */
230 UINT f_r1;
231 UINT f_r2;
232 } fmt_29_ldh;
233 struct { /* e.g. ldh $dr,@($slo16,$sr) */
234 UINT f_r1;
235 UINT f_r2;
236 HI f_simm16;
237 } fmt_30_ldh_d;
238 struct { /* e.g. ld24 $dr,#$uimm24 */
239 UINT f_r1;
240 ADDR f_uimm24;
241 } fmt_31_ld24;
242 struct { /* e.g. ldi $dr,#$simm8 */
243 UINT f_r1;
244 SI f_simm8;
245 } fmt_32_ldi8;
246 struct { /* e.g. ldi $dr,$slo16 */
247 UINT f_r1;
248 HI f_simm16;
249 } fmt_33_ldi16;
8e420152
DE		 250 struct { /* e.g. machi $src1,$src2,$acc */
251 UINT f_r1;
252 UINT f_acc;
253 UINT f_r2;
b8a9943d 254 } fmt_34_machi_a;
8e420152
DE		 255 struct { /* e.g. mulhi $src1,$src2,$acc */
256 UINT f_r1;
257 UINT f_acc;
258 UINT f_r2;
b8a9943d 259 } fmt_35_mulhi_a;
8e420152
DE		 260 struct { /* e.g. mv $dr,$sr */
261 UINT f_r1;
262 UINT f_r2;
b8a9943d 263 } fmt_36_mv;
8e420152
DE		 264 struct { /* e.g. mvfachi $dr,$accs */
265 UINT f_r1;
266 UINT f_accs;
b8a9943d 267 } fmt_37_mvfachi_a;
8e420152
DE		 268 struct { /* e.g. mvfc $dr,$scr */
269 UINT f_r1;
270 UINT f_r2;
b8a9943d 271 } fmt_38_mvfc;
8e420152
DE		 272 struct { /* e.g. mvtachi $src1,$accs */
273 UINT f_r1;
274 UINT f_accs;
b8a9943d 275 } fmt_39_mvtachi_a;
8e420152
DE		 276 struct { /* e.g. mvtc $sr,$dcr */
277 UINT f_r1;
278 UINT f_r2;
b8a9943d 279 } fmt_40_mvtc;
8e420152
DE		 280 struct { /* e.g. nop */
281 int empty;
b8a9943d 282 } fmt_41_nop;
8e420152
DE		 283 struct { /* e.g. rac $accs */
284 UINT f_accs;
b8a9943d
DE		 285 } fmt_42_rac_a;
286 struct { /* e.g. rte */
287 int empty;
288 } fmt_43_rte;
289 struct { /* e.g. seth $dr,#$hi16 */
8e420152
DE		 290 UINT f_r1;
291 UHI f_hi16;
b8a9943d 292 } fmt_44_seth;
8e420152
DE		 293 struct { /* e.g. slli $dr,#$uimm5 */
294 UINT f_r1;
295 USI f_uimm5;
b8a9943d 296 } fmt_45_slli;
8e420152
DE		 297 struct { /* e.g. st $src1,@($slo16,$src2) */
298 UINT f_r1;
299 UINT f_r2;
300 HI f_simm16;
b8a9943d 301 } fmt_46_st_d;
8e420152
DE		 302 struct { /* e.g. trap #$uimm4 */
303 USI f_uimm4;
b8a9943d 304 } fmt_47_trap;
8e420152
DE		 305 struct { /* e.g. satb $dr,$src2 */
306 UINT f_r1;
307 UINT f_r2;
b8a9943d
DE		 308 } fmt_48_satb;
309 struct { /* e.g. sat $dr,$src2 */
310 UINT f_r1;
8e420152 311 UINT f_r2;
b8a9943d 312 } fmt_49_sat;
8e420152
DE		 313 struct { /* e.g. sadd */
314 int empty;
b8a9943d 315 } fmt_50_sadd;
8e420152
DE		 316 struct { /* e.g. macwu1 $src1,$src2 */
317 UINT f_r1;
318 UINT f_r2;
b8a9943d
DE		 319 } fmt_51_macwu1;
320 struct { /* e.g. msblo $src1,$src2 */
321 UINT f_r1;
322 UINT f_r2;
323 } fmt_52_msblo;
8e420152
DE		 324 struct { /* e.g. sc */
325 int empty;
b8a9943d 326 } fmt_53_sc;
8e420152
DE		 327 } fields;
328#if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
329 unsigned long h_gr_get;
330 unsigned long h_gr_set;
331#endif
332};
333
334/* A cached insn.
335 This is also used in the non-scache case. In this situation we assume
336 the cache size is 1, and do a few things a little differently. */
337
338struct scache {
339 IADDR next;
340 union {
341#if ! WITH_SEM_SWITCH_FULL
342 SEMANTIC_FN *sem_fn;
343#endif
344#if ! WITH_SEM_SWITCH_FAST
345#if WITH_SCACHE
346 SEMANTIC_CACHE_FN *sem_fast_fn;
347#else
348 SEMANTIC_FN *sem_fast_fn;
349#endif
350#endif
351#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
352#ifdef __GNUC__
353 void *sem_case;
354#else
355 int sem_case;
356#endif
357#endif
358 } semantic;
359 struct argbuf argbuf;
360};
361
362/* Macros to simplify extraction, reading and semantic code.
363 These define and assign the local vars that contain the insn's fields. */
364
365#define EXTRACT_FMT_0_ADD_VARS \
366 /* Instruction fields. */ \
367 UINT f_op1; \
368 UINT f_r1; \
369 UINT f_op2; \
370 UINT f_r2; \
371 unsigned int length;
372#define EXTRACT_FMT_0_ADD_CODE \
373 length = 2; \
374 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
375 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
376 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
377 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
378
379#define EXTRACT_FMT_1_ADD3_VARS \
380 /* Instruction fields. */ \
381 UINT f_op1; \
382 UINT f_r1; \
383 UINT f_op2; \
384 UINT f_r2; \
385 int f_simm16; \
386 unsigned int length;
387#define EXTRACT_FMT_1_ADD3_CODE \
388 length = 4; \
389 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
390 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
391 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
392 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
393 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
394
395#define EXTRACT_FMT_2_AND3_VARS \
396 /* Instruction fields. */ \
397 UINT f_op1; \
398 UINT f_r1; \
399 UINT f_op2; \
400 UINT f_r2; \
401 UINT f_uimm16; \
402 unsigned int length;
403#define EXTRACT_FMT_2_AND3_CODE \
404 length = 4; \
405 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
406 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
407 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
408 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
409 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
410
411#define EXTRACT_FMT_3_OR3_VARS \
412 /* Instruction fields. */ \
413 UINT f_op1; \
414 UINT f_r1; \
415 UINT f_op2; \
416 UINT f_r2; \
417 UINT f_uimm16; \
418 unsigned int length;
419#define EXTRACT_FMT_3_OR3_CODE \
420 length = 4; \
421 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
422 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
423 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
424 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
425 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
426
427#define EXTRACT_FMT_4_ADDI_VARS \
428 /* Instruction fields. */ \
429 UINT f_op1; \
430 UINT f_r1; \
431 int f_simm8; \
432 unsigned int length;
433#define EXTRACT_FMT_4_ADDI_CODE \
434 length = 2; \
435 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
436 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
437 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
438
439#define EXTRACT_FMT_5_ADDV3_VARS \
440 /* Instruction fields. */ \
441 UINT f_op1; \
442 UINT f_r1; \
443 UINT f_op2; \
444 UINT f_r2; \
445 int f_simm16; \
446 unsigned int length;
447#define EXTRACT_FMT_5_ADDV3_CODE \
448 length = 4; \
449 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
450 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
451 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
452 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
453 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
454
455#define EXTRACT_FMT_6_ADDX_VARS \
456 /* Instruction fields. */ \
457 UINT f_op1; \
458 UINT f_r1; \
459 UINT f_op2; \
460 UINT f_r2; \
461 unsigned int length;
462#define EXTRACT_FMT_6_ADDX_CODE \
463 length = 2; \
464 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
465 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
466 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
467 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
468
469#define EXTRACT_FMT_7_BC8_VARS \
470 /* Instruction fields. */ \
471 UINT f_op1; \
472 UINT f_r1; \
473 int f_disp8; \
474 unsigned int length;
475#define EXTRACT_FMT_7_BC8_CODE \
476 length = 2; \
477 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
478 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
479 f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
480
481#define EXTRACT_FMT_8_BC24_VARS \
482 /* Instruction fields. */ \
483 UINT f_op1; \
484 UINT f_r1; \
485 int f_disp24; \
486 unsigned int length;
487#define EXTRACT_FMT_8_BC24_CODE \
488 length = 4; \
489 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
490 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
491 f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
492
493#define EXTRACT_FMT_9_BEQ_VARS \
494 /* Instruction fields. */ \
495 UINT f_op1; \
496 UINT f_r1; \
497 UINT f_op2; \
498 UINT f_r2; \
499 int f_disp16; \
500 unsigned int length;
501#define EXTRACT_FMT_9_BEQ_CODE \
502 length = 4; \
503 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
504 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
505 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
506 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
507 f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
508
509#define EXTRACT_FMT_10_BEQZ_VARS \
510 /* Instruction fields. */ \
511 UINT f_op1; \
512 UINT f_r1; \
513 UINT f_op2; \
514 UINT f_r2; \
515 int f_disp16; \
516 unsigned int length;
517#define EXTRACT_FMT_10_BEQZ_CODE \
518 length = 4; \
519 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
520 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
521 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
522 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
523 f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
524
525#define EXTRACT_FMT_11_BL8_VARS \
526 /* Instruction fields. */ \
527 UINT f_op1; \
528 UINT f_r1; \
529 int f_disp8; \
530 unsigned int length;
531#define EXTRACT_FMT_11_BL8_CODE \
532 length = 2; \
533 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
534 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
535 f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
536
537#define EXTRACT_FMT_12_BL24_VARS \
538 /* Instruction fields. */ \
539 UINT f_op1; \
540 UINT f_r1; \
541 int f_disp24; \
542 unsigned int length;
543#define EXTRACT_FMT_12_BL24_CODE \
544 length = 4; \
545 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
546 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
547 f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
548
549#define EXTRACT_FMT_13_BCL8_VARS \
550 /* Instruction fields. */ \
551 UINT f_op1; \
552 UINT f_r1; \
553 int f_disp8; \
554 unsigned int length;
555#define EXTRACT_FMT_13_BCL8_CODE \
556 length = 2; \
557 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
558 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
559 f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
560
561#define EXTRACT_FMT_14_BCL24_VARS \
562 /* Instruction fields. */ \
563 UINT f_op1; \
564 UINT f_r1; \
565 int f_disp24; \
566 unsigned int length;
567#define EXTRACT_FMT_14_BCL24_CODE \
568 length = 4; \
569 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
570 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
571 f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
572
573#define EXTRACT_FMT_15_BRA8_VARS \
574 /* Instruction fields. */ \
575 UINT f_op1; \
576 UINT f_r1; \
577 int f_disp8; \
578 unsigned int length;
579#define EXTRACT_FMT_15_BRA8_CODE \
580 length = 2; \
581 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
582 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
583 f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
584
585#define EXTRACT_FMT_16_BRA24_VARS \
586 /* Instruction fields. */ \
587 UINT f_op1; \
588 UINT f_r1; \
589 int f_disp24; \
590 unsigned int length;
591#define EXTRACT_FMT_16_BRA24_CODE \
592 length = 4; \
593 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
594 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
595 f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
596
597#define EXTRACT_FMT_17_CMP_VARS \
598 /* Instruction fields. */ \
599 UINT f_op1; \
600 UINT f_r1; \
601 UINT f_op2; \
602 UINT f_r2; \
603 unsigned int length;
604#define EXTRACT_FMT_17_CMP_CODE \
605 length = 2; \
606 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
607 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
608 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
609 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
610
611#define EXTRACT_FMT_18_CMPI_VARS \
612 /* Instruction fields. */ \
613 UINT f_op1; \
614 UINT f_r1; \
615 UINT f_op2; \
616 UINT f_r2; \
617 int f_simm16; \
618 unsigned int length;
619#define EXTRACT_FMT_18_CMPI_CODE \
620 length = 4; \
621 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
622 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
623 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
624 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
625 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
626
627#define EXTRACT_FMT_19_CMPUI_VARS \
628 /* Instruction fields. */ \
629 UINT f_op1; \
630 UINT f_r1; \
631 UINT f_op2; \
632 UINT f_r2; \
633 UINT f_uimm16; \
634 unsigned int length;
635#define EXTRACT_FMT_19_CMPUI_CODE \
636 length = 4; \
637 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
638 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
639 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
640 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
641 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
642
643#define EXTRACT_FMT_20_CMPZ_VARS \
644 /* Instruction fields. */ \
645 UINT f_op1; \
646 UINT f_r1; \
647 UINT f_op2; \
648 UINT f_r2; \
649 unsigned int length;
650#define EXTRACT_FMT_20_CMPZ_CODE \
651 length = 2; \
652 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
653 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
654 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
655 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
656
657#define EXTRACT_FMT_21_DIV_VARS \
658 /* Instruction fields. */ \
659 UINT f_op1; \
660 UINT f_r1; \
661 UINT f_op2; \
662 UINT f_r2; \
663 int f_simm16; \
664 unsigned int length;
665#define EXTRACT_FMT_21_DIV_CODE \
666 length = 4; \
667 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
668 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
669 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
670 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
671 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
672
673#define EXTRACT_FMT_22_JC_VARS \
674 /* Instruction fields. */ \
675 UINT f_op1; \
676 UINT f_r1; \
677 UINT f_op2; \
678 UINT f_r2; \
679 unsigned int length;
680#define EXTRACT_FMT_22_JC_CODE \
681 length = 2; \
682 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
683 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
684 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
685 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
686
687#define EXTRACT_FMT_23_JL_VARS \
688 /* Instruction fields. */ \
689 UINT f_op1; \
690 UINT f_r1; \
691 UINT f_op2; \
692 UINT f_r2; \
693 unsigned int length;
694#define EXTRACT_FMT_23_JL_CODE \
695 length = 2; \
696 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
697 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
698 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
699 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
700
701#define EXTRACT_FMT_24_JMP_VARS \
702 /* Instruction fields. */ \
703 UINT f_op1; \
704 UINT f_r1; \
705 UINT f_op2; \
706 UINT f_r2; \
707 unsigned int length;
708#define EXTRACT_FMT_24_JMP_CODE \
709 length = 2; \
710 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
711 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
712 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
713 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
714
715#define EXTRACT_FMT_25_LD_VARS \
716 /* Instruction fields. */ \
717 UINT f_op1; \
718 UINT f_r1; \
719 UINT f_op2; \
720 UINT f_r2; \
721 unsigned int length;
722#define EXTRACT_FMT_25_LD_CODE \
723 length = 2; \
724 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
725 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
726 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
727 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
728
729#define EXTRACT_FMT_26_LD_D_VARS \
730 /* Instruction fields. */ \
731 UINT f_op1; \
732 UINT f_r1; \
733 UINT f_op2; \
734 UINT f_r2; \
735 int f_simm16; \
736 unsigned int length;
737#define EXTRACT_FMT_26_LD_D_CODE \
738 length = 4; \
739 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
740 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
741 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
742 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
743 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
744
745#define EXTRACT_FMT_27_LDB_VARS \
746 /* Instruction fields. */ \
747 UINT f_op1; \
748 UINT f_r1; \
749 UINT f_op2; \
750 UINT f_r2; \
751 unsigned int length;
752#define EXTRACT_FMT_27_LDB_CODE \
753 length = 2; \
754 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
755 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
756 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
757 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
758
759#define EXTRACT_FMT_28_LDB_D_VARS \
760 /* Instruction fields. */ \
761 UINT f_op1; \
762 UINT f_r1; \
763 UINT f_op2; \
764 UINT f_r2; \
765 int f_simm16; \
766 unsigned int length;
767#define EXTRACT_FMT_28_LDB_D_CODE \
768 length = 4; \
769 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
770 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
771 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
772 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
773 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
774
775#define EXTRACT_FMT_29_LDH_VARS \
776 /* Instruction fields. */ \
777 UINT f_op1; \
778 UINT f_r1; \
779 UINT f_op2; \
780 UINT f_r2; \
781 unsigned int length;
782#define EXTRACT_FMT_29_LDH_CODE \
783 length = 2; \
784 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
785 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
786 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
787 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
788
789#define EXTRACT_FMT_30_LDH_D_VARS \
790 /* Instruction fields. */ \
791 UINT f_op1; \
792 UINT f_r1; \
793 UINT f_op2; \
794 UINT f_r2; \
795 int f_simm16; \
796 unsigned int length;
797#define EXTRACT_FMT_30_LDH_D_CODE \
798 length = 4; \
799 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
800 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
801 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
802 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
803 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
804
805#define EXTRACT_FMT_31_LD24_VARS \
806 /* Instruction fields. */ \
807 UINT f_op1; \
808 UINT f_r1; \
809 UINT f_uimm24; \
810 unsigned int length;
811#define EXTRACT_FMT_31_LD24_CODE \
812 length = 4; \
813 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
814 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
815 f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
816
817#define EXTRACT_FMT_32_LDI8_VARS \
818 /* Instruction fields. */ \
819 UINT f_op1; \
820 UINT f_r1; \
821 int f_simm8; \
822 unsigned int length;
823#define EXTRACT_FMT_32_LDI8_CODE \
824 length = 2; \
825 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
826 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
827 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
828
829#define EXTRACT_FMT_33_LDI16_VARS \
830 /* Instruction fields. */ \
831 UINT f_op1; \
832 UINT f_r1; \
833 UINT f_op2; \
834 UINT f_r2; \
835 int f_simm16; \
836 unsigned int length;
837#define EXTRACT_FMT_33_LDI16_CODE \
838 length = 4; \
839 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
840 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
841 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
842 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
843 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
844
b8a9943d 845#define EXTRACT_FMT_34_MACHI_A_VARS \
8e420152
DE		 846 /* Instruction fields. */ \
847 UINT f_op1; \
848 UINT f_r1; \
849 UINT f_acc; \
850 UINT f_op23; \
851 UINT f_r2; \
852 unsigned int length;
b8a9943d 853#define EXTRACT_FMT_34_MACHI_A_CODE \
8e420152
DE		 854 length = 2; \
855 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
856 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
857 f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
858 f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
859 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
860
b8a9943d 861#define EXTRACT_FMT_35_MULHI_A_VARS \
8e420152
DE		 862 /* Instruction fields. */ \
863 UINT f_op1; \
864 UINT f_r1; \
865 UINT f_acc; \
866 UINT f_op23; \
867 UINT f_r2; \
868 unsigned int length;
b8a9943d 869#define EXTRACT_FMT_35_MULHI_A_CODE \
8e420152
DE		 870 length = 2; \
871 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
872 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
873 f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
874 f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
875 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
876
b8a9943d 877#define EXTRACT_FMT_36_MV_VARS \
8e420152
DE		 878 /* Instruction fields. */ \
879 UINT f_op1; \
880 UINT f_r1; \
881 UINT f_op2; \
882 UINT f_r2; \
883 unsigned int length;
b8a9943d 884#define EXTRACT_FMT_36_MV_CODE \
8e420152
DE		 885 length = 2; \
886 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
887 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
888 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
889 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
890
b8a9943d 891#define EXTRACT_FMT_37_MVFACHI_A_VARS \
8e420152
DE		 892 /* Instruction fields. */ \
893 UINT f_op1; \
894 UINT f_r1; \
895 UINT f_op2; \
896 UINT f_accs; \
897 UINT f_op3; \
898 unsigned int length;
b8a9943d 899#define EXTRACT_FMT_37_MVFACHI_A_CODE \
8e420152
DE		 900 length = 2; \
901 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
902 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
903 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
904 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
905 f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
906
b8a9943d 907#define EXTRACT_FMT_38_MVFC_VARS \
8e420152
DE		 908 /* Instruction fields. */ \
909 UINT f_op1; \
910 UINT f_r1; \
911 UINT f_op2; \
912 UINT f_r2; \
913 unsigned int length;
b8a9943d 914#define EXTRACT_FMT_38_MVFC_CODE \
8e420152
DE		 915 length = 2; \
916 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
917 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
918 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
919 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
920
b8a9943d 921#define EXTRACT_FMT_39_MVTACHI_A_VARS \
8e420152
DE		 922 /* Instruction fields. */ \
923 UINT f_op1; \
924 UINT f_r1; \
925 UINT f_op2; \
926 UINT f_accs; \
927 UINT f_op3; \
928 unsigned int length;
b8a9943d 929#define EXTRACT_FMT_39_MVTACHI_A_CODE \
8e420152
DE		 930 length = 2; \
931 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
932 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
933 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
934 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
935 f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
936
b8a9943d 937#define EXTRACT_FMT_40_MVTC_VARS \
8e420152
DE		 938 /* Instruction fields. */ \
939 UINT f_op1; \
940 UINT f_r1; \
941 UINT f_op2; \
942 UINT f_r2; \
943 unsigned int length;
b8a9943d 944#define EXTRACT_FMT_40_MVTC_CODE \
8e420152
DE		 945 length = 2; \
946 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
947 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
948 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
949 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
950
b8a9943d 951#define EXTRACT_FMT_41_NOP_VARS \
8e420152
DE		 952 /* Instruction fields. */ \
953 UINT f_op1; \
954 UINT f_r1; \
955 UINT f_op2; \
956 UINT f_r2; \
957 unsigned int length;
b8a9943d 958#define EXTRACT_FMT_41_NOP_CODE \
8e420152
DE		 959 length = 2; \
960 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
961 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
962 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
963 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
964
b8a9943d 965#define EXTRACT_FMT_42_RAC_A_VARS \
8e420152
DE		 966 /* Instruction fields. */ \
967 UINT f_op1; \
968 UINT f_r1; \
969 UINT f_op2; \
b8a9943d
DE		 970 UINT f_accs; \
971 UINT f_op3; \
8e420152 972 unsigned int length;
b8a9943d 973#define EXTRACT_FMT_42_RAC_A_CODE \
8e420152
DE		 974 length = 2; \
975 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
976 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
977 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
b8a9943d
DE		 978 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
979 f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
8e420152 980
b8a9943d 981#define EXTRACT_FMT_43_RTE_VARS \
8e420152
DE		 982 /* Instruction fields. */ \
983 UINT f_op1; \
984 UINT f_r1; \
985 UINT f_op2; \
b8a9943d 986 UINT f_r2; \
8e420152 987 unsigned int length;
b8a9943d 988#define EXTRACT_FMT_43_RTE_CODE \
8e420152
DE		 989 length = 2; \
990 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
991 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
992 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
b8a9943d 993 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
8e420152 994
b8a9943d 995#define EXTRACT_FMT_44_SETH_VARS \
8e420152
DE		 996 /* Instruction fields. */ \
997 UINT f_op1; \
998 UINT f_r1; \
999 UINT f_op2; \
1000 UINT f_r2; \
1001 UINT f_hi16; \
1002 unsigned int length;
b8a9943d 1003#define EXTRACT_FMT_44_SETH_CODE \
8e420152
DE		 1004 length = 4; \
1005 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1006 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1007 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1008 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1009 f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1010
b8a9943d 1011#define EXTRACT_FMT_45_SLLI_VARS \
8e420152
DE		 1012 /* Instruction fields. */ \
1013 UINT f_op1; \
1014 UINT f_r1; \
1015 UINT f_shift_op2; \
1016 UINT f_uimm5; \
1017 unsigned int length;
b8a9943d 1018#define EXTRACT_FMT_45_SLLI_CODE \
8e420152
DE		 1019 length = 2; \
1020 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1021 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1022 f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
1023 f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
1024
b8a9943d 1025#define EXTRACT_FMT_46_ST_D_VARS \
8e420152
DE		 1026 /* Instruction fields. */ \
1027 UINT f_op1; \
1028 UINT f_r1; \
1029 UINT f_op2; \
1030 UINT f_r2; \
1031 int f_simm16; \
1032 unsigned int length;
b8a9943d 1033#define EXTRACT_FMT_46_ST_D_CODE \
8e420152
DE		 1034 length = 4; \
1035 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1036 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1037 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1038 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1039 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1040
b8a9943d 1041#define EXTRACT_FMT_47_TRAP_VARS \
8e420152
DE		 1042 /* Instruction fields. */ \
1043 UINT f_op1; \
1044 UINT f_r1; \
1045 UINT f_op2; \
1046 UINT f_uimm4; \
1047 unsigned int length;
b8a9943d 1048#define EXTRACT_FMT_47_TRAP_CODE \
8e420152
DE		 1049 length = 2; \
1050 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1051 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1052 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1053 f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1054
b8a9943d
DE		 1055#define EXTRACT_FMT_48_SATB_VARS \
1056 /* Instruction fields. */ \
1057 UINT f_op1; \
1058 UINT f_r1; \
1059 UINT f_op2; \
1060 UINT f_r2; \
1061 UINT f_uimm16; \
1062 unsigned int length;
1063#define EXTRACT_FMT_48_SATB_CODE \
1064 length = 4; \
1065 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1066 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1067 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1068 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1069 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1070
1071#define EXTRACT_FMT_49_SAT_VARS \
8e420152
DE		 1072 /* Instruction fields. */ \
1073 UINT f_op1; \
1074 UINT f_r1; \
1075 UINT f_op2; \
1076 UINT f_r2; \
1077 UINT f_uimm16; \
1078 unsigned int length;
b8a9943d 1079#define EXTRACT_FMT_49_SAT_CODE \
8e420152
DE		 1080 length = 4; \
1081 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1082 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1083 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1084 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1085 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1086
b8a9943d 1087#define EXTRACT_FMT_50_SADD_VARS \
8e420152
DE		 1088 /* Instruction fields. */ \
1089 UINT f_op1; \
1090 UINT f_r1; \
1091 UINT f_op2; \
1092 UINT f_r2; \
1093 unsigned int length;
b8a9943d 1094#define EXTRACT_FMT_50_SADD_CODE \
8e420152
DE		 1095 length = 2; \
1096 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1097 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1098 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1099 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1100
b8a9943d 1101#define EXTRACT_FMT_51_MACWU1_VARS \
8e420152
DE		 1102 /* Instruction fields. */ \
1103 UINT f_op1; \
1104 UINT f_r1; \
1105 UINT f_op2; \
1106 UINT f_r2; \
1107 unsigned int length;
b8a9943d 1108#define EXTRACT_FMT_51_MACWU1_CODE \
8e420152
DE		 1109 length = 2; \
1110 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1111 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1112 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1113 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1114
b8a9943d 1115#define EXTRACT_FMT_52_MSBLO_VARS \
8e420152
DE		 1116 /* Instruction fields. */ \
1117 UINT f_op1; \
1118 UINT f_r1; \
1119 UINT f_op2; \
1120 UINT f_r2; \
1121 unsigned int length;
b8a9943d 1122#define EXTRACT_FMT_52_MSBLO_CODE \
8e420152
DE		 1123 length = 2; \
1124 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1125 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1126 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1127 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1128
b8a9943d 1129#define EXTRACT_FMT_53_SC_VARS \
8e420152
DE		 1130 /* Instruction fields. */ \
1131 UINT f_op1; \
1132 UINT f_r1; \
1133 UINT f_op2; \
1134 UINT f_r2; \
1135 unsigned int length;
b8a9943d 1136#define EXTRACT_FMT_53_SC_CODE \
8e420152
DE		 1137 length = 2; \
1138 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1139 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1140 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1141 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1142
1143/* Fetched input values of an instruction. */
1144
1145struct parallel_exec {
1146 union {
1147 struct { /* e.g. add $dr,$sr */
1148 SI dr;
1149 SI sr;
1150 } fmt_0_add;
1151 struct { /* e.g. add3 $dr,$sr,#$slo16 */
1152 HI slo16;
1153 SI sr;
1154 } fmt_1_add3;
1155 struct { /* e.g. and3 $dr,$sr,#$uimm16 */
1156 SI sr;
1157 USI uimm16;
1158 } fmt_2_and3;
1159 struct { /* e.g. or3 $dr,$sr,#$ulo16 */
1160 SI sr;
1161 UHI ulo16;
1162 } fmt_3_or3;
1163 struct { /* e.g. addi $dr,#$simm8 */
1164 SI dr;
1165 SI simm8;
1166 } fmt_4_addi;
1167 struct { /* e.g. addv3 $dr,$sr,#$simm16 */
1168 SI simm16;
1169 SI sr;
1170 } fmt_5_addv3;
1171 struct { /* e.g. addx $dr,$sr */
1172 UBI condbit;
1173 SI dr;
1174 SI sr;
1175 } fmt_6_addx;
1176 struct { /* e.g. bc $disp8 */
1177 UBI condbit;
1178 IADDR disp8;
1179 } fmt_7_bc8;
1180 struct { /* e.g. bc $disp24 */
1181 UBI condbit;
1182 IADDR disp24;
1183 } fmt_8_bc24;
1184 struct { /* e.g. beq $src1,$src2,$disp16 */
1185 IADDR disp16;
1186 SI src1;
1187 SI src2;
1188 } fmt_9_beq;
1189 struct { /* e.g. beqz $src2,$disp16 */
1190 IADDR disp16;
1191 SI src2;
1192 } fmt_10_beqz;
1193 struct { /* e.g. bl $disp8 */
1194 IADDR disp8;
1195 USI pc;
1196 } fmt_11_bl8;
1197 struct { /* e.g. bl $disp24 */
1198 IADDR disp24;
1199 USI pc;
1200 } fmt_12_bl24;
1201 struct { /* e.g. bcl $disp8 */
1202 UBI condbit;
1203 IADDR disp8;
1204 USI pc;
1205 } fmt_13_bcl8;
1206 struct { /* e.g. bcl $disp24 */
1207 UBI condbit;
1208 IADDR disp24;
1209 USI pc;
1210 } fmt_14_bcl24;
1211 struct { /* e.g. bra $disp8 */
1212 IADDR disp8;
1213 } fmt_15_bra8;
1214 struct { /* e.g. bra $disp24 */
1215 IADDR disp24;
1216 } fmt_16_bra24;
1217 struct { /* e.g. cmp $src1,$src2 */
1218 SI src1;
1219 SI src2;
1220 } fmt_17_cmp;
1221 struct { /* e.g. cmpi $src2,#$simm16 */
1222 SI simm16;
1223 SI src2;
1224 } fmt_18_cmpi;
1225 struct { /* e.g. cmpui $src2,#$uimm16 */
1226 SI src2;
1227 USI uimm16;
1228 } fmt_19_cmpui;
1229 struct { /* e.g. cmpz $src2 */
1230 SI src2;
1231 } fmt_20_cmpz;
1232 struct { /* e.g. div $dr,$sr */
1233 SI dr;
1234 SI sr;
1235 } fmt_21_div;
1236 struct { /* e.g. jc $sr */
1237 UBI condbit;
1238 SI sr;
1239 } fmt_22_jc;
1240 struct { /* e.g. jl $sr */
1241 USI pc;
1242 SI sr;
1243 } fmt_23_jl;
1244 struct { /* e.g. jmp $sr */
1245 SI sr;
1246 } fmt_24_jmp;
1247 struct { /* e.g. ld $dr,@$sr */
b8a9943d 1248 UQI h_memory_sr;
8e420152
DE		 1249 SI sr;
1250 } fmt_25_ld;
1251 struct { /* e.g. ld $dr,@($slo16,$sr) */
b8a9943d 1252 UQI h_memory_add_WI_sr_slo16;
8e420152
DE		 1253 HI slo16;
1254 SI sr;
1255 } fmt_26_ld_d;
1256 struct { /* e.g. ldb $dr,@$sr */
b8a9943d 1257 UQI h_memory_sr;
8e420152
DE		 1258 SI sr;
1259 } fmt_27_ldb;
1260 struct { /* e.g. ldb $dr,@($slo16,$sr) */
b8a9943d 1261 UQI h_memory_add_WI_sr_slo16;
8e420152
DE		 1262 HI slo16;
1263 SI sr;
1264 } fmt_28_ldb_d;
1265 struct { /* e.g. ldh $dr,@$sr */
b8a9943d 1266 UQI h_memory_sr;
8e420152
DE		 1267 SI sr;
1268 } fmt_29_ldh;
1269 struct { /* e.g. ldh $dr,@($slo16,$sr) */
b8a9943d 1270 UQI h_memory_add_WI_sr_slo16;
8e420152
DE		 1271 HI slo16;
1272 SI sr;
1273 } fmt_30_ldh_d;
1274 struct { /* e.g. ld24 $dr,#$uimm24 */
1275 ADDR uimm24;
1276 } fmt_31_ld24;
1277 struct { /* e.g. ldi $dr,#$simm8 */
1278 SI simm8;
1279 } fmt_32_ldi8;
1280 struct { /* e.g. ldi $dr,$slo16 */
1281 HI slo16;
1282 } fmt_33_ldi16;
8e420152
DE		 1283 struct { /* e.g. machi $src1,$src2,$acc */
1284 DI acc;
1285 SI src1;
1286 SI src2;
b8a9943d 1287 } fmt_34_machi_a;
8e420152
DE		 1288 struct { /* e.g. mulhi $src1,$src2,$acc */
1289 SI src1;
1290 SI src2;
b8a9943d 1291 } fmt_35_mulhi_a;
8e420152
DE		 1292 struct { /* e.g. mv $dr,$sr */
1293 SI sr;
b8a9943d 1294 } fmt_36_mv;
8e420152
DE		 1295 struct { /* e.g. mvfachi $dr,$accs */
1296 DI accs;
b8a9943d 1297 } fmt_37_mvfachi_a;
8e420152
DE		 1298 struct { /* e.g. mvfc $dr,$scr */
1299 SI scr;
b8a9943d 1300 } fmt_38_mvfc;
8e420152
DE		 1301 struct { /* e.g. mvtachi $src1,$accs */
1302 DI accs;
1303 SI src1;
b8a9943d 1304 } fmt_39_mvtachi_a;
8e420152
DE		 1305 struct { /* e.g. mvtc $sr,$dcr */
1306 SI sr;
b8a9943d 1307 } fmt_40_mvtc;
8e420152
DE		 1308 struct { /* e.g. nop */
1309 int empty;
b8a9943d 1310 } fmt_41_nop;
8e420152
DE		 1311 struct { /* e.g. rac $accs */
1312 DI accs;
b8a9943d
DE		 1313 } fmt_42_rac_a;
1314 struct { /* e.g. rte */
1315 UBI h_bcond_0;
1316 UBI h_bie_0;
1317 SI h_bpc_0;
1318 UBI h_bsm_0;
1319 } fmt_43_rte;
1320 struct { /* e.g. seth $dr,#$hi16 */
8e420152 1321 UHI hi16;
b8a9943d 1322 } fmt_44_seth;
8e420152
DE		 1323 struct { /* e.g. slli $dr,#$uimm5 */
1324 SI dr;
1325 USI uimm5;
b8a9943d 1326 } fmt_45_slli;
8e420152
DE		 1327 struct { /* e.g. st $src1,@($slo16,$src2) */
1328 HI slo16;
1329 SI src1;
1330 SI src2;
b8a9943d 1331 } fmt_46_st_d;
8e420152
DE		 1332 struct { /* e.g. trap #$uimm4 */
1333 USI uimm4;
b8a9943d 1334 } fmt_47_trap;
8e420152 1335 struct { /* e.g. satb $dr,$src2 */
b8a9943d
DE		 1336 SI src2;
1337 } fmt_48_satb;
1338 struct { /* e.g. sat $dr,$src2 */
1339 UBI condbit;
1340 SI src2;
1341 } fmt_49_sat;
8e420152 1342 struct { /* e.g. sadd */
b8a9943d
DE		 1343 DI h_accums_0;
1344 DI h_accums_1;
1345 } fmt_50_sadd;
8e420152 1346 struct { /* e.g. macwu1 $src1,$src2 */
b8a9943d
DE		 1347 DI h_accums_1;
1348 SI src1;
1349 SI src2;
1350 } fmt_51_macwu1;
1351 struct { /* e.g. msblo $src1,$src2 */
1352 DI accum;
8e420152
DE		 1353 SI src1;
1354 SI src2;
b8a9943d 1355 } fmt_52_msblo;
8e420152
DE		 1356 struct { /* e.g. sc */
1357 UBI condbit;
b8a9943d 1358 } fmt_53_sc;
8e420152
DE		 1359 } operands;
1360};
1361
1362#endif /* CPU_M32RX_H */
GDB Binutils - Deliverables
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