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* cpu.h,extract.c: Regenerate. pc-rel calcs done on f_dispNN now.
[deliverable/binutils-gdb.git] / sim / m32r / cpux.h
CommitLineData
8e420152
DE		 1/* CPU family header for m32rx.
2
7422fa0c 3THIS FILE IS MACHINE GENERATED WITH CGEN.
b8a9943d 4
8e420152
DE		 5Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
6
7This file is part of the GNU Simulators.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#ifndef CPU_M32RX_H
26#define CPU_M32RX_H
27
28/* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30#define MAX_LIW_INSNS 2
31
32/* Maximum number of instructions that can be executed in parallel. */
33#define MAX_PARALLEL_INSNS 2
34
35/* CPU state information. */
36typedef struct {
37 /* Hardware elements. */
38 struct {
39 /* program counter */
40 USI h_pc;
41#define GET_H_PC() CPU (h_pc)
42#define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
44 SI h_gr[16];
45#define GET_H_GR(a1) CPU (h_gr)[a1]
46#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
7422fa0c 48 USI h_cr[16];
8e420152
DE		 49#define GET_H_CR(a1) CPU (h_cr)[a1]
50#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
51 /* accumulator */
52 DI h_accum;
53#define GET_H_ACCUM() CPU (h_accum)
54#define SET_H_ACCUM(x) (CPU (h_accum) = (x))
b8a9943d 55/* start-sanitize-m32rx */
8e420152
DE		 56 /* accumulators */
57 DI h_accums[2];
b8a9943d 58/* end-sanitize-m32rx */
8e420152
DE		 59#define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
60#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
8e420152
DE		 61 /* condition bit */
62 UBI h_cond;
63#define GET_H_COND() CPU (h_cond)
64#define SET_H_COND(x) (CPU (h_cond) = (x))
65 /* sm */
66 UBI h_sm;
67#define GET_H_SM() CPU (h_sm)
68#define SET_H_SM(x) (CPU (h_sm) = (x))
69 /* bsm */
70 UBI h_bsm;
71#define GET_H_BSM() CPU (h_bsm)
72#define SET_H_BSM(x) (CPU (h_bsm) = (x))
73 /* ie */
74 UBI h_ie;
75#define GET_H_IE() CPU (h_ie)
76#define SET_H_IE(x) (CPU (h_ie) = (x))
77 /* bie */
78 UBI h_bie;
79#define GET_H_BIE() CPU (h_bie)
80#define SET_H_BIE(x) (CPU (h_bie) = (x))
81 /* bcond */
82 UBI h_bcond;
83#define GET_H_BCOND() CPU (h_bcond)
84#define SET_H_BCOND(x) (CPU (h_bcond) = (x))
85 /* bpc */
86 SI h_bpc;
87#define GET_H_BPC() CPU (h_bpc)
88#define SET_H_BPC(x) (CPU (h_bpc) = (x))
cab58155
DE		 89 /* lock */
90 UBI h_lock;
91#define GET_H_LOCK() CPU (h_lock)
92#define SET_H_LOCK(x) (CPU (h_lock) = (x))
8e420152
DE		 93 } hardware;
94#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
95 /* CPU profiling state information. */
96 struct {
97 /* general registers */
98 unsigned long h_gr;
99 } profile;
100#define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
101} M32RX_CPU_DATA;
102
cab58155
DE		 103USI m32rx_h_pc_get (SIM_CPU *);
104void m32rx_h_pc_set (SIM_CPU *, USI);
105SI m32rx_h_gr_get (SIM_CPU *, UINT);
106void m32rx_h_gr_set (SIM_CPU *, UINT, SI);
107USI m32rx_h_cr_get (SIM_CPU *, UINT);
108void m32rx_h_cr_set (SIM_CPU *, UINT, USI);
109DI m32rx_h_accum_get (SIM_CPU *);
110void m32rx_h_accum_set (SIM_CPU *, DI);
111DI m32rx_h_accums_get (SIM_CPU *, UINT);
112void m32rx_h_accums_set (SIM_CPU *, UINT, DI);
cab58155
DE		 113UBI m32rx_h_cond_get (SIM_CPU *);
114void m32rx_h_cond_set (SIM_CPU *, UBI);
115UBI m32rx_h_sm_get (SIM_CPU *);
116void m32rx_h_sm_set (SIM_CPU *, UBI);
117UBI m32rx_h_bsm_get (SIM_CPU *);
118void m32rx_h_bsm_set (SIM_CPU *, UBI);
119UBI m32rx_h_ie_get (SIM_CPU *);
120void m32rx_h_ie_set (SIM_CPU *, UBI);
121UBI m32rx_h_bie_get (SIM_CPU *);
122void m32rx_h_bie_set (SIM_CPU *, UBI);
123UBI m32rx_h_bcond_get (SIM_CPU *);
124void m32rx_h_bcond_set (SIM_CPU *, UBI);
125SI m32rx_h_bpc_get (SIM_CPU *);
126void m32rx_h_bpc_set (SIM_CPU *, SI);
127UBI m32rx_h_lock_get (SIM_CPU *);
128void m32rx_h_lock_set (SIM_CPU *, UBI);
7422fa0c
DE		 129
130/* These must be hand-written. */
131extern CPUREG_FETCH_FN m32rx_fetch_register;
132extern CPUREG_STORE_FN m32rx_store_register;
8e420152
DE		 133
134/* The ARGBUF struct. */
135struct argbuf {
136 /* These are the baseclass definitions. */
137 unsigned int length;
138 PCADDR addr;
7422fa0c 139 const IDESC *idesc;
8e420152 140 /* cpu specific data follows */
7422fa0c 141 insn_t insn;
8e420152
DE		 142 union {
143 struct { /* e.g. add $dr,$sr */
144 UINT f_r1;
145 UINT f_r2;
7422fa0c
DE		 146 } fmt_add;
147 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
8e420152
DE		 148 UINT f_r1;
149 UINT f_r2;
150 HI f_simm16;
7422fa0c
DE		 151 } fmt_add3;
152 struct { /* e.g. and3 $dr,$sr,$uimm16 */
8e420152
DE		 153 UINT f_r1;
154 UINT f_r2;
155 USI f_uimm16;
7422fa0c
DE		 156 } fmt_and3;
157 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
8e420152
DE		 158 UINT f_r1;
159 UINT f_r2;
160 UHI f_uimm16;
7422fa0c
DE		 161 } fmt_or3;
162 struct { /* e.g. addi $dr,$simm8 */
8e420152
DE		 163 UINT f_r1;
164 SI f_simm8;
7422fa0c 165 } fmt_addi;
cab58155
DE		 166 struct { /* e.g. addv $dr,$sr */
167 UINT f_r1;
168 UINT f_r2;
7422fa0c
DE		 169 } fmt_addv;
170 struct { /* e.g. addv3 $dr,$sr,$simm16 */
8e420152
DE		 171 UINT f_r1;
172 UINT f_r2;
173 SI f_simm16;
7422fa0c 174 } fmt_addv3;
8e420152
DE		 175 struct { /* e.g. addx $dr,$sr */
176 UINT f_r1;
177 UINT f_r2;
7422fa0c
DE		 178 } fmt_addx;
179 struct { /* e.g. bc.s $disp8 */
8e420152 180 IADDR f_disp8;
7422fa0c
DE		 181 } fmt_bc8;
182 struct { /* e.g. bc.l $disp24 */
8e420152 183 IADDR f_disp24;
7422fa0c 184 } fmt_bc24;
8e420152
DE		 185 struct { /* e.g. beq $src1,$src2,$disp16 */
186 UINT f_r1;
187 UINT f_r2;
188 IADDR f_disp16;
7422fa0c 189 } fmt_beq;
8e420152
DE		 190 struct { /* e.g. beqz $src2,$disp16 */
191 UINT f_r2;
192 IADDR f_disp16;
7422fa0c
DE		 193 } fmt_beqz;
194 struct { /* e.g. bl.s $disp8 */
8e420152 195 IADDR f_disp8;
7422fa0c
DE		 196 } fmt_bl8;
197 struct { /* e.g. bl.l $disp24 */
8e420152 198 IADDR f_disp24;
7422fa0c
DE		 199 } fmt_bl24;
200 struct { /* e.g. bcl.s $disp8 */
8e420152 201 IADDR f_disp8;
7422fa0c
DE		 202 } fmt_bcl8;
203 struct { /* e.g. bcl.l $disp24 */
8e420152 204 IADDR f_disp24;
7422fa0c
DE		 205 } fmt_bcl24;
206 struct { /* e.g. bra.s $disp8 */
8e420152 207 IADDR f_disp8;
7422fa0c
DE		 208 } fmt_bra8;
209 struct { /* e.g. bra.l $disp24 */
8e420152 210 IADDR f_disp24;
7422fa0c 211 } fmt_bra24;
8e420152
DE		 212 struct { /* e.g. cmp $src1,$src2 */
213 UINT f_r1;
214 UINT f_r2;
7422fa0c
DE		 215 } fmt_cmp;
216 struct { /* e.g. cmpi $src2,$simm16 */
8e420152
DE		 217 UINT f_r2;
218 SI f_simm16;
7422fa0c 219 } fmt_cmpi;
8e420152
DE		 220 struct { /* e.g. cmpz $src2 */
221 UINT f_r2;
7422fa0c 222 } fmt_cmpz;
8e420152
DE		 223 struct { /* e.g. div $dr,$sr */
224 UINT f_r1;
225 UINT f_r2;
7422fa0c 226 } fmt_div;
8e420152
DE		 227 struct { /* e.g. jc $sr */
228 UINT f_r2;
7422fa0c 229 } fmt_jc;
8e420152
DE		 230 struct { /* e.g. jl $sr */
231 UINT f_r2;
7422fa0c 232 } fmt_jl;
8e420152
DE		 233 struct { /* e.g. jmp $sr */
234 UINT f_r2;
7422fa0c 235 } fmt_jmp;
8e420152
DE		 236 struct { /* e.g. ld $dr,@$sr */
237 UINT f_r1;
238 UINT f_r2;
7422fa0c 239 } fmt_ld;
8e420152
DE		 240 struct { /* e.g. ld $dr,@($slo16,$sr) */
241 UINT f_r1;
242 UINT f_r2;
243 HI f_simm16;
7422fa0c 244 } fmt_ld_d;
8e420152
DE		 245 struct { /* e.g. ldb $dr,@$sr */
246 UINT f_r1;
247 UINT f_r2;
7422fa0c 248 } fmt_ldb;
8e420152
DE		 249 struct { /* e.g. ldb $dr,@($slo16,$sr) */
250 UINT f_r1;
251 UINT f_r2;
252 HI f_simm16;
7422fa0c 253 } fmt_ldb_d;
8e420152
DE		 254 struct { /* e.g. ldh $dr,@$sr */
255 UINT f_r1;
256 UINT f_r2;
7422fa0c 257 } fmt_ldh;
8e420152
DE		 258 struct { /* e.g. ldh $dr,@($slo16,$sr) */
259 UINT f_r1;
260 UINT f_r2;
261 HI f_simm16;
7422fa0c 262 } fmt_ldh_d;
cab58155
DE		 263 struct { /* e.g. ld $dr,@$sr+ */
264 UINT f_r1;
265 UINT f_r2;
7422fa0c
DE		 266 } fmt_ld_plus;
267 struct { /* e.g. ld24 $dr,$uimm24 */
8e420152
DE		 268 UINT f_r1;
269 ADDR f_uimm24;
7422fa0c
DE		 270 } fmt_ld24;
271 struct { /* e.g. ldi8 $dr,$simm8 */
8e420152
DE		 272 UINT f_r1;
273 SI f_simm8;
7422fa0c
DE		 274 } fmt_ldi8;
275 struct { /* e.g. ldi16 $dr,$hash$slo16 */
8e420152
DE		 276 UINT f_r1;
277 HI f_simm16;
7422fa0c 278 } fmt_ldi16;
cab58155
DE		 279 struct { /* e.g. lock $dr,@$sr */
280 UINT f_r1;
281 UINT f_r2;
7422fa0c 282 } fmt_lock;
8e420152
DE		 283 struct { /* e.g. machi $src1,$src2,$acc */
284 UINT f_r1;
285 UINT f_acc;
286 UINT f_r2;
7422fa0c
DE		 287 } fmt_machi_a;
288 struct { /* e.g. macwhi $src1,$src2 */
289 UINT f_r1;
290 UINT f_r2;
291 } fmt_macwhi;
8e420152
DE		 292 struct { /* e.g. mulhi $src1,$src2,$acc */
293 UINT f_r1;
294 UINT f_acc;
295 UINT f_r2;
7422fa0c
DE		 296 } fmt_mulhi_a;
297 struct { /* e.g. mulwhi $src1,$src2 */
298 UINT f_r1;
299 UINT f_r2;
300 } fmt_mulwhi;
8e420152
DE		 301 struct { /* e.g. mv $dr,$sr */
302 UINT f_r1;
303 UINT f_r2;
7422fa0c 304 } fmt_mv;
8e420152
DE		 305 struct { /* e.g. mvfachi $dr,$accs */
306 UINT f_r1;
307 UINT f_accs;
7422fa0c 308 } fmt_mvfachi_a;
8e420152
DE		 309 struct { /* e.g. mvfc $dr,$scr */
310 UINT f_r1;
311 UINT f_r2;
7422fa0c 312 } fmt_mvfc;
8e420152
DE		 313 struct { /* e.g. mvtachi $src1,$accs */
314 UINT f_r1;
315 UINT f_accs;
7422fa0c 316 } fmt_mvtachi_a;
8e420152
DE		 317 struct { /* e.g. mvtc $sr,$dcr */
318 UINT f_r1;
319 UINT f_r2;
7422fa0c 320 } fmt_mvtc;
8e420152
DE		 321 struct { /* e.g. nop */
322 int empty;
7422fa0c
DE		 323 } fmt_nop;
324 struct { /* e.g. rac $accd,$accs,$imm1 */
e0bd6e18
DE		 325 UINT f_accd;
326 UINT f_accs;
327 USI f_imm1;
7422fa0c 328 } fmt_rac_dsi;
b8a9943d
DE		 329 struct { /* e.g. rte */
330 int empty;
7422fa0c
DE		 331 } fmt_rte;
332 struct { /* e.g. seth $dr,$hash$hi16 */
8e420152
DE		 333 UINT f_r1;
334 UHI f_hi16;
7422fa0c
DE		 335 } fmt_seth;
336 struct { /* e.g. sll3 $dr,$sr,$simm16 */
cab58155
DE		 337 UINT f_r1;
338 UINT f_r2;
339 SI f_simm16;
7422fa0c
DE		 340 } fmt_sll3;
341 struct { /* e.g. slli $dr,$uimm5 */
8e420152
DE		 342 UINT f_r1;
343 USI f_uimm5;
7422fa0c 344 } fmt_slli;
cab58155
DE		 345 struct { /* e.g. st $src1,@$src2 */
346 UINT f_r1;
347 UINT f_r2;
7422fa0c 348 } fmt_st;
8e420152
DE		 349 struct { /* e.g. st $src1,@($slo16,$src2) */
350 UINT f_r1;
351 UINT f_r2;
352 HI f_simm16;
7422fa0c 353 } fmt_st_d;
cab58155
DE		 354 struct { /* e.g. stb $src1,@$src2 */
355 UINT f_r1;
356 UINT f_r2;
7422fa0c 357 } fmt_stb;
cab58155
DE		 358 struct { /* e.g. stb $src1,@($slo16,$src2) */
359 UINT f_r1;
360 UINT f_r2;
361 HI f_simm16;
7422fa0c 362 } fmt_stb_d;
cab58155
DE		 363 struct { /* e.g. sth $src1,@$src2 */
364 UINT f_r1;
365 UINT f_r2;
7422fa0c 366 } fmt_sth;
cab58155
DE		 367 struct { /* e.g. sth $src1,@($slo16,$src2) */
368 UINT f_r1;
369 UINT f_r2;
370 HI f_simm16;
7422fa0c 371 } fmt_sth_d;
cab58155
DE		 372 struct { /* e.g. st $src1,@+$src2 */
373 UINT f_r1;
374 UINT f_r2;
7422fa0c
DE		 375 } fmt_st_plus;
376 struct { /* e.g. trap $uimm4 */
8e420152 377 USI f_uimm4;
7422fa0c 378 } fmt_trap;
cab58155 379 struct { /* e.g. unlock $src1,@$src2 */
8e420152
DE		 380 UINT f_r1;
381 UINT f_r2;
7422fa0c 382 } fmt_unlock;
cab58155 383 struct { /* e.g. satb $dr,$sr */
b8a9943d 384 UINT f_r1;
8e420152 385 UINT f_r2;
7422fa0c 386 } fmt_satb;
cab58155
DE		 387 struct { /* e.g. sat $dr,$sr */
388 UINT f_r1;
389 UINT f_r2;
7422fa0c 390 } fmt_sat;
8e420152
DE		 391 struct { /* e.g. sadd */
392 int empty;
7422fa0c 393 } fmt_sadd;
8e420152
DE		 394 struct { /* e.g. macwu1 $src1,$src2 */
395 UINT f_r1;
396 UINT f_r2;
7422fa0c 397 } fmt_macwu1;
cab58155
DE		 398 struct { /* e.g. mulwu1 $src1,$src2 */
399 UINT f_r1;
400 UINT f_r2;
7422fa0c 401 } fmt_mulwu1;
8e420152
DE		 402 struct { /* e.g. sc */
403 int empty;
7422fa0c 404 } fmt_sc;
8e420152
DE		 405 } fields;
406#if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
407 unsigned long h_gr_get;
408 unsigned long h_gr_set;
409#endif
410};
411
412/* A cached insn.
cab58155
DE		 413 This is currently also used in the non-scache case. In this situation we
414 assume the cache size is 1, and do a few things a little differently. */
415/* FIXME: non-scache version to be redone. */
8e420152
DE		 416
417struct scache {
418 IADDR next;
419 union {
420#if ! WITH_SEM_SWITCH_FULL
7422fa0c 421 SEMANTIC_FN *sem_full;
8e420152
DE		 422#endif
423#if ! WITH_SEM_SWITCH_FAST
7422fa0c 424 SEMANTIC_FN *sem_fast;
8e420152 425#endif
8e420152
DE		 426#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
427#ifdef __GNUC__
428 void *sem_case;
429#else
430 int sem_case;
431#endif
432#endif
433 } semantic;
434 struct argbuf argbuf;
435};
436
437/* Macros to simplify extraction, reading and semantic code.
438 These define and assign the local vars that contain the insn's fields. */
439
7422fa0c 440#define EXTRACT_FMT_ADD_VARS \
8e420152
DE		 441 /* Instruction fields. */ \
442 UINT f_op1; \
443 UINT f_r1; \
444 UINT f_op2; \
445 UINT f_r2; \
446 unsigned int length;
7422fa0c 447#define EXTRACT_FMT_ADD_CODE \
8e420152
DE		 448 length = 2; \
449 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
450 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
451 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
452 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
453
7422fa0c 454#define EXTRACT_FMT_ADD3_VARS \
8e420152
DE		 455 /* Instruction fields. */ \
456 UINT f_op1; \
457 UINT f_r1; \
458 UINT f_op2; \
459 UINT f_r2; \
460 int f_simm16; \
461 unsigned int length;
7422fa0c 462#define EXTRACT_FMT_ADD3_CODE \
8e420152
DE		 463 length = 4; \
464 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
465 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
466 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
467 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
468 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
469
7422fa0c 470#define EXTRACT_FMT_AND3_VARS \
8e420152
DE		 471 /* Instruction fields. */ \
472 UINT f_op1; \
473 UINT f_r1; \
474 UINT f_op2; \
475 UINT f_r2; \
476 UINT f_uimm16; \
477 unsigned int length;
7422fa0c 478#define EXTRACT_FMT_AND3_CODE \
8e420152
DE		 479 length = 4; \
480 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
481 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
482 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
483 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
484 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
485
7422fa0c 486#define EXTRACT_FMT_OR3_VARS \
8e420152
DE		 487 /* Instruction fields. */ \
488 UINT f_op1; \
489 UINT f_r1; \
490 UINT f_op2; \
491 UINT f_r2; \
492 UINT f_uimm16; \
493 unsigned int length;
7422fa0c 494#define EXTRACT_FMT_OR3_CODE \
8e420152
DE		 495 length = 4; \
496 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
497 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
498 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
499 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
500 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
501
7422fa0c 502#define EXTRACT_FMT_ADDI_VARS \
8e420152
DE		 503 /* Instruction fields. */ \
504 UINT f_op1; \
505 UINT f_r1; \
506 int f_simm8; \
507 unsigned int length;
7422fa0c 508#define EXTRACT_FMT_ADDI_CODE \
8e420152
DE		 509 length = 2; \
510 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
511 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
512 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
513
7422fa0c 514#define EXTRACT_FMT_ADDV_VARS \
cab58155
DE		 515 /* Instruction fields. */ \
516 UINT f_op1; \
517 UINT f_r1; \
518 UINT f_op2; \
519 UINT f_r2; \
520 unsigned int length;
7422fa0c 521#define EXTRACT_FMT_ADDV_CODE \
cab58155
DE		 522 length = 2; \
523 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
524 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
525 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
526 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
527
7422fa0c 528#define EXTRACT_FMT_ADDV3_VARS \
8e420152
DE		 529 /* Instruction fields. */ \
530 UINT f_op1; \
531 UINT f_r1; \
532 UINT f_op2; \
533 UINT f_r2; \
534 int f_simm16; \
535 unsigned int length;
7422fa0c 536#define EXTRACT_FMT_ADDV3_CODE \
8e420152
DE		 537 length = 4; \
538 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
539 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
540 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
541 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
542 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
543
7422fa0c 544#define EXTRACT_FMT_ADDX_VARS \
8e420152
DE		 545 /* Instruction fields. */ \
546 UINT f_op1; \
547 UINT f_r1; \
548 UINT f_op2; \
549 UINT f_r2; \
550 unsigned int length;
7422fa0c 551#define EXTRACT_FMT_ADDX_CODE \
8e420152
DE		 552 length = 2; \
553 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
554 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
555 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
556 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
557
7422fa0c 558#define EXTRACT_FMT_BC8_VARS \
8e420152
DE		 559 /* Instruction fields. */ \
560 UINT f_op1; \
561 UINT f_r1; \
562 int f_disp8; \
563 unsigned int length;
7422fa0c 564#define EXTRACT_FMT_BC8_CODE \
8e420152
DE		 565 length = 2; \
566 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
567 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
7422fa0c 568 f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
8e420152 569
7422fa0c 570#define EXTRACT_FMT_BC24_VARS \
8e420152
DE		 571 /* Instruction fields. */ \
572 UINT f_op1; \
573 UINT f_r1; \
574 int f_disp24; \
575 unsigned int length;
7422fa0c 576#define EXTRACT_FMT_BC24_CODE \
8e420152
DE		 577 length = 4; \
578 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
579 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
7422fa0c 580 f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
8e420152 581
7422fa0c 582#define EXTRACT_FMT_BEQ_VARS \
8e420152
DE		 583 /* Instruction fields. */ \
584 UINT f_op1; \
585 UINT f_r1; \
586 UINT f_op2; \
587 UINT f_r2; \
588 int f_disp16; \
589 unsigned int length;
7422fa0c 590#define EXTRACT_FMT_BEQ_CODE \
8e420152
DE		 591 length = 4; \
592 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
593 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
594 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
595 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
7422fa0c 596 f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
8e420152 597
7422fa0c 598#define EXTRACT_FMT_BEQZ_VARS \
8e420152
DE		 599 /* Instruction fields. */ \
600 UINT f_op1; \
601 UINT f_r1; \
602 UINT f_op2; \
603 UINT f_r2; \
604 int f_disp16; \
605 unsigned int length;
7422fa0c 606#define EXTRACT_FMT_BEQZ_CODE \
8e420152
DE		 607 length = 4; \
608 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
609 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
610 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
611 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
7422fa0c 612 f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
8e420152 613
7422fa0c 614#define EXTRACT_FMT_BL8_VARS \
8e420152
DE		 615 /* Instruction fields. */ \
616 UINT f_op1; \
617 UINT f_r1; \
618 int f_disp8; \
619 unsigned int length;
7422fa0c 620#define EXTRACT_FMT_BL8_CODE \
8e420152
DE		 621 length = 2; \
622 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
623 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
7422fa0c 624 f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
8e420152 625
7422fa0c 626#define EXTRACT_FMT_BL24_VARS \
8e420152
DE		 627 /* Instruction fields. */ \
628 UINT f_op1; \
629 UINT f_r1; \
630 int f_disp24; \
631 unsigned int length;
7422fa0c 632#define EXTRACT_FMT_BL24_CODE \
8e420152
DE		 633 length = 4; \
634 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
635 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
7422fa0c 636 f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
8e420152 637
7422fa0c 638#define EXTRACT_FMT_BCL8_VARS \
8e420152
DE		 639 /* Instruction fields. */ \
640 UINT f_op1; \
641 UINT f_r1; \
642 int f_disp8; \
643 unsigned int length;
7422fa0c 644#define EXTRACT_FMT_BCL8_CODE \
8e420152
DE		 645 length = 2; \
646 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
647 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
7422fa0c 648 f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
8e420152 649
7422fa0c 650#define EXTRACT_FMT_BCL24_VARS \
8e420152
DE		 651 /* Instruction fields. */ \
652 UINT f_op1; \
653 UINT f_r1; \
654 int f_disp24; \
655 unsigned int length;
7422fa0c 656#define EXTRACT_FMT_BCL24_CODE \
8e420152
DE		 657 length = 4; \
658 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
659 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
7422fa0c 660 f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
8e420152 661
7422fa0c 662#define EXTRACT_FMT_BRA8_VARS \
8e420152
DE		 663 /* Instruction fields. */ \
664 UINT f_op1; \
665 UINT f_r1; \
666 int f_disp8; \
667 unsigned int length;
7422fa0c 668#define EXTRACT_FMT_BRA8_CODE \
8e420152
DE		 669 length = 2; \
670 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
671 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
7422fa0c 672 f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
8e420152 673
7422fa0c 674#define EXTRACT_FMT_BRA24_VARS \
8e420152
DE		 675 /* Instruction fields. */ \
676 UINT f_op1; \
677 UINT f_r1; \
678 int f_disp24; \
679 unsigned int length;
7422fa0c 680#define EXTRACT_FMT_BRA24_CODE \
8e420152
DE		 681 length = 4; \
682 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
683 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
7422fa0c 684 f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
8e420152 685
7422fa0c 686#define EXTRACT_FMT_CMP_VARS \
8e420152
DE		 687 /* Instruction fields. */ \
688 UINT f_op1; \
689 UINT f_r1; \
690 UINT f_op2; \
691 UINT f_r2; \
692 unsigned int length;
7422fa0c 693#define EXTRACT_FMT_CMP_CODE \
8e420152
DE		 694 length = 2; \
695 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
696 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
697 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
698 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
699
7422fa0c 700#define EXTRACT_FMT_CMPI_VARS \
8e420152
DE		 701 /* Instruction fields. */ \
702 UINT f_op1; \
703 UINT f_r1; \
704 UINT f_op2; \
705 UINT f_r2; \
706 int f_simm16; \
707 unsigned int length;
7422fa0c 708#define EXTRACT_FMT_CMPI_CODE \
8e420152
DE		 709 length = 4; \
710 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
711 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
712 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
713 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
714 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
715
7422fa0c 716#define EXTRACT_FMT_CMPZ_VARS \
8e420152
DE		 717 /* Instruction fields. */ \
718 UINT f_op1; \
719 UINT f_r1; \
720 UINT f_op2; \
721 UINT f_r2; \
8e420152 722 unsigned int length;
7422fa0c 723#define EXTRACT_FMT_CMPZ_CODE \
8e420152
DE		 724 length = 2; \
725 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
726 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
727 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
728 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
729
7422fa0c 730#define EXTRACT_FMT_DIV_VARS \
8e420152
DE		 731 /* Instruction fields. */ \
732 UINT f_op1; \
733 UINT f_r1; \
734 UINT f_op2; \
735 UINT f_r2; \
736 int f_simm16; \
737 unsigned int length;
7422fa0c 738#define EXTRACT_FMT_DIV_CODE \
8e420152
DE		 739 length = 4; \
740 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
741 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
742 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
743 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
744 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
745
7422fa0c 746#define EXTRACT_FMT_JC_VARS \
8e420152
DE		 747 /* Instruction fields. */ \
748 UINT f_op1; \
749 UINT f_r1; \
750 UINT f_op2; \
751 UINT f_r2; \
752 unsigned int length;
7422fa0c 753#define EXTRACT_FMT_JC_CODE \
8e420152
DE		 754 length = 2; \
755 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
756 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
757 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
758 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
759
7422fa0c 760#define EXTRACT_FMT_JL_VARS \
8e420152
DE		 761 /* Instruction fields. */ \
762 UINT f_op1; \
763 UINT f_r1; \
764 UINT f_op2; \
765 UINT f_r2; \
766 unsigned int length;
7422fa0c 767#define EXTRACT_FMT_JL_CODE \
8e420152
DE		 768 length = 2; \
769 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
770 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
771 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
772 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
773
7422fa0c 774#define EXTRACT_FMT_JMP_VARS \
8e420152
DE		 775 /* Instruction fields. */ \
776 UINT f_op1; \
777 UINT f_r1; \
778 UINT f_op2; \
779 UINT f_r2; \
780 unsigned int length;
7422fa0c 781#define EXTRACT_FMT_JMP_CODE \
8e420152
DE		 782 length = 2; \
783 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
784 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
785 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
786 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
787
7422fa0c 788#define EXTRACT_FMT_LD_VARS \
8e420152
DE		 789 /* Instruction fields. */ \
790 UINT f_op1; \
791 UINT f_r1; \
792 UINT f_op2; \
793 UINT f_r2; \
794 unsigned int length;
7422fa0c 795#define EXTRACT_FMT_LD_CODE \
8e420152
DE		 796 length = 2; \
797 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
798 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
799 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
800 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
801
7422fa0c 802#define EXTRACT_FMT_LD_D_VARS \
8e420152
DE		 803 /* Instruction fields. */ \
804 UINT f_op1; \
805 UINT f_r1; \
806 UINT f_op2; \
807 UINT f_r2; \
808 int f_simm16; \
809 unsigned int length;
7422fa0c 810#define EXTRACT_FMT_LD_D_CODE \
8e420152
DE		 811 length = 4; \
812 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
813 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
814 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
815 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
816 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
817
7422fa0c 818#define EXTRACT_FMT_LDB_VARS \
8e420152
DE		 819 /* Instruction fields. */ \
820 UINT f_op1; \
821 UINT f_r1; \
822 UINT f_op2; \
823 UINT f_r2; \
824 unsigned int length;
7422fa0c 825#define EXTRACT_FMT_LDB_CODE \
8e420152
DE		 826 length = 2; \
827 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
828 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
829 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
830 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
831
7422fa0c 832#define EXTRACT_FMT_LDB_D_VARS \
8e420152
DE		 833 /* Instruction fields. */ \
834 UINT f_op1; \
835 UINT f_r1; \
836 UINT f_op2; \
837 UINT f_r2; \
838 int f_simm16; \
839 unsigned int length;
7422fa0c 840#define EXTRACT_FMT_LDB_D_CODE \
8e420152
DE		 841 length = 4; \
842 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
843 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
844 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
845 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
846 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
847
7422fa0c 848#define EXTRACT_FMT_LDH_VARS \
8e420152
DE		 849 /* Instruction fields. */ \
850 UINT f_op1; \
851 UINT f_r1; \
852 UINT f_op2; \
853 UINT f_r2; \
854 unsigned int length;
7422fa0c 855#define EXTRACT_FMT_LDH_CODE \
8e420152
DE		 856 length = 2; \
857 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
858 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
859 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
860 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
861
7422fa0c 862#define EXTRACT_FMT_LDH_D_VARS \
8e420152
DE		 863 /* Instruction fields. */ \
864 UINT f_op1; \
865 UINT f_r1; \
866 UINT f_op2; \
867 UINT f_r2; \
868 int f_simm16; \
869 unsigned int length;
7422fa0c 870#define EXTRACT_FMT_LDH_D_CODE \
8e420152
DE		 871 length = 4; \
872 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
873 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
874 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
875 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
876 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
877
7422fa0c 878#define EXTRACT_FMT_LD_PLUS_VARS \
cab58155
DE		 879 /* Instruction fields. */ \
880 UINT f_op1; \
881 UINT f_r1; \
882 UINT f_op2; \
883 UINT f_r2; \
884 unsigned int length;
7422fa0c 885#define EXTRACT_FMT_LD_PLUS_CODE \
cab58155
DE		 886 length = 2; \
887 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
888 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
889 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
890 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
891
7422fa0c 892#define EXTRACT_FMT_LD24_VARS \
8e420152
DE		 893 /* Instruction fields. */ \
894 UINT f_op1; \
895 UINT f_r1; \
896 UINT f_uimm24; \
897 unsigned int length;
7422fa0c 898#define EXTRACT_FMT_LD24_CODE \
8e420152
DE		 899 length = 4; \
900 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
901 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
902 f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
903
7422fa0c 904#define EXTRACT_FMT_LDI8_VARS \
8e420152
DE		 905 /* Instruction fields. */ \
906 UINT f_op1; \
907 UINT f_r1; \
908 int f_simm8; \
909 unsigned int length;
7422fa0c 910#define EXTRACT_FMT_LDI8_CODE \
8e420152
DE		 911 length = 2; \
912 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
913 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
914 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
915
7422fa0c 916#define EXTRACT_FMT_LDI16_VARS \
8e420152
DE		 917 /* Instruction fields. */ \
918 UINT f_op1; \
919 UINT f_r1; \
920 UINT f_op2; \
921 UINT f_r2; \
922 int f_simm16; \
923 unsigned int length;
7422fa0c 924#define EXTRACT_FMT_LDI16_CODE \
8e420152
DE		 925 length = 4; \
926 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
927 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
928 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
929 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
930 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
931
7422fa0c 932#define EXTRACT_FMT_LOCK_VARS \
cab58155
DE		 933 /* Instruction fields. */ \
934 UINT f_op1; \
935 UINT f_r1; \
936 UINT f_op2; \
937 UINT f_r2; \
938 unsigned int length;
7422fa0c 939#define EXTRACT_FMT_LOCK_CODE \
cab58155
DE		 940 length = 2; \
941 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
942 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
943 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
944 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
945
7422fa0c 946#define EXTRACT_FMT_MACHI_A_VARS \
8e420152
DE		 947 /* Instruction fields. */ \
948 UINT f_op1; \
949 UINT f_r1; \
950 UINT f_acc; \
951 UINT f_op23; \
952 UINT f_r2; \
953 unsigned int length;
7422fa0c 954#define EXTRACT_FMT_MACHI_A_CODE \
8e420152
DE		 955 length = 2; \
956 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
957 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
958 f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
959 f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
960 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
961
7422fa0c
DE		 962#define EXTRACT_FMT_MACWHI_VARS \
963 /* Instruction fields. */ \
964 UINT f_op1; \
965 UINT f_r1; \
966 UINT f_op2; \
967 UINT f_r2; \
968 unsigned int length;
969#define EXTRACT_FMT_MACWHI_CODE \
970 length = 2; \
971 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
972 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
973 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
974 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
975
976#define EXTRACT_FMT_MULHI_A_VARS \
8e420152
DE		 977 /* Instruction fields. */ \
978 UINT f_op1; \
979 UINT f_r1; \
980 UINT f_acc; \
981 UINT f_op23; \
982 UINT f_r2; \
983 unsigned int length;
7422fa0c 984#define EXTRACT_FMT_MULHI_A_CODE \
8e420152
DE		 985 length = 2; \
986 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
987 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
988 f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
989 f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
990 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
991
7422fa0c 992#define EXTRACT_FMT_MULWHI_VARS \
8e420152
DE		 993 /* Instruction fields. */ \
994 UINT f_op1; \
995 UINT f_r1; \
996 UINT f_op2; \
997 UINT f_r2; \
998 unsigned int length;
7422fa0c 999#define EXTRACT_FMT_MULWHI_CODE \
8e420152
DE		 1000 length = 2; \
1001 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1002 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1003 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1004 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1005
7422fa0c
DE		 1006#define EXTRACT_FMT_MV_VARS \
1007 /* Instruction fields. */ \
1008 UINT f_op1; \
1009 UINT f_r1; \
1010 UINT f_op2; \
1011 UINT f_r2; \
1012 unsigned int length;
1013#define EXTRACT_FMT_MV_CODE \
1014 length = 2; \
1015 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1016 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1017 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1018 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1019
1020#define EXTRACT_FMT_MVFACHI_A_VARS \
8e420152
DE		 1021 /* Instruction fields. */ \
1022 UINT f_op1; \
1023 UINT f_r1; \
1024 UINT f_op2; \
1025 UINT f_accs; \
1026 UINT f_op3; \
1027 unsigned int length;
7422fa0c 1028#define EXTRACT_FMT_MVFACHI_A_CODE \
8e420152
DE		 1029 length = 2; \
1030 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1031 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1032 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1033 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1034 f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
1035
7422fa0c 1036#define EXTRACT_FMT_MVFC_VARS \
8e420152
DE		 1037 /* Instruction fields. */ \
1038 UINT f_op1; \
1039 UINT f_r1; \
1040 UINT f_op2; \
1041 UINT f_r2; \
1042 unsigned int length;
7422fa0c 1043#define EXTRACT_FMT_MVFC_CODE \
8e420152
DE		 1044 length = 2; \
1045 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1046 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1047 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1048 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1049
7422fa0c 1050#define EXTRACT_FMT_MVTACHI_A_VARS \
8e420152
DE		 1051 /* Instruction fields. */ \
1052 UINT f_op1; \
1053 UINT f_r1; \
1054 UINT f_op2; \
1055 UINT f_accs; \
1056 UINT f_op3; \
1057 unsigned int length;
7422fa0c 1058#define EXTRACT_FMT_MVTACHI_A_CODE \
8e420152
DE		 1059 length = 2; \
1060 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1061 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1062 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1063 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1064 f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
1065
7422fa0c 1066#define EXTRACT_FMT_MVTC_VARS \
8e420152
DE		 1067 /* Instruction fields. */ \
1068 UINT f_op1; \
1069 UINT f_r1; \
1070 UINT f_op2; \
1071 UINT f_r2; \
1072 unsigned int length;
7422fa0c 1073#define EXTRACT_FMT_MVTC_CODE \
8e420152
DE		 1074 length = 2; \
1075 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1076 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1077 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1078 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1079
7422fa0c 1080#define EXTRACT_FMT_NOP_VARS \
8e420152
DE		 1081 /* Instruction fields. */ \
1082 UINT f_op1; \
1083 UINT f_r1; \
1084 UINT f_op2; \
1085 UINT f_r2; \
1086 unsigned int length;
7422fa0c 1087#define EXTRACT_FMT_NOP_CODE \
8e420152
DE		 1088 length = 2; \
1089 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1090 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1091 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1092 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1093
7422fa0c 1094#define EXTRACT_FMT_RAC_DSI_VARS \
8e420152
DE		 1095 /* Instruction fields. */ \
1096 UINT f_op1; \
e0bd6e18
DE		 1097 UINT f_accd; \
1098 UINT f_bits67; \
8e420152 1099 UINT f_op2; \
b8a9943d 1100 UINT f_accs; \
e0bd6e18
DE		 1101 UINT f_bit14; \
1102 UINT f_imm1; \
8e420152 1103 unsigned int length;
7422fa0c 1104#define EXTRACT_FMT_RAC_DSI_CODE \
8e420152
DE		 1105 length = 2; \
1106 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
e0bd6e18
DE		 1107 f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
1108 f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
8e420152 1109 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
b8a9943d 1110 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
e0bd6e18 1111 f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
cab58155 1112 f_imm1 = ((EXTRACT_UNSIGNED (insn, 16, 15, 1)) + (1)); \
8e420152 1113
7422fa0c 1114#define EXTRACT_FMT_RTE_VARS \
e0bd6e18
DE		 1115 /* Instruction fields. */ \
1116 UINT f_op1; \
cab58155 1117 UINT f_r1; \
e0bd6e18 1118 UINT f_op2; \
cab58155 1119 UINT f_r2; \
e0bd6e18 1120 unsigned int length;
7422fa0c 1121#define EXTRACT_FMT_RTE_CODE \
e0bd6e18
DE		 1122 length = 2; \
1123 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
cab58155 1124 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
e0bd6e18 1125 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
cab58155 1126 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
e0bd6e18 1127
7422fa0c 1128#define EXTRACT_FMT_SETH_VARS \
e0bd6e18
DE		 1129 /* Instruction fields. */ \
1130 UINT f_op1; \
cab58155 1131 UINT f_r1; \
e0bd6e18 1132 UINT f_op2; \
cab58155
DE		 1133 UINT f_r2; \
1134 UINT f_hi16; \
1135 unsigned int length;
7422fa0c 1136#define EXTRACT_FMT_SETH_CODE \
cab58155
DE		 1137 length = 4; \
1138 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1139 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1140 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1141 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1142 f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1143
7422fa0c 1144#define EXTRACT_FMT_SLL3_VARS \
cab58155
DE		 1145 /* Instruction fields. */ \
1146 UINT f_op1; \
1147 UINT f_r1; \
1148 UINT f_op2; \
1149 UINT f_r2; \
1150 int f_simm16; \
e0bd6e18 1151 unsigned int length;
7422fa0c 1152#define EXTRACT_FMT_SLL3_CODE \
cab58155
DE		 1153 length = 4; \
1154 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1155 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1156 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1157 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1158 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1159
7422fa0c 1160#define EXTRACT_FMT_SLLI_VARS \
cab58155
DE		 1161 /* Instruction fields. */ \
1162 UINT f_op1; \
1163 UINT f_r1; \
1164 UINT f_shift_op2; \
1165 UINT f_uimm5; \
1166 unsigned int length;
7422fa0c 1167#define EXTRACT_FMT_SLLI_CODE \
e0bd6e18
DE		 1168 length = 2; \
1169 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
cab58155
DE		 1170 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1171 f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
1172 f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
1173
7422fa0c 1174#define EXTRACT_FMT_ST_VARS \
cab58155
DE		 1175 /* Instruction fields. */ \
1176 UINT f_op1; \
1177 UINT f_r1; \
1178 UINT f_op2; \
1179 UINT f_r2; \
1180 unsigned int length;
7422fa0c 1181#define EXTRACT_FMT_ST_CODE \
cab58155
DE		 1182 length = 2; \
1183 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1184 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
e0bd6e18 1185 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
cab58155 1186 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
e0bd6e18 1187
7422fa0c 1188#define EXTRACT_FMT_ST_D_VARS \
8e420152
DE		 1189 /* Instruction fields. */ \
1190 UINT f_op1; \
1191 UINT f_r1; \
1192 UINT f_op2; \
b8a9943d 1193 UINT f_r2; \
cab58155 1194 int f_simm16; \
8e420152 1195 unsigned int length;
7422fa0c 1196#define EXTRACT_FMT_ST_D_CODE \
cab58155
DE		 1197 length = 4; \
1198 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1199 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1200 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1201 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1202 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1203
7422fa0c 1204#define EXTRACT_FMT_STB_VARS \
cab58155
DE		 1205 /* Instruction fields. */ \
1206 UINT f_op1; \
1207 UINT f_r1; \
1208 UINT f_op2; \
1209 UINT f_r2; \
1210 unsigned int length;
7422fa0c 1211#define EXTRACT_FMT_STB_CODE \
8e420152
DE		 1212 length = 2; \
1213 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1214 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1215 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
b8a9943d 1216 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
8e420152 1217
7422fa0c 1218#define EXTRACT_FMT_STB_D_VARS \
8e420152
DE		 1219 /* Instruction fields. */ \
1220 UINT f_op1; \
1221 UINT f_r1; \
1222 UINT f_op2; \
1223 UINT f_r2; \
cab58155 1224 int f_simm16; \
8e420152 1225 unsigned int length;
7422fa0c 1226#define EXTRACT_FMT_STB_D_CODE \
8e420152
DE		 1227 length = 4; \
1228 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1229 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1230 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1231 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
cab58155 1232 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
8e420152 1233
7422fa0c 1234#define EXTRACT_FMT_STH_VARS \
8e420152
DE		 1235 /* Instruction fields. */ \
1236 UINT f_op1; \
1237 UINT f_r1; \
cab58155
DE		 1238 UINT f_op2; \
1239 UINT f_r2; \
8e420152 1240 unsigned int length;
7422fa0c 1241#define EXTRACT_FMT_STH_CODE \
8e420152
DE		 1242 length = 2; \
1243 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1244 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
cab58155
DE		 1245 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1246 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
8e420152 1247
7422fa0c 1248#define EXTRACT_FMT_STH_D_VARS \
8e420152
DE		 1249 /* Instruction fields. */ \
1250 UINT f_op1; \
1251 UINT f_r1; \
1252 UINT f_op2; \
1253 UINT f_r2; \
1254 int f_simm16; \
1255 unsigned int length;
7422fa0c 1256#define EXTRACT_FMT_STH_D_CODE \
8e420152
DE		 1257 length = 4; \
1258 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1259 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1260 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1261 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1262 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1263
7422fa0c 1264#define EXTRACT_FMT_ST_PLUS_VARS \
cab58155
DE		 1265 /* Instruction fields. */ \
1266 UINT f_op1; \
1267 UINT f_r1; \
1268 UINT f_op2; \
1269 UINT f_r2; \
1270 unsigned int length;
7422fa0c 1271#define EXTRACT_FMT_ST_PLUS_CODE \
cab58155
DE		 1272 length = 2; \
1273 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1274 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1275 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1276 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1277
7422fa0c 1278#define EXTRACT_FMT_TRAP_VARS \
8e420152
DE		 1279 /* Instruction fields. */ \
1280 UINT f_op1; \
1281 UINT f_r1; \
1282 UINT f_op2; \
1283 UINT f_uimm4; \
1284 unsigned int length;
7422fa0c 1285#define EXTRACT_FMT_TRAP_CODE \
8e420152
DE		 1286 length = 2; \
1287 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1288 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1289 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1290 f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1291
7422fa0c 1292#define EXTRACT_FMT_UNLOCK_VARS \
cab58155
DE		 1293 /* Instruction fields. */ \
1294 UINT f_op1; \
1295 UINT f_r1; \
1296 UINT f_op2; \
1297 UINT f_r2; \
1298 unsigned int length;
7422fa0c 1299#define EXTRACT_FMT_UNLOCK_CODE \
cab58155
DE		 1300 length = 2; \
1301 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1302 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1303 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1304 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1305
7422fa0c 1306#define EXTRACT_FMT_SATB_VARS \
b8a9943d
DE		 1307 /* Instruction fields. */ \
1308 UINT f_op1; \
1309 UINT f_r1; \
1310 UINT f_op2; \
1311 UINT f_r2; \
1312 UINT f_uimm16; \
1313 unsigned int length;
7422fa0c 1314#define EXTRACT_FMT_SATB_CODE \
b8a9943d
DE		 1315 length = 4; \
1316 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1317 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1318 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1319 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1320 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1321
7422fa0c 1322#define EXTRACT_FMT_SAT_VARS \
8e420152
DE		 1323 /* Instruction fields. */ \
1324 UINT f_op1; \
1325 UINT f_r1; \
1326 UINT f_op2; \
1327 UINT f_r2; \
1328 UINT f_uimm16; \
1329 unsigned int length;
7422fa0c 1330#define EXTRACT_FMT_SAT_CODE \
8e420152
DE		 1331 length = 4; \
1332 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1333 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1334 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1335 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1336 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1337
7422fa0c 1338#define EXTRACT_FMT_SADD_VARS \
8e420152
DE		 1339 /* Instruction fields. */ \
1340 UINT f_op1; \
1341 UINT f_r1; \
1342 UINT f_op2; \
1343 UINT f_r2; \
1344 unsigned int length;
7422fa0c 1345#define EXTRACT_FMT_SADD_CODE \
8e420152
DE		 1346 length = 2; \
1347 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1348 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1349 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1350 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1351
7422fa0c 1352#define EXTRACT_FMT_MACWU1_VARS \
8e420152
DE		 1353 /* Instruction fields. */ \
1354 UINT f_op1; \
1355 UINT f_r1; \
1356 UINT f_op2; \
1357 UINT f_r2; \
1358 unsigned int length;
7422fa0c 1359#define EXTRACT_FMT_MACWU1_CODE \
8e420152
DE		 1360 length = 2; \
1361 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1362 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1363 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1364 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1365
7422fa0c 1366#define EXTRACT_FMT_MULWU1_VARS \
8e420152
DE		 1367 /* Instruction fields. */ \
1368 UINT f_op1; \
1369 UINT f_r1; \
1370 UINT f_op2; \
1371 UINT f_r2; \
1372 unsigned int length;
7422fa0c 1373#define EXTRACT_FMT_MULWU1_CODE \
8e420152
DE		 1374 length = 2; \
1375 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1376 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1377 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1378 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1379
7422fa0c 1380#define EXTRACT_FMT_SC_VARS \
8e420152
DE		 1381 /* Instruction fields. */ \
1382 UINT f_op1; \
1383 UINT f_r1; \
1384 UINT f_op2; \
1385 UINT f_r2; \
1386 unsigned int length;
7422fa0c 1387#define EXTRACT_FMT_SC_CODE \
8e420152
DE		 1388 length = 2; \
1389 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1390 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1391 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1392 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1393
1394/* Fetched input values of an instruction. */
1395
e0bd6e18 1396struct parexec {
8e420152
DE		 1397 union {
1398 struct { /* e.g. add $dr,$sr */
1399 SI dr;
1400 SI sr;
7422fa0c
DE		 1401 } fmt_add;
1402 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
8e420152 1403 SI sr;
7422fa0c
DE		 1404 HI slo16;
1405 } fmt_add3;
1406 struct { /* e.g. and3 $dr,$sr,$uimm16 */
8e420152
DE		 1407 SI sr;
1408 USI uimm16;
7422fa0c
DE		 1409 } fmt_and3;
1410 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
8e420152
DE		 1411 SI sr;
1412 UHI ulo16;
7422fa0c
DE		 1413 } fmt_or3;
1414 struct { /* e.g. addi $dr,$simm8 */
8e420152
DE		 1415 SI dr;
1416 SI simm8;
7422fa0c 1417 } fmt_addi;
cab58155
DE		 1418 struct { /* e.g. addv $dr,$sr */
1419 SI dr;
1420 SI sr;
7422fa0c
DE		 1421 } fmt_addv;
1422 struct { /* e.g. addv3 $dr,$sr,$simm16 */
8e420152 1423 SI sr;
7422fa0c
DE		 1424 SI simm16;
1425 } fmt_addv3;
8e420152 1426 struct { /* e.g. addx $dr,$sr */
8e420152
DE		 1427 SI dr;
1428 SI sr;
8e420152 1429 UBI condbit;
7422fa0c
DE		 1430 } fmt_addx;
1431 struct { /* e.g. bc.s $disp8 */
1432 UBI condbit;
1433 USI disp8;
1434 } fmt_bc8;
1435 struct { /* e.g. bc.l $disp24 */
8e420152 1436 UBI condbit;
7422fa0c
DE		 1437 USI disp24;
1438 } fmt_bc24;
8e420152 1439 struct { /* e.g. beq $src1,$src2,$disp16 */
8e420152
DE		 1440 SI src1;
1441 SI src2;
7422fa0c
DE		 1442 USI disp16;
1443 } fmt_beq;
8e420152 1444 struct { /* e.g. beqz $src2,$disp16 */
8e420152 1445 SI src2;
7422fa0c
DE		 1446 USI disp16;
1447 } fmt_beqz;
1448 struct { /* e.g. bl.s $disp8 */
8e420152 1449 USI pc;
7422fa0c
DE		 1450 USI disp8;
1451 } fmt_bl8;
1452 struct { /* e.g. bl.l $disp24 */
8e420152 1453 USI pc;
7422fa0c
DE		 1454 USI disp24;
1455 } fmt_bl24;
1456 struct { /* e.g. bcl.s $disp8 */
8e420152 1457 UBI condbit;
8e420152 1458 USI pc;
7422fa0c
DE		 1459 USI disp8;
1460 } fmt_bcl8;
1461 struct { /* e.g. bcl.l $disp24 */
8e420152 1462 UBI condbit;
8e420152 1463 USI pc;
7422fa0c
DE		 1464 USI disp24;
1465 } fmt_bcl24;
1466 struct { /* e.g. bra.s $disp8 */
1467 USI disp8;
1468 } fmt_bra8;
1469 struct { /* e.g. bra.l $disp24 */
1470 USI disp24;
1471 } fmt_bra24;
8e420152
DE		 1472 struct { /* e.g. cmp $src1,$src2 */
1473 SI src1;
1474 SI src2;
7422fa0c
DE		 1475 } fmt_cmp;
1476 struct { /* e.g. cmpi $src2,$simm16 */
8e420152 1477 SI src2;
7422fa0c
DE		 1478 SI simm16;
1479 } fmt_cmpi;
8e420152
DE		 1480 struct { /* e.g. cmpz $src2 */
1481 SI src2;
7422fa0c 1482 } fmt_cmpz;
8e420152
DE		 1483 struct { /* e.g. div $dr,$sr */
1484 SI dr;
1485 SI sr;
7422fa0c 1486 } fmt_div;
8e420152
DE		 1487 struct { /* e.g. jc $sr */
1488 UBI condbit;
1489 SI sr;
7422fa0c 1490 } fmt_jc;
8e420152
DE		 1491 struct { /* e.g. jl $sr */
1492 USI pc;
1493 SI sr;
7422fa0c 1494 } fmt_jl;
8e420152
DE		 1495 struct { /* e.g. jmp $sr */
1496 SI sr;
7422fa0c 1497 } fmt_jmp;
8e420152 1498 struct { /* e.g. ld $dr,@$sr */
02310b01 1499 SI h_memory_sr;
7422fa0c
DE		 1500 USI sr;
1501 } fmt_ld;
8e420152 1502 struct { /* e.g. ld $dr,@($slo16,$sr) */
7422fa0c 1503 SI h_memory_add__VM_sr_slo16;
8e420152 1504 SI sr;
7422fa0c
DE		 1505 HI slo16;
1506 } fmt_ld_d;
8e420152 1507 struct { /* e.g. ldb $dr,@$sr */
02310b01 1508 QI h_memory_sr;
7422fa0c
DE		 1509 USI sr;
1510 } fmt_ldb;
8e420152 1511 struct { /* e.g. ldb $dr,@($slo16,$sr) */
7422fa0c 1512 QI h_memory_add__VM_sr_slo16;
8e420152 1513 SI sr;
7422fa0c
DE		 1514 HI slo16;
1515 } fmt_ldb_d;
8e420152 1516 struct { /* e.g. ldh $dr,@$sr */
02310b01 1517 HI h_memory_sr;
7422fa0c
DE		 1518 USI sr;
1519 } fmt_ldh;
8e420152 1520 struct { /* e.g. ldh $dr,@($slo16,$sr) */
7422fa0c 1521 HI h_memory_add__VM_sr_slo16;
8e420152 1522 SI sr;
7422fa0c
DE		 1523 HI slo16;
1524 } fmt_ldh_d;
cab58155 1525 struct { /* e.g. ld $dr,@$sr+ */
02310b01 1526 SI h_memory_sr;
cab58155 1527 SI sr;
7422fa0c
DE		 1528 } fmt_ld_plus;
1529 struct { /* e.g. ld24 $dr,$uimm24 */
1530 USI uimm24;
1531 } fmt_ld24;
1532 struct { /* e.g. ldi8 $dr,$simm8 */
8e420152 1533 SI simm8;
7422fa0c
DE		 1534 } fmt_ldi8;
1535 struct { /* e.g. ldi16 $dr,$hash$slo16 */
8e420152 1536 HI slo16;
7422fa0c 1537 } fmt_ldi16;
cab58155 1538 struct { /* e.g. lock $dr,@$sr */
02310b01 1539 SI h_memory_sr;
7422fa0c
DE		 1540 USI sr;
1541 } fmt_lock;
8e420152
DE		 1542 struct { /* e.g. machi $src1,$src2,$acc */
1543 DI acc;
1544 SI src1;
1545 SI src2;
7422fa0c
DE		 1546 } fmt_machi_a;
1547 struct { /* e.g. macwhi $src1,$src2 */
1548 DI accum;
1549 SI src1;
1550 SI src2;
1551 } fmt_macwhi;
8e420152
DE		 1552 struct { /* e.g. mulhi $src1,$src2,$acc */
1553 SI src1;
1554 SI src2;
7422fa0c
DE		 1555 } fmt_mulhi_a;
1556 struct { /* e.g. mulwhi $src1,$src2 */
1557 SI src1;
1558 SI src2;
1559 } fmt_mulwhi;
8e420152
DE		 1560 struct { /* e.g. mv $dr,$sr */
1561 SI sr;
7422fa0c 1562 } fmt_mv;
8e420152
DE		 1563 struct { /* e.g. mvfachi $dr,$accs */
1564 DI accs;
7422fa0c 1565 } fmt_mvfachi_a;
8e420152 1566 struct { /* e.g. mvfc $dr,$scr */
cab58155 1567 USI scr;
7422fa0c 1568 } fmt_mvfc;
8e420152
DE		 1569 struct { /* e.g. mvtachi $src1,$accs */
1570 DI accs;
1571 SI src1;
7422fa0c 1572 } fmt_mvtachi_a;
8e420152
DE		 1573 struct { /* e.g. mvtc $sr,$dcr */
1574 SI sr;
7422fa0c 1575 } fmt_mvtc;
8e420152
DE		 1576 struct { /* e.g. nop */
1577 int empty;
7422fa0c
DE		 1578 } fmt_nop;
1579 struct { /* e.g. rac $accd,$accs,$imm1 */
8e420152 1580 DI accs;
e0bd6e18 1581 USI imm1;
7422fa0c 1582 } fmt_rac_dsi;
b8a9943d 1583 struct { /* e.g. rte */
7422fa0c 1584 UBI h_bsm_0;
b8a9943d 1585 UBI h_bie_0;
7422fa0c 1586 UBI h_bcond_0;
b8a9943d 1587 SI h_bpc_0;
7422fa0c
DE		 1588 } fmt_rte;
1589 struct { /* e.g. seth $dr,$hash$hi16 */
1590 SI hi16;
1591 } fmt_seth;
1592 struct { /* e.g. sll3 $dr,$sr,$simm16 */
cab58155 1593 SI sr;
7422fa0c
DE		 1594 SI simm16;
1595 } fmt_sll3;
1596 struct { /* e.g. slli $dr,$uimm5 */
8e420152
DE		 1597 SI dr;
1598 USI uimm5;
7422fa0c 1599 } fmt_slli;
cab58155 1600 struct { /* e.g. st $src1,@$src2 */
7422fa0c 1601 USI src2;
cab58155 1602 SI src1;
7422fa0c 1603 } fmt_st;
8e420152 1604 struct { /* e.g. st $src1,@($slo16,$src2) */
7422fa0c 1605 SI src2;
8e420152
DE		 1606 HI slo16;
1607 SI src1;
7422fa0c 1608 } fmt_st_d;
cab58155 1609 struct { /* e.g. stb $src1,@$src2 */
7422fa0c
DE		 1610 USI src2;
1611 QI src1;
1612 } fmt_stb;
cab58155 1613 struct { /* e.g. stb $src1,@($slo16,$src2) */
cab58155 1614 SI src2;
7422fa0c
DE		 1615 HI slo16;
1616 QI src1;
1617 } fmt_stb_d;
cab58155 1618 struct { /* e.g. sth $src1,@$src2 */
7422fa0c
DE		 1619 USI src2;
1620 HI src1;
1621 } fmt_sth;
cab58155 1622 struct { /* e.g. sth $src1,@($slo16,$src2) */
cab58155 1623 SI src2;
7422fa0c
DE		 1624 HI slo16;
1625 HI src1;
1626 } fmt_sth_d;
cab58155 1627 struct { /* e.g. st $src1,@+$src2 */
cab58155 1628 SI src2;
7422fa0c
DE		 1629 SI src1;
1630 } fmt_st_plus;
1631 struct { /* e.g. trap $uimm4 */
cab58155 1632 USI pc;
7422fa0c
DE		 1633 USI h_cr_0;
1634 SI uimm4;
1635 } fmt_trap;
cab58155
DE		 1636 struct { /* e.g. unlock $src1,@$src2 */
1637 UBI h_lock_0;
7422fa0c 1638 USI src2;
cab58155 1639 SI src1;
7422fa0c 1640 } fmt_unlock;
cab58155
DE		 1641 struct { /* e.g. satb $dr,$sr */
1642 SI sr;
7422fa0c 1643 } fmt_satb;
cab58155 1644 struct { /* e.g. sat $dr,$sr */
b8a9943d 1645 UBI condbit;
cab58155 1646 SI sr;
7422fa0c 1647 } fmt_sat;
8e420152 1648 struct { /* e.g. sadd */
b8a9943d 1649 DI h_accums_1;
7422fa0c
DE		 1650 DI h_accums_0;
1651 } fmt_sadd;
8e420152 1652 struct { /* e.g. macwu1 $src1,$src2 */
b8a9943d
DE		 1653 DI h_accums_1;
1654 SI src1;
1655 SI src2;
7422fa0c 1656 } fmt_macwu1;
cab58155
DE		 1657 struct { /* e.g. mulwu1 $src1,$src2 */
1658 SI src1;
1659 SI src2;
7422fa0c 1660 } fmt_mulwu1;
8e420152
DE		 1661 struct { /* e.g. sc */
1662 UBI condbit;
7422fa0c 1663 } fmt_sc;
8e420152
DE		 1664 } operands;
1665};
1666
1667#endif /* CPU_M32RX_H */
GDB Binutils - Deliverables
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