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c906108c SS |
1 | /* collection of junk waiting time to sort out |
2 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. | |
3 | Contributed by Cygnus Support. | |
4 | ||
5 | This file is part of the GNU Simulators. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #ifndef M32R_SIM_H | |
22 | #define M32R_SIM_H | |
23 | ||
24 | /* gdb register numbers */ | |
25 | #define PSW_REGNUM 16 | |
26 | #define CBR_REGNUM 17 | |
27 | #define SPI_REGNUM 18 | |
28 | #define SPU_REGNUM 19 | |
29 | #define BPC_REGNUM 20 | |
30 | #define PC_REGNUM 21 | |
31 | #define ACCL_REGNUM 22 | |
32 | #define ACCH_REGNUM 23 | |
33 | #define ACC1L_REGNUM 24 | |
34 | #define ACC1H_REGNUM 25 | |
35 | #define BBPSW_REGNUM 26 | |
36 | #define BBPC_REGNUM 27 | |
37 | ||
38 | extern int m32r_decode_gdb_ctrl_regnum (int); | |
39 | ||
40 | /* Cover macros for hardware accesses. | |
41 | FIXME: Eventually move to cgen. */ | |
42 | #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0) | |
43 | ||
7a292a7a SS |
44 | extern SI a_m32r_h_gr_get (SIM_CPU *, UINT); |
45 | extern void a_m32r_h_gr_set (SIM_CPU *, UINT, SI); | |
46 | extern USI a_m32r_h_cr_get (SIM_CPU *, UINT); | |
47 | extern void a_m32r_h_cr_set (SIM_CPU *, UINT, USI); | |
48 | ||
c906108c SS |
49 | extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT); |
50 | extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI); | |
c906108c SS |
51 | |
52 | extern UQI m32rbf_h_psw_get_handler (SIM_CPU *); | |
53 | extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI); | |
c906108c SS |
54 | |
55 | extern DI m32rbf_h_accum_get_handler (SIM_CPU *); | |
56 | extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI); | |
c906108c SS |
57 | |
58 | \f | |
59 | /* Misc. profile data. */ | |
60 | ||
61 | typedef struct { | |
62 | /* nop insn slot filler count */ | |
63 | unsigned int fillnop_count; | |
64 | /* number of parallel insns */ | |
65 | unsigned int parallel_count; | |
66 | ||
67 | /* FIXME: generalize this to handle all insn lengths, move to common. */ | |
68 | /* number of short insns, not including parallel ones */ | |
69 | unsigned int short_count; | |
70 | /* number of long insns */ | |
71 | unsigned int long_count; | |
72 | ||
73 | /* Working area for computing cycle counts. */ | |
74 | unsigned long insn_cycles; /* FIXME: delete */ | |
75 | unsigned long cti_stall; | |
76 | unsigned long load_stall; | |
77 | unsigned long biggest_cycles; | |
78 | ||
79 | /* Bitmask of registers loaded by previous insn. */ | |
80 | unsigned int load_regs; | |
81 | /* Bitmask of registers loaded by current insn. */ | |
82 | unsigned int load_regs_pending; | |
83 | } M32R_MISC_PROFILE; | |
84 | ||
85 | /* Initialize the working area. */ | |
86 | void m32r_init_insn_cycles (SIM_CPU *, int); | |
87 | /* Update the totals for the insn. */ | |
88 | void m32r_record_insn_cycles (SIM_CPU *, int); | |
89 | ||
90 | /* This is invoked by the nop pattern in the .cpu file. */ | |
91 | #define PROFILE_COUNT_FILLNOPS(cpu, addr) \ | |
92 | do { \ | |
93 | if (PROFILE_INSN_P (cpu) \ | |
94 | && (addr & 3) != 0) \ | |
95 | ++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \ | |
96 | } while (0) | |
97 | ||
98 | /* This is invoked by the execute section of mloop{,x}.in. */ | |
99 | #define PROFILE_COUNT_PARINSNS(cpu) \ | |
100 | do { \ | |
101 | if (PROFILE_INSN_P (cpu)) \ | |
102 | ++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \ | |
103 | } while (0) | |
104 | ||
105 | /* This is invoked by the execute section of mloop{,x}.in. */ | |
106 | #define PROFILE_COUNT_SHORTINSNS(cpu) \ | |
107 | do { \ | |
108 | if (PROFILE_INSN_P (cpu)) \ | |
109 | ++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \ | |
110 | } while (0) | |
111 | ||
112 | /* This is invoked by the execute section of mloop{,x}.in. */ | |
113 | #define PROFILE_COUNT_LONGINSNS(cpu) \ | |
114 | do { \ | |
115 | if (PROFILE_INSN_P (cpu)) \ | |
116 | ++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \ | |
117 | } while (0) | |
118 | \f | |
119 | #define GETTWI GETTSI | |
120 | #define SETTWI SETTSI | |
121 | \f | |
122 | /* Additional execution support. */ | |
123 | ||
124 | \f | |
125 | /* Hardware/device support. | |
126 | ??? Will eventually want to move device stuff to config files. */ | |
127 | ||
128 | /* Exception, Interrupt, and Trap addresses */ | |
129 | #define EIT_SYSBREAK_ADDR 0x10 | |
130 | #define EIT_RSVD_INSN_ADDR 0x20 | |
131 | #define EIT_ADDR_EXCP_ADDR 0x30 | |
132 | #define EIT_TRAP_BASE_ADDR 0x40 | |
133 | #define EIT_EXTERN_ADDR 0x80 | |
134 | #define EIT_RESET_ADDR 0x7ffffff0 | |
135 | #define EIT_WAKEUP_ADDR 0x7ffffff0 | |
136 | ||
137 | /* Special purpose traps. */ | |
138 | #define TRAP_SYSCALL 0 | |
139 | #define TRAP_BREAKPOINT 1 | |
140 | ||
141 | /* Support for the MSPR register (Cache Purge Control Register) | |
142 | and the MCCR register (Cache Control Register) are needed in order for | |
143 | overlays to work correctly with the scache. | |
144 | MSPR no longer exists but is supported for upward compatibility with | |
145 | early overlay support. */ | |
146 | ||
147 | /* Cache Purge Control (only exists on early versions of chips) */ | |
148 | #define MSPR_ADDR 0xfffffff7 | |
149 | #define MSPR_PURGE 1 | |
150 | ||
151 | /* Lock Control Register (not supported) */ | |
152 | #define MLCR_ADDR 0xfffffff7 | |
153 | #define MLCR_LM 1 | |
154 | ||
155 | /* Power Management Control Register (not supported) */ | |
156 | #define MPMR_ADDR 0xfffffffb | |
157 | ||
158 | /* Cache Control Register */ | |
159 | #define MCCR_ADDR 0xffffffff | |
160 | #define MCCR_CP 0x80 | |
161 | /* not supported */ | |
162 | #define MCCR_CM0 2 | |
163 | #define MCCR_CM1 1 | |
164 | ||
165 | /* Serial device addresses. */ | |
166 | #ifdef M32R_EVA /* orig eva board, no longer supported */ | |
167 | #define UART_INCHAR_ADDR 0xff102013 | |
168 | #define UART_OUTCHAR_ADDR 0xff10200f | |
169 | #define UART_STATUS_ADDR 0xff102006 | |
170 | /* Indicate ready bit is inverted. */ | |
171 | #define UART_INPUT_READY0 | |
172 | #else | |
173 | /* These are the values for the MSA2000 board. | |
174 | ??? Will eventually need to move this to a config file. */ | |
175 | #define UART_INCHAR_ADDR 0xff004009 | |
176 | #define UART_OUTCHAR_ADDR 0xff004007 | |
177 | #define UART_STATUS_ADDR 0xff004002 | |
178 | #endif | |
179 | ||
180 | #define UART_INPUT_READY 0x4 | |
181 | #define UART_OUTPUT_READY 0x1 | |
182 | ||
183 | /* Start address and length of all device support. */ | |
184 | #define M32R_DEVICE_ADDR 0xff000000 | |
7a292a7a | 185 | #define M32R_DEVICE_LEN 0x01000000 |
c906108c SS |
186 | |
187 | /* sim_core_attach device argument. */ | |
188 | extern device m32r_devices; | |
189 | ||
190 | /* FIXME: Temporary, until device support ready. */ | |
191 | struct _device { int foo; }; | |
192 | ||
193 | /* Handle the trap insn. */ | |
194 | USI m32r_trap (SIM_CPU *, PCADDR, int); | |
195 | ||
196 | #endif /* M32R_SIM_H */ |