Commit | Line | Data |
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8e420152 DE |
1 | /* Simulator instruction operand reader for m32r. |
2 | ||
1148b104 | 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
b8a9943d | 4 | |
8e420152 DE |
5 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. |
6 | ||
7 | This file is part of the GNU Simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
8e420152 DE |
25 | #ifdef DEFINE_LABELS |
26 | #undef DEFINE_LABELS | |
27 | ||
8e420152 DE |
28 | /* The labels have the case they have because the enum of insn types |
29 | is all uppercase and in the non-stdc case the fmt symbol is built | |
40c680ba DE |
30 | into the enum name. */ |
31 | ||
32 | static struct { | |
33 | int index; | |
34 | void *label; | |
35 | } labels[] = { | |
36 | { M32RX_XINSN_ILLEGAL, && case_read_READ_ILLEGAL }, | |
37 | { M32RX_XINSN_ADD, && case_read_READ_FMT_ADD }, | |
38 | { M32RX_XINSN_ADD3, && case_read_READ_FMT_ADD3 }, | |
39 | { M32RX_XINSN_AND, && case_read_READ_FMT_ADD }, | |
40 | { M32RX_XINSN_AND3, && case_read_READ_FMT_AND3 }, | |
41 | { M32RX_XINSN_OR, && case_read_READ_FMT_ADD }, | |
42 | { M32RX_XINSN_OR3, && case_read_READ_FMT_OR3 }, | |
43 | { M32RX_XINSN_XOR, && case_read_READ_FMT_ADD }, | |
44 | { M32RX_XINSN_XOR3, && case_read_READ_FMT_AND3 }, | |
45 | { M32RX_XINSN_ADDI, && case_read_READ_FMT_ADDI }, | |
46 | { M32RX_XINSN_ADDV, && case_read_READ_FMT_ADDV }, | |
47 | { M32RX_XINSN_ADDV3, && case_read_READ_FMT_ADDV3 }, | |
48 | { M32RX_XINSN_ADDX, && case_read_READ_FMT_ADDX }, | |
49 | { M32RX_XINSN_BC8, && case_read_READ_FMT_BC8 }, | |
50 | { M32RX_XINSN_BC24, && case_read_READ_FMT_BC24 }, | |
51 | { M32RX_XINSN_BEQ, && case_read_READ_FMT_BEQ }, | |
52 | { M32RX_XINSN_BEQZ, && case_read_READ_FMT_BEQZ }, | |
53 | { M32RX_XINSN_BGEZ, && case_read_READ_FMT_BEQZ }, | |
54 | { M32RX_XINSN_BGTZ, && case_read_READ_FMT_BEQZ }, | |
55 | { M32RX_XINSN_BLEZ, && case_read_READ_FMT_BEQZ }, | |
56 | { M32RX_XINSN_BLTZ, && case_read_READ_FMT_BEQZ }, | |
57 | { M32RX_XINSN_BNEZ, && case_read_READ_FMT_BEQZ }, | |
58 | { M32RX_XINSN_BL8, && case_read_READ_FMT_BL8 }, | |
59 | { M32RX_XINSN_BL24, && case_read_READ_FMT_BL24 }, | |
60 | { M32RX_XINSN_BCL8, && case_read_READ_FMT_BCL8 }, | |
61 | { M32RX_XINSN_BCL24, && case_read_READ_FMT_BCL24 }, | |
62 | { M32RX_XINSN_BNC8, && case_read_READ_FMT_BC8 }, | |
63 | { M32RX_XINSN_BNC24, && case_read_READ_FMT_BC24 }, | |
64 | { M32RX_XINSN_BNE, && case_read_READ_FMT_BEQ }, | |
65 | { M32RX_XINSN_BRA8, && case_read_READ_FMT_BRA8 }, | |
66 | { M32RX_XINSN_BRA24, && case_read_READ_FMT_BRA24 }, | |
67 | { M32RX_XINSN_BNCL8, && case_read_READ_FMT_BCL8 }, | |
68 | { M32RX_XINSN_BNCL24, && case_read_READ_FMT_BCL24 }, | |
69 | { M32RX_XINSN_CMP, && case_read_READ_FMT_CMP }, | |
70 | { M32RX_XINSN_CMPI, && case_read_READ_FMT_CMPI }, | |
71 | { M32RX_XINSN_CMPU, && case_read_READ_FMT_CMP }, | |
72 | { M32RX_XINSN_CMPUI, && case_read_READ_FMT_CMPI }, | |
73 | { M32RX_XINSN_CMPEQ, && case_read_READ_FMT_CMP }, | |
74 | { M32RX_XINSN_CMPZ, && case_read_READ_FMT_CMPZ }, | |
75 | { M32RX_XINSN_DIV, && case_read_READ_FMT_DIV }, | |
76 | { M32RX_XINSN_DIVU, && case_read_READ_FMT_DIV }, | |
77 | { M32RX_XINSN_REM, && case_read_READ_FMT_DIV }, | |
78 | { M32RX_XINSN_REMU, && case_read_READ_FMT_DIV }, | |
79 | { M32RX_XINSN_DIVH, && case_read_READ_FMT_DIV }, | |
80 | { M32RX_XINSN_JC, && case_read_READ_FMT_JC }, | |
81 | { M32RX_XINSN_JNC, && case_read_READ_FMT_JC }, | |
82 | { M32RX_XINSN_JL, && case_read_READ_FMT_JL }, | |
83 | { M32RX_XINSN_JMP, && case_read_READ_FMT_JMP }, | |
84 | { M32RX_XINSN_LD, && case_read_READ_FMT_LD }, | |
85 | { M32RX_XINSN_LD_D, && case_read_READ_FMT_LD_D }, | |
86 | { M32RX_XINSN_LDB, && case_read_READ_FMT_LDB }, | |
87 | { M32RX_XINSN_LDB_D, && case_read_READ_FMT_LDB_D }, | |
88 | { M32RX_XINSN_LDH, && case_read_READ_FMT_LDH }, | |
89 | { M32RX_XINSN_LDH_D, && case_read_READ_FMT_LDH_D }, | |
90 | { M32RX_XINSN_LDUB, && case_read_READ_FMT_LDB }, | |
91 | { M32RX_XINSN_LDUB_D, && case_read_READ_FMT_LDB_D }, | |
92 | { M32RX_XINSN_LDUH, && case_read_READ_FMT_LDH }, | |
93 | { M32RX_XINSN_LDUH_D, && case_read_READ_FMT_LDH_D }, | |
94 | { M32RX_XINSN_LD_PLUS, && case_read_READ_FMT_LD_PLUS }, | |
95 | { M32RX_XINSN_LD24, && case_read_READ_FMT_LD24 }, | |
96 | { M32RX_XINSN_LDI8, && case_read_READ_FMT_LDI8 }, | |
97 | { M32RX_XINSN_LDI16, && case_read_READ_FMT_LDI16 }, | |
98 | { M32RX_XINSN_LOCK, && case_read_READ_FMT_LOCK }, | |
99 | { M32RX_XINSN_MACHI_A, && case_read_READ_FMT_MACHI_A }, | |
100 | { M32RX_XINSN_MACLO_A, && case_read_READ_FMT_MACHI_A }, | |
101 | { M32RX_XINSN_MACWHI, && case_read_READ_FMT_MACWHI }, | |
102 | { M32RX_XINSN_MACWLO, && case_read_READ_FMT_MACWHI }, | |
103 | { M32RX_XINSN_MUL, && case_read_READ_FMT_ADD }, | |
104 | { M32RX_XINSN_MULHI_A, && case_read_READ_FMT_MULHI_A }, | |
105 | { M32RX_XINSN_MULLO_A, && case_read_READ_FMT_MULHI_A }, | |
106 | { M32RX_XINSN_MULWHI, && case_read_READ_FMT_MULWHI }, | |
107 | { M32RX_XINSN_MULWLO, && case_read_READ_FMT_MULWHI }, | |
108 | { M32RX_XINSN_MV, && case_read_READ_FMT_MV }, | |
109 | { M32RX_XINSN_MVFACHI_A, && case_read_READ_FMT_MVFACHI_A }, | |
110 | { M32RX_XINSN_MVFACLO_A, && case_read_READ_FMT_MVFACHI_A }, | |
111 | { M32RX_XINSN_MVFACMI_A, && case_read_READ_FMT_MVFACHI_A }, | |
112 | { M32RX_XINSN_MVFC, && case_read_READ_FMT_MVFC }, | |
113 | { M32RX_XINSN_MVTACHI_A, && case_read_READ_FMT_MVTACHI_A }, | |
114 | { M32RX_XINSN_MVTACLO_A, && case_read_READ_FMT_MVTACHI_A }, | |
115 | { M32RX_XINSN_MVTC, && case_read_READ_FMT_MVTC }, | |
116 | { M32RX_XINSN_NEG, && case_read_READ_FMT_MV }, | |
117 | { M32RX_XINSN_NOP, && case_read_READ_FMT_NOP }, | |
118 | { M32RX_XINSN_NOT, && case_read_READ_FMT_MV }, | |
119 | { M32RX_XINSN_RAC_DSI, && case_read_READ_FMT_RAC_DSI }, | |
120 | { M32RX_XINSN_RACH_DSI, && case_read_READ_FMT_RAC_DSI }, | |
121 | { M32RX_XINSN_RTE, && case_read_READ_FMT_RTE }, | |
122 | { M32RX_XINSN_SETH, && case_read_READ_FMT_SETH }, | |
123 | { M32RX_XINSN_SLL, && case_read_READ_FMT_ADD }, | |
124 | { M32RX_XINSN_SLL3, && case_read_READ_FMT_SLL3 }, | |
125 | { M32RX_XINSN_SLLI, && case_read_READ_FMT_SLLI }, | |
126 | { M32RX_XINSN_SRA, && case_read_READ_FMT_ADD }, | |
127 | { M32RX_XINSN_SRA3, && case_read_READ_FMT_SLL3 }, | |
128 | { M32RX_XINSN_SRAI, && case_read_READ_FMT_SLLI }, | |
129 | { M32RX_XINSN_SRL, && case_read_READ_FMT_ADD }, | |
130 | { M32RX_XINSN_SRL3, && case_read_READ_FMT_SLL3 }, | |
131 | { M32RX_XINSN_SRLI, && case_read_READ_FMT_SLLI }, | |
132 | { M32RX_XINSN_ST, && case_read_READ_FMT_ST }, | |
133 | { M32RX_XINSN_ST_D, && case_read_READ_FMT_ST_D }, | |
134 | { M32RX_XINSN_STB, && case_read_READ_FMT_STB }, | |
135 | { M32RX_XINSN_STB_D, && case_read_READ_FMT_STB_D }, | |
136 | { M32RX_XINSN_STH, && case_read_READ_FMT_STH }, | |
137 | { M32RX_XINSN_STH_D, && case_read_READ_FMT_STH_D }, | |
138 | { M32RX_XINSN_ST_PLUS, && case_read_READ_FMT_ST_PLUS }, | |
139 | { M32RX_XINSN_ST_MINUS, && case_read_READ_FMT_ST_PLUS }, | |
140 | { M32RX_XINSN_SUB, && case_read_READ_FMT_ADD }, | |
141 | { M32RX_XINSN_SUBV, && case_read_READ_FMT_ADDV }, | |
142 | { M32RX_XINSN_SUBX, && case_read_READ_FMT_ADDX }, | |
143 | { M32RX_XINSN_TRAP, && case_read_READ_FMT_TRAP }, | |
144 | { M32RX_XINSN_UNLOCK, && case_read_READ_FMT_UNLOCK }, | |
145 | { M32RX_XINSN_SATB, && case_read_READ_FMT_SATB }, | |
146 | { M32RX_XINSN_SATH, && case_read_READ_FMT_SATB }, | |
147 | { M32RX_XINSN_SAT, && case_read_READ_FMT_SAT }, | |
148 | { M32RX_XINSN_PCMPBZ, && case_read_READ_FMT_CMPZ }, | |
149 | { M32RX_XINSN_SADD, && case_read_READ_FMT_SADD }, | |
150 | { M32RX_XINSN_MACWU1, && case_read_READ_FMT_MACWU1 }, | |
151 | { M32RX_XINSN_MSBLO, && case_read_READ_FMT_MACWHI }, | |
152 | { M32RX_XINSN_MULWU1, && case_read_READ_FMT_MULWU1 }, | |
153 | { M32RX_XINSN_MACLH1, && case_read_READ_FMT_MACWU1 }, | |
154 | { M32RX_XINSN_SC, && case_read_READ_FMT_SC }, | |
155 | { M32RX_XINSN_SNC, && case_read_READ_FMT_SC }, | |
156 | { 0, 0 } | |
8e420152 | 157 | }; |
8e420152 DE |
158 | int i; |
159 | ||
40c680ba DE |
160 | for (i = 0; labels[i].label != 0; ++i) |
161 | CPU_IDESC (current_cpu) [labels[i].index].read = labels[i].label; | |
8e420152 DE |
162 | |
163 | #endif /* DEFINE_LABELS */ | |
164 | ||
165 | #ifdef DEFINE_SWITCH | |
166 | #undef DEFINE_SWITCH | |
167 | ||
168 | { | |
169 | SWITCH (read, decode->read) | |
170 | { | |
171 | ||
172 | CASE (read, READ_ILLEGAL) : | |
173 | { | |
174 | sim_engine_illegal_insn (current_cpu, NULL_CIA /*FIXME*/); | |
175 | } | |
176 | BREAK (read); | |
177 | ||
e0a85af6 | 178 | CASE (read, READ_FMT_ADD) : /* e.g. add $dr,$sr */ |
8e420152 | 179 | { |
e0a85af6 DE |
180 | #define OPRND(f) par_exec->operands.fmt_add.f |
181 | EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
182 | EXTRACT_FMT_ADD_CODE | |
8e420152 DE |
183 | /* Fetch the input operands for the semantic handler. */ |
184 | OPRND (dr) = CPU (h_gr[f_r1]); | |
185 | OPRND (sr) = CPU (h_gr[f_r2]); | |
186 | #undef OPRND | |
187 | } | |
188 | BREAK (read); | |
189 | ||
e0a85af6 | 190 | CASE (read, READ_FMT_ADD3) : /* e.g. add3 $dr,$sr,$hash$slo16 */ |
8e420152 | 191 | { |
e0a85af6 DE |
192 | #define OPRND(f) par_exec->operands.fmt_add3.f |
193 | EXTRACT_FMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ | |
194 | EXTRACT_FMT_ADD3_CODE | |
8e420152 | 195 | /* Fetch the input operands for the semantic handler. */ |
8e420152 | 196 | OPRND (sr) = CPU (h_gr[f_r2]); |
a040908c | 197 | OPRND (slo16) = f_simm16; |
8e420152 DE |
198 | #undef OPRND |
199 | } | |
200 | BREAK (read); | |
201 | ||
e0a85af6 | 202 | CASE (read, READ_FMT_AND3) : /* e.g. and3 $dr,$sr,$uimm16 */ |
8e420152 | 203 | { |
e0a85af6 DE |
204 | #define OPRND(f) par_exec->operands.fmt_and3.f |
205 | EXTRACT_FMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ | |
206 | EXTRACT_FMT_AND3_CODE | |
8e420152 DE |
207 | /* Fetch the input operands for the semantic handler. */ |
208 | OPRND (sr) = CPU (h_gr[f_r2]); | |
209 | OPRND (uimm16) = f_uimm16; | |
210 | #undef OPRND | |
211 | } | |
212 | BREAK (read); | |
213 | ||
e0a85af6 | 214 | CASE (read, READ_FMT_OR3) : /* e.g. or3 $dr,$sr,$hash$ulo16 */ |
8e420152 | 215 | { |
e0a85af6 DE |
216 | #define OPRND(f) par_exec->operands.fmt_or3.f |
217 | EXTRACT_FMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ | |
218 | EXTRACT_FMT_OR3_CODE | |
8e420152 DE |
219 | /* Fetch the input operands for the semantic handler. */ |
220 | OPRND (sr) = CPU (h_gr[f_r2]); | |
221 | OPRND (ulo16) = f_uimm16; | |
222 | #undef OPRND | |
223 | } | |
224 | BREAK (read); | |
225 | ||
e0a85af6 | 226 | CASE (read, READ_FMT_ADDI) : /* e.g. addi $dr,$simm8 */ |
8e420152 | 227 | { |
e0a85af6 DE |
228 | #define OPRND(f) par_exec->operands.fmt_addi.f |
229 | EXTRACT_FMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */ | |
230 | EXTRACT_FMT_ADDI_CODE | |
8e420152 DE |
231 | /* Fetch the input operands for the semantic handler. */ |
232 | OPRND (dr) = CPU (h_gr[f_r1]); | |
233 | OPRND (simm8) = f_simm8; | |
234 | #undef OPRND | |
235 | } | |
236 | BREAK (read); | |
237 | ||
e0a85af6 | 238 | CASE (read, READ_FMT_ADDV) : /* e.g. addv $dr,$sr */ |
8e420152 | 239 | { |
e0a85af6 DE |
240 | #define OPRND(f) par_exec->operands.fmt_addv.f |
241 | EXTRACT_FMT_ADDV_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
242 | EXTRACT_FMT_ADDV_CODE | |
b8641a4d DE |
243 | /* Fetch the input operands for the semantic handler. */ |
244 | OPRND (dr) = CPU (h_gr[f_r1]); | |
245 | OPRND (sr) = CPU (h_gr[f_r2]); | |
246 | #undef OPRND | |
247 | } | |
248 | BREAK (read); | |
249 | ||
e0a85af6 | 250 | CASE (read, READ_FMT_ADDV3) : /* e.g. addv3 $dr,$sr,$simm16 */ |
b8641a4d | 251 | { |
e0a85af6 DE |
252 | #define OPRND(f) par_exec->operands.fmt_addv3.f |
253 | EXTRACT_FMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ | |
254 | EXTRACT_FMT_ADDV3_CODE | |
8e420152 | 255 | /* Fetch the input operands for the semantic handler. */ |
8e420152 | 256 | OPRND (sr) = CPU (h_gr[f_r2]); |
a040908c | 257 | OPRND (simm16) = f_simm16; |
8e420152 DE |
258 | #undef OPRND |
259 | } | |
260 | BREAK (read); | |
261 | ||
e0a85af6 | 262 | CASE (read, READ_FMT_ADDX) : /* e.g. addx $dr,$sr */ |
8e420152 | 263 | { |
e0a85af6 DE |
264 | #define OPRND(f) par_exec->operands.fmt_addx.f |
265 | EXTRACT_FMT_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
266 | EXTRACT_FMT_ADDX_CODE | |
8e420152 | 267 | /* Fetch the input operands for the semantic handler. */ |
8e420152 DE |
268 | OPRND (dr) = CPU (h_gr[f_r1]); |
269 | OPRND (sr) = CPU (h_gr[f_r2]); | |
a040908c | 270 | OPRND (condbit) = CPU (h_cond); |
8e420152 DE |
271 | #undef OPRND |
272 | } | |
273 | BREAK (read); | |
274 | ||
d9e3a135 | 275 | CASE (read, READ_FMT_BC8) : /* e.g. bc.s $disp8 */ |
8e420152 | 276 | { |
e0a85af6 DE |
277 | #define OPRND(f) par_exec->operands.fmt_bc8.f |
278 | EXTRACT_FMT_BC8_VARS /* f-op1 f-r1 f-disp8 */ | |
279 | EXTRACT_FMT_BC8_CODE | |
8e420152 DE |
280 | /* Fetch the input operands for the semantic handler. */ |
281 | OPRND (condbit) = CPU (h_cond); | |
1148b104 | 282 | OPRND (disp8) = (pc & -4L) + f_disp8; |
8e420152 DE |
283 | #undef OPRND |
284 | } | |
285 | BREAK (read); | |
286 | ||
d9e3a135 | 287 | CASE (read, READ_FMT_BC24) : /* e.g. bc.l $disp24 */ |
8e420152 | 288 | { |
e0a85af6 DE |
289 | #define OPRND(f) par_exec->operands.fmt_bc24.f |
290 | EXTRACT_FMT_BC24_VARS /* f-op1 f-r1 f-disp24 */ | |
291 | EXTRACT_FMT_BC24_CODE | |
8e420152 DE |
292 | /* Fetch the input operands for the semantic handler. */ |
293 | OPRND (condbit) = CPU (h_cond); | |
b8641a4d | 294 | OPRND (disp24) = pc + f_disp24; |
8e420152 DE |
295 | #undef OPRND |
296 | } | |
297 | BREAK (read); | |
298 | ||
e0a85af6 | 299 | CASE (read, READ_FMT_BEQ) : /* e.g. beq $src1,$src2,$disp16 */ |
8e420152 | 300 | { |
e0a85af6 DE |
301 | #define OPRND(f) par_exec->operands.fmt_beq.f |
302 | EXTRACT_FMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */ | |
303 | EXTRACT_FMT_BEQ_CODE | |
8e420152 | 304 | /* Fetch the input operands for the semantic handler. */ |
8e420152 DE |
305 | OPRND (src1) = CPU (h_gr[f_r1]); |
306 | OPRND (src2) = CPU (h_gr[f_r2]); | |
a040908c | 307 | OPRND (disp16) = pc + f_disp16; |
8e420152 DE |
308 | #undef OPRND |
309 | } | |
310 | BREAK (read); | |
311 | ||
e0a85af6 | 312 | CASE (read, READ_FMT_BEQZ) : /* e.g. beqz $src2,$disp16 */ |
8e420152 | 313 | { |
e0a85af6 DE |
314 | #define OPRND(f) par_exec->operands.fmt_beqz.f |
315 | EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */ | |
316 | EXTRACT_FMT_BEQZ_CODE | |
8e420152 | 317 | /* Fetch the input operands for the semantic handler. */ |
8e420152 | 318 | OPRND (src2) = CPU (h_gr[f_r2]); |
a040908c | 319 | OPRND (disp16) = pc + f_disp16; |
8e420152 DE |
320 | #undef OPRND |
321 | } | |
322 | BREAK (read); | |
323 | ||
d9e3a135 | 324 | CASE (read, READ_FMT_BL8) : /* e.g. bl.s $disp8 */ |
8e420152 | 325 | { |
e0a85af6 DE |
326 | #define OPRND(f) par_exec->operands.fmt_bl8.f |
327 | EXTRACT_FMT_BL8_VARS /* f-op1 f-r1 f-disp8 */ | |
328 | EXTRACT_FMT_BL8_CODE | |
8e420152 | 329 | /* Fetch the input operands for the semantic handler. */ |
8e420152 | 330 | OPRND (pc) = CPU (h_pc); |
1148b104 | 331 | OPRND (disp8) = (pc & -4L) + f_disp8; |
8e420152 DE |
332 | #undef OPRND |
333 | } | |
334 | BREAK (read); | |
335 | ||
d9e3a135 | 336 | CASE (read, READ_FMT_BL24) : /* e.g. bl.l $disp24 */ |
8e420152 | 337 | { |
e0a85af6 DE |
338 | #define OPRND(f) par_exec->operands.fmt_bl24.f |
339 | EXTRACT_FMT_BL24_VARS /* f-op1 f-r1 f-disp24 */ | |
340 | EXTRACT_FMT_BL24_CODE | |
8e420152 | 341 | /* Fetch the input operands for the semantic handler. */ |
8e420152 | 342 | OPRND (pc) = CPU (h_pc); |
a040908c | 343 | OPRND (disp24) = pc + f_disp24; |
8e420152 DE |
344 | #undef OPRND |
345 | } | |
346 | BREAK (read); | |
347 | ||
d9e3a135 | 348 | CASE (read, READ_FMT_BCL8) : /* e.g. bcl.s $disp8 */ |
8e420152 | 349 | { |
e0a85af6 DE |
350 | #define OPRND(f) par_exec->operands.fmt_bcl8.f |
351 | EXTRACT_FMT_BCL8_VARS /* f-op1 f-r1 f-disp8 */ | |
352 | EXTRACT_FMT_BCL8_CODE | |
8e420152 DE |
353 | /* Fetch the input operands for the semantic handler. */ |
354 | OPRND (condbit) = CPU (h_cond); | |
8e420152 | 355 | OPRND (pc) = CPU (h_pc); |
1148b104 | 356 | OPRND (disp8) = (pc & -4L) + f_disp8; |
8e420152 DE |
357 | #undef OPRND |
358 | } | |
359 | BREAK (read); | |
360 | ||
d9e3a135 | 361 | CASE (read, READ_FMT_BCL24) : /* e.g. bcl.l $disp24 */ |
8e420152 | 362 | { |
e0a85af6 DE |
363 | #define OPRND(f) par_exec->operands.fmt_bcl24.f |
364 | EXTRACT_FMT_BCL24_VARS /* f-op1 f-r1 f-disp24 */ | |
365 | EXTRACT_FMT_BCL24_CODE | |
8e420152 DE |
366 | /* Fetch the input operands for the semantic handler. */ |
367 | OPRND (condbit) = CPU (h_cond); | |
8e420152 | 368 | OPRND (pc) = CPU (h_pc); |
a040908c | 369 | OPRND (disp24) = pc + f_disp24; |
8e420152 DE |
370 | #undef OPRND |
371 | } | |
372 | BREAK (read); | |
373 | ||
d9e3a135 | 374 | CASE (read, READ_FMT_BRA8) : /* e.g. bra.s $disp8 */ |
8e420152 | 375 | { |
e0a85af6 DE |
376 | #define OPRND(f) par_exec->operands.fmt_bra8.f |
377 | EXTRACT_FMT_BRA8_VARS /* f-op1 f-r1 f-disp8 */ | |
378 | EXTRACT_FMT_BRA8_CODE | |
8e420152 | 379 | /* Fetch the input operands for the semantic handler. */ |
1148b104 | 380 | OPRND (disp8) = (pc & -4L) + f_disp8; |
8e420152 DE |
381 | #undef OPRND |
382 | } | |
383 | BREAK (read); | |
384 | ||
d9e3a135 | 385 | CASE (read, READ_FMT_BRA24) : /* e.g. bra.l $disp24 */ |
8e420152 | 386 | { |
e0a85af6 DE |
387 | #define OPRND(f) par_exec->operands.fmt_bra24.f |
388 | EXTRACT_FMT_BRA24_VARS /* f-op1 f-r1 f-disp24 */ | |
389 | EXTRACT_FMT_BRA24_CODE | |
8e420152 | 390 | /* Fetch the input operands for the semantic handler. */ |
b8641a4d | 391 | OPRND (disp24) = pc + f_disp24; |
8e420152 DE |
392 | #undef OPRND |
393 | } | |
394 | BREAK (read); | |
395 | ||
e0a85af6 | 396 | CASE (read, READ_FMT_CMP) : /* e.g. cmp $src1,$src2 */ |
8e420152 | 397 | { |
e0a85af6 DE |
398 | #define OPRND(f) par_exec->operands.fmt_cmp.f |
399 | EXTRACT_FMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
400 | EXTRACT_FMT_CMP_CODE | |
8e420152 DE |
401 | /* Fetch the input operands for the semantic handler. */ |
402 | OPRND (src1) = CPU (h_gr[f_r1]); | |
403 | OPRND (src2) = CPU (h_gr[f_r2]); | |
404 | #undef OPRND | |
405 | } | |
406 | BREAK (read); | |
407 | ||
e0a85af6 | 408 | CASE (read, READ_FMT_CMPI) : /* e.g. cmpi $src2,$simm16 */ |
8e420152 | 409 | { |
e0a85af6 DE |
410 | #define OPRND(f) par_exec->operands.fmt_cmpi.f |
411 | EXTRACT_FMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ | |
412 | EXTRACT_FMT_CMPI_CODE | |
8e420152 | 413 | /* Fetch the input operands for the semantic handler. */ |
8e420152 | 414 | OPRND (src2) = CPU (h_gr[f_r2]); |
a040908c | 415 | OPRND (simm16) = f_simm16; |
8e420152 DE |
416 | #undef OPRND |
417 | } | |
418 | BREAK (read); | |
419 | ||
e0a85af6 | 420 | CASE (read, READ_FMT_CMPZ) : /* e.g. cmpz $src2 */ |
8e420152 | 421 | { |
e0a85af6 DE |
422 | #define OPRND(f) par_exec->operands.fmt_cmpz.f |
423 | EXTRACT_FMT_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
424 | EXTRACT_FMT_CMPZ_CODE | |
8e420152 DE |
425 | /* Fetch the input operands for the semantic handler. */ |
426 | OPRND (src2) = CPU (h_gr[f_r2]); | |
427 | #undef OPRND | |
428 | } | |
429 | BREAK (read); | |
430 | ||
e0a85af6 | 431 | CASE (read, READ_FMT_DIV) : /* e.g. div $dr,$sr */ |
8e420152 | 432 | { |
e0a85af6 DE |
433 | #define OPRND(f) par_exec->operands.fmt_div.f |
434 | EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ | |
435 | EXTRACT_FMT_DIV_CODE | |
8e420152 DE |
436 | /* Fetch the input operands for the semantic handler. */ |
437 | OPRND (dr) = CPU (h_gr[f_r1]); | |
438 | OPRND (sr) = CPU (h_gr[f_r2]); | |
439 | #undef OPRND | |
440 | } | |
441 | BREAK (read); | |
442 | ||
e0a85af6 | 443 | CASE (read, READ_FMT_JC) : /* e.g. jc $sr */ |
8e420152 | 444 | { |
e0a85af6 DE |
445 | #define OPRND(f) par_exec->operands.fmt_jc.f |
446 | EXTRACT_FMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
447 | EXTRACT_FMT_JC_CODE | |
8e420152 DE |
448 | /* Fetch the input operands for the semantic handler. */ |
449 | OPRND (condbit) = CPU (h_cond); | |
450 | OPRND (sr) = CPU (h_gr[f_r2]); | |
451 | #undef OPRND | |
452 | } | |
453 | BREAK (read); | |
454 | ||
e0a85af6 | 455 | CASE (read, READ_FMT_JL) : /* e.g. jl $sr */ |
8e420152 | 456 | { |
e0a85af6 DE |
457 | #define OPRND(f) par_exec->operands.fmt_jl.f |
458 | EXTRACT_FMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
459 | EXTRACT_FMT_JL_CODE | |
8e420152 DE |
460 | /* Fetch the input operands for the semantic handler. */ |
461 | OPRND (pc) = CPU (h_pc); | |
462 | OPRND (sr) = CPU (h_gr[f_r2]); | |
463 | #undef OPRND | |
464 | } | |
465 | BREAK (read); | |
466 | ||
e0a85af6 | 467 | CASE (read, READ_FMT_JMP) : /* e.g. jmp $sr */ |
8e420152 | 468 | { |
e0a85af6 DE |
469 | #define OPRND(f) par_exec->operands.fmt_jmp.f |
470 | EXTRACT_FMT_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
471 | EXTRACT_FMT_JMP_CODE | |
8e420152 DE |
472 | /* Fetch the input operands for the semantic handler. */ |
473 | OPRND (sr) = CPU (h_gr[f_r2]); | |
474 | #undef OPRND | |
475 | } | |
476 | BREAK (read); | |
477 | ||
e0a85af6 | 478 | CASE (read, READ_FMT_LD) : /* e.g. ld $dr,@$sr */ |
8e420152 | 479 | { |
e0a85af6 DE |
480 | #define OPRND(f) par_exec->operands.fmt_ld.f |
481 | EXTRACT_FMT_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
482 | EXTRACT_FMT_LD_CODE | |
8e420152 | 483 | /* Fetch the input operands for the semantic handler. */ |
b8a9943d | 484 | OPRND (h_memory_sr) = GETMEMSI (current_cpu, CPU (h_gr[f_r2])); |
8e420152 DE |
485 | OPRND (sr) = CPU (h_gr[f_r2]); |
486 | #undef OPRND | |
487 | } | |
488 | BREAK (read); | |
489 | ||
e0a85af6 | 490 | CASE (read, READ_FMT_LD_D) : /* e.g. ld $dr,@($slo16,$sr) */ |
8e420152 | 491 | { |
e0a85af6 DE |
492 | #define OPRND(f) par_exec->operands.fmt_ld_d.f |
493 | EXTRACT_FMT_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ | |
494 | EXTRACT_FMT_LD_D_CODE | |
8e420152 | 495 | /* Fetch the input operands for the semantic handler. */ |
a040908c | 496 | OPRND (h_memory_add__VM_sr_slo16) = GETMEMSI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16)); |
8e420152 | 497 | OPRND (sr) = CPU (h_gr[f_r2]); |
a040908c | 498 | OPRND (slo16) = f_simm16; |
8e420152 DE |
499 | #undef OPRND |
500 | } | |
501 | BREAK (read); | |
502 | ||
e0a85af6 | 503 | CASE (read, READ_FMT_LDB) : /* e.g. ldb $dr,@$sr */ |
8e420152 | 504 | { |
e0a85af6 DE |
505 | #define OPRND(f) par_exec->operands.fmt_ldb.f |
506 | EXTRACT_FMT_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
507 | EXTRACT_FMT_LDB_CODE | |
8e420152 | 508 | /* Fetch the input operands for the semantic handler. */ |
b8a9943d | 509 | OPRND (h_memory_sr) = GETMEMQI (current_cpu, CPU (h_gr[f_r2])); |
8e420152 DE |
510 | OPRND (sr) = CPU (h_gr[f_r2]); |
511 | #undef OPRND | |
512 | } | |
513 | BREAK (read); | |
514 | ||
e0a85af6 | 515 | CASE (read, READ_FMT_LDB_D) : /* e.g. ldb $dr,@($slo16,$sr) */ |
8e420152 | 516 | { |
e0a85af6 DE |
517 | #define OPRND(f) par_exec->operands.fmt_ldb_d.f |
518 | EXTRACT_FMT_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ | |
519 | EXTRACT_FMT_LDB_D_CODE | |
8e420152 | 520 | /* Fetch the input operands for the semantic handler. */ |
a040908c | 521 | OPRND (h_memory_add__VM_sr_slo16) = GETMEMQI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16)); |
8e420152 | 522 | OPRND (sr) = CPU (h_gr[f_r2]); |
a040908c | 523 | OPRND (slo16) = f_simm16; |
8e420152 DE |
524 | #undef OPRND |
525 | } | |
526 | BREAK (read); | |
527 | ||
e0a85af6 | 528 | CASE (read, READ_FMT_LDH) : /* e.g. ldh $dr,@$sr */ |
8e420152 | 529 | { |
e0a85af6 DE |
530 | #define OPRND(f) par_exec->operands.fmt_ldh.f |
531 | EXTRACT_FMT_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
532 | EXTRACT_FMT_LDH_CODE | |
8e420152 | 533 | /* Fetch the input operands for the semantic handler. */ |
b8a9943d | 534 | OPRND (h_memory_sr) = GETMEMHI (current_cpu, CPU (h_gr[f_r2])); |
8e420152 DE |
535 | OPRND (sr) = CPU (h_gr[f_r2]); |
536 | #undef OPRND | |
537 | } | |
538 | BREAK (read); | |
539 | ||
e0a85af6 | 540 | CASE (read, READ_FMT_LDH_D) : /* e.g. ldh $dr,@($slo16,$sr) */ |
8e420152 | 541 | { |
e0a85af6 DE |
542 | #define OPRND(f) par_exec->operands.fmt_ldh_d.f |
543 | EXTRACT_FMT_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ | |
544 | EXTRACT_FMT_LDH_D_CODE | |
8e420152 | 545 | /* Fetch the input operands for the semantic handler. */ |
a040908c | 546 | OPRND (h_memory_add__VM_sr_slo16) = GETMEMHI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16)); |
8e420152 | 547 | OPRND (sr) = CPU (h_gr[f_r2]); |
a040908c | 548 | OPRND (slo16) = f_simm16; |
8e420152 DE |
549 | #undef OPRND |
550 | } | |
551 | BREAK (read); | |
552 | ||
e0a85af6 | 553 | CASE (read, READ_FMT_LD_PLUS) : /* e.g. ld $dr,@$sr+ */ |
8e420152 | 554 | { |
e0a85af6 DE |
555 | #define OPRND(f) par_exec->operands.fmt_ld_plus.f |
556 | EXTRACT_FMT_LD_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
557 | EXTRACT_FMT_LD_PLUS_CODE | |
b8641a4d DE |
558 | /* Fetch the input operands for the semantic handler. */ |
559 | OPRND (h_memory_sr) = GETMEMSI (current_cpu, CPU (h_gr[f_r2])); | |
560 | OPRND (sr) = CPU (h_gr[f_r2]); | |
561 | #undef OPRND | |
562 | } | |
563 | BREAK (read); | |
564 | ||
e0a85af6 | 565 | CASE (read, READ_FMT_LD24) : /* e.g. ld24 $dr,$uimm24 */ |
b8641a4d | 566 | { |
e0a85af6 DE |
567 | #define OPRND(f) par_exec->operands.fmt_ld24.f |
568 | EXTRACT_FMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */ | |
569 | EXTRACT_FMT_LD24_CODE | |
8e420152 DE |
570 | /* Fetch the input operands for the semantic handler. */ |
571 | OPRND (uimm24) = f_uimm24; | |
572 | #undef OPRND | |
573 | } | |
574 | BREAK (read); | |
575 | ||
d9e3a135 | 576 | CASE (read, READ_FMT_LDI8) : /* e.g. ldi8 $dr,$simm8 */ |
8e420152 | 577 | { |
e0a85af6 DE |
578 | #define OPRND(f) par_exec->operands.fmt_ldi8.f |
579 | EXTRACT_FMT_LDI8_VARS /* f-op1 f-r1 f-simm8 */ | |
580 | EXTRACT_FMT_LDI8_CODE | |
8e420152 DE |
581 | /* Fetch the input operands for the semantic handler. */ |
582 | OPRND (simm8) = f_simm8; | |
583 | #undef OPRND | |
584 | } | |
585 | BREAK (read); | |
586 | ||
d9e3a135 | 587 | CASE (read, READ_FMT_LDI16) : /* e.g. ldi16 $dr,$hash$slo16 */ |
8e420152 | 588 | { |
e0a85af6 DE |
589 | #define OPRND(f) par_exec->operands.fmt_ldi16.f |
590 | EXTRACT_FMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ | |
591 | EXTRACT_FMT_LDI16_CODE | |
8e420152 DE |
592 | /* Fetch the input operands for the semantic handler. */ |
593 | OPRND (slo16) = f_simm16; | |
594 | #undef OPRND | |
595 | } | |
596 | BREAK (read); | |
597 | ||
e0a85af6 | 598 | CASE (read, READ_FMT_LOCK) : /* e.g. lock $dr,@$sr */ |
b8641a4d | 599 | { |
e0a85af6 DE |
600 | #define OPRND(f) par_exec->operands.fmt_lock.f |
601 | EXTRACT_FMT_LOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
602 | EXTRACT_FMT_LOCK_CODE | |
b8641a4d | 603 | /* Fetch the input operands for the semantic handler. */ |
cab58155 | 604 | OPRND (h_memory_sr) = GETMEMSI (current_cpu, CPU (h_gr[f_r2])); |
b8641a4d DE |
605 | OPRND (sr) = CPU (h_gr[f_r2]); |
606 | #undef OPRND | |
607 | } | |
608 | BREAK (read); | |
609 | ||
e0a85af6 | 610 | CASE (read, READ_FMT_MACHI_A) : /* e.g. machi $src1,$src2,$acc */ |
8e420152 | 611 | { |
e0a85af6 DE |
612 | #define OPRND(f) par_exec->operands.fmt_machi_a.f |
613 | EXTRACT_FMT_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */ | |
614 | EXTRACT_FMT_MACHI_A_CODE | |
8e420152 DE |
615 | /* Fetch the input operands for the semantic handler. */ |
616 | OPRND (acc) = m32rx_h_accums_get (current_cpu, f_acc); | |
617 | OPRND (src1) = CPU (h_gr[f_r1]); | |
618 | OPRND (src2) = CPU (h_gr[f_r2]); | |
619 | #undef OPRND | |
620 | } | |
621 | BREAK (read); | |
622 | ||
e0a85af6 | 623 | CASE (read, READ_FMT_MACWHI) : /* e.g. macwhi $src1,$src2 */ |
8e420152 | 624 | { |
e0a85af6 DE |
625 | #define OPRND(f) par_exec->operands.fmt_macwhi.f |
626 | EXTRACT_FMT_MACWHI_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
627 | EXTRACT_FMT_MACWHI_CODE | |
8e420152 | 628 | /* Fetch the input operands for the semantic handler. */ |
970a8fd6 | 629 | OPRND (accum) = m32rx_h_accum_get (current_cpu); |
8e420152 DE |
630 | OPRND (src1) = CPU (h_gr[f_r1]); |
631 | OPRND (src2) = CPU (h_gr[f_r2]); | |
632 | #undef OPRND | |
633 | } | |
634 | BREAK (read); | |
635 | ||
e0a85af6 | 636 | CASE (read, READ_FMT_MULHI_A) : /* e.g. mulhi $src1,$src2,$acc */ |
8e420152 | 637 | { |
e0a85af6 DE |
638 | #define OPRND(f) par_exec->operands.fmt_mulhi_a.f |
639 | EXTRACT_FMT_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */ | |
640 | EXTRACT_FMT_MULHI_A_CODE | |
83d9ce00 DE |
641 | /* Fetch the input operands for the semantic handler. */ |
642 | OPRND (src1) = CPU (h_gr[f_r1]); | |
643 | OPRND (src2) = CPU (h_gr[f_r2]); | |
644 | #undef OPRND | |
645 | } | |
646 | BREAK (read); | |
647 | ||
e0a85af6 | 648 | CASE (read, READ_FMT_MULWHI) : /* e.g. mulwhi $src1,$src2 */ |
83d9ce00 | 649 | { |
e0a85af6 DE |
650 | #define OPRND(f) par_exec->operands.fmt_mulwhi.f |
651 | EXTRACT_FMT_MULWHI_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
652 | EXTRACT_FMT_MULWHI_CODE | |
83d9ce00 DE |
653 | /* Fetch the input operands for the semantic handler. */ |
654 | OPRND (src1) = CPU (h_gr[f_r1]); | |
655 | OPRND (src2) = CPU (h_gr[f_r2]); | |
656 | #undef OPRND | |
657 | } | |
658 | BREAK (read); | |
659 | ||
e0a85af6 | 660 | CASE (read, READ_FMT_MV) : /* e.g. mv $dr,$sr */ |
83d9ce00 | 661 | { |
e0a85af6 DE |
662 | #define OPRND(f) par_exec->operands.fmt_mv.f |
663 | EXTRACT_FMT_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
664 | EXTRACT_FMT_MV_CODE | |
8e420152 DE |
665 | /* Fetch the input operands for the semantic handler. */ |
666 | OPRND (sr) = CPU (h_gr[f_r2]); | |
667 | #undef OPRND | |
668 | } | |
669 | BREAK (read); | |
670 | ||
e0a85af6 | 671 | CASE (read, READ_FMT_MVFACHI_A) : /* e.g. mvfachi $dr,$accs */ |
8e420152 | 672 | { |
e0a85af6 DE |
673 | #define OPRND(f) par_exec->operands.fmt_mvfachi_a.f |
674 | EXTRACT_FMT_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */ | |
675 | EXTRACT_FMT_MVFACHI_A_CODE | |
8e420152 DE |
676 | /* Fetch the input operands for the semantic handler. */ |
677 | OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs); | |
678 | #undef OPRND | |
679 | } | |
680 | BREAK (read); | |
681 | ||
e0a85af6 | 682 | CASE (read, READ_FMT_MVFC) : /* e.g. mvfc $dr,$scr */ |
8e420152 | 683 | { |
e0a85af6 DE |
684 | #define OPRND(f) par_exec->operands.fmt_mvfc.f |
685 | EXTRACT_FMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
686 | EXTRACT_FMT_MVFC_CODE | |
8e420152 DE |
687 | /* Fetch the input operands for the semantic handler. */ |
688 | OPRND (scr) = m32rx_h_cr_get (current_cpu, f_r2); | |
689 | #undef OPRND | |
690 | } | |
691 | BREAK (read); | |
692 | ||
e0a85af6 | 693 | CASE (read, READ_FMT_MVTACHI_A) : /* e.g. mvtachi $src1,$accs */ |
8e420152 | 694 | { |
e0a85af6 DE |
695 | #define OPRND(f) par_exec->operands.fmt_mvtachi_a.f |
696 | EXTRACT_FMT_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */ | |
697 | EXTRACT_FMT_MVTACHI_A_CODE | |
8e420152 DE |
698 | /* Fetch the input operands for the semantic handler. */ |
699 | OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs); | |
700 | OPRND (src1) = CPU (h_gr[f_r1]); | |
701 | #undef OPRND | |
702 | } | |
703 | BREAK (read); | |
704 | ||
e0a85af6 | 705 | CASE (read, READ_FMT_MVTC) : /* e.g. mvtc $sr,$dcr */ |
8e420152 | 706 | { |
e0a85af6 DE |
707 | #define OPRND(f) par_exec->operands.fmt_mvtc.f |
708 | EXTRACT_FMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
709 | EXTRACT_FMT_MVTC_CODE | |
8e420152 DE |
710 | /* Fetch the input operands for the semantic handler. */ |
711 | OPRND (sr) = CPU (h_gr[f_r2]); | |
712 | #undef OPRND | |
713 | } | |
714 | BREAK (read); | |
715 | ||
e0a85af6 | 716 | CASE (read, READ_FMT_NOP) : /* e.g. nop */ |
8e420152 | 717 | { |
e0a85af6 DE |
718 | #define OPRND(f) par_exec->operands.fmt_nop.f |
719 | EXTRACT_FMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
720 | EXTRACT_FMT_NOP_CODE | |
8e420152 DE |
721 | /* Fetch the input operands for the semantic handler. */ |
722 | #undef OPRND | |
723 | } | |
724 | BREAK (read); | |
725 | ||
e0a85af6 | 726 | CASE (read, READ_FMT_RAC_DSI) : /* e.g. rac $accd,$accs,$imm1 */ |
e0bd6e18 | 727 | { |
e0a85af6 DE |
728 | #define OPRND(f) par_exec->operands.fmt_rac_dsi.f |
729 | EXTRACT_FMT_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ | |
730 | EXTRACT_FMT_RAC_DSI_CODE | |
8e420152 | 731 | /* Fetch the input operands for the semantic handler. */ |
b8a9943d | 732 | OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs); |
e0bd6e18 | 733 | OPRND (imm1) = f_imm1; |
8e420152 DE |
734 | #undef OPRND |
735 | } | |
736 | BREAK (read); | |
737 | ||
e0a85af6 | 738 | CASE (read, READ_FMT_RTE) : /* e.g. rte */ |
8e420152 | 739 | { |
e0a85af6 DE |
740 | #define OPRND(f) par_exec->operands.fmt_rte.f |
741 | EXTRACT_FMT_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
742 | EXTRACT_FMT_RTE_CODE | |
8e420152 | 743 | /* Fetch the input operands for the semantic handler. */ |
a040908c | 744 | OPRND (h_bsm_0) = CPU (h_bsm); |
b8a9943d | 745 | OPRND (h_bie_0) = CPU (h_bie); |
a040908c | 746 | OPRND (h_bcond_0) = CPU (h_bcond); |
b8a9943d | 747 | OPRND (h_bpc_0) = CPU (h_bpc); |
8e420152 DE |
748 | #undef OPRND |
749 | } | |
750 | BREAK (read); | |
751 | ||
e0a85af6 | 752 | CASE (read, READ_FMT_SETH) : /* e.g. seth $dr,$hash$hi16 */ |
8e420152 | 753 | { |
e0a85af6 DE |
754 | #define OPRND(f) par_exec->operands.fmt_seth.f |
755 | EXTRACT_FMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */ | |
756 | EXTRACT_FMT_SETH_CODE | |
8e420152 DE |
757 | /* Fetch the input operands for the semantic handler. */ |
758 | OPRND (hi16) = f_hi16; | |
759 | #undef OPRND | |
760 | } | |
761 | BREAK (read); | |
762 | ||
e0a85af6 | 763 | CASE (read, READ_FMT_SLL3) : /* e.g. sll3 $dr,$sr,$simm16 */ |
8e420152 | 764 | { |
e0a85af6 DE |
765 | #define OPRND(f) par_exec->operands.fmt_sll3.f |
766 | EXTRACT_FMT_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ | |
767 | EXTRACT_FMT_SLL3_CODE | |
b8641a4d | 768 | /* Fetch the input operands for the semantic handler. */ |
b8641a4d | 769 | OPRND (sr) = CPU (h_gr[f_r2]); |
a040908c | 770 | OPRND (simm16) = f_simm16; |
b8641a4d DE |
771 | #undef OPRND |
772 | } | |
773 | BREAK (read); | |
774 | ||
e0a85af6 | 775 | CASE (read, READ_FMT_SLLI) : /* e.g. slli $dr,$uimm5 */ |
b8641a4d | 776 | { |
e0a85af6 DE |
777 | #define OPRND(f) par_exec->operands.fmt_slli.f |
778 | EXTRACT_FMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */ | |
779 | EXTRACT_FMT_SLLI_CODE | |
8e420152 DE |
780 | /* Fetch the input operands for the semantic handler. */ |
781 | OPRND (dr) = CPU (h_gr[f_r1]); | |
782 | OPRND (uimm5) = f_uimm5; | |
783 | #undef OPRND | |
784 | } | |
785 | BREAK (read); | |
786 | ||
e0a85af6 | 787 | CASE (read, READ_FMT_ST) : /* e.g. st $src1,@$src2 */ |
8e420152 | 788 | { |
e0a85af6 DE |
789 | #define OPRND(f) par_exec->operands.fmt_st.f |
790 | EXTRACT_FMT_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
791 | EXTRACT_FMT_ST_CODE | |
b8641a4d | 792 | /* Fetch the input operands for the semantic handler. */ |
b8641a4d | 793 | OPRND (src2) = CPU (h_gr[f_r2]); |
a040908c | 794 | OPRND (src1) = CPU (h_gr[f_r1]); |
b8641a4d DE |
795 | #undef OPRND |
796 | } | |
797 | BREAK (read); | |
798 | ||
e0a85af6 | 799 | CASE (read, READ_FMT_ST_D) : /* e.g. st $src1,@($slo16,$src2) */ |
b8641a4d | 800 | { |
e0a85af6 DE |
801 | #define OPRND(f) par_exec->operands.fmt_st_d.f |
802 | EXTRACT_FMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ | |
803 | EXTRACT_FMT_ST_D_CODE | |
8e420152 | 804 | /* Fetch the input operands for the semantic handler. */ |
a040908c | 805 | OPRND (src2) = CPU (h_gr[f_r2]); |
8e420152 DE |
806 | OPRND (slo16) = f_simm16; |
807 | OPRND (src1) = CPU (h_gr[f_r1]); | |
8e420152 DE |
808 | #undef OPRND |
809 | } | |
810 | BREAK (read); | |
811 | ||
e0a85af6 | 812 | CASE (read, READ_FMT_STB) : /* e.g. stb $src1,@$src2 */ |
b8641a4d | 813 | { |
e0a85af6 DE |
814 | #define OPRND(f) par_exec->operands.fmt_stb.f |
815 | EXTRACT_FMT_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
816 | EXTRACT_FMT_STB_CODE | |
b8641a4d | 817 | /* Fetch the input operands for the semantic handler. */ |
b8641a4d | 818 | OPRND (src2) = CPU (h_gr[f_r2]); |
a040908c | 819 | OPRND (src1) = CPU (h_gr[f_r1]); |
b8641a4d DE |
820 | #undef OPRND |
821 | } | |
822 | BREAK (read); | |
823 | ||
e0a85af6 | 824 | CASE (read, READ_FMT_STB_D) : /* e.g. stb $src1,@($slo16,$src2) */ |
8e420152 | 825 | { |
e0a85af6 DE |
826 | #define OPRND(f) par_exec->operands.fmt_stb_d.f |
827 | EXTRACT_FMT_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ | |
828 | EXTRACT_FMT_STB_D_CODE | |
b8641a4d | 829 | /* Fetch the input operands for the semantic handler. */ |
a040908c | 830 | OPRND (src2) = CPU (h_gr[f_r2]); |
b8641a4d DE |
831 | OPRND (slo16) = f_simm16; |
832 | OPRND (src1) = CPU (h_gr[f_r1]); | |
b8641a4d DE |
833 | #undef OPRND |
834 | } | |
835 | BREAK (read); | |
836 | ||
e0a85af6 | 837 | CASE (read, READ_FMT_STH) : /* e.g. sth $src1,@$src2 */ |
b8641a4d | 838 | { |
e0a85af6 DE |
839 | #define OPRND(f) par_exec->operands.fmt_sth.f |
840 | EXTRACT_FMT_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
841 | EXTRACT_FMT_STH_CODE | |
b8641a4d | 842 | /* Fetch the input operands for the semantic handler. */ |
b8641a4d | 843 | OPRND (src2) = CPU (h_gr[f_r2]); |
a040908c | 844 | OPRND (src1) = CPU (h_gr[f_r1]); |
b8641a4d DE |
845 | #undef OPRND |
846 | } | |
847 | BREAK (read); | |
848 | ||
e0a85af6 | 849 | CASE (read, READ_FMT_STH_D) : /* e.g. sth $src1,@($slo16,$src2) */ |
b8641a4d | 850 | { |
e0a85af6 DE |
851 | #define OPRND(f) par_exec->operands.fmt_sth_d.f |
852 | EXTRACT_FMT_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ | |
853 | EXTRACT_FMT_STH_D_CODE | |
b8641a4d | 854 | /* Fetch the input operands for the semantic handler. */ |
a040908c | 855 | OPRND (src2) = CPU (h_gr[f_r2]); |
b8641a4d DE |
856 | OPRND (slo16) = f_simm16; |
857 | OPRND (src1) = CPU (h_gr[f_r1]); | |
b8641a4d DE |
858 | #undef OPRND |
859 | } | |
860 | BREAK (read); | |
861 | ||
e0a85af6 | 862 | CASE (read, READ_FMT_ST_PLUS) : /* e.g. st $src1,@+$src2 */ |
b8641a4d | 863 | { |
e0a85af6 DE |
864 | #define OPRND(f) par_exec->operands.fmt_st_plus.f |
865 | EXTRACT_FMT_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
866 | EXTRACT_FMT_ST_PLUS_CODE | |
b8641a4d | 867 | /* Fetch the input operands for the semantic handler. */ |
b8641a4d | 868 | OPRND (src2) = CPU (h_gr[f_r2]); |
a040908c | 869 | OPRND (src1) = CPU (h_gr[f_r1]); |
b8641a4d DE |
870 | #undef OPRND |
871 | } | |
872 | BREAK (read); | |
873 | ||
e0a85af6 | 874 | CASE (read, READ_FMT_TRAP) : /* e.g. trap $uimm4 */ |
b8641a4d | 875 | { |
e0a85af6 DE |
876 | #define OPRND(f) par_exec->operands.fmt_trap.f |
877 | EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */ | |
878 | EXTRACT_FMT_TRAP_CODE | |
8e420152 | 879 | /* Fetch the input operands for the semantic handler. */ |
cab58155 | 880 | OPRND (pc) = CPU (h_pc); |
1148b104 | 881 | OPRND (h_cr_0) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 0)); |
8e420152 DE |
882 | OPRND (uimm4) = f_uimm4; |
883 | #undef OPRND | |
884 | } | |
885 | BREAK (read); | |
886 | ||
e0a85af6 | 887 | CASE (read, READ_FMT_UNLOCK) : /* e.g. unlock $src1,@$src2 */ |
8e420152 | 888 | { |
e0a85af6 DE |
889 | #define OPRND(f) par_exec->operands.fmt_unlock.f |
890 | EXTRACT_FMT_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
891 | EXTRACT_FMT_UNLOCK_CODE | |
8e420152 | 892 | /* Fetch the input operands for the semantic handler. */ |
cab58155 | 893 | OPRND (h_lock_0) = CPU (h_lock); |
b8a9943d | 894 | OPRND (src2) = CPU (h_gr[f_r2]); |
a040908c | 895 | OPRND (src1) = CPU (h_gr[f_r1]); |
8e420152 DE |
896 | #undef OPRND |
897 | } | |
898 | BREAK (read); | |
899 | ||
e0a85af6 | 900 | CASE (read, READ_FMT_SATB) : /* e.g. satb $dr,$sr */ |
b8641a4d | 901 | { |
e0a85af6 DE |
902 | #define OPRND(f) par_exec->operands.fmt_satb.f |
903 | EXTRACT_FMT_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ | |
904 | EXTRACT_FMT_SATB_CODE | |
b8641a4d DE |
905 | /* Fetch the input operands for the semantic handler. */ |
906 | OPRND (sr) = CPU (h_gr[f_r2]); | |
907 | #undef OPRND | |
908 | } | |
909 | BREAK (read); | |
910 | ||
e0a85af6 | 911 | CASE (read, READ_FMT_SAT) : /* e.g. sat $dr,$sr */ |
8e420152 | 912 | { |
e0a85af6 DE |
913 | #define OPRND(f) par_exec->operands.fmt_sat.f |
914 | EXTRACT_FMT_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ | |
915 | EXTRACT_FMT_SAT_CODE | |
8e420152 | 916 | /* Fetch the input operands for the semantic handler. */ |
b8a9943d | 917 | OPRND (condbit) = CPU (h_cond); |
b8641a4d | 918 | OPRND (sr) = CPU (h_gr[f_r2]); |
8e420152 DE |
919 | #undef OPRND |
920 | } | |
921 | BREAK (read); | |
922 | ||
e0a85af6 | 923 | CASE (read, READ_FMT_SADD) : /* e.g. sadd */ |
8e420152 | 924 | { |
e0a85af6 DE |
925 | #define OPRND(f) par_exec->operands.fmt_sadd.f |
926 | EXTRACT_FMT_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
927 | EXTRACT_FMT_SADD_CODE | |
8e420152 | 928 | /* Fetch the input operands for the semantic handler. */ |
1148b104 DE |
929 | OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, ((HOSTUINT) 1)); |
930 | OPRND (h_accums_0) = m32rx_h_accums_get (current_cpu, ((HOSTUINT) 0)); | |
8e420152 DE |
931 | #undef OPRND |
932 | } | |
933 | BREAK (read); | |
934 | ||
e0a85af6 | 935 | CASE (read, READ_FMT_MACWU1) : /* e.g. macwu1 $src1,$src2 */ |
8e420152 | 936 | { |
e0a85af6 DE |
937 | #define OPRND(f) par_exec->operands.fmt_macwu1.f |
938 | EXTRACT_FMT_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
939 | EXTRACT_FMT_MACWU1_CODE | |
8e420152 | 940 | /* Fetch the input operands for the semantic handler. */ |
1148b104 | 941 | OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, ((HOSTUINT) 1)); |
8e420152 DE |
942 | OPRND (src1) = CPU (h_gr[f_r1]); |
943 | OPRND (src2) = CPU (h_gr[f_r2]); | |
944 | #undef OPRND | |
945 | } | |
946 | BREAK (read); | |
947 | ||
e0a85af6 | 948 | CASE (read, READ_FMT_MULWU1) : /* e.g. mulwu1 $src1,$src2 */ |
b8641a4d | 949 | { |
e0a85af6 DE |
950 | #define OPRND(f) par_exec->operands.fmt_mulwu1.f |
951 | EXTRACT_FMT_MULWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
952 | EXTRACT_FMT_MULWU1_CODE | |
b8641a4d DE |
953 | /* Fetch the input operands for the semantic handler. */ |
954 | OPRND (src1) = CPU (h_gr[f_r1]); | |
955 | OPRND (src2) = CPU (h_gr[f_r2]); | |
956 | #undef OPRND | |
957 | } | |
958 | BREAK (read); | |
959 | ||
e0a85af6 | 960 | CASE (read, READ_FMT_SC) : /* e.g. sc */ |
b8a9943d | 961 | { |
e0a85af6 DE |
962 | #define OPRND(f) par_exec->operands.fmt_sc.f |
963 | EXTRACT_FMT_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */ | |
964 | EXTRACT_FMT_SC_CODE | |
8e420152 DE |
965 | /* Fetch the input operands for the semantic handler. */ |
966 | OPRND (condbit) = CPU (h_cond); | |
967 | #undef OPRND | |
968 | } | |
969 | BREAK (read); | |
970 | ||
971 | } | |
972 | ENDSWITCH (read) /* End of read switch. */ | |
973 | } | |
974 | ||
975 | #endif /* DEFINE_SWITCH */ |