projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| c906108c SS |
1 | /* Main header for the m32r. */ |
| 2 | ||
| 3 | #ifndef SIM_MAIN_H | |
| 4 | #define SIM_MAIN_H | |
| 5 | ||
| f0c1b768 MF |
6 | /* This is a global setting. Different cpu families can't mix-n-match -scache |
| 7 | and -pbb. However some cpu families may use -simple while others use | |
| 8 | one of -scache/-pbb. */ | |
| 9 | #define WITH_SCACHE_PBB 1 | |
| 10 | ||
| c906108c SS |
11 | #include "symcat.h" |
| 12 | #include "sim-basics.h" | |
| 13 | #include "cgen-types.h" | |
| 14 | #include "m32r-desc.h" | |
| 15 | #include "m32r-opc.h" | |
| 16 | #include "arch.h" | |
| c906108c SS |
17 | #include "sim-base.h" |
| 18 | #include "cgen-sim.h" | |
| 19 | #include "m32r-sim.h" | |
| 20 | #include "opcode/cgen.h" | |
| 21 | \f | |
| 22 | /* The _sim_cpu struct. */ | |
| 23 | ||
| 24 | struct _sim_cpu { | |
| 25 | /* sim/common cpu base. */ | |
| 26 | sim_cpu_base base; | |
| 27 | ||
| 28 | /* Static parts of cgen. */ | |
| 29 | CGEN_CPU cgen_cpu; | |
| 30 | ||
| 31 | M32R_MISC_PROFILE m32r_misc_profile; | |
| 32 | #define CPU_M32R_MISC_PROFILE(cpu) (& (cpu)->m32r_misc_profile) | |
| 33 | ||
| 34 | /* CPU specific parts go here. | |
| 35 | Note that in files that don't need to access these pieces WANT_CPU_FOO | |
| 36 | won't be defined and thus these parts won't appear. This is ok in the | |
| 37 | sense that things work. It is a source of bugs though. | |
| 38 | One has to of course be careful to not take the size of this | |
| 39 | struct and no structure members accessed in non-cpu specific files can | |
| 40 | go after here. Oh for a better language. */ | |
| 41 | #if defined (WANT_CPU_M32RBF) | |
| 42 | M32RBF_CPU_DATA cpu_data; | |
| 43 | #endif | |
| 16b47b25 NC |
44 | #if defined (WANT_CPU_M32RXF) |
| 45 | M32RXF_CPU_DATA cpu_data; | |
| 46 | #elif defined (WANT_CPU_M32R2F) | |
| 47 | M32R2F_CPU_DATA cpu_data; | |
| 48 | #endif | |
| c906108c SS |
49 | }; |
| 50 | \f | |
| 51 | /* The sim_state struct. */ | |
| 52 | ||
| 53 | struct sim_state { | |
| f95f4ed2 | 54 | sim_cpu *cpu[MAX_NR_PROCESSORS]; |
| c906108c SS |
55 | |
| 56 | CGEN_STATE cgen_state; | |
| 57 | ||
| 58 | sim_state_base base; | |
| 59 | }; | |
| 60 | \f | |
| 61 | /* Misc. */ | |
| 62 | ||
| 63 | /* Catch address exceptions. */ | |
| 64 | extern SIM_CORE_SIGNAL_FN m32r_core_signal; | |
| 65 | #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ | |
| 66 | m32r_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \ | |
| 67 | (TRANSFER), (ERROR)) | |
| 68 | ||
| 69 | /* Default memory size. */ | |
| 6edf0760 NC |
70 | #ifdef M32R_LINUX |
| 71 | #define M32R_DEFAULT_MEM_SIZE 0x2000000 /* 32M */ | |
| 72 | #else | |
| c906108c | 73 | #define M32R_DEFAULT_MEM_SIZE 0x800000 /* 8M */ |
| 6edf0760 | 74 | #endif |
| c906108c SS |
75 | |
| 76 | #endif /* SIM_MAIN_H */ |