[deliverable/binutils-gdb.git] / sim / m68hc11 / dv-m68hc11sio.c

/*  dv-m68hc11sio.c -- Simulation of the 68HC11 serial device.
    Copyright (C) 1999, 2000 Free Software Foundation, Inc.
    Written by Stephane Carrez (stcarrez@worldnet.fr)
    (From a driver model Contributed by Cygnus Solutions.)

    This file is part of the program GDB, the GNU debugger.
    
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.
    
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
    
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
    
    */


#include "sim-main.h"
#include "hw-main.h"
#include "dv-sockser.h"
#include "sim-assert.h"


/* DEVICE

        m68hc11sio - m68hc11 serial I/O

   
   DESCRIPTION

        Implements the m68hc11 serial I/O controller described in the m68hc11
        user guide. The serial I/O controller is directly connected to the CPU
        interrupt. The simulator implements:

            - baud rate emulation
            - 8-bits transfers
    
   PROPERTIES

   backend {tcp | stdio}

        Use dv-sockser TCP-port backend or stdio for backend.  Default: stdio.

   
   PORTS

   reset (input)

        Reset port. This port is only used to simulate a reset of the serial
        I/O controller. It should be connected to the RESET output of the cpu.

   */


/* port ID's */

enum
{
  RESET_PORT
};


static const struct hw_port_descriptor m68hc11sio_ports[] = 
{
  { "reset", RESET_PORT, 0, input_port, },
  { NULL, },
};


/* Serial Controller information.  */
struct m68hc11sio 
{
  enum {sio_tcp, sio_stdio} backend; /* backend */

  /* Number of cpu cycles to send a bit on the wire.  */
  unsigned long baud_cycle;

  /* Length in bits of characters sent, this includes the
     start/stop and parity bits.  Together with baud_cycle, this
     is used to find the number of cpu cycles to send/receive a data.  */
  unsigned int  data_length;

  /* Information about next character to be transmited.  */
  unsigned char tx_has_char;
  unsigned char tx_char;

  unsigned char rx_char;
  unsigned char rx_clear_scsr;
  
  /* Periodic I/O polling.  */
  struct hw_event* tx_poll_event;
  struct hw_event* rx_poll_event;
};


/* Finish off the partially created hw device.  Attach our local
   callbacks.  Wire up our port names etc.  */

static hw_io_read_buffer_method m68hc11sio_io_read_buffer;
static hw_io_write_buffer_method m68hc11sio_io_write_buffer;
static hw_port_event_method m68hc11sio_port_event;
static hw_ioctl_method m68hc11sio_ioctl;

#define M6811_SCI_FIRST_REG (M6811_BAUD)
#define M6811_SCI_LAST_REG  (M6811_SCDR)


static void
attach_m68hc11sio_regs (struct hw *me,
                        struct m68hc11sio *controller)
{
  hw_attach_address (hw_parent (me), M6811_IO_LEVEL, io_map,
                     M6811_SCI_FIRST_REG,
                     M6811_SCI_LAST_REG - M6811_SCI_FIRST_REG + 1,
		     me);

  if (hw_find_property(me, "backend") != NULL)
    {
      const char *value = hw_find_string_property(me, "backend");
      if(! strcmp(value, "tcp"))
	controller->backend = sio_tcp;
      else if(! strcmp(value, "stdio"))
	controller->backend = sio_stdio;
      else
	hw_abort (me, "illegal value for backend parameter `%s':"
                  "use tcp or stdio", value);
    }
}


static void
m68hc11sio_finish (struct hw *me)
{
  struct m68hc11sio *controller;

  controller = HW_ZALLOC (me, struct m68hc11sio);
  set_hw_data (me, controller);
  set_hw_io_read_buffer (me, m68hc11sio_io_read_buffer);
  set_hw_io_write_buffer (me, m68hc11sio_io_write_buffer);
  set_hw_ports (me, m68hc11sio_ports);
  set_hw_port_event (me, m68hc11sio_port_event);
#ifdef set_hw_ioctl
  set_hw_ioctl (me, m68hc11sio_ioctl);
#else
  me->to_ioctl = m68hc11sio_ioctl;
#endif

  /* Preset defaults.  */
  controller->backend = sio_stdio;

  /* Attach ourself to our parent bus.  */
  attach_m68hc11sio_regs (me, controller);

  /* Initialize to reset state.  */
  controller->tx_poll_event = NULL;
  controller->rx_poll_event = NULL;
  controller->tx_char       = 0;
  controller->tx_has_char   = 0;
  controller->rx_clear_scsr = 0;
  controller->rx_char       = 0;
}


/* An event arrives on an interrupt port.  */

static void
m68hc11sio_port_event (struct hw *me,
                       int my_port,
                       struct hw *source,
                       int source_port,
                       int level)
{
  SIM_DESC sd;
  struct m68hc11sio *controller;
  sim_cpu *cpu;
  unsigned8 val;
  
  controller = hw_data (me);
  sd         = hw_system (me);
  cpu        = STATE_CPU (sd, 0);  
  switch (my_port)
    {
    case RESET_PORT:
      {
	HW_TRACE ((me, "SCI reset"));

        /* Reset the state of SCI registers.  */
        val = 0;
        m68hc11sio_io_write_buffer (me, &val, io_map,
                                    (unsigned_word) M6811_BAUD, 1);
        m68hc11sio_io_write_buffer (me, &val, io_map,
                                    (unsigned_word) M6811_SCCR1, 1);
        m68hc11sio_io_write_buffer (me, &val, io_map,
                                    (unsigned_word) M6811_SCCR2, 1);
        
        cpu->ios[M6811_SCSR]    = M6811_TC | M6811_TDRE;
        controller->rx_char     = 0;
        controller->tx_char     = 0;
        controller->tx_has_char = 0;
        controller->rx_clear_scsr = 0;
        if (controller->rx_poll_event)
          {
            hw_event_queue_deschedule (me, controller->rx_poll_event);
            controller->rx_poll_event = 0;
          }
        if (controller->tx_poll_event)
          {
            hw_event_queue_deschedule (me, controller->tx_poll_event);
            controller->tx_poll_event = 0;
          }

        /* In bootstrap mode, initialize the SCI to 1200 bauds to
           simulate some initial setup by the internal rom.  */
        if (((cpu->ios[M6811_HPRIO]) & (M6811_SMOD | M6811_MDA)) == M6811_SMOD)
          {
            unsigned char val = 0x33;
            
            m68hc11sio_io_write_buffer (me, &val, io_map,
                                        (unsigned_word) M6811_BAUD, 1);
            val = 0x12;
            m68hc11sio_io_write_buffer (me, &val, io_map,
                                        (unsigned_word) M6811_SCCR2, 1);
          }
        break;
      }

    default:
      hw_abort (me, "Event on unknown port %d", my_port);
      break;
    }
}


void
m68hc11sio_rx_poll (struct hw *me, void *data)
{
  SIM_DESC sd;
  struct m68hc11sio *controller;
  sim_cpu *cpu;
  char cc;
  int cnt;
  int check_interrupt = 0;
  
  controller = hw_data (me);
  sd         = hw_system (me);
  cpu        = STATE_CPU (sd, 0);
  switch (controller->backend)
    {
    case sio_tcp:
      cnt = dv_sockser_read (sd);
      if (cnt != -1)
        {
          cc = (char) cnt;
          cnt = 1;
        }
      break;

    case sio_stdio:
      cnt = sim_io_poll_read (sd, 0 /* stdin */, &cc, 1);
      break;

    default:
      cnt = 0;
      break;
    }

  if (cnt == 1)
    {
      /* Raise the overrun flag if the previous character was not read.  */
      if (cpu->ios[M6811_SCSR] & M6811_RDRF)
        cpu->ios[M6811_SCSR] |= M6811_OR;

      cpu->ios[M6811_SCSR]     |= M6811_RDRF;
      controller->rx_char       = cc;
      controller->rx_clear_scsr = 0;
      check_interrupt = 1;
    }
  else
    {
      /* handle idle line detect here.  */
      ;
    }

  if (controller->rx_poll_event)
    {
      hw_event_queue_deschedule (me, controller->rx_poll_event);
      controller->rx_poll_event = 0;
    }

  if (cpu->ios[M6811_SCCR2] & M6811_RE)
    {
      unsigned long clock_cycle;

      /* Compute CPU clock cycles to wait for the next character.  */
      clock_cycle = controller->data_length * controller->baud_cycle;

      controller->rx_poll_event = hw_event_queue_schedule (me, clock_cycle,
                                                           m68hc11sio_rx_poll,
                                                           NULL);
    }

  if (check_interrupt)
      interrupts_update_pending (&cpu->cpu_interrupts);
}


void
m68hc11sio_tx_poll (struct hw *me, void *data)
{
  SIM_DESC sd;
  struct m68hc11sio *controller;
  sim_cpu *cpu;
  int check_interrupt = 0;
  
  controller = hw_data (me);
  sd         = hw_system (me);
  cpu        = STATE_CPU (sd, 0);

  cpu->ios[M6811_SCSR] |= M6811_TDRE;
  cpu->ios[M6811_SCSR] |= M6811_TC;
  
  /* Transmitter is enabled and we have something to sent.  */
  if ((cpu->ios[M6811_SCCR2] & M6811_TE) && controller->tx_has_char)
    {
      cpu->ios[M6811_SCSR] &= ~M6811_TDRE;
      cpu->ios[M6811_SCSR] &= ~M6811_TC;
      controller->tx_has_char = 0;
      check_interrupt = 1;
      switch (controller->backend)
        {
        case sio_tcp:
          dv_sockser_write (sd, controller->tx_char);
          break;

        case sio_stdio:
          sim_io_write_stdout (sd, &controller->tx_char, 1);
          sim_io_flush_stdout (sd);
          break;

        default:
          break;
        }
    }

  if (controller->tx_poll_event)
    {
      hw_event_queue_deschedule (me, controller->tx_poll_event);
      controller->tx_poll_event = 0;
    }
  
  if ((cpu->ios[M6811_SCCR2] & M6811_TE)
      && ((cpu->ios[M6811_SCSR] & M6811_TC) == 0))
    {
      unsigned long clock_cycle;
      
      /* Compute CPU clock cycles to wait for the next character.  */
      clock_cycle = controller->data_length * controller->baud_cycle;

      controller->tx_poll_event = hw_event_queue_schedule (me, clock_cycle,
                                                           m68hc11sio_tx_poll,
                                                           NULL);
    }

  if (check_interrupt)
      interrupts_update_pending (&cpu->cpu_interrupts);
}

/* Descriptions of the SIO I/O ports.  These descriptions are only used to
   give information of the SIO device under GDB.  */
io_reg_desc sccr2_desc[] = {
  { M6811_TIE,   "TIE  ", "Transmit Interrupt Enable" },
  { M6811_TCIE,  "TCIE ", "Transmit Complete Interrupt Enable" },
  { M6811_RIE,   "RIE  ", "Receive Interrupt Enable" },
  { M6811_ILIE,  "ILIE ", "Idle Line Interrupt Enable" },
  { M6811_TE,    "TE   ", "Transmit Enable" },
  { M6811_RE,    "RE   ", "Receive Enable" },
  { M6811_RWU,   "RWU  ", "Receiver Wake Up" },
  { M6811_SBK,   "SBRK ", "Send Break" },
  { 0,  0, 0 }
};

io_reg_desc sccr1_desc[] = {
  { M6811_R8,    "R8   ", "Receive Data bit 8" },
  { M6811_T8,    "T8   ", "Transmit Data bit 8" },
  { M6811_M,     "M    ", "SCI Character length (0=8-bits, 1=9-bits)" },
  { M6811_WAKE,  "WAKE ", "Wake up method select (0=idle, 1=addr mark" },
  { 0,  0, 0 }
};

io_reg_desc scsr_desc[] = {
  { M6811_TDRE,  "TDRE ", "Transmit Data Register Empty" },
  { M6811_TC,    "TC   ", "Transmit Complete" },
  { M6811_RDRF,  "RDRF ", "Receive Data Register Full" },
  { M6811_IDLE,  "IDLE ", "Idle Line Detect" },
  { M6811_OR,    "OR   ", "Overrun Error" },
  { M6811_NF,    "NF   ", "Noise Flag" },
  { M6811_FE,    "FE   ", "Framing Error" },
  { 0,  0, 0 }
};

io_reg_desc baud_desc[] = {
  { M6811_TCLR,  "TCLR ", "Clear baud rate (test mode)" },
  { M6811_SCP1,  "SCP1 ", "SCI baud rate prescaler select (SCP1)" },
  { M6811_SCP0,  "SCP0 ", "SCI baud rate prescaler select (SCP0)" },
  { M6811_RCKB,  "RCKB ", "Baur Rate Clock Check (test mode)" },
  { M6811_SCR2,  "SCR2 ", "SCI Baud rate select (SCR2)" },
  { M6811_SCR1,  "SCR1 ", "SCI Baud rate select (SCR1)" },
  { M6811_SCR0,  "SCR0 ", "SCI Baud rate select (SCR0)" },
  { 0,  0, 0 }
};

static void
m68hc11sio_info (struct hw *me)
{
  SIM_DESC sd;
  uint16 base = 0;
  sim_cpu *cpu;
  struct m68hc11sio *controller;
  uint8 val;
  long clock_cycle;
  
  sd = hw_system (me);
  cpu = STATE_CPU (sd, 0);
  controller = hw_data (me);
  
  sim_io_printf (sd, "M68HC11 SIO:\n");

  base = cpu_get_io_base (cpu);

  val  = cpu->ios[M6811_BAUD];
  print_io_byte (sd, "BAUD ", baud_desc, val, base + M6811_BAUD);
  sim_io_printf (sd, " (%ld baud)\n",
                 (cpu->cpu_frequency / 4) / controller->baud_cycle);

  val = cpu->ios[M6811_SCCR1];
  print_io_byte (sd, "SCCR1", sccr1_desc, val, base + M6811_SCCR1);
  sim_io_printf (sd, "  (%d bits) (%dN1)\n",
                 controller->data_length, controller->data_length - 2);

  val = cpu->ios[M6811_SCCR2];
  print_io_byte (sd, "SCCR2", sccr2_desc, val, base + M6811_SCCR2);
  sim_io_printf (sd, "\n");

  val = cpu->ios[M6811_SCSR];
  print_io_byte (sd, "SCSR ", scsr_desc, val, base + M6811_SCSR);
  sim_io_printf (sd, "\n");

  clock_cycle = controller->data_length * controller->baud_cycle;
  
  if (controller->tx_poll_event)
    {
      signed64 t;
      int n;

      t = hw_event_remain_time (me, controller->tx_poll_event);
      n = (clock_cycle - t) / controller->baud_cycle;
      n = controller->data_length - n;
      sim_io_printf (sd, "  Transmit finished in %s (%d bit%s)\n",
		     cycle_to_string (cpu, t), n, (n > 1 ? "s" : ""));
    }
  if (controller->rx_poll_event)
    {
      signed64 t;

      t = hw_event_remain_time (me, controller->rx_poll_event);
      sim_io_printf (sd, "  Receive finished in %s\n",
		     cycle_to_string (cpu, t));
    }
  
}

static int
m68hc11sio_ioctl (struct hw *me,
                  hw_ioctl_request request,
                  va_list ap)
{
  m68hc11sio_info (me);
  return 0;
}

/* generic read/write */

static unsigned
m68hc11sio_io_read_buffer (struct hw *me,
                           void *dest,
                           int space,
                           unsigned_word base,
                           unsigned nr_bytes)
{
  SIM_DESC sd;
  struct m68hc11sio *controller;
  sim_cpu *cpu;
  unsigned8 val;
  
  HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));

  sd  = hw_system (me);
  cpu = STATE_CPU (sd, 0);
  controller = hw_data (me);

  switch (base)
    {
    case M6811_SCSR:
      controller->rx_clear_scsr = cpu->ios[M6811_SCSR]
        & (M6811_RDRF | M6811_IDLE | M6811_OR | M6811_NF | M6811_FE);
      
    case M6811_BAUD:
    case M6811_SCCR1:
    case M6811_SCCR2:
      val = cpu->ios[base];
      break;
      
    case M6811_SCDR:
      if (controller->rx_clear_scsr)
        {
          cpu->ios[M6811_SCSR] &= ~controller->rx_clear_scsr;
        }
      val = controller->rx_char;
      break;
      
    default:
      return 0;
    }
  *((unsigned8*) dest) = val;
  return 1;
}

static unsigned
m68hc11sio_io_write_buffer (struct hw *me,
                            const void *source,
                            int space,
                            unsigned_word base,
                            unsigned nr_bytes)
{
  SIM_DESC sd;
  struct m68hc11sio *controller;
  sim_cpu *cpu;
  unsigned8 val;

  HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));

  sd  = hw_system (me);
  cpu = STATE_CPU (sd, 0);
  controller = hw_data (me);
  
  val = *((const unsigned8*) source);
  switch (base)
    {
    case M6811_BAUD:
      {
        long divisor;
        long baud;

        cpu->ios[M6811_BAUD] = val;        
        switch (val & (M6811_SCP1|M6811_SCP0))
          {
          case M6811_BAUD_DIV_1:
            divisor = 1 * 16;
            break;

          case M6811_BAUD_DIV_3:
            divisor = 3 * 16;
            break;

          case M6811_BAUD_DIV_4:
            divisor = 4 * 16;
            break;

          default:
          case M6811_BAUD_DIV_13:
            divisor = 13 * 16;
            break;
          }
        val &= (M6811_SCR2|M6811_SCR1|M6811_SCR0);
        divisor *= (1 << val);

        baud = (cpu->cpu_frequency / 4) / divisor;

        HW_TRACE ((me, "divide rate %ld, baud rate %ld",
                   divisor, baud));

        controller->baud_cycle = divisor;
      }
      break;
      
    case M6811_SCCR1:
      {
        if (val & M6811_M)
          controller->data_length = 11;
        else
          controller->data_length = 10;

        cpu->ios[M6811_SCCR1] = val;
      }
      break;
      
    case M6811_SCCR2:
      if ((val & M6811_RE) == 0)
        {
          val &= ~(M6811_RDRF|M6811_IDLE|M6811_OR|M6811_NF|M6811_NF);
          val |= (cpu->ios[M6811_SCCR2]
                  & (M6811_RDRF|M6811_IDLE|M6811_OR|M6811_NF|M6811_NF));
          cpu->ios[M6811_SCCR2] = val;
          break;
        }

      /* Activate reception.  */
      if (controller->rx_poll_event == 0)
        {
          long clock_cycle;
          
          /* Compute CPU clock cycles to wait for the next character.  */
          clock_cycle = controller->data_length * controller->baud_cycle;

          controller->rx_poll_event = hw_event_queue_schedule (me, clock_cycle,
                                                               m68hc11sio_rx_poll,
                                                               NULL);
        }      
      cpu->ios[M6811_SCCR2] = val;
      interrupts_update_pending (&cpu->cpu_interrupts);
      break;

      /* No effect.  */
    case M6811_SCSR:
      return 1;
      
    case M6811_SCDR:
      if (!(cpu->ios[M6811_SCSR] & M6811_TDRE))
        {
          return 0;
        }

      controller->tx_char     = val;
      controller->tx_has_char = 1;
      if ((cpu->ios[M6811_SCCR2] & M6811_TE)
          && controller->tx_poll_event == 0)
        {
          m68hc11sio_tx_poll (me, NULL);
        }
      return 1;
      
    default:
      return 0;
    }
  return nr_bytes;
}     


const struct hw_descriptor dv_m68hc11sio_descriptor[] = {
  { "m68hc11sio", m68hc11sio_finish, },
  { NULL },
};
Commit	Line	Data
e0709f50 AC	1	/* dv-m68hc11sio.c -- Simulation of the 68HC11 serial device.
	2	Copyright (C) 1999, 2000 Free Software Foundation, Inc.
	3	Written by Stephane Carrez (stcarrez@worldnet.fr)
	4	(From a driver model Contributed by Cygnus Solutions.)
	5
	6	This file is part of the program GDB, the GNU debugger.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
	20	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	21
	22	*/
	23
	24
	25	#include "sim-main.h"
	26	#include "hw-main.h"
	27	#include "dv-sockser.h"
	28	#include "sim-assert.h"
	29
	30
	31	/* DEVICE
	32
	33	m68hc11sio - m68hc11 serial I/O
	34
	35
	36	DESCRIPTION
	37
	38	Implements the m68hc11 serial I/O controller described in the m68hc11
	39	user guide. The serial I/O controller is directly connected to the CPU
	40	interrupt. The simulator implements:
	41
	42	- baud rate emulation
	43	- 8-bits transfers
	44
	45	PROPERTIES
	46
	47	backend {tcp \| stdio}
	48
	49	Use dv-sockser TCP-port backend or stdio for backend. Default: stdio.
	50
	51
	52	PORTS
	53
	54	reset (input)
	55
	56	Reset port. This port is only used to simulate a reset of the serial
	57	I/O controller. It should be connected to the RESET output of the cpu.
	58
	59	*/
	60
	61
	62
	63	/* port ID's */
	64
65	enum
66	{
67	RESET_PORT
68	};
69
70
71	static const struct hw_port_descriptor m68hc11sio_ports[] =
72	{
73	{ "reset", RESET_PORT, 0, input_port, },
74	{ NULL, },
75	};
76
77
78	/* Serial Controller information. */
79	struct m68hc11sio
80	{
81	enum {sio_tcp, sio_stdio} backend; /* backend */
82
83	/* Number of cpu cycles to send a bit on the wire. */
84	unsigned long baud_cycle;
85
86	/* Length in bits of characters sent, this includes the
87	start/stop and parity bits. Together with baud_cycle, this
88	is used to find the number of cpu cycles to send/receive a data. */
89	unsigned int data_length;
90
91	/* Information about next character to be transmited. */
92	unsigned char tx_has_char;
93	unsigned char tx_char;
94
95	unsigned char rx_char;
96	unsigned char rx_clear_scsr;
97
98	/* Periodic I/O polling. */
99	struct hw_event* tx_poll_event;
100	struct hw_event* rx_poll_event;
101	};
102
103
104
105	/* Finish off the partially created hw device. Attach our local
106	callbacks. Wire up our port names etc. */
107
108	static hw_io_read_buffer_method m68hc11sio_io_read_buffer;
109	static hw_io_write_buffer_method m68hc11sio_io_write_buffer;
110	static hw_port_event_method m68hc11sio_port_event;
111	static hw_ioctl_method m68hc11sio_ioctl;
112
113	#define M6811_SCI_FIRST_REG (M6811_BAUD)
114	#define M6811_SCI_LAST_REG (M6811_SCDR)
115
116
117	static void
118	attach_m68hc11sio_regs (struct hw *me,
119	struct m68hc11sio *controller)
120	{
63348d04	121	hw_attach_address (hw_parent (me), M6811_IO_LEVEL, io_map,
e0709f50 AC	122	M6811_SCI_FIRST_REG,
	123	M6811_SCI_LAST_REG - M6811_SCI_FIRST_REG + 1,
	124	me);
	125
	126	if (hw_find_property(me, "backend") != NULL)
	127	{
	128	const char *value = hw_find_string_property(me, "backend");
	129	if(! strcmp(value, "tcp"))
	130	controller->backend = sio_tcp;
	131	else if(! strcmp(value, "stdio"))
	132	controller->backend = sio_stdio;
	133	else
	134	hw_abort (me, "illegal value for backend parameter `%s':"
	135	"use tcp or stdio", value);
	136	}
	137	}
	138
	139
	140	static void
	141	m68hc11sio_finish (struct hw *me)
	142	{
	143	struct m68hc11sio *controller;
	144
	145	controller = HW_ZALLOC (me, struct m68hc11sio);
e0709f50 AC	146	set_hw_data (me, controller);
	147	set_hw_io_read_buffer (me, m68hc11sio_io_read_buffer);
	148	set_hw_io_write_buffer (me, m68hc11sio_io_write_buffer);
	149	set_hw_ports (me, m68hc11sio_ports);
	150	set_hw_port_event (me, m68hc11sio_port_event);
	151	#ifdef set_hw_ioctl
	152	set_hw_ioctl (me, m68hc11sio_ioctl);
	153	#else
	154	me->to_ioctl = m68hc11sio_ioctl;
	155	#endif
	156
	157	/* Preset defaults. */
	158	controller->backend = sio_stdio;
	159
	160	/* Attach ourself to our parent bus. */
	161	attach_m68hc11sio_regs (me, controller);
	162
	163	/* Initialize to reset state. */
	164	controller->tx_poll_event = NULL;
	165	controller->rx_poll_event = NULL;
	166	controller->tx_char = 0;
	167	controller->tx_has_char = 0;
	168	controller->rx_clear_scsr = 0;
	169	controller->rx_char = 0;
	170	}
	171
	172
	173
	174	/* An event arrives on an interrupt port. */
	175
	176	static void
	177	m68hc11sio_port_event (struct hw *me,
	178	int my_port,
	179	struct hw *source,
	180	int source_port,
	181	int level)
	182	{
	183	SIM_DESC sd;
	184	struct m68hc11sio *controller;
	185	sim_cpu *cpu;
	186	unsigned8 val;
	187
	188	controller = hw_data (me);
	189	sd = hw_system (me);
	190	cpu = STATE_CPU (sd, 0);
	191	switch (my_port)
	192	{
	193	case RESET_PORT:
	194	{
	195	HW_TRACE ((me, "SCI reset"));
	196
	197	/* Reset the state of SCI registers. */
	198	val = 0;
	199	m68hc11sio_io_write_buffer (me, &val, io_map,
	200	(unsigned_word) M6811_BAUD, 1);
	201	m68hc11sio_io_write_buffer (me, &val, io_map,
	202	(unsigned_word) M6811_SCCR1, 1);
	203	m68hc11sio_io_write_buffer (me, &val, io_map,
	204	(unsigned_word) M6811_SCCR2, 1);
	205
	206	cpu->ios[M6811_SCSR] = M6811_TC \| M6811_TDRE;
	207	controller->rx_char = 0;
	208	controller->tx_char = 0;
	209	controller->tx_has_char = 0;
210	controller->rx_clear_scsr = 0;
211	if (controller->rx_poll_event)
212	{
213	hw_event_queue_deschedule (me, controller->rx_poll_event);
214	controller->rx_poll_event = 0;
215	}
216	if (controller->tx_poll_event)
217	{
218	hw_event_queue_deschedule (me, controller->tx_poll_event);
219	controller->tx_poll_event = 0;
220	}
221
222	/* In bootstrap mode, initialize the SCI to 1200 bauds to
223	simulate some initial setup by the internal rom. */
224	if (((cpu->ios[M6811_HPRIO]) & (M6811_SMOD \| M6811_MDA)) == M6811_SMOD)
225	{
226	unsigned char val = 0x33;
227
228	m68hc11sio_io_write_buffer (me, &val, io_map,
229	(unsigned_word) M6811_BAUD, 1);
230	val = 0x12;
231	m68hc11sio_io_write_buffer (me, &val, io_map,
232	(unsigned_word) M6811_SCCR2, 1);
233	}
234	break;
235	}
236
237	default:
238	hw_abort (me, "Event on unknown port %d", my_port);
239	break;
240	}
241	}
242
243
244	void
245	m68hc11sio_rx_poll (struct hw me, void data)
246	{
247	SIM_DESC sd;
248	struct m68hc11sio *controller;
249	sim_cpu *cpu;
250	char cc;
251	int cnt;
252	int check_interrupt = 0;
253
254	controller = hw_data (me);
255	sd = hw_system (me);
256	cpu = STATE_CPU (sd, 0);
257	switch (controller->backend)
258	{
259	case sio_tcp:
260	cnt = dv_sockser_read (sd);
261	if (cnt != -1)
262	{
263	cc = (char) cnt;
264	cnt = 1;
265	}
266	break;
267
268	case sio_stdio:
269	cnt = sim_io_poll_read (sd, 0 /* stdin */, &cc, 1);
270	break;
271
272	default:
273	cnt = 0;
274	break;
275	}
276
277	if (cnt == 1)
278	{
279	/* Raise the overrun flag if the previous character was not read. */
280	if (cpu->ios[M6811_SCSR] & M6811_RDRF)
281	cpu->ios[M6811_SCSR] \|= M6811_OR;
282
283	cpu->ios[M6811_SCSR] \|= M6811_RDRF;
284	controller->rx_char = cc;
285	controller->rx_clear_scsr = 0;
286	check_interrupt = 1;
287	}
288	else
289	{
290	/* handle idle line detect here. */
291	;
292	}
293
294	if (controller->rx_poll_event)
295	{
296	hw_event_queue_deschedule (me, controller->rx_poll_event);
297	controller->rx_poll_event = 0;
298	}
299
300	if (cpu->ios[M6811_SCCR2] & M6811_RE)
301	{
302	unsigned long clock_cycle;
303
304	/* Compute CPU clock cycles to wait for the next character. */
305	clock_cycle = controller->data_length * controller->baud_cycle;
306
307	controller->rx_poll_event = hw_event_queue_schedule (me, clock_cycle,
308	m68hc11sio_rx_poll,
309	NULL);
310	}
311
312	if (check_interrupt)
313	interrupts_update_pending (&cpu->cpu_interrupts);
314	}
315
316
317	void
318	m68hc11sio_tx_poll (struct hw me, void data)
319	{
320	SIM_DESC sd;
321	struct m68hc11sio *controller;
322	sim_cpu *cpu;
323	int check_interrupt = 0;
324
325	controller = hw_data (me);
326	sd = hw_system (me);
327	cpu = STATE_CPU (sd, 0);
328
329	cpu->ios[M6811_SCSR] \|= M6811_TDRE;
330	cpu->ios[M6811_SCSR] \|= M6811_TC;
331
332	/* Transmitter is enabled and we have something to sent. */
333	if ((cpu->ios[M6811_SCCR2] & M6811_TE) && controller->tx_has_char)
334	{
335	cpu->ios[M6811_SCSR] &= ~M6811_TDRE;
336	cpu->ios[M6811_SCSR] &= ~M6811_TC;
337	controller->tx_has_char = 0;
338	check_interrupt = 1;
339	switch (controller->backend)
340	{
341	case sio_tcp:
342	dv_sockser_write (sd, controller->tx_char);
343	break;
344
345	case sio_stdio:
346	sim_io_write_stdout (sd, &controller->tx_char, 1);
347	sim_io_flush_stdout (sd);
348	break;
349
350	default:
351	break;
352	}
353	}
354
355	if (controller->tx_poll_event)
356	{
357	hw_event_queue_deschedule (me, controller->tx_poll_event);
358	controller->tx_poll_event = 0;
359	}
360
361	if ((cpu->ios[M6811_SCCR2] & M6811_TE)
362	&& ((cpu->ios[M6811_SCSR] & M6811_TC) == 0))
363	{
364	unsigned long clock_cycle;
365
366	/* Compute CPU clock cycles to wait for the next character. */
367	clock_cycle = controller->data_length * controller->baud_cycle;
368
369	controller->tx_poll_event = hw_event_queue_schedule (me, clock_cycle,
370	m68hc11sio_tx_poll,
371	NULL);
372	}
373
374	if (check_interrupt)
375	interrupts_update_pending (&cpu->cpu_interrupts);
376	}
377
378	/* Descriptions of the SIO I/O ports. These descriptions are only used to
379	give information of the SIO device under GDB. */
380	io_reg_desc sccr2_desc[] = {
381	{ M6811_TIE, "TIE ", "Transmit Interrupt Enable" },
382	{ M6811_TCIE, "TCIE ", "Transmit Complete Interrupt Enable" },
383	{ M6811_RIE, "RIE ", "Receive Interrupt Enable" },
384	{ M6811_ILIE, "ILIE ", "Idle Line Interrupt Enable" },
385	{ M6811_TE, "TE ", "Transmit Enable" },
386	{ M6811_RE, "RE ", "Receive Enable" },
387	{ M6811_RWU, "RWU ", "Receiver Wake Up" },
388	{ M6811_SBK, "SBRK ", "Send Break" },
389	{ 0, 0, 0 }
390	};
391
392	io_reg_desc sccr1_desc[] = {
393	{ M6811_R8, "R8 ", "Receive Data bit 8" },
394	{ M6811_T8, "T8 ", "Transmit Data bit 8" },
395	{ M6811_M, "M ", "SCI Character length (0=8-bits, 1=9-bits)" },
396	{ M6811_WAKE, "WAKE ", "Wake up method select (0=idle, 1=addr mark" },
397	{ 0, 0, 0 }
398	};
399
400	io_reg_desc scsr_desc[] = {
401	{ M6811_TDRE, "TDRE ", "Transmit Data Register Empty" },
402	{ M6811_TC, "TC ", "Transmit Complete" },
403	{ M6811_RDRF, "RDRF ", "Receive Data Register Full" },
404	{ M6811_IDLE, "IDLE ", "Idle Line Detect" },
405	{ M6811_OR, "OR ", "Overrun Error" },
406	{ M6811_NF, "NF ", "Noise Flag" },
407	{ M6811_FE, "FE ", "Framing Error" },
408	{ 0, 0, 0 }
409	};
410
411	io_reg_desc baud_desc[] = {
412	{ M6811_TCLR, "TCLR ", "Clear baud rate (test mode)" },
413	{ M6811_SCP1, "SCP1 ", "SCI baud rate prescaler select (SCP1)" },
414	{ M6811_SCP0, "SCP0 ", "SCI baud rate prescaler select (SCP0)" },
415	{ M6811_RCKB, "RCKB ", "Baur Rate Clock Check (test mode)" },
416	{ M6811_SCR2, "SCR2 ", "SCI Baud rate select (SCR2)" },
417	{ M6811_SCR1, "SCR1 ", "SCI Baud rate select (SCR1)" },
418	{ M6811_SCR0, "SCR0 ", "SCI Baud rate select (SCR0)" },
419	{ 0, 0, 0 }
420	};
421
422	static void
423	m68hc11sio_info (struct hw *me)
424	{
425	SIM_DESC sd;
426	uint16 base = 0;
427	sim_cpu *cpu;
428	struct m68hc11sio *controller;
429	uint8 val;
430	long clock_cycle;
431
432	sd = hw_system (me);
433	cpu = STATE_CPU (sd, 0);
434	controller = hw_data (me);
435
436	sim_io_printf (sd, "M68HC11 SIO:\n");
437
438	base = cpu_get_io_base (cpu);
439
440	val = cpu->ios[M6811_BAUD];
441	print_io_byte (sd, "BAUD ", baud_desc, val, base + M6811_BAUD);
442	sim_io_printf (sd, " (%ld baud)\n",
443	(cpu->cpu_frequency / 4) / controller->baud_cycle);
444
445	val = cpu->ios[M6811_SCCR1];
446	print_io_byte (sd, "SCCR1", sccr1_desc, val, base + M6811_SCCR1);
447	sim_io_printf (sd, " (%d bits) (%dN1)\n",
448	controller->data_length, controller->data_length - 2);
449
450	val = cpu->ios[M6811_SCCR2];
451	print_io_byte (sd, "SCCR2", sccr2_desc, val, base + M6811_SCCR2);
452	sim_io_printf (sd, "\n");
453
454	val = cpu->ios[M6811_SCSR];
455	print_io_byte (sd, "SCSR ", scsr_desc, val, base + M6811_SCSR);
456	sim_io_printf (sd, "\n");
457
458	clock_cycle = controller->data_length * controller->baud_cycle;
459
460	if (controller->tx_poll_event)
461	{
462	signed64 t;
463	int n;
464
465	t = hw_event_remain_time (me, controller->tx_poll_event);
466	n = (clock_cycle - t) / controller->baud_cycle;
467	n = controller->data_length - n;
2990a9f4 SC	468	sim_io_printf (sd, " Transmit finished in %s (%d bit%s)\n",
2990a9f4 SC	469	cycle_to_string (cpu, t), n, (n > 1 ? "s" : ""));
e0709f50 AC	470	}
	471	if (controller->rx_poll_event)
	472	{
	473	signed64 t;
	474
	475	t = hw_event_remain_time (me, controller->rx_poll_event);
2990a9f4 SC	476	sim_io_printf (sd, " Receive finished in %s\n",
2990a9f4 SC	477	cycle_to_string (cpu, t));
e0709f50 AC	478	}
	479
	480	}
	481
	482	static int
	483	m68hc11sio_ioctl (struct hw *me,
	484	hw_ioctl_request request,
	485	va_list ap)
	486	{
	487	m68hc11sio_info (me);
	488	return 0;
	489	}
	490
	491	/* generic read/write */
	492
	493	static unsigned
	494	m68hc11sio_io_read_buffer (struct hw *me,
	495	void *dest,
	496	int space,
	497	unsigned_word base,
	498	unsigned nr_bytes)
	499	{
	500	SIM_DESC sd;
	501	struct m68hc11sio *controller;
	502	sim_cpu *cpu;
	503	unsigned8 val;
	504
	505	HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
	506
	507	sd = hw_system (me);
	508	cpu = STATE_CPU (sd, 0);
	509	controller = hw_data (me);
	510
	511	switch (base)
	512	{
	513	case M6811_SCSR:
	514	controller->rx_clear_scsr = cpu->ios[M6811_SCSR]
	515	& (M6811_RDRF \| M6811_IDLE \| M6811_OR \| M6811_NF \| M6811_FE);
	516
	517	case M6811_BAUD:
	518	case M6811_SCCR1:
	519	case M6811_SCCR2:
	520	val = cpu->ios[base];
	521	break;
	522
	523	case M6811_SCDR:
	524	if (controller->rx_clear_scsr)
	525	{
	526	cpu->ios[M6811_SCSR] &= ~controller->rx_clear_scsr;
	527	}
	528	val = controller->rx_char;
	529	break;
	530
	531	default:
	532	return 0;
	533	}
	534	((unsigned8) dest) = val;
	535	return 1;
	536	}
	537
	538	static unsigned
	539	m68hc11sio_io_write_buffer (struct hw *me,
	540	const void *source,
	541	int space,
542	unsigned_word base,
543	unsigned nr_bytes)
544	{
545	SIM_DESC sd;
546	struct m68hc11sio *controller;
547	sim_cpu *cpu;
548	unsigned8 val;
549
550	HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
551
552	sd = hw_system (me);
553	cpu = STATE_CPU (sd, 0);
554	controller = hw_data (me);
555
556	val = ((const unsigned8) source);
557	switch (base)
558	{
559	case M6811_BAUD:
560	{
561	long divisor;
562	long baud;
563
564	cpu->ios[M6811_BAUD] = val;
565	switch (val & (M6811_SCP1\|M6811_SCP0))
566	{
567	case M6811_BAUD_DIV_1:
568	divisor = 1 * 16;
569	break;
570
571	case M6811_BAUD_DIV_3:
572	divisor = 3 * 16;
573	break;
574
575	case M6811_BAUD_DIV_4:
576	divisor = 4 * 16;
577	break;
578
579	default:
580	case M6811_BAUD_DIV_13:
581	divisor = 13 * 16;
582	break;
583	}
584	val &= (M6811_SCR2\|M6811_SCR1\|M6811_SCR0);
585	divisor *= (1 << val);
586
587	baud = (cpu->cpu_frequency / 4) / divisor;
588
589	HW_TRACE ((me, "divide rate %ld, baud rate %ld",
590	divisor, baud));
591
592	controller->baud_cycle = divisor;
593	}
594	break;
595
596	case M6811_SCCR1:
597	{
598	if (val & M6811_M)
599	controller->data_length = 11;
600	else
601	controller->data_length = 10;
602
603	cpu->ios[M6811_SCCR1] = val;
604	}
605	break;
606
607	case M6811_SCCR2:
608	if ((val & M6811_RE) == 0)
609	{
610	val &= ~(M6811_RDRF\|M6811_IDLE\|M6811_OR\|M6811_NF\|M6811_NF);
611	val \|= (cpu->ios[M6811_SCCR2]
612	& (M6811_RDRF\|M6811_IDLE\|M6811_OR\|M6811_NF\|M6811_NF));
613	cpu->ios[M6811_SCCR2] = val;
614	break;
615	}
616
617	/* Activate reception. */
618	if (controller->rx_poll_event == 0)
619	{
620	long clock_cycle;
621
622	/* Compute CPU clock cycles to wait for the next character. */
623	clock_cycle = controller->data_length * controller->baud_cycle;
624
625	controller->rx_poll_event = hw_event_queue_schedule (me, clock_cycle,
626	m68hc11sio_rx_poll,
627	NULL);
628	}
629	cpu->ios[M6811_SCCR2] = val;
630	interrupts_update_pending (&cpu->cpu_interrupts);
631	break;
632
633	/* No effect. */
634	case M6811_SCSR:
635	return 1;
636
637	case M6811_SCDR:
638	if (!(cpu->ios[M6811_SCSR] & M6811_TDRE))
639	{
640	return 0;
641	}
642
643	controller->tx_char = val;
644	controller->tx_has_char = 1;
645	if ((cpu->ios[M6811_SCCR2] & M6811_TE)
646	&& controller->tx_poll_event == 0)
647	{
648	m68hc11sio_tx_poll (me, NULL);
649	}
650	return 1;
651
652	default:
653	return 0;
654	}
655	return nr_bytes;
656	}
657
658
659	const struct hw_descriptor dv_m68hc11sio_descriptor[] = {
660	{ "m68hc11sio", m68hc11sio_finish, },
661	{ NULL },
662	};
663