[deliverable/binutils-gdb.git] / sim / m68hc11 / sim-main.h

/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   Copyright (C) 1999-2015 Free Software Foundation, Inc.
   Written by Stephane Carrez (stcarrez@nerim.fr)

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef _SIM_MAIN_H
#define _SIM_MAIN_H

#define WITH_WATCHPOINTS 1
#define SIM_HANDLES_LMA 1

#include "sim-basics.h"
#include "sim-signal.h"
#include "sim-base.h"

#include "bfd.h"

#include "opcode/m68hc11.h"

#include "gdb/callback.h"
#include "gdb/remote-sim.h"
#include "opcode/m68hc11.h"
#include "sim-types.h"

typedef unsigned8 uint8;
typedef unsigned16 uint16;
typedef signed16 int16;
typedef unsigned32 uint32;
typedef signed32 int32;
typedef unsigned64 uint64;
typedef signed64 int64;

struct _sim_cpu;

#include "interrupts.h"
#include <setjmp.h>

/* Specifies the level of mapping for the IO, EEprom, nvram and external
   RAM.  IO registers are mapped over everything and the external RAM
   is last (ie, it can be hidden by everything above it in the list).  */
enum m68hc11_map_level
{
  M6811_IO_LEVEL,
  M6811_EEPROM_LEVEL,
  M6811_NVRAM_LEVEL,
  M6811_RAM_LEVEL
};

enum cpu_type
{
  CPU_M6811,
  CPU_M6812
};

#define X_REGNUM 	0
#define D_REGNUM	1
#define Y_REGNUM        2
#define SP_REGNUM 	3
#define PC_REGNUM 	4
#define A_REGNUM        5
#define B_REGNUM        6
#define PSW_REGNUM 	7
#define PAGE_REGNUM     8
#define Z_REGNUM        9

typedef struct m6811_regs {
    unsigned short      d;
    unsigned short      ix;
    unsigned short      iy;
    unsigned short      sp;
    unsigned short      pc;
    unsigned char       ccr;
  unsigned short      page;
} m6811_regs;


/* Description of 68HC11 IO registers.  Such description is only provided
   for the info command to display the current setting of IO registers
   from GDB.  */
struct io_reg_desc
{
  int        mask;
  const char *short_name;
  const char *long_name;
};
typedef struct io_reg_desc io_reg_desc;

extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
			       int mode);
extern void print_io_byte (SIM_DESC sd, const char *name,
			   io_reg_desc *desc, uint8 val, uint16 addr);
extern void print_io_word (SIM_DESC sd, const char *name,
			   io_reg_desc *desc, uint16 val, uint16 addr);


/* List of special 68HC11&68HC12 instructions that are not handled by the
   'gencode.c' generator.  These complex instructions are implemented
   by 'cpu_special'.  */
enum M6811_Special
{
  /* 68HC11 instructions.  */
  M6811_DAA,
  M6811_EMUL_SYSCALL,
  M6811_ILLEGAL,
  M6811_RTI,
  M6811_STOP,
  M6811_SWI,
  M6811_TEST,
  M6811_WAI,

  /* 68HC12 instructions.  */
  M6812_BGND,
  M6812_CALL,
  M6812_CALL_INDIRECT,
  M6812_IDIVS,
  M6812_EDIV,
  M6812_EDIVS,
  M6812_EMACS,
  M6812_EMUL,
  M6812_EMULS,
  M6812_ETBL,
  M6812_MEM,
  M6812_REV,
  M6812_REVW,
  M6812_RTC,
  M6812_RTI,
  M6812_WAV
};

#define M6811_MAX_PORTS (0x03f+1)
#define M6812_MAX_PORTS (0x3ff+1)
#define MAX_PORTS       (M6812_MAX_PORTS)

struct _sim_cpu;

typedef void (* cpu_interp) (struct _sim_cpu*);

struct _sim_cpu {
  /* CPU registers.  */
  struct m6811_regs     cpu_regs;

  /* CPU interrupts.  */
  struct interrupts     cpu_interrupts;

  /* Pointer to the interpretor routine.  */
  cpu_interp            cpu_interpretor;

  /* Pointer to the architecture currently configured in the simulator.  */
  const struct bfd_arch_info  *cpu_configured_arch;
  
  /* CPU absolute cycle time.  The cycle time is updated after
     each instruction, by the number of cycles taken by the instruction.
     It is cleared only when reset occurs.  */
  signed64              cpu_absolute_cycle;

  /* Number of cycles to increment after the current instruction.
     This is also the number of ticks for the generic event scheduler.  */
  uint8                 cpu_current_cycle;
  int                   cpu_emul_syscall;
  int                   cpu_is_initialized;
  int                   cpu_running;
  int                   cpu_check_memory;
  int                   cpu_stop_on_interrupt;

  /* When this is set, start execution of program at address specified
     in the ELF header.  This is used for testing some programs that do not
     have an interrupt table linked with them.  Programs created during the
     GCC validation are like this. A normal 68HC11 does not behave like
     this (unless there is some OS or downloadable feature).  */
  int                   cpu_use_elf_start;

  /* The starting address specified in ELF header.  */
  int                   cpu_elf_start;
  
  uint16                cpu_insn_pc;

  /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
     get the cycle time.  This is used for the timer rate and for the baud
     rate generation.  */
  unsigned long         cpu_frequency;

  /* The mode in which the CPU is configured (MODA and MODB pins).  */
  unsigned int          cpu_mode;
  const char*           cpu_start_mode;

  /* The cpu being configured.  */
  enum cpu_type         cpu_type;
  
  /* Initial value of the CONFIG register.  */
  uint8                 cpu_config;
  uint8                 cpu_use_local_config;
  
  uint8                 ios[MAX_PORTS];

  /* Memory bank parameters which describe how the memory bank window
     is mapped in memory and how to convert it in virtual address.  */
  uint16                bank_start;
  uint16                bank_end;
  address_word          bank_virtual;
  unsigned              bank_shift;
  

  struct hw            *hw_cpu;

  /* ... base type ... */
  sim_cpu_base base;
};

/* Returns the cpu absolute cycle time (A virtual counter incremented
   at each 68HC11 E clock).  */
#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
#define cpu_add_cycles(PROC,T)  ((PROC)->cpu_current_cycle += (signed64) (T))
#define cpu_is_running(PROC)    ((PROC)->cpu_running)

/* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
#define cpu_get_io_base(PROC) \
        (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
#define cpu_get_reg_base(PROC) \
        (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)

/* Returns the different CPU registers.  */
#define cpu_get_ccr(PROC)          ((PROC)->cpu_regs.ccr)
#define cpu_get_pc(PROC)           ((PROC)->cpu_regs.pc)
#define cpu_get_d(PROC)            ((PROC)->cpu_regs.d)
#define cpu_get_x(PROC)            ((PROC)->cpu_regs.ix)
#define cpu_get_y(PROC)            ((PROC)->cpu_regs.iy)
#define cpu_get_sp(PROC)           ((PROC)->cpu_regs.sp)
#define cpu_get_a(PROC)            ((PROC->cpu_regs.d >> 8) & 0x0FF)
#define cpu_get_b(PROC)            ((PROC->cpu_regs.d) & 0x0FF)
#define cpu_get_page(PROC)         ((PROC)->cpu_regs.page)

/* 68HC12 specific and Motorola internal registers.  */
#define cpu_get_tmp3(PROC)         (0)
#define cpu_get_tmp2(PROC)         (0)

#define cpu_set_d(PROC,VAL)        (((PROC)->cpu_regs.d) = (VAL))
#define cpu_set_x(PROC,VAL)        (((PROC)->cpu_regs.ix) = (VAL))
#define cpu_set_y(PROC,VAL)        (((PROC)->cpu_regs.iy) = (VAL))
#define cpu_set_page(PROC,VAL)     (((PROC)->cpu_regs.page) = (VAL))

/* 68HC12 specific and Motorola internal registers.  */
#define cpu_set_tmp3(PROC,VAL)     (0)
#define cpu_set_tmp2(PROC,VAL)     (void) (0)

#if 0
/* This is a function in m68hc11_sim.c to keep track of the frame.  */
#define cpu_set_sp(PROC,VAL)       (((PROC)->cpu_regs.sp) = (VAL))
#endif

#define cpu_set_pc(PROC,VAL)       (((PROC)->cpu_regs.pc) = (VAL))

#define cpu_set_a(PROC,VAL)  \
      cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
#define cpu_set_b(PROC,VAL)  \
      cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))

#define cpu_set_ccr(PROC,VAL)      ((PROC)->cpu_regs.ccr = (VAL))
#define cpu_get_ccr_H(PROC)        ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
#define cpu_get_ccr_X(PROC)        ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
#define cpu_get_ccr_S(PROC)        ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
#define cpu_get_ccr_N(PROC)        ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
#define cpu_get_ccr_V(PROC)        ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
#define cpu_get_ccr_C(PROC)        ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
#define cpu_get_ccr_Z(PROC)        ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
#define cpu_get_ccr_I(PROC)        ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)

#define cpu_set_ccr_flag(S,B,V) \
cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))

#define cpu_set_ccr_H(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
#define cpu_set_ccr_X(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
#define cpu_set_ccr_S(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
#define cpu_set_ccr_N(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
#define cpu_set_ccr_V(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
#define cpu_set_ccr_C(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
#define cpu_set_ccr_Z(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
#define cpu_set_ccr_I(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)

#undef inline
#define inline static __inline__

extern void cpu_memory_exception (struct _sim_cpu *proc,
                                  SIM_SIGNAL excep,
                                  uint16 addr,
                                  const char *message);

inline address_word
phys_to_virt (sim_cpu *cpu, address_word addr)
{
  if (addr >= cpu->bank_start && addr < cpu->bank_end)
    return ((address_word) (addr - cpu->bank_start)
            + (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
            + cpu->bank_virtual);
  else
    return (address_word) (addr);
}

inline uint8
memory_read8 (sim_cpu *cpu, uint16 addr)
{
  uint8 val;

  if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Read error");
    }
  return val;
}

inline void
memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
{
  if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Write error");
    }
}

inline uint16
memory_read16 (sim_cpu *cpu, uint16 addr)
{
  uint8 b[2];

  if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Read error");
    }
  return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
}

inline void
memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
{
  uint8 b[2];

  b[0] = val >> 8;
  b[1] = val;
  if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Write error");
    }
}
extern void
cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);

     inline void
cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
{
  cpu_set_ccr_V (proc, 0);
  cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
}

     inline void
cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
{
  cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
  cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
}

     inline void
cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
{
  cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
  cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
}

inline void
cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
{
  cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
}


inline void
cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
{
  cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
}

inline void
cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
{
  cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
}

inline void
cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
{
  cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
}

/* Push and pop instructions for 68HC11 (next-available stack mode).  */
inline void
cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
{
  uint16 addr = proc->cpu_regs.sp;

  memory_write8 (proc, addr, val);
  proc->cpu_regs.sp = addr - 1;
}

inline void
cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
{
  uint16 addr = proc->cpu_regs.sp - 1;

  memory_write16 (proc, addr, val);
  proc->cpu_regs.sp = addr - 1;
}

inline uint8
cpu_m68hc11_pop_uint8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint8 val;
  
  val = memory_read8 (proc, addr + 1);
  proc->cpu_regs.sp = addr + 1;
  return val;
}

inline uint16
cpu_m68hc11_pop_uint16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint16 val;
  
  val = memory_read16 (proc, addr + 1);
  proc->cpu_regs.sp = addr + 2;
  return val;
}

/* Push and pop instructions for 68HC12 (last-used stack mode).  */
inline void
cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
{
  uint16 addr = proc->cpu_regs.sp;

  addr --;
  memory_write8 (proc, addr, val);
  proc->cpu_regs.sp = addr;
}

inline void
cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
{
  uint16 addr = proc->cpu_regs.sp;

  addr -= 2;
  memory_write16 (proc, addr, val);
  proc->cpu_regs.sp = addr;
}

inline uint8
cpu_m68hc12_pop_uint8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint8 val;
  
  val = memory_read8 (proc, addr);
  proc->cpu_regs.sp = addr + 1;
  return val;
}

inline uint16
cpu_m68hc12_pop_uint16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint16 val;
  
  val = memory_read16 (proc, addr);
  proc->cpu_regs.sp = addr + 2;
  return val;
}

/* Fetch a 8/16 bit value and update the PC.  */
inline uint8
cpu_fetch8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.pc;
  uint8 val;
  
  val = memory_read8 (proc, addr);
  proc->cpu_regs.pc = addr + 1;
  return val;
}

inline uint16
cpu_fetch16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.pc;
  uint16 val;
  
  val = memory_read16 (proc, addr);
  proc->cpu_regs.pc = addr + 2;
  return val;
}

extern void cpu_call (sim_cpu* proc, uint16 addr);
extern void cpu_exg (sim_cpu* proc, uint8 code);
extern void cpu_dbcc (sim_cpu* proc);
extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
extern void cpu_move8 (sim_cpu *proc, uint8 op);
extern void cpu_move16 (sim_cpu *proc, uint8 op);

extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
extern void cpu_push_all (sim_cpu *proc);
extern void cpu_single_step (sim_cpu *proc);

extern void cpu_info (SIM_DESC sd, sim_cpu *proc);

extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);

/* Returns the address of a 68HC12 indexed operand.
   Pre and post modifications are handled on the source register.  */
extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);

extern void cpu_return (sim_cpu *cpu);
extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
extern int cpu_reset (sim_cpu *cpu);
extern int cpu_restart (sim_cpu *cpu);
extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
                              uint16 addr, const char *message, ...);
extern void emul_os (int op, sim_cpu *cpu);
extern void cpu_interp_m6811 (sim_cpu *cpu);
extern void cpu_interp_m6812 (sim_cpu *cpu);

extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
				      double ton, double toff,
				      signed64 repeat);
extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
				 unsigned addr, uint8 val);

/* The current state of the processor; registers, memory, etc.  */

struct sim_state {
  sim_cpu        *cpu[MAX_NR_PROCESSORS];
  device         *devices;
  sim_state_base base;
};

extern void sim_board_reset (SIM_DESC sd);

#define PRINT_TIME  0x01
#define PRINT_CYCLE 0x02
extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags);

#endif
Commit	Line	Data
81e09ed8	1	/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
32d0add0	2	Copyright (C) 1999-2015 Free Software Foundation, Inc.
63f36def	3	Written by Stephane Carrez (stcarrez@nerim.fr)
e0709f50 AC	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
4744ac1b JB	9	the Free Software Foundation; either version 3 of the License, or
4744ac1b JB	10	(at your option) any later version.
e0709f50 AC	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
4744ac1b JB	17	You should have received a copy of the GNU General Public License
4744ac1b JB	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
e0709f50 AC	19
	20	#ifndef _SIM_MAIN_H
	21	#define _SIM_MAIN_H
	22
e0709f50 AC	23	#define WITH_WATCHPOINTS 1
	24	#define SIM_HANDLES_LMA 1
	25
	26	#include "sim-basics.h"
e0709f50 AC	27	#include "sim-signal.h"
	28	#include "sim-base.h"
	29
	30	#include "bfd.h"
	31
	32	#include "opcode/m68hc11.h"
	33
3c25f8c7 AC	34	#include "gdb/callback.h"
3c25f8c7 AC	35	#include "gdb/remote-sim.h"
e0709f50 AC	36	#include "opcode/m68hc11.h"
	37	#include "sim-types.h"
	38
	39	typedef unsigned8 uint8;
	40	typedef unsigned16 uint16;
	41	typedef signed16 int16;
	42	typedef unsigned32 uint32;
	43	typedef signed32 int32;
	44	typedef unsigned64 uint64;
	45	typedef signed64 int64;
	46
	47	struct _sim_cpu;
	48
	49	#include "interrupts.h"
	50	#include <setjmp.h>
	51
63348d04 SC	52	/* Specifies the level of mapping for the IO, EEprom, nvram and external
	53	RAM. IO registers are mapped over everything and the external RAM
	54	is last (ie, it can be hidden by everything above it in the list). */
	55	enum m68hc11_map_level
	56	{
	57	M6811_IO_LEVEL,
	58	M6811_EEPROM_LEVEL,
	59	M6811_NVRAM_LEVEL,
	60	M6811_RAM_LEVEL
	61	};
	62
81e09ed8 SC	63	enum cpu_type
	64	{
	65	CPU_M6811,
	66	CPU_M6812
	67	};
63348d04	68
e0709f50 AC	69	#define X_REGNUM 0
	70	#define D_REGNUM 1
	71	#define Y_REGNUM 2
	72	#define SP_REGNUM 3
	73	#define PC_REGNUM 4
	74	#define A_REGNUM 5
	75	#define B_REGNUM 6
	76	#define PSW_REGNUM 7
53b3cd22 SC	77	#define PAGE_REGNUM 8
53b3cd22 SC	78	#define Z_REGNUM 9
e0709f50 AC	79
	80	typedef struct m6811_regs {
	81	unsigned short d;
	82	unsigned short ix;
	83	unsigned short iy;
	84	unsigned short sp;
	85	unsigned short pc;
	86	unsigned char ccr;
63f36def	87	unsigned short page;
e0709f50 AC	88	} m6811_regs;
	89
	90
	91	/* Description of 68HC11 IO registers. Such description is only provided
	92	for the info command to display the current setting of IO registers
	93	from GDB. */
	94	struct io_reg_desc
	95	{
	96	int mask;
	97	const char *short_name;
	98	const char *long_name;
	99	};
	100	typedef struct io_reg_desc io_reg_desc;
	101
	102	extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
	103	int mode);
	104	extern void print_io_byte (SIM_DESC sd, const char *name,
	105	io_reg_desc *desc, uint8 val, uint16 addr);
962e9d85 SC	106	extern void print_io_word (SIM_DESC sd, const char *name,
962e9d85 SC	107	io_reg_desc *desc, uint16 val, uint16 addr);
e0709f50 AC	108
e0709f50 AC	109
81e09ed8	110	/* List of special 68HC11&68HC12 instructions that are not handled by the
e0709f50 AC	111	'gencode.c' generator. These complex instructions are implemented
	112	by 'cpu_special'. */
	113	enum M6811_Special
	114	{
81e09ed8 SC	115	/* 68HC11 instructions. */
	116	M6811_DAA,
	117	M6811_EMUL_SYSCALL,
	118	M6811_ILLEGAL,
e0709f50	119	M6811_RTI,
81e09ed8	120	M6811_STOP,
e0709f50 AC	121	M6811_SWI,
e0709f50 AC	122	M6811_TEST,
81e09ed8 SC	123	M6811_WAI,
	124
	125	/* 68HC12 instructions. */
	126	M6812_BGND,
	127	M6812_CALL,
63f36def	128	M6812_CALL_INDIRECT,
81e09ed8 SC	129	M6812_IDIVS,
	130	M6812_EDIV,
	131	M6812_EDIVS,
	132	M6812_EMACS,
	133	M6812_EMUL,
	134	M6812_EMULS,
	135	M6812_ETBL,
	136	M6812_MEM,
	137	M6812_REV,
	138	M6812_REVW,
	139	M6812_RTC,
	140	M6812_RTI,
	141	M6812_WAV
e0709f50 AC	142	};
e0709f50 AC	143
81e09ed8 SC	144	#define M6811_MAX_PORTS (0x03f+1)
	145	#define M6812_MAX_PORTS (0x3ff+1)
	146	#define MAX_PORTS (M6812_MAX_PORTS)
e0709f50	147
81e09ed8 SC	148	struct _sim_cpu;
	149
	150	typedef void (* cpu_interp) (struct _sim_cpu*);
	151
e0709f50 AC	152	struct _sim_cpu {
	153	/* CPU registers. */
	154	struct m6811_regs cpu_regs;
	155
	156	/* CPU interrupts. */
	157	struct interrupts cpu_interrupts;
	158
81e09ed8 SC	159	/* Pointer to the interpretor routine. */
	160	cpu_interp cpu_interpretor;
	161
	162	/* Pointer to the architecture currently configured in the simulator. */
	163	const struct bfd_arch_info *cpu_configured_arch;
	164
e0709f50 AC	165	/* CPU absolute cycle time. The cycle time is updated after
	166	each instruction, by the number of cycles taken by the instruction.
	167	It is cleared only when reset occurs. */
	168	signed64 cpu_absolute_cycle;
	169
	170	/* Number of cycles to increment after the current instruction.
	171	This is also the number of ticks for the generic event scheduler. */
	172	uint8 cpu_current_cycle;
	173	int cpu_emul_syscall;
	174	int cpu_is_initialized;
	175	int cpu_running;
	176	int cpu_check_memory;
	177	int cpu_stop_on_interrupt;
	178
	179	/* When this is set, start execution of program at address specified
	180	in the ELF header. This is used for testing some programs that do not
	181	have an interrupt table linked with them. Programs created during the
	182	GCC validation are like this. A normal 68HC11 does not behave like
	183	this (unless there is some OS or downloadable feature). */
	184	int cpu_use_elf_start;
	185
	186	/* The starting address specified in ELF header. */
	187	int cpu_elf_start;
	188
	189	uint16 cpu_insn_pc;
e0709f50 AC	190
	191	/* CPU frequency. This is the quartz frequency. It is divided by 4 to
	192	get the cycle time. This is used for the timer rate and for the baud
	193	rate generation. */
	194	unsigned long cpu_frequency;
	195
	196	/* The mode in which the CPU is configured (MODA and MODB pins). */
	197	unsigned int cpu_mode;
a685700c	198	const char* cpu_start_mode;
e0709f50	199
81e09ed8 SC	200	/* The cpu being configured. */
	201	enum cpu_type cpu_type;
	202
e0709f50 AC	203	/* Initial value of the CONFIG register. */
	204	uint8 cpu_config;
	205	uint8 cpu_use_local_config;
	206
81e09ed8	207	uint8 ios[MAX_PORTS];
827ec39a	208
77342e5e SC	209	/* Memory bank parameters which describe how the memory bank window
	210	is mapped in memory and how to convert it in virtual address. */
	211	uint16 bank_start;
	212	uint16 bank_end;
	213	address_word bank_virtual;
	214	unsigned bank_shift;
	215
	216
827ec39a SC	217	struct hw *hw_cpu;
827ec39a SC	218
e0709f50 AC	219	/* ... base type ... */
	220	sim_cpu_base base;
	221	};
	222
	223	/* Returns the cpu absolute cycle time (A virtual counter incremented
	224	at each 68HC11 E clock). */
	225	#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
	226	#define cpu_add_cycles(PROC,T) ((PROC)->cpu_current_cycle += (signed64) (T))
	227	#define cpu_is_running(PROC) ((PROC)->cpu_running)
	228
	229	/* Get the IO/RAM base addresses depending on the M6811_INIT register. */
	230	#define cpu_get_io_base(PROC) \
	231	(((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
	232	#define cpu_get_reg_base(PROC) \
	233	(((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
	234
	235	/* Returns the different CPU registers. */
	236	#define cpu_get_ccr(PROC) ((PROC)->cpu_regs.ccr)
	237	#define cpu_get_pc(PROC) ((PROC)->cpu_regs.pc)
	238	#define cpu_get_d(PROC) ((PROC)->cpu_regs.d)
	239	#define cpu_get_x(PROC) ((PROC)->cpu_regs.ix)
	240	#define cpu_get_y(PROC) ((PROC)->cpu_regs.iy)
	241	#define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp)
	242	#define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF)
	243	#define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF)
77342e5e	244	#define cpu_get_page(PROC) ((PROC)->cpu_regs.page)
e0709f50	245
81e09ed8 SC	246	/* 68HC12 specific and Motorola internal registers. */
	247	#define cpu_get_tmp3(PROC) (0)
	248	#define cpu_get_tmp2(PROC) (0)
	249
e0709f50 AC	250	#define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL))
	251	#define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL))
	252	#define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL))
77342e5e	253	#define cpu_set_page(PROC,VAL) (((PROC)->cpu_regs.page) = (VAL))
e0709f50	254
81e09ed8 SC	255	/* 68HC12 specific and Motorola internal registers. */
81e09ed8 SC	256	#define cpu_set_tmp3(PROC,VAL) (0)
63f36def	257	#define cpu_set_tmp2(PROC,VAL) (void) (0)
81e09ed8	258
e0709f50 AC	259	#if 0
	260	/* This is a function in m68hc11_sim.c to keep track of the frame. */
	261	#define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL))
	262	#endif
	263
	264	#define cpu_set_pc(PROC,VAL) (((PROC)->cpu_regs.pc) = (VAL))
	265
	266	#define cpu_set_a(PROC,VAL) \
	267	cpu_set_d(PROC,((VAL) << 8) \| cpu_get_b(PROC))
	268	#define cpu_set_b(PROC,VAL) \
	269	cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)\|(VAL & 0x0FF))
	270
	271	#define cpu_set_ccr(PROC,VAL) ((PROC)->cpu_regs.ccr = (VAL))
	272	#define cpu_get_ccr_H(PROC) ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
	273	#define cpu_get_ccr_X(PROC) ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
	274	#define cpu_get_ccr_S(PROC) ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
	275	#define cpu_get_ccr_N(PROC) ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
	276	#define cpu_get_ccr_V(PROC) ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
	277	#define cpu_get_ccr_C(PROC) ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
	278	#define cpu_get_ccr_Z(PROC) ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
	279	#define cpu_get_ccr_I(PROC) ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
	280
	281	#define cpu_set_ccr_flag(S,B,V) \
	282	cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) \| ((V) ? B : 0))
	283
	284	#define cpu_set_ccr_H(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
	285	#define cpu_set_ccr_X(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
	286	#define cpu_set_ccr_S(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
	287	#define cpu_set_ccr_N(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
	288	#define cpu_set_ccr_V(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
	289	#define cpu_set_ccr_C(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
	290	#define cpu_set_ccr_Z(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
	291	#define cpu_set_ccr_I(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
	292
	293	#undef inline
	294	#define inline static __inline__
	295
	296	extern void cpu_memory_exception (struct _sim_cpu *proc,
	297	SIM_SIGNAL excep,
	298	uint16 addr,
	299	const char *message);
	300
63f36def SC	301	inline address_word
	302	phys_to_virt (sim_cpu *cpu, address_word addr)
	303	{
77342e5e SC	304	if (addr >= cpu->bank_start && addr < cpu->bank_end)
	305	return ((address_word) (addr - cpu->bank_start)
	306	+ (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
	307	+ cpu->bank_virtual);
63f36def SC	308	else
	309	return (address_word) (addr);
	310	}
	311
e0709f50 AC	312	inline uint8
	313	memory_read8 (sim_cpu *cpu, uint16 addr)
	314	{
	315	uint8 val;
63f36def	316
e0709f50 AC	317	if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
	318	{
	319	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	320	"Read error");
	321	}
	322	return val;
	323	}
	324
	325	inline void
	326	memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
	327	{
	328	if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
	329	{
	330	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	331	"Write error");
	332	}
	333	}
	334
	335	inline uint16
	336	memory_read16 (sim_cpu *cpu, uint16 addr)
	337	{
	338	uint8 b[2];
63f36def	339
e0709f50 AC	340	if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
	341	{
	342	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	343	"Read error");
	344	}
	345	return (((uint16) (b[0])) << 8) \| ((uint16) b[1]);
	346	}
	347
	348	inline void
	349	memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
	350	{
	351	uint8 b[2];
	352
	353	b[0] = val >> 8;
	354	b[1] = val;
	355	if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
	356	{
	357	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	358	"Write error");
	359	}
	360	}
	361	extern void
	362	cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);
	363
	364	inline void
	365	cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
	366	{
	367	cpu_set_ccr_V (proc, 0);
	368	cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
	369	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	370	}
	371
	372	inline void
	373	cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
	374	{
	375	cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
	376	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	377	cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
	378	}
	379
	380	inline void
	381	cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
	382	{
	383	cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
	384	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	385	cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
	386	}
	387
	388	inline void
	389	cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
	390	{
	391	cpu_set_ccr_C (proc, ((a & b) \| (b & ~r) \| (a & ~r)) & 0x80 ? 1 : 0);
	392	cpu_set_ccr_V (proc, ((a & b & ~r) \| (~a & ~b & r)) & 0x80 ? 1 : 0);
	393	cpu_set_ccr_Z (proc, r == 0);
	394	cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
	395	}
	396
	397
	398	inline void
	399	cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
	400	{
	401	cpu_set_ccr_C (proc, ((~a & b) \| (b & r) \| (~a & r)) & 0x80 ? 1 : 0);
	402	cpu_set_ccr_V (proc, ((a & ~b & ~r) \| (~a & b & r)) & 0x80 ? 1 : 0);
	403	cpu_set_ccr_Z (proc, r == 0);
404	cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
405	}
406
407	inline void
408	cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
409	{
410	cpu_set_ccr_C (proc, ((a & b) \| (b & ~r) \| (a & ~r)) & 0x8000 ? 1 : 0);
411	cpu_set_ccr_V (proc, ((a & b & ~r) \| (~a & ~b & r)) & 0x8000 ? 1 : 0);
412	cpu_set_ccr_Z (proc, r == 0);
413	cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
414	}
415
416	inline void
417	cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
418	{
419	cpu_set_ccr_C (proc, ((~a & b) \| (b & r) \| (~a & r)) & 0x8000 ? 1 : 0);
420	cpu_set_ccr_V (proc, ((a & ~b & ~r) \| (~a & b & r)) & 0x8000 ? 1 : 0);
421	cpu_set_ccr_Z (proc, r == 0);
422	cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
423	}
424
81e09ed8	425	/* Push and pop instructions for 68HC11 (next-available stack mode). */
e0709f50	426	inline void
81e09ed8	427	cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
e0709f50 AC	428	{
	429	uint16 addr = proc->cpu_regs.sp;
	430
	431	memory_write8 (proc, addr, val);
	432	proc->cpu_regs.sp = addr - 1;
e0709f50 AC	433	}
	434
	435	inline void
81e09ed8	436	cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
e0709f50 AC	437	{
	438	uint16 addr = proc->cpu_regs.sp - 1;
	439
	440	memory_write16 (proc, addr, val);
	441	proc->cpu_regs.sp = addr - 1;
e0709f50 AC	442	}
	443
	444	inline uint8
81e09ed8	445	cpu_m68hc11_pop_uint8 (sim_cpu *proc)
e0709f50 AC	446	{
	447	uint16 addr = proc->cpu_regs.sp;
	448	uint8 val;
	449
	450	val = memory_read8 (proc, addr + 1);
	451	proc->cpu_regs.sp = addr + 1;
e0709f50 AC	452	return val;
	453	}
	454
	455	inline uint16
81e09ed8	456	cpu_m68hc11_pop_uint16 (sim_cpu *proc)
e0709f50 AC	457	{
	458	uint16 addr = proc->cpu_regs.sp;
	459	uint16 val;
	460
	461	val = memory_read16 (proc, addr + 1);
	462	proc->cpu_regs.sp = addr + 2;
e0709f50 AC	463	return val;
	464	}
	465
81e09ed8 SC	466	/* Push and pop instructions for 68HC12 (last-used stack mode). */
	467	inline void
	468	cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
	469	{
	470	uint16 addr = proc->cpu_regs.sp;
	471
	472	addr --;
	473	memory_write8 (proc, addr, val);
	474	proc->cpu_regs.sp = addr;
81e09ed8 SC	475	}
	476
	477	inline void
	478	cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
	479	{
	480	uint16 addr = proc->cpu_regs.sp;
	481
	482	addr -= 2;
	483	memory_write16 (proc, addr, val);
	484	proc->cpu_regs.sp = addr;
81e09ed8 SC	485	}
	486
	487	inline uint8
	488	cpu_m68hc12_pop_uint8 (sim_cpu *proc)
	489	{
	490	uint16 addr = proc->cpu_regs.sp;
	491	uint8 val;
	492
	493	val = memory_read8 (proc, addr);
	494	proc->cpu_regs.sp = addr + 1;
81e09ed8 SC	495	return val;
	496	}
	497
	498	inline uint16
	499	cpu_m68hc12_pop_uint16 (sim_cpu *proc)
	500	{
	501	uint16 addr = proc->cpu_regs.sp;
	502	uint16 val;
	503
	504	val = memory_read16 (proc, addr);
	505	proc->cpu_regs.sp = addr + 2;
81e09ed8 SC	506	return val;
	507	}
	508
	509	/* Fetch a 8/16 bit value and update the PC. */
e0709f50 AC	510	inline uint8
	511	cpu_fetch8 (sim_cpu *proc)
	512	{
	513	uint16 addr = proc->cpu_regs.pc;
	514	uint8 val;
	515
	516	val = memory_read8 (proc, addr);
	517	proc->cpu_regs.pc = addr + 1;
	518	return val;
	519	}
	520
	521	inline uint16
	522	cpu_fetch16 (sim_cpu *proc)
	523	{
	524	uint16 addr = proc->cpu_regs.pc;
	525	uint16 val;
	526
	527	val = memory_read16 (proc, addr);
	528	proc->cpu_regs.pc = addr + 2;
	529	return val;
	530	}
	531
	532	extern void cpu_call (sim_cpu* proc, uint16 addr);
81e09ed8 SC	533	extern void cpu_exg (sim_cpu* proc, uint8 code);
81e09ed8 SC	534	extern void cpu_dbcc (sim_cpu* proc);
e0709f50	535	extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
81e09ed8 SC	536	extern void cpu_move8 (sim_cpu *proc, uint8 op);
81e09ed8 SC	537	extern void cpu_move16 (sim_cpu *proc, uint8 op);
e0709f50 AC	538
e0709f50 AC	539	extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
81e09ed8	540	extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
e0709f50 AC	541	extern void cpu_push_all (sim_cpu *proc);
	542	extern void cpu_single_step (sim_cpu *proc);
	543
	544	extern void cpu_info (SIM_DESC sd, sim_cpu *proc);
	545
	546	extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
	547
63f36def SC	548	/* Returns the address of a 68HC12 indexed operand.
63f36def SC	549	Pre and post modifications are handled on the source register. */
2b6ca062	550	extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
63f36def SC	551
63f36def SC	552	extern void cpu_return (sim_cpu *cpu);
e0709f50	553	extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
e0709f50 AC	554	extern int cpu_reset (sim_cpu *cpu);
	555	extern int cpu_restart (sim_cpu *cpu);
	556	extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
	557	uint16 addr, const char *message, ...);
	558	extern void emul_os (int op, sim_cpu *cpu);
81e09ed8 SC	559	extern void cpu_interp_m6811 (sim_cpu *cpu);
81e09ed8 SC	560	extern void cpu_interp_m6812 (sim_cpu *cpu);
e0709f50	561
827ec39a SC	562	extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
	563	double ton, double toff,
	564	signed64 repeat);
	565	extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
	566	extern void m68hc11cpu_set_port (struct hw me, sim_cpu cpu,
	567	unsigned addr, uint8 val);
	568
e0709f50 AC	569	/* The current state of the processor; registers, memory, etc. */
e0709f50 AC	570
e0709f50	571	struct sim_state {
bea3f671	572	sim_cpu *cpu[MAX_NR_PROCESSORS];
e0709f50 AC	573	device *devices;
	574	sim_state_base base;
	575	};
	576
e0709f50 AC	577	extern void sim_board_reset (SIM_DESC sd);
e0709f50 AC	578
a685700c SC	579	#define PRINT_TIME 0x01
	580	#define PRINT_CYCLE 0x02
	581	extern const char cycle_to_string (sim_cpu cpu, signed64 t, int flags);
2990a9f4	582
e0709f50 AC	583	#endif
	584
	585