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sim: hw: rework configure option & device selection
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
be0387ee
MF		 12021-06-21 Mike Frysinger <vapier@gentoo.org>
2
3 * Makefile.in (SIM_EXTRA_HW_DEVICES): Define.
4 * configure.ac (SIM_AC_OPTION_HARDWARE): Delete call.
5 * configure: Regenerate.
6
3eda63f2
MF		 72021-06-20 Mike Frysinger <vapier@gentoo.org>
8
9 * configure.ac (SIM_AC_COMMON): Delete.
10 * aclocal.m4, configure: Regenerate.
11
d73f39ee
MF		 122021-06-20 Mike Frysinger <vapier@gentoo.org>
13
14 * aclocal.m4: Regenerate.
15 * configure: Regenerate.
16
b5689863
MF		 172021-06-19 Mike Frysinger <vapier@gentoo.org>
18
19 * aclocal.m4: Regenerate.
20 * configure: Regenerate.
21
17a5da80
MF		 222021-06-19 Mike Frysinger <vapier@gentoo.org>
23
24 * configure.ac: Delete AC_PATH_X call.
25 * configure: Regenerate.
26
07490bf8
MF		 272021-06-19 Mike Frysinger <vapier@gentoo.org>
28
29 * configure.ac: Delete AC_CHECK_LIB calls.
30 * configure: Regenerate.
31
47ce766a
MF		 322021-06-18 Mike Frysinger <vapier@gentoo.org>
33
34 * aclocal.m4, configure: Regenerate.
35
982c3a65
MF		 362021-06-18 Mike Frysinger <vapier@gentoo.org>
37
38 * Makefile.in (SIM_WERROR_CFLAGS): New variable.
39 * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS.
40 * configure: Regenerate.
41
1fef66b0
MF		 422021-06-18 Mike Frysinger <vapier@gentoo.org>
43
44 * interp.c: Include sim-signal.h.
45
f9a4d543
MF		 462021-06-17 Mike Frysinger <vapier@gentoo.org>
47
48 * configure.ac: Delete SIM_AC_OPTION_ENDIAN call.
49 * aclocal.m4, configure: Regenerate.
50
b80d4475
MF		 512021-06-16 Mike Frysinger <vapier@gentoo.org>
52
53 * interp.c (dotrace): Make comment const.
54 * sim-main.h (dotrace): Likewise. Add ATTRIBUTE_PRINTF.
55
6828a302
MF		 562021-06-16 Mike Frysinger <vapier@gentoo.org>
57
58 * interp.c (sim_monitor): Change ap type to address_word*.
59 (_P, P): New macros. Rewrite dynamic printf logic to use these.
60
df32b446
MF		 612021-06-16 Mike Frysinger <vapier@gentoo.org>
62
63 * dv-tx3904sio.c (tx3904sio_fifo_push): Change next_buf to
64 unsigned_1.
65
7b2298cb
MF		 662021-06-16 Mike Frysinger <vapier@gentoo.org>
67
68 * dv-tx3904irc.c (tx3904irc_io_write_buffer): Initialize
69 register_value to 0.
70
a8a3d907
MF		 712021-06-16 Mike Frysinger <vapier@gentoo.org>
72
73 * configure: Regenerate.
74
dae666c9
MF		 752021-06-16 Mike Frysinger <vapier@gentoo.org>
76
77 * interp.c (sim_open): Change %lx to %x and PRIx macros.
78
52d37d2c
MF		 792021-06-16 Mike Frysinger <vapier@gentoo.org>
80
81 * configure: Regenerate.
82 * config.in: Removed.
83
bcaa61f7
MF		 842021-06-15 Mike Frysinger <vapier@gentoo.org>
85
86 * config.in, configure: Regenerate.
87
ba307cdd
MF		 882021-06-12 Mike Frysinger <vapier@gentoo.org>
89
90 * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
91
dba333c1
MF		 922021-06-12 Mike Frysinger <vapier@gentoo.org>
93
94 * aclocal.m4, config.in, configure: Regenerate.
95
b15c5d7a
MF		 962021-06-12 Mike Frysinger <vapier@gentoo.org>
97
98 * configure.ac: Delete call to AC_CHECK_FUNCS.
99 * config.in, configure: Regenerate.
100
a55b92be
MF		 1012021-06-08 Mike Frysinger <vapier@gentoo.org>
102
103 * Makefile.in: Replace $(IGEN) with $(IGEN_RUN) and ../igen/igen
104 with $(IGEN).
105
8ea881d9
MF		 1062021-05-29 Mike Frysinger <vapier@gentoo.org>
107
108 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL.
109
b312488f
FS		 1102021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
111
168671c1
FS		 112 * interp.c (sim_open): Add shadow mappings from 32-bit
113 address space to 64-bit sign-extended address space.
114
1152021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
116
b312488f
FS		 117 * interp.c (sim_create_inferior): Only truncate sign extension
118 bits for 32-bit target models.
119
f4fdd845
MF		 1202021-05-17 Mike Frysinger <vapier@gentoo.org>
121
122 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
123
8ea7241c
MF		 1242021-05-17 Mike Frysinger <vapier@gentoo.org>
125
126 * interp.c (sim_open): Switch to sim_state_alloc_extra.
127 * micromips.igen: Change SD to mips_sim_state.
128 * micromipsrun.c (sim_engine_run): Likewise.
129 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
130 (watch_options_install): Delete.
131 (struct swatch): Delete.
132 (struct sim_state): Delete.
133 (struct mips_sim_state): New struct.
134 (MIPS_SIM_STATE): Define.
135
6df01ab8
MF		 1362021-05-16 Mike Frysinger <vapier@gentoo.org>
137
138 * interp.c: Replace config.h include with defs.h.
139 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c,
140 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c:
141 Include defs.h.
142
79633c12
MF		 1432021-05-16 Mike Frysinger <vapier@gentoo.org>
144
145 * config.in, configure: Regenerate.
146
df68e12b
MF		 1472021-05-14 Mike Frysinger <vapier@gentoo.org>
148
149 * interp.c: Update include path.
150
77c0fdb7
MF		 1512021-05-04 Mike Frysinger <vapier@gentoo.org>
152
153 * dv-tx3904sio.c: Include stdlib.h.
154
9b1af85c
MF		 1552021-05-04 Mike Frysinger <vapier@gentoo.org>
156
157 * configure.ac (hw_extra_devices): Inline contents into
158 SIM_AC_OPTION_HARDWARE and delete.
159 * configure: Regenerate.
160
d97ba9c6
MF		 1612021-05-04 Mike Frysinger <vapier@gentoo.org>
162
163 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
164 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
165 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
166 * configure: Regenerate.
167
4df817de
MF		 1682021-05-04 Mike Frysinger <vapier@gentoo.org>
169
170 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
171
aa0fca16
MF		 1722021-05-04 Mike Frysinger <vapier@gentoo.org>
173
174 * configure: Regenerate.
175
adbaa7b8
MF		 1762021-05-01 Mike Frysinger <vapier@gentoo.org>
177
178 * cp1.c (store_fcr): Mark static.
179
fe348617
MF		 1802021-05-01 Mike Frysinger <vapier@gentoo.org>
181
182 * config.in, configure: Regenerate.
183
9d903352
MF		 1842021-04-23 Mike Frysinger <vapier@gentoo.org>
185
186 * configure.ac (hw_enabled): Delete.
187 (SIM_AC_OPTION_HARDWARE): Delete first two args.
188 * configure: Regenerate.
189
19f6a43c
TT		 1902021-04-22 Tom Tromey <tom@tromey.com>
191
192 * configure, config.in: Rebuild.
193
e7d8f1da
TT		 1942021-04-22 Tom Tromey <tom@tromey.com>
195
196 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
197 Remove.
198 (SIM_EXTRA_DEPS): New variable.
199
efd82ac7
TT		 2002021-04-22 Tom Tromey <tom@tromey.com>
201
202 * configure: Rebuild.
203
2662c237
MF		 2042021-04-21 Mike Frysinger <vapier@gentoo.org>
205
206 * aclocal.m4: Regenerate.
207
1f195bc3
SM		 2082021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
209
210 * configure: Regenerate.
211
37e9f182
MF		 2122021-04-18 Mike Frysinger <vapier@gentoo.org>
213
214 * configure: Regenerate.
215
d5a71b11
MF		 2162021-04-12 Mike Frysinger <vapier@gentoo.org>
217
218 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
219
2b8d134b
SM		 2202021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
221
222 * Makefile.in: Set ASAN_OPTIONS when running igen.
223
5c6f091a
FS		 2242021-04-04 Steve Ellcey <sellcey@mips.com>
225 Faraz Shahbazker <fshahbazker@wavecomp.com>
226
227 * interp.c (sim_monitor): Add switch entries for unlink (13),
228 lseek (14), and stat (15).
229
b6b1c790
MF		 2302021-04-02 Mike Frysinger <vapier@gentoo.org>
231
232 * Makefile.in (../igen/igen): Delete rule.
233 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
234
c2783492
MF		 2352021-04-02 Mike Frysinger <vapier@gentoo.org>
236
237 * aclocal.m4, configure: Regenerate.
238
ebe9564b
MF		 2392021-02-28 Mike Frysinger <vapier@gentoo.org>
240
241 * configure: Regenerate.
242
f8069d55
MF		 2432021-02-27 Mike Frysinger <vapier@gentoo.org>
244
245 * Makefile.in (SIM_EXTRA_ALL): Delete.
246 (all): New target.
247
760b3e8b
MF		 2482021-02-21 Mike Frysinger <vapier@gentoo.org>
249
250 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
251 * aclocal.m4, configure: Regenerate.
252
136da8cd
MF		 2532021-02-13 Mike Frysinger <vapier@gentoo.org>
254
255 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
256 * aclocal.m4, configure: Regenerate.
257
4c0d76b9
MF		 2582021-02-06 Mike Frysinger <vapier@gentoo.org>
259
260 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
261
aa09469f
MF		 2622021-02-06 Mike Frysinger <vapier@gentoo.org>
263
264 * configure: Regenerate.
265
d4e3adda
MF		 2662021-01-30 Mike Frysinger <vapier@gentoo.org>
267
268 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
269
68ed2854
MF		 2702021-01-11 Mike Frysinger <vapier@gentoo.org>
271
272 * config.in, configure: Regenerate.
273 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
274 and strings.h include.
275
50df264d
MF		 2762021-01-09 Mike Frysinger <vapier@gentoo.org>
277
278 * configure: Regenerate.
279
bf470982
MF		 2802021-01-09 Mike Frysinger <vapier@gentoo.org>
281
282 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
283 * configure: Regenerate.
284
46f900c0
MF		 2852021-01-08 Mike Frysinger <vapier@gentoo.org>
286
287 * configure: Regenerate.
288
dfb856ba
MF		 2892021-01-04 Mike Frysinger <vapier@gentoo.org>
290
291 * configure: Regenerate.
292
382bc56b
PK		 2932020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
294
295 * sim-main.c: Include <stdlib.h>.
296
ad9675dd
PK		 2972020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
298
299 * cp1.c: Include <stdlib.h>.
300
f693213d
SM		 3012020-07-29 Simon Marchi <simon.marchi@efficios.com>
302
303 * configure: Re-generate.
304
5c887dd5
JB		 3052017-09-06 John Baldwin <jhb@FreeBSD.org>
306
307 * configure: Regenerate.
308
91588b3a
MF		 3092016-11-11 Mike Frysinger <vapier@gentoo.org>
310
6cb2202b 311 PR sim/20808
91588b3a
MF		 312 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
313 and SD to sd.
314
e04659e8
MF		 3152016-11-11 Mike Frysinger <vapier@gentoo.org>
316
6cb2202b 317 PR sim/20809
e04659e8
MF		 318 * mips.igen (check_u64): Enable for `r3900'.
319
1554f758
MF		 3202016-02-05 Mike Frysinger <vapier@gentoo.org>
321
322 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
323 STATE_PROG_BFD (sd).
324 * configure: Regenerate.
325
3d304f48
AB		 3262016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
327 Maciej W. Rozycki <macro@imgtec.com>
328
329 PR sim/19441
330 * micromips.igen (delayslot_micromips): Enable for `micromips32',
331 `micromips64' and `micromipsdsp' only.
332 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
333 (do_micromips_jalr, do_micromips_jal): Likewise.
334 (compute_movep_src_reg): Likewise.
335 (compute_andi16_imm): Likewise.
336 (convert_fmt_micromips): Likewise.
337 (convert_fmt_micromips_cvt_d): Likewise.
338 (convert_fmt_micromips_cvt_s): Likewise.
339 (FMT_MICROMIPS): Likewise.
340 (FMT_MICROMIPS_CVT_D): Likewise.
341 (FMT_MICROMIPS_CVT_S): Likewise.
342
b36d953b
MF		 3432016-01-12 Mike Frysinger <vapier@gentoo.org>
344
345 * interp.c: Include elf-bfd.h.
346 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
347 ELFCLASS32.
348
ce39bd38
MF		 3492016-01-10 Mike Frysinger <vapier@gentoo.org>
350
351 * config.in, configure: Regenerate.
352
99d8e879
MF		 3532016-01-10 Mike Frysinger <vapier@gentoo.org>
354
355 * configure: Regenerate.
356
35656e95
MF		 3572016-01-10 Mike Frysinger <vapier@gentoo.org>
358
359 * configure: Regenerate.
360
16f7876d
MF		 3612016-01-10 Mike Frysinger <vapier@gentoo.org>
362
363 * configure: Regenerate.
364
e19418e0
MF		 3652016-01-10 Mike Frysinger <vapier@gentoo.org>
366
367 * configure: Regenerate.
368
6d90347b
MF		 3692016-01-10 Mike Frysinger <vapier@gentoo.org>
370
371 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
372 * configure: Regenerate.
373
347fe5bb
MF		 3742016-01-10 Mike Frysinger <vapier@gentoo.org>
375
376 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
377 * configure: Regenerate.
378
22be3fbe
MF		 3792016-01-10 Mike Frysinger <vapier@gentoo.org>
380
381 * configure: Regenerate.
382
0dc73ef7
MF		 3832016-01-10 Mike Frysinger <vapier@gentoo.org>
384
385 * configure: Regenerate.
386
936df756
MF		 3872016-01-09 Mike Frysinger <vapier@gentoo.org>
388
389 * config.in, configure: Regenerate.
390
2e3d4f4d
MF		 3912016-01-06 Mike Frysinger <vapier@gentoo.org>
392
393 * interp.c (sim_open): Mark argv const.
394 (sim_create_inferior): Mark argv and env const.
395
9bbf6f91
MF		 3962016-01-04 Mike Frysinger <vapier@gentoo.org>
397
398 * configure: Regenerate.
399
77cf2ef5
MF		 4002016-01-03 Mike Frysinger <vapier@gentoo.org>
401
402 * interp.c (sim_open): Update sim_parse_args comment.
403
0cb8d851
MF		 4042016-01-03 Mike Frysinger <vapier@gentoo.org>
405
406 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
407 * configure: Regenerate.
408
1ac72f06
MF		 4092016-01-02 Mike Frysinger <vapier@gentoo.org>
410
411 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
412 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
413 * configure: Regenerate.
414 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
415
d47f5b30
MF		 4162016-01-02 Mike Frysinger <vapier@gentoo.org>
417
418 * dv-tx3904cpu.c (CPU, SD): Delete.
419
e1211e55
MF		 4202015-12-30 Mike Frysinger <vapier@gentoo.org>
421
422 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
423 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
424 (sim_store_register): Rename to ...
425 (mips_reg_store): ... this. Delete local cpu var.
426 Update sim_io_eprintf calls.
427 (sim_fetch_register): Rename to ...
428 (mips_reg_fetch): ... this. Delete local cpu var.
429 Update sim_io_eprintf calls.
430
5e744ef8
MF		 4312015-12-27 Mike Frysinger <vapier@gentoo.org>
432
433 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
434
1b393626
MF		 4352015-12-26 Mike Frysinger <vapier@gentoo.org>
436
437 * config.in, configure: Regenerate.
438
26f8bf63
MF		 4392015-12-26 Mike Frysinger <vapier@gentoo.org>
440
441 * interp.c (sim_write, sim_read): Delete.
442 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
443 (load_word): Likewise.
444 * micromips.igen (cache): Likewise.
445 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
446 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
447 do_store_left, do_store_right, do_load_double, do_store_double):
448 Likewise.
449 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
450 (do_prefx): Likewise.
451 * sim-main.c (address_translation, prefetch): Delete.
452 (ifetch32, ifetch16): Delete call to AddressTranslation and set
453 paddr=vaddr.
454 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
455 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
456 (LoadMemory, StoreMemory): Delete CCA arg.
457
ef04e371
MF		 4582015-12-24 Mike Frysinger <vapier@gentoo.org>
459
460 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
461 * configure: Regenerated.
462
cb379ede
MF		 4632015-12-24 Mike Frysinger <vapier@gentoo.org>
464
465 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
466 * tconfig.h: Delete.
467
26936211
MF		 4682015-12-24 Mike Frysinger <vapier@gentoo.org>
469
470 * tconfig.h (SIM_HANDLES_LMA): Delete.
471
84e8e361
MF		 4722015-12-24 Mike Frysinger <vapier@gentoo.org>
473
474 * sim-main.h (WITH_WATCHPOINTS): Delete.
475
3cabaf66
MF		 4762015-12-24 Mike Frysinger <vapier@gentoo.org>
477
478 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
479
8abe6c66
MF		 4802015-12-24 Mike Frysinger <vapier@gentoo.org>
481
482 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
483
1d19cae7
DV		 4842015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
485
486 * micromips.igen (process_isa_mode): Fix left shift of negative
487 value.
488
cdf850e9
MF		 4892015-11-17 Mike Frysinger <vapier@gentoo.org>
490
491 * sim-main.h (WITH_MODULO_MEMORY): Delete.
492
797eee42
MF		 4932015-11-15 Mike Frysinger <vapier@gentoo.org>
494
495 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
496
6e4f085c
MF		 4972015-11-14 Mike Frysinger <vapier@gentoo.org>
498
499 * interp.c (sim_close): Rename to ...
500 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
501 sim_io_shutdown.
502 * sim-main.h (mips_sim_close): Declare.
503 (SIM_CLOSE_HOOK): Define.
504
8e394ffc
AB		 5052015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
506 Ali Lown <ali.lown@imgtec.com>
507
508 * Makefile.in (tmp-micromips): New rule.
509 (tmp-mach-multi): Add support for micromips.
510 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
511 that works for both mips64 and micromips64.
512 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
513 micromips32.
514 Add build support for micromips.
515 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
516 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
517 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
518 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
519 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
520 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
521 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
522 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
523 Refactored instruction code to use these functions.
524 * dsp2.igen: Refactored instruction code to use the new functions.
525 * interp.c (decode_coproc): Refactored to work with any instruction
526 encoding.
527 (isa_mode): New variable
528 (RSVD_INSTRUCTION): Changed to 0x00000039.
529 * m16.igen (BREAK16): Refactored instruction to use do_break16.
530 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
531 * micromips.dc: New file.
532 * micromips.igen: New file.
533 * micromips16.dc: New file.
534 * micromipsdsp.igen: New file.
535 * micromipsrun.c: New file.
536 * mips.igen (do_swc1): Changed to work with any instruction encoding.
537 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
538 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
539 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
540 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
541 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
542 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
543 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
544 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
545 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
546 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
547 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
548 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
549 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
550 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
551 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
552 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
553 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
554 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
555 instructions.
556 Refactored instruction code to use these functions.
557 (RSVD): Changed to use new reserved instruction.
558 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
559 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
560 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
561 do_store_double): Added micromips32 and micromips64 models.
562 Added include for micromips.igen and micromipsdsp.igen
563 Add micromips32 and micromips64 models.
564 (DecodeCoproc): Updated to use new macro definition.
565 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
566 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
567 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
568 Refactored instruction code to use these functions.
569 * sim-main.h (CP0_operation): New enum.
570 (DecodeCoproc): Updated macro.
571 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
572 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
573 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
574 ISA_MODE_MICROMIPS): New defines.
575 (sim_state): Add isa_mode field.
576
8d0978fb
MF		 5772015-06-23 Mike Frysinger <vapier@gentoo.org>
578
579 * configure: Regenerate.
580
306f4178
MF		 5812015-06-12 Mike Frysinger <vapier@gentoo.org>
582
583 * configure.ac: Change configure.in to configure.ac.
584 * configure: Regenerate.
585
a3487082
MF		 5862015-06-12 Mike Frysinger <vapier@gentoo.org>
587
588 * configure: Regenerate.
589
29bc024d
MF		 5902015-06-12 Mike Frysinger <vapier@gentoo.org>
591
592 * interp.c [TRACE]: Delete.
593 (TRACE): Change to WITH_TRACE_ANY_P.
594 [!WITH_TRACE_ANY_P] (open_trace): Define.
595 (mips_option_handler, open_trace, sim_close, dotrace):
596 Change defined(TRACE) to WITH_TRACE_ANY_P.
597 (sim_open): Delete TRACE ifdef check.
598 * sim-main.c (load_memory): Delete TRACE ifdef check.
599 (store_memory): Likewise.
600 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
601 [!WITH_TRACE_ANY_P] (dotrace): Define.
602
3ebe2863
MF		 6032015-04-18 Mike Frysinger <vapier@gentoo.org>
604
605 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
606 comments.
607
20bca71d
MF		 6082015-04-18 Mike Frysinger <vapier@gentoo.org>
609
610 * sim-main.h (SIM_CPU): Delete.
611
7e83aa92
MF		 6122015-04-18 Mike Frysinger <vapier@gentoo.org>
613
614 * sim-main.h (sim_cia): Delete.
615
034685f9
MF		 6162015-04-17 Mike Frysinger <vapier@gentoo.org>
617
618 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
619 PU_PC_GET.
620 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
621 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
622 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
623 CIA_SET to CPU_PC_SET.
624 * sim-main.h (CIA_GET, CIA_SET): Delete.
625
78e9aa70
MF		 6262015-04-15 Mike Frysinger <vapier@gentoo.org>
627
628 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
629 * sim-main.h (STATE_CPU): Delete.
630
bf12d44e
MF		 6312015-04-13 Mike Frysinger <vapier@gentoo.org>
632
633 * configure: Regenerate.
634
7bebb329
MF		 6352015-04-13 Mike Frysinger <vapier@gentoo.org>
636
637 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
638 * interp.c (mips_pc_get, mips_pc_set): New functions.
639 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
640 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
641 (sim_pc_get): Delete.
642 * sim-main.h (SIM_CPU): Define.
643 (struct sim_state): Change cpu to an array of pointers.
644 (STATE_CPU): Drop &.
645
8ac57fbd
MF		 6462015-04-13 Mike Frysinger <vapier@gentoo.org>
647
648 * interp.c (mips_option_handler, open_trace, sim_close,
649 sim_write, sim_read, sim_store_register, sim_fetch_register,
650 sim_create_inferior, pr_addr, pr_uword64): Convert old style
651 prototypes.
652 (sim_open): Convert old style prototype. Change casts with
653 sim_write to unsigned char *.
654 (fetch_str): Change null to unsigned char, and change cast to
655 unsigned char *.
656 (sim_monitor): Change c & ch to unsigned char. Change cast to
657 unsigned char *.
658
e787f858
MF		 6592015-04-12 Mike Frysinger <vapier@gentoo.org>
660
661 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
662
122bbfb5
MF		 6632015-04-06 Mike Frysinger <vapier@gentoo.org>
664
665 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
666
0fe84f3f
MF		 6672015-04-01 Mike Frysinger <vapier@gentoo.org>
668
669 * tconfig.h (SIM_HAVE_PROFILE): Delete.
670
aadc9410
MF		 6712015-03-31 Mike Frysinger <vapier@gentoo.org>
672
673 * config.in, configure: Regenerate.
674
05f53ed6
MF		 6752015-03-24 Mike Frysinger <vapier@gentoo.org>
676
677 * interp.c (sim_pc_get): New function.
678
c0931f26
MF		 6792015-03-24 Mike Frysinger <vapier@gentoo.org>
680
681 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
682 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
683
30452bbe
MF		 6842015-03-24 Mike Frysinger <vapier@gentoo.org>
685
686 * configure: Regenerate.
687
64dd13df
MF		 6882015-03-23 Mike Frysinger <vapier@gentoo.org>
689
690 * configure: Regenerate.
691
49cd1634
MF		 6922015-03-23 Mike Frysinger <vapier@gentoo.org>
693
694 * configure: Regenerate.
695 * configure.ac (mips_extra_objs): Delete.
696 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
697 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
698
3649cb06
MF		 6992015-03-23 Mike Frysinger <vapier@gentoo.org>
700
701 * configure: Regenerate.
702 * configure.ac: Delete sim_hw checks for dv-sockser.
703
ae7d0cac
MF		 7042015-03-16 Mike Frysinger <vapier@gentoo.org>
705
706 * config.in, configure: Regenerate.
707 * tconfig.in: Rename file ...
708 * tconfig.h: ... here.
709
8406bb59
MF		 7102015-03-15 Mike Frysinger <vapier@gentoo.org>
711
712 * tconfig.in: Delete includes.
713 [HAVE_DV_SOCKSER]: Delete.
714
465fb143
MF		 7152015-03-14 Mike Frysinger <vapier@gentoo.org>
716
717 * Makefile.in (SIM_RUN_OBJS): Delete.
718
5cddc23a
MF		 7192015-03-14 Mike Frysinger <vapier@gentoo.org>
720
721 * configure.ac (AC_CHECK_HEADERS): Delete.
722 * aclocal.m4, configure: Regenerate.
723
2974be62
AM		 7242014-08-19 Alan Modra <amodra@gmail.com>
725
726 * configure: Regenerate.
727
faa743bb
RM		 7282014-08-15 Roland McGrath <mcgrathr@google.com>
729
730 * configure: Regenerate.
731 * config.in: Regenerate.
732
1a8a700e
MF		 7332014-03-04 Mike Frysinger <vapier@gentoo.org>
734
735 * configure: Regenerate.
736
bf3d9781
AM		 7372013-09-23 Alan Modra <amodra@gmail.com>
738
739 * configure: Regenerate.
740
31e6ad7d
MF		 7412013-06-03 Mike Frysinger <vapier@gentoo.org>
742
743 * aclocal.m4, configure: Regenerate.
744
d3685d60
TT		 7452013-05-10 Freddie Chopin <freddie_chopin@op.pl>
746
747 * configure: Rebuild.
748
1517bd27
MF		 7492013-03-26 Mike Frysinger <vapier@gentoo.org>
750
751 * configure: Regenerate.
752
3be31516
JS		 7532013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
754
755 * configure.ac: Address use of dv-sockser.o.
756 * tconfig.in: Conditionalize use of dv_sockser_install.
757 * configure: Regenerated.
758 * config.in: Regenerated.
759
37cb8f8e
SE		 7602012-10-04 Chao-ying Fu <fu@mips.com>
761 Steve Ellcey <sellcey@mips.com>
762
763 * mips/mips3264r2.igen (rdhwr): New.
764
87c8644f
JS		 7652012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
766
767 * configure.ac: Always link against dv-sockser.o.
768 * configure: Regenerate.
769
5f3ef9d0
JB		 7702012-06-15 Joel Brobecker <brobecker@adacore.com>
771
772 * config.in, configure: Regenerate.
773
a6ff997c
NC		 7742012-05-18 Nick Clifton <nickc@redhat.com>
775
776 PR 14072
777 * interp.c: Include config.h before system header files.
778
2232061b
MF		 7792012-03-24 Mike Frysinger <vapier@gentoo.org>
780
781 * aclocal.m4, config.in, configure: Regenerate.
782
db2e4d67
MF		 7832011-12-03 Mike Frysinger <vapier@gentoo.org>
784
785 * aclocal.m4: New file.
786 * configure: Regenerate.
787
4399a56b
MF		 7882011-10-19 Mike Frysinger <vapier@gentoo.org>
789
790 * configure: Regenerate after common/acinclude.m4 update.
791
9c082ca8
MF		 7922011-10-17 Mike Frysinger <vapier@gentoo.org>
793
794 * configure.ac: Change include to common/acinclude.m4.
795
6ffe910a
MF		 7962011-10-17 Mike Frysinger <vapier@gentoo.org>
797
798 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
799 call. Replace common.m4 include with SIM_AC_COMMON.
800 * configure: Regenerate.
801
31b28250
HPN		 8022011-07-08 Hans-Peter Nilsson <hp@axis.com>
803
3faa01e3
HPN		 804 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
805 $(SIM_EXTRA_DEPS).
806 (tmp-mach-multi): Exit early when igen fails.
31b28250 807
2419798b
MF		 8082011-07-05 Mike Frysinger <vapier@gentoo.org>
809
810 * interp.c (sim_do_command): Delete.
811
d79fe0d6
MF		 8122011-02-14 Mike Frysinger <vapier@gentoo.org>
813
814 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
815 (tx3904sio_fifo_reset): Likewise.
816 * interp.c (sim_monitor): Likewise.
817
5558e7e6
MF		 8182010-04-14 Mike Frysinger <vapier@gentoo.org>
819
820 * interp.c (sim_write): Add const to buffer arg.
821
35aafff4
JB		 8222010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
823
824 * interp.c: Don't include sysdep.h
825
3725885a
RW		 8262010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
827
828 * configure: Regenerate.
829
d6416cdc
RW		 8302009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
831
81ecdfbb
RW		 832 * config.in: Regenerate.
833 * configure: Likewise.
834
d6416cdc
RW		 835 * configure: Regenerate.
836
b5bd9624
HPN		 8372008-07-11 Hans-Peter Nilsson <hp@axis.com>
838
839 * configure: Regenerate to track ../common/common.m4 changes.
840 * config.in: Ditto.
841
6efef468 8422008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 843 Daniel Jacobowitz <dan@codesourcery.com>
844 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 845
846 * configure: Regenerate.
847
60dc88db
RS		 8482007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
849
850 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
851 that unconditionally allows fmt_ps.
852 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
853 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
854 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
855 filter from 64,f to 32,f.
856 (PREFX): Change filter from 64 to 32.
857 (LDXC1, LUXC1): Provide separate mips32r2 implementations
858 that use do_load_double instead of do_load. Make both LUXC1
859 versions unpredictable if SizeFGR () != 64.
860 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
861 instead of do_store. Remove unused variable. Make both SUXC1
862 versions unpredictable if SizeFGR () != 64.
863
599ca73e
RS		 8642007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
865
866 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
867 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
868 shifts for that case.
869
2525df03
NC		 8702007-09-04 Nick Clifton <nickc@redhat.com>
871
872 * interp.c (options enum): Add OPTION_INFO_MEMORY.
873 (display_mem_info): New static variable.
874 (mips_option_handler): Handle OPTION_INFO_MEMORY.
875 (mips_options): Add info-memory and memory-info.
876 (sim_open): After processing the command line and board
877 specification, check display_mem_info. If it is set then
878 call the real handler for the --memory-info command line
879 switch.
880
35ee6e1e
JB		 8812007-08-24 Joel Brobecker <brobecker@adacore.com>
882
883 * configure.ac: Change license of multi-run.c to GPL version 3.
884 * configure: Regenerate.
885
d5fb0879
RS		 8862007-06-28 Richard Sandiford <richard@codesourcery.com>
887
888 * configure.ac, configure: Revert last patch.
889
2a2ce21b
RS		 8902007-06-26 Richard Sandiford <richard@codesourcery.com>
891
892 * configure.ac (sim_mipsisa3264_configs): New variable.
893 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
894 every configuration support all four targets, using the triplet to
895 determine the default.
896 * configure: Regenerate.
897
efdcccc9
RS		 8982007-06-25 Richard Sandiford <richard@codesourcery.com>
899
0a7692b2 900 * Makefile.in (m16run.o): New rule.
efdcccc9 901
f532a356
TS		 9022007-05-15 Thiemo Seufer <ths@mips.com>
903
904 * mips3264r2.igen (DSHD): Fix compile warning.
905
bfe9c90b
TS		 9062007-05-14 Thiemo Seufer <ths@mips.com>
907
908 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
909 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
910 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
911 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
912 for mips32r2.
913
53f4826b
TS		 9142007-03-01 Thiemo Seufer <ths@mips.com>
915
916 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
917 and mips64.
918
8bf3ddc8
TS		 9192007-02-20 Thiemo Seufer <ths@mips.com>
920
921 * dsp.igen: Update copyright notice.
922 * dsp2.igen: Fix copyright notice.
923
8b082fb1 9242007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 925 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 926
927 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
928 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
929 Add dsp2 to sim_igen_machine.
930 * configure: Regenerate.
931 * dsp.igen (do_ph_op): Add MUL support when op = 2.
932 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
933 (mulq_rs.ph): Use do_ph_mulq.
934 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
935 * mips.igen: Add dsp2 model and include dsp2.igen.
936 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
937 for *mips32r2, *mips64r2, *dsp.
938 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
939 for *mips32r2, *mips64r2, *dsp2.
940 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
941
b1004875 9422007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 943 Nigel Stephens <nigel@mips.com>
b1004875
TS		 944
945 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
946 jumps with hazard barrier.
947
f8df4c77 9482007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 949 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 950
951 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
952 after each call to sim_io_write.
953
b1004875 9542007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 955 Nigel Stephens <nigel@mips.com>
b1004875
TS		 956
957 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
958 supported by this simulator.
07802d98
TS		 959 (decode_coproc): Recognise additional CP0 Config registers
960 correctly.
961
14fb6c5a 9622007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 963 Nigel Stephens <nigel@mips.com>
964 David Ung <davidu@mips.com>
14fb6c5a
TS		 965
966 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
967 uninterpreted formats. If fmt is one of the uninterpreted types
968 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
969 fmt_word, and fmt_uninterpreted_64 like fmt_long.
970 (store_fpr): When writing an invalid odd register, set the
971 matching even register to fmt_unknown, not the following register.
972 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
973 the the memory window at offset 0 set by --memory-size command
974 line option.
975 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
976 point register.
977 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
978 register.
979 (sim_monitor): When returning the memory size to the MIPS
980 application, use the value in STATE_MEM_SIZE, not an arbitrary
981 hardcoded value.
982 (cop_lw): Don' mess around with FPR_STATE, just pass
983 fmt_uninterpreted_32 to StoreFPR.
984 (cop_sw): Similarly.
985 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
986 (cop_sd): Similarly.
987 * mips.igen (not_word_value): Single version for mips32, mips64
988 and mips16.
989
c8847145 9902007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 991 Nigel Stephens <nigel@mips.com>
c8847145
TS		 992
993 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
994 MBytes.
995
4b5d35ee
TS		 9962007-02-17 Thiemo Seufer <ths@mips.com>
997
998 * configure.ac (mips*-sde-elf*): Move in front of generic machine
999 configuration.
1000 * configure: Regenerate.
1001
3669427c
TS		 10022007-02-17 Thiemo Seufer <ths@mips.com>
1003
1004 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
1005 Add mdmx to sim_igen_machine.
1006 (mipsisa64*-*-*): Likewise. Remove dsp.
1007 (mipsisa32*-*-*): Remove dsp.
1008 * configure: Regenerate.
1009
109ad085
TS		 10102007-02-13 Thiemo Seufer <ths@mips.com>
1011
1012 * configure.ac: Add mips*-sde-elf* target.
1013 * configure: Regenerate.
1014
921d7ad3
HPN		 10152006-12-21 Hans-Peter Nilsson <hp@axis.com>
1016
1017 * acconfig.h: Remove.
1018 * config.in, configure: Regenerate.
1019
02f97da7
TS		 10202006-11-07 Thiemo Seufer <ths@mips.com>
1021
1022 * dsp.igen (do_w_op): Fix compiler warning.
1023
2d2733fc 10242006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 1025 David Ung <davidu@mips.com>
2d2733fc
TS		 1026
1027 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
1028 sim_igen_machine.
1029 * configure: Regenerate.
1030 * mips.igen (model): Add smartmips.
1031 (MADDU): Increment ACX if carry.
1032 (do_mult): Clear ACX.
1033 (ROR,RORV): Add smartmips.
72f4393d 1034 (include): Include smartmips.igen.
2d2733fc
TS		 1035 * sim-main.h (ACX): Set to REGISTERS[89].
1036 * smartmips.igen: New file.
1037
d85c3a10 10382006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 1039 David Ung <davidu@mips.com>
d85c3a10
TS		 1040
1041 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
1042 mips3264r2.igen. Add missing dependency rules.
1043 * m16e.igen: Support for mips16e save/restore instructions.
1044
e85e3205
RE		 10452006-06-13 Richard Earnshaw <rearnsha@arm.com>
1046
1047 * configure: Regenerated.
1048
2f0122dc
DJ		 10492006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
1050
1051 * configure: Regenerated.
1052
20e95c23
DJ		 10532006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
1054
1055 * configure: Regenerated.
1056
69088b17
CF		 10572006-05-15 Chao-ying Fu <fu@mips.com>
1058
1059 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
1060
0275de4e
NC		 10612006-04-18 Nick Clifton <nickc@redhat.com>
1062
1063 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
1064 statement.
1065
b3a3ffef
HPN		 10662006-03-29 Hans-Peter Nilsson <hp@axis.com>
1067
1068 * configure: Regenerate.
1069
40a5538e
CF		 10702005-12-14 Chao-ying Fu <fu@mips.com>
1071
1072 * Makefile.in (SIM_OBJS): Add dsp.o.
1073 (dsp.o): New dependency.
1074 (IGEN_INCLUDE): Add dsp.igen.
1075 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
1076 mipsisa64*-*-*): Add dsp to sim_igen_machine.
1077 * configure: Regenerate.
1078 * mips.igen: Add dsp model and include dsp.igen.
1079 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
1080 because these instructions are extended in DSP ASE.
1081 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
1082 adding 6 DSP accumulator registers and 1 DSP control register.
1083 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
1084 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
1085 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
1086 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
1087 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
1088 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
1089 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
1090 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
1091 DSPCR_CCOND_SMASK): New define.
1092 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
1093 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
1094
21d14896
ILT		 10952005-07-08 Ian Lance Taylor <ian@airs.com>
1096
1097 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
1098
b16d63da 10992005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 1100 Nigel Stephens <nigel@mips.com>
1101
1102 * mips.igen: New mips16e model and include m16e.igen.
1103 (check_u64): Add mips16e tag.
1104 * m16e.igen: New file for MIPS16e instructions.
1105 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
1106 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
1107 models.
1108 * configure: Regenerate.
b16d63da 1109
e70cb6cd 11102005-05-26 David Ung <davidu@mips.com>
72f4393d 1111
e70cb6cd
CD		 1112 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
1113 tags to all instructions which are applicable to the new ISAs.
1114 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
1115 vr.igen.
1116 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 1117 instructions.
e70cb6cd
CD		 1118 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
1119 to mips.igen.
1120 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
1121 * configure: Regenerate.
72f4393d 1122
2b193c4a
MK		 11232005-03-23 Mark Kettenis <kettenis@gnu.org>
1124
1125 * configure: Regenerate.
1126
35695fd6
AC		 11272005-01-14 Andrew Cagney <cagney@gnu.org>
1128
1129 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
1130 explicit call to AC_CONFIG_HEADER.
1131 * configure: Regenerate.
1132
f0569246
AC		 11332005-01-12 Andrew Cagney <cagney@gnu.org>
1134
1135 * configure.ac: Update to use ../common/common.m4.
1136 * configure: Re-generate.
1137
38f48d72
AC		 11382005-01-11 Andrew Cagney <cagney@localhost.localdomain>
1139
1140 * configure: Regenerated to track ../common/aclocal.m4 changes.
1141
b7026657
AC		 11422005-01-07 Andrew Cagney <cagney@gnu.org>
1143
1144 * configure.ac: Rename configure.in, require autoconf 2.59.
1145 * configure: Re-generate.
1146
379832de
HPN		 11472004-12-08 Hans-Peter Nilsson <hp@axis.com>
1148
1149 * configure: Regenerate for ../common/aclocal.m4 update.
1150
cd62154c 11512004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1152
cd62154c
AC		 1153 Committed by Andrew Cagney.
1154 * m16.igen (CMP, CMPI): Fix assembler.
1155
e5da76ec
CD		 11562004-08-18 Chris Demetriou <cgd@broadcom.com>
1157
1158 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1159 * configure: Regenerate.
1160
139181c8
CD		 11612004-06-25 Chris Demetriou <cgd@broadcom.com>
1162
1163 * configure.in (sim_m16_machine): Include mipsIII.
1164 * configure: Regenerate.
1165
1a27f959
CD		 11662004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1167
72f4393d 1168 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1169 from COP0_BADVADDR.
1170 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1171
5dbb7b5a
CD		 11722004-04-10 Chris Demetriou <cgd@broadcom.com>
1173
1174 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1175
14234056
CD		 11762004-04-09 Chris Demetriou <cgd@broadcom.com>
1177
1178 * mips.igen (check_fmt): Remove.
1179 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1180 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1181 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1182 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1183 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1184 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1185 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1186 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1187 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1188 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1189
c6f9085c
CD		 11902004-04-09 Chris Demetriou <cgd@broadcom.com>
1191
1192 * sb1.igen (check_sbx): New function.
1193 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1194
11d66e66 11952004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1196 Richard Sandiford <rsandifo@redhat.com>
1197
1198 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1199 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1200 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1201 separate implementations for mipsIV and mipsV. Use new macros to
1202 determine whether the restrictions apply.
1203
b3208fb8
CD		 12042004-01-19 Chris Demetriou <cgd@broadcom.com>
1205
1206 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1207 (check_mult_hilo): Improve comments.
1208 (check_div_hilo): Likewise. Also, fork off a new version
1209 to handle mips32/mips64 (since there are no hazards to check
1210 in MIPS32/MIPS64).
1211
9a1d84fb
CD		 12122003-06-17 Richard Sandiford <rsandifo@redhat.com>
1213
1214 * mips.igen (do_dmultx): Fix check for negative operands.
1215
ae451ac6
ILT		 12162003-05-16 Ian Lance Taylor <ian@airs.com>
1217
1218 * Makefile.in (SHELL): Make sure this is defined.
1219 (various): Use $(SHELL) whenever we invoke move-if-change.
1220
dd69d292
CD		 12212003-05-03 Chris Demetriou <cgd@broadcom.com>
1222
1223 * cp1.c: Tweak attribution slightly.
1224 * cp1.h: Likewise.
1225 * mdmx.c: Likewise.
1226 * mdmx.igen: Likewise.
1227 * mips3d.igen: Likewise.
1228 * sb1.igen: Likewise.
1229
bcd0068e
CD		 12302003-04-15 Richard Sandiford <rsandifo@redhat.com>
1231
1232 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1233 unsigned operands.
1234
6b4a8935
AC		 12352003-02-27 Andrew Cagney <cagney@redhat.com>
1236
601da316
AC		 1237 * interp.c (sim_open): Rename _bfd to bfd.
1238 (sim_create_inferior): Ditto.
6b4a8935 1239
d29e330f
CD		 12402003-01-14 Chris Demetriou <cgd@broadcom.com>
1241
1242 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1243
a2353a08
CD		 12442003-01-14 Chris Demetriou <cgd@broadcom.com>
1245
1246 * mips.igen (EI, DI): Remove.
1247
80551777
CD		 12482003-01-05 Richard Sandiford <rsandifo@redhat.com>
1249
1250 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1251
4c54fc26
CD		 12522003-01-04 Richard Sandiford <rsandifo@redhat.com>
1253 Andrew Cagney <ac131313@redhat.com>
1254 Gavin Romig-Koch <gavin@redhat.com>
1255 Graydon Hoare <graydon@redhat.com>
1256 Aldy Hernandez <aldyh@redhat.com>
1257 Dave Brolley <brolley@redhat.com>
1258 Chris Demetriou <cgd@broadcom.com>
1259
1260 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1261 (sim_mach_default): New variable.
1262 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1263 Add a new simulator generator, MULTI.
1264 * configure: Regenerate.
1265 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1266 (multi-run.o): New dependency.
1267 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1268 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1269 (tmp-multi): Combine them.
1270 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1271 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1272 (distclean-extra): New rule.
1273 * sim-main.h: Include bfd.h.
1274 (MIPS_MACH): New macro.
1275 * mips.igen (vr4120, vr5400, vr5500): New models.
1276 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1277 * vr.igen: Replace with new version.
1278
e6c674b8
CD		 12792003-01-04 Chris Demetriou <cgd@broadcom.com>
1280
1281 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1282 * configure: Regenerate.
1283
28f50ac8
CD		 12842002-12-31 Chris Demetriou <cgd@broadcom.com>
1285
1286 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1287 * mips.igen: Remove all invocations of check_branch_bug and
1288 mark_branch_bug.
1289
5071ffe6
CD		 12902002-12-16 Chris Demetriou <cgd@broadcom.com>
1291
72f4393d 1292 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1293
06e7837e
CD		 12942002-07-30 Chris Demetriou <cgd@broadcom.com>
1295
1296 * mips.igen (do_load_double, do_store_double): New functions.
1297 (LDC1, SDC1): Rename to...
1298 (LDC1b, SDC1b): respectively.
1299 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1300
2265c243
MS		 13012002-07-29 Michael Snyder <msnyder@redhat.com>
1302
1303 * cp1.c (fp_recip2): Modify initialization expression so that
1304 GCC will recognize it as constant.
1305
a2f8b4f3
CD		 13062002-06-18 Chris Demetriou <cgd@broadcom.com>
1307
1308 * mdmx.c (SD_): Delete.
1309 (Unpredictable): Re-define, for now, to directly invoke
1310 unpredictable_action().
1311 (mdmx_acc_op): Fix error in .ob immediate handling.
1312
b4b6c939
AC		 13132002-06-18 Andrew Cagney <cagney@redhat.com>
1314
1315 * interp.c (sim_firmware_command): Initialize `address'.
1316
c8cca39f
AC		 13172002-06-16 Andrew Cagney <ac131313@redhat.com>
1318
1319 * configure: Regenerated to track ../common/aclocal.m4 changes.
1320
e7e81181 13212002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1322 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1323
1324 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1325 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1326 * mips.igen: Include mips3d.igen.
1327 (mips3d): New model name for MIPS-3D ASE instructions.
1328 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1329 instructions.
e7e81181
CD		 1330 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1331 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1332 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1333 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1334 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1335 (RSquareRoot1, RSquareRoot2): New macros.
1336 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1337 (fp_rsqrt2): New functions.
1338 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1339 * configure: Regenerate.
1340
3a2b820e 13412002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1342 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1343
1344 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1345 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1346 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1347 (convert): Note that this function is not used for paired-single
1348 format conversions.
1349 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1350 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1351 (check_fmt_p): Enable paired-single support.
1352 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1353 (PUU.PS): New instructions.
1354 (CVT.S.fmt): Don't use this instruction for paired-single format
1355 destinations.
1356 * sim-main.h (FP_formats): New value 'fmt_ps.'
1357 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1358 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1359
d18ea9c2
CD		 13602002-06-12 Chris Demetriou <cgd@broadcom.com>
1361
1362 * mips.igen: Fix formatting of function calls in
1363 many FP operations.
1364
95fd5cee
CD		 13652002-06-12 Chris Demetriou <cgd@broadcom.com>
1366
1367 * mips.igen (MOVN, MOVZ): Trace result.
1368 (TNEI): Print "tnei" as the opcode name in traces.
1369 (CEIL.W): Add disassembly string for traces.
1370 (RSQRT.fmt): Make location of disassembly string consistent
1371 with other instructions.
1372
4f0d55ae
CD		 13732002-06-12 Chris Demetriou <cgd@broadcom.com>
1374
1375 * mips.igen (X): Delete unused function.
1376
3c25f8c7
AC		 13772002-06-08 Andrew Cagney <cagney@redhat.com>
1378
1379 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1380
f3c08b7e 13812002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1382 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1383
1384 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1385 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1386 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1387 (fp_nmsub): New prototypes.
1388 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1389 (NegMultiplySub): New defines.
1390 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1391 (MADD.D, MADD.S): Replace with...
1392 (MADD.fmt): New instruction.
1393 (MSUB.D, MSUB.S): Replace with...
1394 (MSUB.fmt): New instruction.
1395 (NMADD.D, NMADD.S): Replace with...
1396 (NMADD.fmt): New instruction.
1397 (NMSUB.D, MSUB.S): Replace with...
1398 (NMSUB.fmt): New instruction.
1399
52714ff9 14002002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1401 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1402
1403 * cp1.c: Fix more comment spelling and formatting.
1404 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1405 (denorm_mode): New function.
1406 (fpu_unary, fpu_binary): Round results after operation, collect
1407 status from rounding operations, and update the FCSR.
1408 (convert): Collect status from integer conversions and rounding
1409 operations, and update the FCSR. Adjust NaN values that result
1410 from conversions. Convert to use sim_io_eprintf rather than
1411 fprintf, and remove some debugging code.
1412 * cp1.h (fenr_FS): New define.
1413
577d8c4b
CD		 14142002-06-07 Chris Demetriou <cgd@broadcom.com>
1415
1416 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1417 rounding mode to sim FP rounding mode flag conversion code into...
1418 (rounding_mode): New function.
1419
196496ed
CD		 14202002-06-07 Chris Demetriou <cgd@broadcom.com>
1421
1422 * cp1.c: Clean up formatting of a few comments.
1423 (value_fpr): Reformat switch statement.
1424
cfe9ea23 14252002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1426 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1427
1428 * cp1.h: New file.
1429 * sim-main.h: Include cp1.h.
1430 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1431 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1432 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1433 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1434 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1435 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1436 * cp1.c: Don't include sim-fpu.h; already included by
1437 sim-main.h. Clean up formatting of some comments.
1438 (NaN, Equal, Less): Remove.
1439 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1440 (fp_cmp): New functions.
1441 * mips.igen (do_c_cond_fmt): Remove.
1442 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1443 Compare. Add result tracing.
1444 (CxC1): Remove, replace with...
1445 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1446 (DMxC1): Remove, replace with...
1447 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1448 (MxC1): Remove, replace with...
1449 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1450
ee7254b0
CD		 14512002-06-04 Chris Demetriou <cgd@broadcom.com>
1452
1453 * sim-main.h (FGRIDX): Remove, replace all uses with...
1454 (FGR_BASE): New macro.
1455 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1456 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1457 (NR_FGR, FGR): Likewise.
1458 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1459 * mips.igen: Likewise.
1460
d3eb724f
CD		 14612002-06-04 Chris Demetriou <cgd@broadcom.com>
1462
1463 * cp1.c: Add an FSF Copyright notice to this file.
1464
ba46ddd0 14652002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1466 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1467
1468 * cp1.c (Infinity): Remove.
1469 * sim-main.h (Infinity): Likewise.
1470
1471 * cp1.c (fp_unary, fp_binary): New functions.
1472 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1473 (fp_sqrt): New functions, implemented in terms of the above.
1474 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1475 (Recip, SquareRoot): Remove (replaced by functions above).
1476 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1477 (fp_recip, fp_sqrt): New prototypes.
1478 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1479 (Recip, SquareRoot): Replace prototypes with #defines which
1480 invoke the functions above.
72f4393d 1481
18d8a52d
CD		 14822002-06-03 Chris Demetriou <cgd@broadcom.com>
1483
1484 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1485 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1486 file, remove PARAMS from prototypes.
1487 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1488 simulator state arguments.
1489 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1490 pass simulator state arguments.
1491 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1492 (store_fpr, convert): Remove 'sd' argument.
1493 (value_fpr): Likewise. Convert to use 'SD' instead.
1494
0f154cbd
CD		 14952002-06-03 Chris Demetriou <cgd@broadcom.com>
1496
1497 * cp1.c (Min, Max): Remove #if 0'd functions.
1498 * sim-main.h (Min, Max): Remove.
1499
e80fc152
CD		 15002002-06-03 Chris Demetriou <cgd@broadcom.com>
1501
1502 * cp1.c: fix formatting of switch case and default labels.
1503 * interp.c: Likewise.
1504 * sim-main.c: Likewise.
1505
bad673a9
CD		 15062002-06-03 Chris Demetriou <cgd@broadcom.com>
1507
1508 * cp1.c: Clean up comments which describe FP formats.
1509 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1510
7cbea089 15112002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1512 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1513
1514 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1515 Broadcom SiByte SB-1 processor configurations.
1516 * configure: Regenerate.
1517 * sb1.igen: New file.
1518 * mips.igen: Include sb1.igen.
1519 (sb1): New model.
1520 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1521 * mdmx.igen: Add "sb1" model to all appropriate functions and
1522 instructions.
1523 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1524 (ob_func, ob_acc): Reference the above.
1525 (qh_acc): Adjust to keep the same size as ob_acc.
1526 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1527 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1528
909daa82
CD		 15292002-06-03 Chris Demetriou <cgd@broadcom.com>
1530
1531 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1532
f4f1b9f1 15332002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1534 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1535
1536 * mips.igen (mdmx): New (pseudo-)model.
1537 * mdmx.c, mdmx.igen: New files.
1538 * Makefile.in (SIM_OBJS): Add mdmx.o.
1539 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1540 New typedefs.
1541 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1542 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1543 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1544 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1545 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1546 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1547 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1548 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1549 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1550 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1551 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1552 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1553 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1554 (qh_fmtsel): New macros.
1555 (_sim_cpu): New member "acc".
1556 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1557 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1558
5accf1ff
CD		 15592002-05-01 Chris Demetriou <cgd@broadcom.com>
1560
1561 * interp.c: Use 'deprecated' rather than 'depreciated.'
1562 * sim-main.h: Likewise.
1563
402586aa
CD		 15642002-05-01 Chris Demetriou <cgd@broadcom.com>
1565
1566 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1567 which wouldn't compile anyway.
1568 * sim-main.h (unpredictable_action): New function prototype.
1569 (Unpredictable): Define to call igen function unpredictable().
1570 (NotWordValue): New macro to call igen function not_word_value().
1571 (UndefinedResult): Remove.
1572 * interp.c (undefined_result): Remove.
1573 (unpredictable_action): New function.
1574 * mips.igen (not_word_value, unpredictable): New functions.
1575 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1576 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1577 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1578 NotWordValue() to check for unpredictable inputs, then
1579 Unpredictable() to handle them.
1580
c9b9995a
CD		 15812002-02-24 Chris Demetriou <cgd@broadcom.com>
1582
1583 * mips.igen: Fix formatting of calls to Unpredictable().
1584
e1015982
AC		 15852002-04-20 Andrew Cagney <ac131313@redhat.com>
1586
1587 * interp.c (sim_open): Revert previous change.
1588
b882a66b
AO		 15892002-04-18 Alexandre Oliva <aoliva@redhat.com>
1590
1591 * interp.c (sim_open): Disable chunk of code that wrote code in
1592 vector table entries.
1593
c429b7dd
CD		 15942002-03-19 Chris Demetriou <cgd@broadcom.com>
1595
1596 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1597 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1598 unused definitions.
1599
37d146fa
CD		 16002002-03-19 Chris Demetriou <cgd@broadcom.com>
1601
1602 * cp1.c: Fix many formatting issues.
1603
07892c0b
CD		 16042002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1605
1606 * cp1.c (fpu_format_name): New function to replace...
1607 (DOFMT): This. Delete, and update all callers.
1608 (fpu_rounding_mode_name): New function to replace...
1609 (RMMODE): This. Delete, and update all callers.
1610
487f79b7
CD		 16112002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1612
1613 * interp.c: Move FPU support routines from here to...
1614 * cp1.c: Here. New file.
1615 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1616 (cp1.o): New target.
1617
1e799e28
CD		 16182002-03-12 Chris Demetriou <cgd@broadcom.com>
1619
1620 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1621 * mips.igen (mips32, mips64): New models, add to all instructions
1622 and functions as appropriate.
1623 (loadstore_ea, check_u64): New variant for model mips64.
1624 (check_fmt_p): New variant for models mipsV and mips64, remove
1625 mipsV model marking fro other variant.
1626 (SLL) Rename to...
1627 (SLLa) this.
1628 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1629 for mips32 and mips64.
1630 (DCLO, DCLZ): New instructions for mips64.
1631
82f728db
CD		 16322002-03-07 Chris Demetriou <cgd@broadcom.com>
1633
1634 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1635 immediate or code as a hex value with the "%#lx" format.
1636 (ANDI): Likewise, and fix printed instruction name.
1637
b96e7ef1
CD		 16382002-03-05 Chris Demetriou <cgd@broadcom.com>
1639
1640 * sim-main.h (UndefinedResult, Unpredictable): New macros
1641 which currently do nothing.
1642
d35d4f70
CD		 16432002-03-05 Chris Demetriou <cgd@broadcom.com>
1644
1645 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1646 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1647 (status_CU3): New definitions.
1648
1649 * sim-main.h (ExceptionCause): Add new values for MIPS32
1650 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1651 for DebugBreakPoint and NMIReset to note their status in
1652 MIPS32 and MIPS64.
1653 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1654 (SignalExceptionCacheErr): New exception macros.
1655
3ad6f714
CD		 16562002-03-05 Chris Demetriou <cgd@broadcom.com>
1657
1658 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1659 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1660 is always enabled.
1661 (SignalExceptionCoProcessorUnusable): Take as argument the
1662 unusable coprocessor number.
1663
86b77b47
CD		 16642002-03-05 Chris Demetriou <cgd@broadcom.com>
1665
1666 * mips.igen: Fix formatting of all SignalException calls.
1667
97a88e93 16682002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1669
1670 * sim-main.h (SIGNEXTEND): Remove.
1671
97a88e93 16722002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1673
1674 * mips.igen: Remove gencode comment from top of file, fix
1675 spelling in another comment.
1676
97a88e93 16772002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1678
1679 * mips.igen (check_fmt, check_fmt_p): New functions to check
1680 whether specific floating point formats are usable.
1681 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1682 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1683 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1684 Use the new functions.
1685 (do_c_cond_fmt): Remove format checks...
1686 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1687
97a88e93 16882002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1689
1690 * mips.igen: Fix formatting of check_fpu calls.
1691
41774c9d
CD		 16922002-03-03 Chris Demetriou <cgd@broadcom.com>
1693
1694 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1695
4a0bd876
CD		 16962002-03-03 Chris Demetriou <cgd@broadcom.com>
1697
1698 * mips.igen: Remove whitespace at end of lines.
1699
09297648
CD		 17002002-03-02 Chris Demetriou <cgd@broadcom.com>
1701
1702 * mips.igen (loadstore_ea): New function to do effective
1703 address calculations.
1704 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1705 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1706 CACHE): Use loadstore_ea to do effective address computations.
1707
043b7057
CD		 17082002-03-02 Chris Demetriou <cgd@broadcom.com>
1709
1710 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1711 * mips.igen (LL, CxC1, MxC1): Likewise.
1712
c1e8ada4
CD		 17132002-03-02 Chris Demetriou <cgd@broadcom.com>
1714
1715 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1716 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1717 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1718 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1719 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1720 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1721 Don't split opcode fields by hand, use the opcode field values
1722 provided by igen.
1723
3e1dca16
CD		 17242002-03-01 Chris Demetriou <cgd@broadcom.com>
1725
1726 * mips.igen (do_divu): Fix spacing.
1727
1728 * mips.igen (do_dsllv): Move to be right before DSLLV,
1729 to match the rest of the do_<shift> functions.
1730
fff8d27d
CD		 17312002-03-01 Chris Demetriou <cgd@broadcom.com>
1732
1733 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1734 DSRL32, do_dsrlv): Trace inputs and results.
1735
0d3e762b
CD		 17362002-03-01 Chris Demetriou <cgd@broadcom.com>
1737
1738 * mips.igen (CACHE): Provide instruction-printing string.
1739
1740 * interp.c (signal_exception): Comment tokens after #endif.
1741
eb5fcf93
CD		 17422002-02-28 Chris Demetriou <cgd@broadcom.com>
1743
1744 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1745 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1746 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1747 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1748 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1749 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1750 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1751 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1752
bb22bd7d
CD		 17532002-02-28 Chris Demetriou <cgd@broadcom.com>
1754
1755 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1756 instruction-printing string.
1757 (LWU): Use '64' as the filter flag.
1758
91a177cf
CD		 17592002-02-28 Chris Demetriou <cgd@broadcom.com>
1760
1761 * mips.igen (SDXC1): Fix instruction-printing string.
1762
387f484a
CD		 17632002-02-28 Chris Demetriou <cgd@broadcom.com>
1764
1765 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1766 filter flags "32,f".
1767
3d81f391
CD		 17682002-02-27 Chris Demetriou <cgd@broadcom.com>
1769
1770 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1771 as the filter flag.
1772
af5107af
CD		 17732002-02-27 Chris Demetriou <cgd@broadcom.com>
1774
1775 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1776 add a comma) so that it more closely match the MIPS ISA
1777 documentation opcode partitioning.
1778 (PREF): Put useful names on opcode fields, and include
1779 instruction-printing string.
1780
ca971540
CD		 17812002-02-27 Chris Demetriou <cgd@broadcom.com>
1782
1783 * mips.igen (check_u64): New function which in the future will
1784 check whether 64-bit instructions are usable and signal an
1785 exception if not. Currently a no-op.
1786 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1787 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1788 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1789 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1790
1791 * mips.igen (check_fpu): New function which in the future will
1792 check whether FPU instructions are usable and signal an exception
1793 if not. Currently a no-op.
1794 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1795 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1796 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1797 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1798 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1799 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1800 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1801 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1802
1c47a468
CD		 18032002-02-27 Chris Demetriou <cgd@broadcom.com>
1804
1805 * mips.igen (do_load_left, do_load_right): Move to be immediately
1806 following do_load.
1807 (do_store_left, do_store_right): Move to be immediately following
1808 do_store.
1809
603a98e7
CD		 18102002-02-27 Chris Demetriou <cgd@broadcom.com>
1811
1812 * mips.igen (mipsV): New model name. Also, add it to
1813 all instructions and functions where it is appropriate.
1814
c5d00cc7
CD		 18152002-02-18 Chris Demetriou <cgd@broadcom.com>
1816
1817 * mips.igen: For all functions and instructions, list model
1818 names that support that instruction one per line.
1819
074e9cb8
CD		 18202002-02-11 Chris Demetriou <cgd@broadcom.com>
1821
1822 * mips.igen: Add some additional comments about supported
1823 models, and about which instructions go where.
1824 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1825 order as is used in the rest of the file.
1826
9805e229
CD		 18272002-02-11 Chris Demetriou <cgd@broadcom.com>
1828
1829 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1830 indicating that ALU32_END or ALU64_END are there to check
1831 for overflow.
1832 (DADD): Likewise, but also remove previous comment about
1833 overflow checking.
1834
f701dad2
CD		 18352002-02-10 Chris Demetriou <cgd@broadcom.com>
1836
1837 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1838 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1839 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1840 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1841 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1842 fields (i.e., add and move commas) so that they more closely
1843 match the MIPS ISA documentation opcode partitioning.
1844
18452002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1846
72f4393d
L		 1847 * mips.igen (ADDI): Print immediate value.
1848 (BREAK): Print code.
1849 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1850 (SLL): Print "nop" specially, and don't run the code
1851 that does the shift for the "nop" case.
20ae0098 1852
9e52972e
FF		 18532001-11-17 Fred Fish <fnf@redhat.com>
1854
1855 * sim-main.h (float_operation): Move enum declaration outside
1856 of _sim_cpu struct declaration.
1857
c0efbca4
JB		 18582001-04-12 Jim Blandy <jimb@redhat.com>
1859
1860 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1861 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1862 set of the FCSR.
1863 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1864 PENDING_FILL, and you can get the intended effect gracefully by
1865 calling PENDING_SCHED directly.
1866
fb891446
BE		 18672001-02-23 Ben Elliston <bje@redhat.com>
1868
1869 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1870 already defined elsewhere.
1871
8030f857
BE		 18722001-02-19 Ben Elliston <bje@redhat.com>
1873
1874 * sim-main.h (sim_monitor): Return an int.
1875 * interp.c (sim_monitor): Add return values.
1876 (signal_exception): Handle error conditions from sim_monitor.
1877
56b48a7a
CD		 18782001-02-08 Ben Elliston <bje@redhat.com>
1879
1880 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1881 (store_memory): Likewise, pass cia to sim_core_write*.
1882
d3ee60d9
FCE		 18832000-10-19 Frank Ch. Eigler <fche@redhat.com>
1884
1885 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1886 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1887
071da002
AC		 1888Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1889
1890 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1891 * Makefile.in: Don't delete *.igen when cleaning directory.
1892
a28c02cd
AC		 1893Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1894
1895 * m16.igen (break): Call SignalException not sim_engine_halt.
1896
80ee11fa
AC		 1897Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1898
1899 From Jason Eckhardt:
1900 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1901
673388c0
AC		 1902Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1903
1904 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1905
4c0deff4
NC		 19062000-05-24 Michael Hayes <mhayes@cygnus.com>
1907
1908 * mips.igen (do_dmultx): Fix typo.
1909
eb2d80b4
AC		 1910Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1911
1912 * configure: Regenerated to track ../common/aclocal.m4 changes.
1913
dd37a34b
AC		 1914Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1915
1916 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1917
4c0deff4
NC		 19182000-04-12 Frank Ch. Eigler <fche@redhat.com>
1919
1920 * sim-main.h (GPR_CLEAR): Define macro.
1921
e30db738
AC		 1922Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1923
1924 * interp.c (decode_coproc): Output long using %lx and not %s.
1925
cb7450ea
FCE		 19262000-03-21 Frank Ch. Eigler <fche@redhat.com>
1927
1928 * interp.c (sim_open): Sort & extend dummy memory regions for
1929 --board=jmr3904 for eCos.
1930
a3027dd7
FCE		 19312000-03-02 Frank Ch. Eigler <fche@redhat.com>
1932
1933 * configure: Regenerated.
1934
1935Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1936
1937 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1938 calls, conditional on the simulator being in verbose mode.
1939
dfcd3bfb
JM		 1940Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1941
1942 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1943 cache don't get ReservedInstruction traps.
1944
c2d11a7d
JM		 19451999-11-29 Mark Salter <msalter@cygnus.com>
1946
1947 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1948 to clear status bits in sdisr register. This is how the hardware works.
1949
1950 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1951 being used by cygmon.
1952
4ce44c66
JM		 19531999-11-11 Andrew Haley <aph@cygnus.com>
1954
1955 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1956 instructions.
1957
cff3e48b
JM		 1958Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1959
1960 * mips.igen (MULT): Correct previous mis-applied patch.
1961
d4f3574e
SS		 1962Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1963
1964 * mips.igen (delayslot32): Handle sequence like
1965 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1966 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1967 (MULT): Actually pass the third register...
1968
19691999-09-03 Mark Salter <msalter@cygnus.com>
1970
1971 * interp.c (sim_open): Added more memory aliases for additional
1972 hardware being touched by cygmon on jmr3904 board.
1973
1974Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1975
1976 * configure: Regenerated to track ../common/aclocal.m4 changes.
1977
a0b3c4fd
JM		 1978Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1979
1980 * interp.c (sim_store_register): Handle case where client - GDB -
1981 specifies that a 4 byte register is 8 bytes in size.
1982 (sim_fetch_register): Ditto.
72f4393d 1983
adf40b2e
JM		 19841999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1985
1986 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1987 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1988 (idt_monitor_base): Base address for IDT monitor traps.
1989 (pmon_monitor_base): Ditto for PMON.
1990 (lsipmon_monitor_base): Ditto for LSI PMON.
1991 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1992 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1993 (sim_firmware_command): New function.
1994 (mips_option_handler): Call it for OPTION_FIRMWARE.
1995 (sim_open): Allocate memory for idt_monitor region. If "--board"
1996 option was given, add no monitor by default. Add BREAK hooks only if
1997 monitors are also there.
72f4393d 1998
43e526b9
JM		 1999Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
2000
2001 * interp.c (sim_monitor): Flush output before reading input.
2002
2003Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
2004
2005 * tconfig.in (SIM_HANDLES_LMA): Always define.
2006
2007Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
2008
2009 From Mark Salter <msalter@cygnus.com>:
2010 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
2011 (sim_open): Add setup for BSP board.
2012
9846de1b
JM		 2013Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
2014
2015 * mips.igen (MULT, MULTU): Add syntax for two operand version.
2016 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
2017 them as unimplemented.
2018
cd0fc7c3
SS		 20191999-05-08 Felix Lee <flee@cygnus.com>
2020
2021 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 2022
7a292a7a
SS		 20231999-04-21 Frank Ch. Eigler <fche@cygnus.com>
2024
2025 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
2026
2027Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
2028
2029 * configure.in: Any mips64vr5*-*-* target should have
2030 -DTARGET_ENABLE_FR=1.
2031 (default_endian): Any mips64vr*el-*-* target should default to
2032 LITTLE_ENDIAN.
2033 * configure: Re-generate.
2034
20351999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
2036
2037 * mips.igen (ldl): Extend from _16_, not 32.
2038
2039Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
2040
2041 * interp.c (sim_store_register): Force registers written to by GDB
2042 into an un-interpreted state.
2043
c906108c
SS		 20441999-02-05 Frank Ch. Eigler <fche@cygnus.com>
2045
2046 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
2047 CPU, start periodic background I/O polls.
72f4393d 2048 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 2049
20501998-12-30 Frank Ch. Eigler <fche@cygnus.com>
2051
2052 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 2053
c906108c
SS		 2054Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
2055
2056 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
2057 case statement.
2058
20591998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 2060
2061 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 2062 (load_word): Call SIM_CORE_SIGNAL hook on error.
2063 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
2064 starting. For exception dispatching, pass PC instead of NULL_CIA.
2065 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 2066 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 2067 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
2068 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 2069 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 2070 * mips.igen (*): Replace memory-related SignalException* calls
2071 with references to SIM_CORE_SIGNAL hook.
72f4393d 2072
c906108c
SS		 2073 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
2074 fix.
2075 * sim-main.c (*): Minor warning cleanups.
72f4393d 2076
c906108c
SS		 20771998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
2078
2079 * m16.igen (DADDIU5): Correct type-o.
2080
2081Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
2082
2083 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
2084 variables.
2085
2086Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
2087
2088 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
2089 to include path.
2090 (interp.o): Add dependency on itable.h
2091 (oengine.c, gencode): Delete remaining references.
2092 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 2093
c906108c 20941998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 2095
c906108c
SS		 2096 * vr4run.c: New.
2097 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
2098 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
2099 tmp-run-hack) : New.
2100 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 2101 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 2102 Drop the "64" qualifier to get the HACK generator working.
2103 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
2104 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
2105 qualifier to get the hack generator working.
2106 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
2107 (DSLL): Use do_dsll.
2108 (DSLLV): Use do_dsllv.
2109 (DSRA): Use do_dsra.
2110 (DSRL): Use do_dsrl.
2111 (DSRLV): Use do_dsrlv.
2112 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 2113 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 2114 get the HACK generator working.
2115 (MACC) Rename to get the HACK generator working.
2116 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 2117
c906108c
SS		 21181998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
2119
2120 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
2121 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 2122
c906108c
SS		 21231998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
2124
2125 * mips/interp.c (DEBUG): Cleanups.
2126
21271998-12-10 Frank Ch. Eigler <fche@cygnus.com>
2128
2129 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
2130 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 2131
c906108c
SS		 21321998-12-03 Frank Ch. Eigler <fche@cygnus.com>
2133
2134 * interp.c (sim_close): Uninstall modules.
2135
2136Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
2137
2138 * sim-main.h, interp.c (sim_monitor): Change to global
2139 function.
2140
2141Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2142
2143 * configure.in (vr4100): Only include vr4100 instructions in
2144 simulator.
2145 * configure: Re-generate.
2146 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2147
2148Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2149
2150 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2151 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2152 true alternative.
2153
2154 * configure.in (sim_default_gen, sim_use_gen): Replace with
2155 sim_gen.
2156 (--enable-sim-igen): Delete config option. Always using IGEN.
2157 * configure: Re-generate.
72f4393d 2158
c906108c
SS		 2159 * Makefile.in (gencode): Kill, kill, kill.
2160 * gencode.c: Ditto.
72f4393d 2161
c906108c
SS		 2162Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2163
2164 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2165 bit mips16 igen simulator.
2166 * configure: Re-generate.
2167
2168 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2169 as part of vr4100 ISA.
2170 * vr.igen: Mark all instructions as 64 bit only.
2171
2172Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2173
2174 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2175 Pacify GCC.
2176
2177Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2178
2179 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2180 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2181 * configure: Re-generate.
2182
2183 * m16.igen (BREAK): Define breakpoint instruction.
2184 (JALX32): Mark instruction as mips16 and not r3900.
2185 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2186
2187 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2188
2189Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2190
2191 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2192 insn as a debug breakpoint.
2193
2194 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2195 pending.slot_size.
2196 (PENDING_SCHED): Clean up trace statement.
2197 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2198 (PENDING_FILL): Delay write by only one cycle.
2199 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2200
2201 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2202 of pending writes.
2203 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2204 32 & 64.
2205 (pending_tick): Move incrementing of index to FOR statement.
2206 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2207
c906108c
SS		 2208 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2209 build simulator.
2210 * configure: Re-generate.
72f4393d 2211
c906108c
SS		 2212 * interp.c (sim_engine_run OLD): Delete explicit call to
2213 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2214
c906108c
SS		 2215Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2216
2217 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2218 interrupt level number to match changed SignalExceptionInterrupt
2219 macro.
2220
2221Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2222
2223 * interp.c: #include "itable.h" if WITH_IGEN.
2224 (get_insn_name): New function.
2225 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2226 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2227
2228Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2229
2230 * configure: Rebuilt to inhale new common/aclocal.m4.
2231
2232Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2233
2234 * dv-tx3904sio.c: Include sim-assert.h.
2235
2236Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2237
2238 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2239 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2240 Reorganize target-specific sim-hardware checks.
2241 * configure: rebuilt.
2242 * interp.c (sim_open): For tx39 target boards, set
2243 OPERATING_ENVIRONMENT, add tx3904sio devices.
2244 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2245 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2246
c906108c
SS		 2247 * dv-tx3904irc.c: Compiler warning clean-up.
2248 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2249 frequent hw-trace messages.
2250
2251Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2252
2253 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2254
2255Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2256
2257 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2258
2259 * vr.igen: New file.
2260 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2261 * mips.igen: Define vr4100 model. Include vr.igen.
2262Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2263
2264 * mips.igen (check_mf_hilo): Correct check.
2265
2266Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2267
2268 * sim-main.h (interrupt_event): Add prototype.
2269
2270 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2271 register_ptr, register_value.
2272 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2273
2274 * sim-main.h (tracefh): Make extern.
2275
2276Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2277
2278 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2279 Reduce unnecessarily high timer event frequency.
c906108c 2280 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2281
c906108c
SS		 2282Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2283
2284 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2285 to allay warnings.
2286 (interrupt_event): Made non-static.
72f4393d 2287
c906108c
SS		 2288 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2289 interchange of configuration values for external vs. internal
2290 clock dividers.
72f4393d 2291
c906108c
SS		 2292Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2293
72f4393d 2294 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2295 simulator-reserved break instructions.
2296 * gencode.c (build_instruction): Ditto.
2297 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2298 reserved instructions now use exception vector, rather
c906108c
SS		 2299 than halting sim.
2300 * sim-main.h: Moved magic constants to here.
2301
2302Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2303
2304 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2305 register upon non-zero interrupt event level, clear upon zero
2306 event value.
2307 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2308 by passing zero event value.
2309 (*_io_{read,write}_buffer): Endianness fixes.
2310 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2311 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2312
2313 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2314 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2315
c906108c
SS		 2316Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2317
72f4393d 2318 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2319 and BigEndianCPU.
2320
2321Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2322
2323 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2324 parts.
2325 * configure: Update.
2326
2327Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2328
2329 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2330 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2331 * configure.in: Include tx3904tmr in hw_device list.
2332 * configure: Rebuilt.
2333 * interp.c (sim_open): Instantiate three timer instances.
2334 Fix address typo of tx3904irc instance.
2335
2336Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2337
2338 * interp.c (signal_exception): SystemCall exception now uses
2339 the exception vector.
2340
2341Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2342
2343 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2344 to allay warnings.
2345
2346Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2347
2348 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2349
2350Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2351
2352 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2353
2354 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2355 sim-main.h. Declare a struct hw_descriptor instead of struct
2356 hw_device_descriptor.
2357
2358Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2359
2360 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2361 right bits and then re-align left hand bytes to correct byte
2362 lanes. Fix incorrect computation in do_store_left when loading
2363 bytes from second word.
2364
2365Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2366
2367 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2368 * interp.c (sim_open): Only create a device tree when HW is
2369 enabled.
2370
2371 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2372 * interp.c (signal_exception): Ditto.
2373
2374Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2375
2376 * gencode.c: Mark BEGEZALL as LIKELY.
2377
2378Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2379
2380 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2381 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2382
c906108c
SS		 2383Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2384
2385 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2386 modules. Recognize TX39 target with "mips*tx39" pattern.
2387 * configure: Rebuilt.
2388 * sim-main.h (*): Added many macros defining bits in
2389 TX39 control registers.
2390 (SignalInterrupt): Send actual PC instead of NULL.
2391 (SignalNMIReset): New exception type.
2392 * interp.c (board): New variable for future use to identify
2393 a particular board being simulated.
2394 (mips_option_handler,mips_options): Added "--board" option.
2395 (interrupt_event): Send actual PC.
2396 (sim_open): Make memory layout conditional on board setting.
2397 (signal_exception): Initial implementation of hardware interrupt
2398 handling. Accept another break instruction variant for simulator
2399 exit.
2400 (decode_coproc): Implement RFE instruction for TX39.
2401 (mips.igen): Decode RFE instruction as such.
2402 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2403 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2404 bbegin to implement memory map.
2405 * dv-tx3904cpu.c: New file.
2406 * dv-tx3904irc.c: New file.
2407
2408Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2409
2410 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2411
2412Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2413
2414 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2415 with calls to check_div_hilo.
2416
2417Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2418
2419 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2420 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2421 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2422 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2423 with calls to check_mult_hilo.
2424 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2425 with calls to check_div_hilo.
2426
2427Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2428
2429 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2430 Document a replacement.
2431
2432Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2433
2434 * interp.c (sim_monitor): Make mon_printf work.
2435
2436Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2437
2438 * sim-main.h (INSN_NAME): New arg `cpu'.
2439
2440Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2441
72f4393d 2442 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2443
2444Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2445
2446 * configure: Regenerated to track ../common/aclocal.m4 changes.
2447 * config.in: Ditto.
2448
2449Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2450
2451 * acconfig.h: New file.
2452 * configure.in: Reverted change of Apr 24; use sinclude again.
2453
2454Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2455
2456 * configure: Regenerated to track ../common/aclocal.m4 changes.
2457 * config.in: Ditto.
2458
2459Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2460
2461 * configure.in: Don't call sinclude.
2462
2463Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2464
2465 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2466
2467Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2468
2469 * mips.igen (ERET): Implement.
2470
2471 * interp.c (decode_coproc): Return sign-extended EPC.
2472
2473 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2474
2475 * interp.c (signal_exception): Do not ignore Trap.
2476 (signal_exception): On TRAP, restart at exception address.
2477 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2478 (signal_exception): Update.
2479 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2480 so that TRAP instructions are caught.
2481
2482Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2483
2484 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2485 contains HI/LO access history.
2486 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2487 (HIACCESS, LOACCESS): Delete, replace with
2488 (HIHISTORY, LOHISTORY): New macros.
2489 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2490
c906108c
SS		 2491 * gencode.c (build_instruction): Do not generate checks for
2492 correct HI/LO register usage.
2493
2494 * interp.c (old_engine_run): Delete checks for correct HI/LO
2495 register usage.
2496
2497 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2498 check_mf_cycles): New functions.
2499 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2500 do_divu, domultx, do_mult, do_multu): Use.
2501
2502 * tx.igen ("madd", "maddu"): Use.
72f4393d 2503
c906108c
SS		 2504Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2505
2506 * mips.igen (DSRAV): Use function do_dsrav.
2507 (SRAV): Use new function do_srav.
2508
2509 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2510 (B): Sign extend 11 bit immediate.
2511 (EXT-B*): Shift 16 bit immediate left by 1.
2512 (ADDIU*): Don't sign extend immediate value.
2513
2514Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2515
2516 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2517
2518 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2519 functions.
2520
2521 * mips.igen (delayslot32, nullify_next_insn): New functions.
2522 (m16.igen): Always include.
2523 (do_*): Add more tracing.
2524
2525 * m16.igen (delayslot16): Add NIA argument, could be called by a
2526 32 bit MIPS16 instruction.
72f4393d 2527
c906108c
SS		 2528 * interp.c (ifetch16): Move function from here.
2529 * sim-main.c (ifetch16): To here.
72f4393d 2530
c906108c
SS		 2531 * sim-main.c (ifetch16, ifetch32): Update to match current
2532 implementations of LH, LW.
2533 (signal_exception): Don't print out incorrect hex value of illegal
2534 instruction.
2535
2536Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2537
2538 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2539 instruction.
2540
2541 * m16.igen: Implement MIPS16 instructions.
72f4393d 2542
c906108c
SS		 2543 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2544 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2545 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2546 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2547 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2548 bodies of corresponding code from 32 bit insn to these. Also used
2549 by MIPS16 versions of functions.
72f4393d 2550
c906108c
SS		 2551 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2552 (IMEM16): Drop NR argument from macro.
2553
2554Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2555
2556 * Makefile.in (SIM_OBJS): Add sim-main.o.
2557
2558 * sim-main.h (address_translation, load_memory, store_memory,
2559 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2560 as INLINE_SIM_MAIN.
2561 (pr_addr, pr_uword64): Declare.
2562 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2563
c906108c
SS		 2564 * interp.c (address_translation, load_memory, store_memory,
2565 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2566 from here.
2567 * sim-main.c: To here. Fix compilation problems.
72f4393d 2568
c906108c
SS		 2569 * configure.in: Enable inlining.
2570 * configure: Re-config.
2571
2572Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2573
2574 * configure: Regenerated to track ../common/aclocal.m4 changes.
2575
2576Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2577
2578 * mips.igen: Include tx.igen.
2579 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2580 * tx.igen: New file, contains MADD and MADDU.
2581
2582 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2583 the hardwired constant `7'.
2584 (store_memory): Ditto.
2585 (LOADDRMASK): Move definition to sim-main.h.
2586
2587 mips.igen (MTC0): Enable for r3900.
2588 (ADDU): Add trace.
2589
2590 mips.igen (do_load_byte): Delete.
2591 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2592 do_store_right): New functions.
2593 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2594
2595 configure.in: Let the tx39 use igen again.
2596 configure: Update.
72f4393d 2597
c906108c
SS		 2598Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2599
2600 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2601 not an address sized quantity. Return zero for cache sizes.
2602
2603Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2604
2605 * mips.igen (r3900): r3900 does not support 64 bit integer
2606 operations.
2607
2608Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2609
2610 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2611 than igen one.
2612 * configure : Rebuild.
72f4393d 2613
c906108c
SS		 2614Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2615
2616 * configure: Regenerated to track ../common/aclocal.m4 changes.
2617
2618Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2619
2620 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2621
2622Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2623
2624 * configure: Regenerated to track ../common/aclocal.m4 changes.
2625 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2626
2627Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2628
2629 * configure: Regenerated to track ../common/aclocal.m4 changes.
2630
2631Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2632
2633 * interp.c (Max, Min): Comment out functions. Not yet used.
2634
2635Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2636
2637 * configure: Regenerated to track ../common/aclocal.m4 changes.
2638
2639Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2640
2641 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2642 configurable settings for stand-alone simulator.
72f4393d 2643
c906108c 2644 * configure.in: Added X11 search, just in case.
72f4393d 2645
c906108c
SS		 2646 * configure: Regenerated.
2647
2648Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2649
2650 * interp.c (sim_write, sim_read, load_memory, store_memory):
2651 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2652
2653Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2654
2655 * sim-main.h (GETFCC): Return an unsigned value.
2656
2657Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2658
2659 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2660 (DADD): Result destination is RD not RT.
2661
2662Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2663
2664 * sim-main.h (HIACCESS, LOACCESS): Always define.
2665
2666 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2667
2668 * interp.c (sim_info): Delete.
2669
2670Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2671
2672 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2673 (mips_option_handler): New argument `cpu'.
2674 (sim_open): Update call to sim_add_option_table.
2675
2676Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2677
2678 * mips.igen (CxC1): Add tracing.
2679
2680Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2681
2682 * sim-main.h (Max, Min): Declare.
2683
2684 * interp.c (Max, Min): New functions.
2685
2686 * mips.igen (BC1): Add tracing.
72f4393d 2687
c906108c 2688Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2689
c906108c 2690 * interp.c Added memory map for stack in vr4100
72f4393d 2691
c906108c
SS		 2692Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2693
2694 * interp.c (load_memory): Add missing "break"'s.
2695
2696Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2697
2698 * interp.c (sim_store_register, sim_fetch_register): Pass in
2699 length parameter. Return -1.
2700
2701Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2702
2703 * interp.c: Added hardware init hook, fixed warnings.
2704
2705Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2706
2707 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2708
2709Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2710
2711 * interp.c (ifetch16): New function.
2712
2713 * sim-main.h (IMEM32): Rename IMEM.
2714 (IMEM16_IMMED): Define.
2715 (IMEM16): Define.
2716 (DELAY_SLOT): Update.
72f4393d 2717
c906108c 2718 * m16run.c (sim_engine_run): New file.
72f4393d 2719
c906108c
SS		 2720 * m16.igen: All instructions except LB.
2721 (LB): Call do_load_byte.
2722 * mips.igen (do_load_byte): New function.
2723 (LB): Call do_load_byte.
2724
2725 * mips.igen: Move spec for insn bit size and high bit from here.
2726 * Makefile.in (tmp-igen, tmp-m16): To here.
2727
2728 * m16.dc: New file, decode mips16 instructions.
2729
2730 * Makefile.in (SIM_NO_ALL): Define.
2731 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2732
2733Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2734
2735 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2736 point unit to 32 bit registers.
2737 * configure: Re-generate.
2738
2739Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2740
2741 * configure.in (sim_use_gen): Make IGEN the default simulator
2742 generator for generic 32 and 64 bit mips targets.
2743 * configure: Re-generate.
2744
2745Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2746
2747 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2748 bitsize.
2749
2750 * interp.c (sim_fetch_register, sim_store_register): Read/write
2751 FGR from correct location.
2752 (sim_open): Set size of FGR's according to
2753 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2754
c906108c
SS		 2755 * sim-main.h (FGR): Store floating point registers in a separate
2756 array.
2757
2758Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2759
2760 * configure: Regenerated to track ../common/aclocal.m4 changes.
2761
2762Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2763
2764 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2765
2766 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2767
2768 * interp.c (pending_tick): New function. Deliver pending writes.
2769
2770 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2771 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2772 it can handle mixed sized quantites and single bits.
72f4393d 2773
c906108c
SS		 2774Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2775
2776 * interp.c (oengine.h): Do not include when building with IGEN.
2777 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2778 (sim_info): Ditto for PROCESSOR_64BIT.
2779 (sim_monitor): Replace ut_reg with unsigned_word.
2780 (*): Ditto for t_reg.
2781 (LOADDRMASK): Define.
2782 (sim_open): Remove defunct check that host FP is IEEE compliant,
2783 using software to emulate floating point.
2784 (value_fpr, ...): Always compile, was conditional on HASFPU.
2785
2786Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2787
2788 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2789 size.
2790
2791 * interp.c (SD, CPU): Define.
2792 (mips_option_handler): Set flags in each CPU.
2793 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2794 (sim_close): Do not clear STATE, deleted anyway.
2795 (sim_write, sim_read): Assume CPU zero's vm should be used for
2796 data transfers.
2797 (sim_create_inferior): Set the PC for all processors.
2798 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2799 argument.
2800 (mips16_entry): Pass correct nr of args to store_word, load_word.
2801 (ColdReset): Cold reset all cpu's.
2802 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2803 (sim_monitor, load_memory, store_memory, signal_exception): Use
2804 `CPU' instead of STATE_CPU.
2805
2806
2807 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2808 SD or CPU_.
72f4393d 2809
c906108c
SS		 2810 * sim-main.h (signal_exception): Add sim_cpu arg.
2811 (SignalException*): Pass both SD and CPU to signal_exception.
2812 * interp.c (signal_exception): Update.
72f4393d 2813
c906108c
SS		 2814 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2815 Ditto
2816 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2817 address_translation): Ditto
2818 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2819
c906108c
SS		 2820Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2821
2822 * configure: Regenerated to track ../common/aclocal.m4 changes.
2823
2824Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2825
2826 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2827
72f4393d 2828 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2829
2830 * sim-main.h (CPU_CIA): Delete.
2831 (SET_CIA, GET_CIA): Define
2832
2833Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2834
2835 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2836 regiser.
2837
2838 * configure.in (default_endian): Configure a big-endian simulator
2839 by default.
2840 * configure: Re-generate.
72f4393d 2841
c906108c
SS		 2842Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2843
2844 * configure: Regenerated to track ../common/aclocal.m4 changes.
2845
2846Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2847
2848 * interp.c (sim_monitor): Handle Densan monitor outbyte
2849 and inbyte functions.
2850
28511997-12-29 Felix Lee <flee@cygnus.com>
2852
2853 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2854
2855Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2856
2857 * Makefile.in (tmp-igen): Arrange for $zero to always be
2858 reset to zero after every instruction.
2859
2860Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2861
2862 * configure: Regenerated to track ../common/aclocal.m4 changes.
2863 * config.in: Ditto.
2864
2865Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2866
2867 * mips.igen (MSUB): Fix to work like MADD.
2868 * gencode.c (MSUB): Similarly.
2869
2870Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2871
2872 * configure: Regenerated to track ../common/aclocal.m4 changes.
2873
2874Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2875
2876 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2877
2878Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2879
2880 * sim-main.h (sim-fpu.h): Include.
2881
2882 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2883 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2884 using host independant sim_fpu module.
2885
2886Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2887
2888 * interp.c (signal_exception): Report internal errors with SIGABRT
2889 not SIGQUIT.
2890
2891 * sim-main.h (C0_CONFIG): New register.
2892 (signal.h): No longer include.
2893
2894 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2895
2896Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2897
2898 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2899
2900Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2901
2902 * mips.igen: Tag vr5000 instructions.
2903 (ANDI): Was missing mipsIV model, fix assembler syntax.
2904 (do_c_cond_fmt): New function.
2905 (C.cond.fmt): Handle mips I-III which do not support CC field
2906 separatly.
2907 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2908 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2909 in IV3.2 spec.
2910 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2911 vr5000 which saves LO in a GPR separatly.
72f4393d 2912
c906108c
SS		 2913 * configure.in (enable-sim-igen): For vr5000, select vr5000
2914 specific instructions.
2915 * configure: Re-generate.
72f4393d 2916
c906108c
SS		 2917Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2918
2919 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2920
2921 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2922 fmt_uninterpreted_64 bit cases to switch. Convert to
2923 fmt_formatted,
2924
2925 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2926
2927 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2928 as specified in IV3.2 spec.
2929 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2930
2931Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2932
2933 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2934 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2935 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2936 PENDING_FILL versions of instructions. Simplify.
2937 (X): New function.
2938 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2939 instructions.
2940 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2941 a signed value.
2942 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2943
c906108c
SS		 2944 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2945 global.
2946 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2947
2948Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2949
2950 * gencode.c (build_mips16_operands): Replace IPC with cia.
2951
2952 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2953 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2954 IPC to `cia'.
2955 (UndefinedResult): Replace function with macro/function
2956 combination.
2957 (sim_engine_run): Don't save PC in IPC.
2958
2959 * sim-main.h (IPC): Delete.
2960
2961
2962 * interp.c (signal_exception, store_word, load_word,
2963 address_translation, load_memory, store_memory, cache_op,
2964 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2965 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2966 current instruction address - cia - argument.
2967 (sim_read, sim_write): Call address_translation directly.
2968 (sim_engine_run): Rename variable vaddr to cia.
2969 (signal_exception): Pass cia to sim_monitor
72f4393d 2970
c906108c
SS		 2971 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2972 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2973 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2974
2975 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2976 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2977 SIM_ASSERT.
72f4393d 2978
c906108c
SS		 2979 * interp.c (signal_exception): Pass restart address to
2980 sim_engine_restart.
2981
2982 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2983 idecode.o): Add dependency.
2984
2985 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2986 Delete definitions
2987 (DELAY_SLOT): Update NIA not PC with branch address.
2988 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2989
2990 * mips.igen: Use CIA not PC in branch calculations.
2991 (illegal): Call SignalException.
2992 (BEQ, ADDIU): Fix assembler.
2993
2994Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2995
2996 * m16.igen (JALX): Was missing.
2997
2998 * configure.in (enable-sim-igen): New configuration option.
2999 * configure: Re-generate.
72f4393d 3000
c906108c
SS		 3001 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
3002
3003 * interp.c (load_memory, store_memory): Delete parameter RAW.
3004 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
3005 bypassing {load,store}_memory.
3006
3007 * sim-main.h (ByteSwapMem): Delete definition.
3008
3009 * Makefile.in (SIM_OBJS): Add sim-memopt module.
3010
3011 * interp.c (sim_do_command, sim_commands): Delete mips specific
3012 commands. Handled by module sim-options.
72f4393d 3013
c906108c
SS		 3014 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
3015 (WITH_MODULO_MEMORY): Define.
3016
3017 * interp.c (sim_info): Delete code printing memory size.
3018
3019 * interp.c (mips_size): Nee sim_size, delete function.
3020 (power2): Delete.
3021 (monitor, monitor_base, monitor_size): Delete global variables.
3022 (sim_open, sim_close): Delete code creating monitor and other
3023 memory regions. Use sim-memopts module, via sim_do_commandf, to
3024 manage memory regions.
3025 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 3026
c906108c
SS		 3027 * interp.c (address_translation): Delete all memory map code
3028 except line forcing 32 bit addresses.
3029
3030Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
3031
3032 * sim-main.h (WITH_TRACE): Delete definition. Enables common
3033 trace options.
3034
3035 * interp.c (logfh, logfile): Delete globals.
3036 (sim_open, sim_close): Delete code opening & closing log file.
3037 (mips_option_handler): Delete -l and -n options.
3038 (OPTION mips_options): Ditto.
3039
3040 * interp.c (OPTION mips_options): Rename option trace to dinero.
3041 (mips_option_handler): Update.
3042
3043Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3044
3045 * interp.c (fetch_str): New function.
3046 (sim_monitor): Rewrite using sim_read & sim_write.
3047 (sim_open): Check magic number.
3048 (sim_open): Write monitor vectors into memory using sim_write.
3049 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
3050 (sim_read, sim_write): Simplify - transfer data one byte at a
3051 time.
3052 (load_memory, store_memory): Clarify meaning of parameter RAW.
3053
3054 * sim-main.h (isHOST): Defete definition.
3055 (isTARGET): Mark as depreciated.
3056 (address_translation): Delete parameter HOST.
3057
3058 * interp.c (address_translation): Delete parameter HOST.
3059
3060Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3061
72f4393d 3062 * mips.igen:
c906108c
SS		 3063
3064 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
3065 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
3066
3067Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
3068
3069 * mips.igen: Add model filter field to records.
3070
3071Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3072
3073 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 3074
c906108c
SS		 3075 interp.c (sim_engine_run): Do not compile function sim_engine_run
3076 when WITH_IGEN == 1.
3077
3078 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
3079 target architecture.
3080
3081 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
3082 igen. Replace with configuration variables sim_igen_flags /
3083 sim_m16_flags.
3084
3085 * m16.igen: New file. Copy mips16 insns here.
3086 * mips.igen: From here.
3087
3088Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3089
3090 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
3091 to top.
3092 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
3093
3094Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
3095
3096 * gencode.c (build_instruction): Follow sim_write's lead in using
3097 BigEndianMem instead of !ByteSwapMem.
3098
3099Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
3100
3101 * configure.in (sim_gen): Dependent on target, select type of
3102 generator. Always select old style generator.
3103
3104 configure: Re-generate.
3105
3106 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
3107 targets.
3108 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
3109 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
3110 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
3111 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
3112 SIM_@sim_gen@_*, set by autoconf.
72f4393d 3113
c906108c
SS		 3114Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3115
3116 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
3117
3118 * interp.c (ColdReset): Remove #ifdef HASFPU, check
3119 CURRENT_FLOATING_POINT instead.
3120
3121 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
3122 (address_translation): Raise exception InstructionFetch when
3123 translation fails and isINSTRUCTION.
72f4393d 3124
c906108c
SS		 3125 * interp.c (sim_open, sim_write, sim_monitor, store_word,
3126 sim_engine_run): Change type of of vaddr and paddr to
3127 address_word.
3128 (address_translation, prefetch, load_memory, store_memory,
3129 cache_op): Change type of vAddr and pAddr to address_word.
3130
3131 * gencode.c (build_instruction): Change type of vaddr and paddr to
3132 address_word.
3133
3134Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
3135
3136 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
3137 macro to obtain result of ALU op.
3138
3139Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3140
3141 * interp.c (sim_info): Call profile_print.
3142
3143Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3144
3145 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3146
3147 * sim-main.h (WITH_PROFILE): Do not define, defined in
3148 common/sim-config.h. Use sim-profile module.
3149 (simPROFILE): Delete defintion.
3150
3151 * interp.c (PROFILE): Delete definition.
3152 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3153 (sim_close): Delete code writing profile histogram.
3154 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3155 Delete.
3156 (sim_engine_run): Delete code profiling the PC.
3157
3158Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3159
3160 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3161
3162 * interp.c (sim_monitor): Make register pointers of type
3163 unsigned_word*.
3164
3165 * sim-main.h: Make registers of type unsigned_word not
3166 signed_word.
3167
3168Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3169
3170 * interp.c (sync_operation): Rename from SyncOperation, make
3171 global, add SD argument.
3172 (prefetch): Rename from Prefetch, make global, add SD argument.
3173 (decode_coproc): Make global.
3174
3175 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3176
3177 * gencode.c (build_instruction): Generate DecodeCoproc not
3178 decode_coproc calls.
3179
3180 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3181 (SizeFGR): Move to sim-main.h
3182 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3183 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3184 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3185 sim-main.h.
3186 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3187 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3188 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3189 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3190 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3191 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3192
c906108c
SS		 3193 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3194 exception.
3195 (sim-alu.h): Include.
3196 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3197 (sim_cia): Typedef to instruction_address.
72f4393d 3198
c906108c
SS		 3199Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3200
3201 * Makefile.in (interp.o): Rename generated file engine.c to
3202 oengine.c.
72f4393d 3203
c906108c 3204 * interp.c: Update.
72f4393d 3205
c906108c
SS		 3206Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3207
3208 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3209
c906108c
SS		 3210Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3211
3212 * gencode.c (build_instruction): For "FPSQRT", output correct
3213 number of arguments to Recip.
72f4393d 3214
c906108c
SS		 3215Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3216
3217 * Makefile.in (interp.o): Depends on sim-main.h
3218
3219 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3220
3221 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3222 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3223 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3224 STATE, DSSTATE): Define
3225 (GPR, FGRIDX, ..): Define.
3226
3227 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3228 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3229 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3230
c906108c 3231 * interp.c: Update names to match defines from sim-main.h
72f4393d 3232
c906108c
SS		 3233Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3234
3235 * interp.c (sim_monitor): Add SD argument.
3236 (sim_warning): Delete. Replace calls with calls to
3237 sim_io_eprintf.
3238 (sim_error): Delete. Replace calls with sim_io_error.
3239 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3240 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3241 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3242 argument.
3243 (mips_size): Rename from sim_size. Add SD argument.
3244
3245 * interp.c (simulator): Delete global variable.
3246 (callback): Delete global variable.
3247 (mips_option_handler, sim_open, sim_write, sim_read,
3248 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3249 sim_size,sim_monitor): Use sim_io_* not callback->*.
3250 (sim_open): ZALLOC simulator struct.
3251 (PROFILE): Do not define.
3252
3253Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3254
3255 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3256 support.h with corresponding code.
3257
3258 * sim-main.h (word64, uword64), support.h: Move definition to
3259 sim-main.h.
3260 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3261
3262 * support.h: Delete
3263 * Makefile.in: Update dependencies
3264 * interp.c: Do not include.
72f4393d 3265
c906108c
SS		 3266Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3267
3268 * interp.c (address_translation, load_memory, store_memory,
3269 cache_op): Rename to from AddressTranslation et.al., make global,
3270 add SD argument
72f4393d 3271
c906108c
SS		 3272 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3273 CacheOp): Define.
72f4393d 3274
c906108c
SS		 3275 * interp.c (SignalException): Rename to signal_exception, make
3276 global.
3277
3278 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3279
c906108c
SS		 3280 * sim-main.h (SignalException, SignalExceptionInterrupt,
3281 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3282 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3283 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3284 Define.
72f4393d 3285
c906108c 3286 * interp.c, support.h: Use.
72f4393d 3287
c906108c
SS		 3288Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3289
3290 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3291 to value_fpr / store_fpr. Add SD argument.
3292 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3293 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3294
3295 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3296
c906108c
SS		 3297Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3298
3299 * interp.c (sim_engine_run): Check consistency between configure
3300 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3301 and HASFPU.
3302
3303 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3304 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3305 (mips_endian): Configure WITH_TARGET_ENDIAN.
3306 * configure: Update.
3307
3308Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3309
3310 * configure: Regenerated to track ../common/aclocal.m4 changes.
3311
3312Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3313
3314 * configure: Regenerated.
3315
3316Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3317
3318 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3319
3320Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3321
3322 * gencode.c (print_igen_insn_models): Assume certain architectures
3323 include all mips* instructions.
3324 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3325 instruction.
3326
3327 * Makefile.in (tmp.igen): Add target. Generate igen input from
3328 gencode file.
3329
3330 * gencode.c (FEATURE_IGEN): Define.
3331 (main): Add --igen option. Generate output in igen format.
3332 (process_instructions): Format output according to igen option.
3333 (print_igen_insn_format): New function.
3334 (print_igen_insn_models): New function.
3335 (process_instructions): Only issue warnings and ignore
3336 instructions when no FEATURE_IGEN.
3337
3338Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3339
3340 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3341 MIPS targets.
3342
3343Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3344
3345 * configure: Regenerated to track ../common/aclocal.m4 changes.
3346
3347Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3348
3349 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3350 SIM_RESERVED_BITS): Delete, moved to common.
3351 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3352
c906108c
SS		 3353Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3354
3355 * configure.in: Configure non-strict memory alignment.
3356 * configure: Regenerated to track ../common/aclocal.m4 changes.
3357
3358Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3359
3360 * configure: Regenerated to track ../common/aclocal.m4 changes.
3361
3362Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3363
3364 * gencode.c (SDBBP,DERET): Added (3900) insns.
3365 (RFE): Turn on for 3900.
3366 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3367 (dsstate): Made global.
3368 (SUBTARGET_R3900): Added.
3369 (CANCELDELAYSLOT): New.
3370 (SignalException): Ignore SystemCall rather than ignore and
3371 terminate. Add DebugBreakPoint handling.
3372 (decode_coproc): New insns RFE, DERET; and new registers Debug
3373 and DEPC protected by SUBTARGET_R3900.
3374 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3375 bits explicitly.
3376 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3377 * configure: Update.
c906108c
SS		 3378
3379Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3380
3381 * gencode.c: Add r3900 (tx39).
72f4393d 3382
c906108c
SS		 3383
3384Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3385
3386 * gencode.c (build_instruction): Don't need to subtract 4 for
3387 JALR, just 2.
3388
3389Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3390
3391 * interp.c: Correct some HASFPU problems.
3392
3393Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3394
3395 * configure: Regenerated to track ../common/aclocal.m4 changes.
3396
3397Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3398
3399 * interp.c (mips_options): Fix samples option short form, should
3400 be `x'.
3401
3402Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3403
3404 * interp.c (sim_info): Enable info code. Was just returning.
3405
3406Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3407
3408 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3409 MFC0.
3410
3411Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3412
3413 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3414 constants.
3415 (build_instruction): Ditto for LL.
3416
3417Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3418
3419 * configure: Regenerated to track ../common/aclocal.m4 changes.
3420
3421Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3422
3423 * configure: Regenerated to track ../common/aclocal.m4 changes.
3424 * config.in: Ditto.
3425
3426Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3427
3428 * interp.c (sim_open): Add call to sim_analyze_program, update
3429 call to sim_config.
3430
3431Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3432
3433 * interp.c (sim_kill): Delete.
3434 (sim_create_inferior): Add ABFD argument. Set PC from same.
3435 (sim_load): Move code initializing trap handlers from here.
3436 (sim_open): To here.
3437 (sim_load): Delete, use sim-hload.c.
3438
3439 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3440
3441Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3442
3443 * configure: Regenerated to track ../common/aclocal.m4 changes.
3444 * config.in: Ditto.
3445
3446Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3447
3448 * interp.c (sim_open): Add ABFD argument.
3449 (sim_load): Move call to sim_config from here.
3450 (sim_open): To here. Check return status.
3451
3452Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3453
c906108c
SS		 3454 * gencode.c (build_instruction): Two arg MADD should
3455 not assign result to $0.
72f4393d 3456
c906108c
SS		 3457Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3458
3459 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3460 * sim/mips/configure.in: Regenerate.
3461
3462Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3463
3464 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3465 signed8, unsigned8 et.al. types.
3466
3467 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3468 hosts when selecting subreg.
3469
3470Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3471
3472 * interp.c (sim_engine_run): Reset the ZERO register to zero
3473 regardless of FEATURE_WARN_ZERO.
3474 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3475
3476Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3477
3478 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3479 (SignalException): For BreakPoints ignore any mode bits and just
3480 save the PC.
3481 (SignalException): Always set the CAUSE register.
3482
3483Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3484
3485 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3486 exception has been taken.
3487
3488 * interp.c: Implement the ERET and mt/f sr instructions.
3489
3490Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3491
3492 * interp.c (SignalException): Don't bother restarting an
3493 interrupt.
3494
3495Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3496
3497 * interp.c (SignalException): Really take an interrupt.
3498 (interrupt_event): Only deliver interrupts when enabled.
3499
3500Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3501
3502 * interp.c (sim_info): Only print info when verbose.
3503 (sim_info) Use sim_io_printf for output.
72f4393d 3504
c906108c
SS		 3505Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3506
3507 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3508 mips architectures.
3509
3510Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3511
3512 * interp.c (sim_do_command): Check for common commands if a
3513 simulator specific command fails.
3514
3515Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3516
3517 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3518 and simBE when DEBUG is defined.
3519
3520Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3521
3522 * interp.c (interrupt_event): New function. Pass exception event
3523 onto exception handler.
3524
3525 * configure.in: Check for stdlib.h.
3526 * configure: Regenerate.
3527
3528 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3529 variable declaration.
3530 (build_instruction): Initialize memval1.
3531 (build_instruction): Add UNUSED attribute to byte, bigend,
3532 reverse.
3533 (build_operands): Ditto.
3534
3535 * interp.c: Fix GCC warnings.
3536 (sim_get_quit_code): Delete.
3537
3538 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3539 * Makefile.in: Ditto.
3540 * configure: Re-generate.
72f4393d 3541
c906108c
SS		 3542 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3543
3544Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3545
3546 * interp.c (mips_option_handler): New function parse argumes using
3547 sim-options.
3548 (myname): Replace with STATE_MY_NAME.
3549 (sim_open): Delete check for host endianness - performed by
3550 sim_config.
3551 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3552 (sim_open): Move much of the initialization from here.
3553 (sim_load): To here. After the image has been loaded and
3554 endianness set.
3555 (sim_open): Move ColdReset from here.
3556 (sim_create_inferior): To here.
3557 (sim_open): Make FP check less dependant on host endianness.
3558
3559 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3560 run.
3561 * interp.c (sim_set_callbacks): Delete.
3562
3563 * interp.c (membank, membank_base, membank_size): Replace with
3564 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3565 (sim_open): Remove call to callback->init. gdb/run do this.
3566
3567 * interp.c: Update
3568
3569 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3570
3571 * interp.c (big_endian_p): Delete, replaced by
3572 current_target_byte_order.
3573
3574Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3575
3576 * interp.c (host_read_long, host_read_word, host_swap_word,
3577 host_swap_long): Delete. Using common sim-endian.
3578 (sim_fetch_register, sim_store_register): Use H2T.
3579 (pipeline_ticks): Delete. Handled by sim-events.
3580 (sim_info): Update.
3581 (sim_engine_run): Update.
3582
3583Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3584
3585 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3586 reason from here.
3587 (SignalException): To here. Signal using sim_engine_halt.
3588 (sim_stop_reason): Delete, moved to common.
72f4393d 3589
c906108c
SS		 3590Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3591
3592 * interp.c (sim_open): Add callback argument.
3593 (sim_set_callbacks): Delete SIM_DESC argument.
3594 (sim_size): Ditto.
3595
3596Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3597
3598 * Makefile.in (SIM_OBJS): Add common modules.
3599
3600 * interp.c (sim_set_callbacks): Also set SD callback.
3601 (set_endianness, xfer_*, swap_*): Delete.
3602 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3603 Change to functions using sim-endian macros.
3604 (control_c, sim_stop): Delete, use common version.
3605 (simulate): Convert into.
3606 (sim_engine_run): This function.
3607 (sim_resume): Delete.
72f4393d 3608
c906108c
SS		 3609 * interp.c (simulation): New variable - the simulator object.
3610 (sim_kind): Delete global - merged into simulation.
3611 (sim_load): Cleanup. Move PC assignment from here.
3612 (sim_create_inferior): To here.
3613
3614 * sim-main.h: New file.
3615 * interp.c (sim-main.h): Include.
72f4393d 3616
c906108c
SS		 3617Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3618
3619 * configure: Regenerated to track ../common/aclocal.m4 changes.
3620
3621Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3622
3623 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3624
3625Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3626
72f4393d
L		 3627 * gencode.c (build_instruction): DIV instructions: check
3628 for division by zero and integer overflow before using
c906108c
SS		 3629 host's division operation.
3630
3631Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3632
3633 * Makefile.in (SIM_OBJS): Add sim-load.o.
3634 * interp.c: #include bfd.h.
3635 (target_byte_order): Delete.
3636 (sim_kind, myname, big_endian_p): New static locals.
3637 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3638 after argument parsing. Recognize -E arg, set endianness accordingly.
3639 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3640 load file into simulator. Set PC from bfd.
3641 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3642 (set_endianness): Use big_endian_p instead of target_byte_order.
3643
3644Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3645
3646 * interp.c (sim_size): Delete prototype - conflicts with
3647 definition in remote-sim.h. Correct definition.
3648
3649Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3650
3651 * configure: Regenerated to track ../common/aclocal.m4 changes.
3652 * config.in: Ditto.
3653
3654Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3655
3656 * interp.c (sim_open): New arg `kind'.
3657
3658 * configure: Regenerated to track ../common/aclocal.m4 changes.
3659
3660Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3661
3662 * configure: Regenerated to track ../common/aclocal.m4 changes.
3663
3664Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3665
3666 * interp.c (sim_open): Set optind to 0 before calling getopt.
3667
3668Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3669
3670 * configure: Regenerated to track ../common/aclocal.m4 changes.
3671
3672Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3673
3674 * interp.c : Replace uses of pr_addr with pr_uword64
3675 where the bit length is always 64 independent of SIM_ADDR.
3676 (pr_uword64) : added.
3677
3678Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3679
3680 * configure: Re-generate.
3681
3682Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3683
3684 * configure: Regenerate to track ../common/aclocal.m4 changes.
3685
3686Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3687
3688 * interp.c (sim_open): New SIM_DESC result. Argument is now
3689 in argv form.
3690 (other sim_*): New SIM_DESC argument.
3691
3692Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3693
3694 * interp.c: Fix printing of addresses for non-64-bit targets.
3695 (pr_addr): Add function to print address based on size.
3696
3697Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3698
3699 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3700
3701Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3702
3703 * gencode.c (build_mips16_operands): Correct computation of base
3704 address for extended PC relative instruction.
3705
3706Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3707
3708 * interp.c (mips16_entry): Add support for floating point cases.
3709 (SignalException): Pass floating point cases to mips16_entry.
3710 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3711 registers.
3712 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3713 or fmt_word.
3714 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3715 and then set the state to fmt_uninterpreted.
3716 (COP_SW): Temporarily set the state to fmt_word while calling
3717 ValueFPR.
3718
3719Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3720
3721 * gencode.c (build_instruction): The high order may be set in the
3722 comparison flags at any ISA level, not just ISA 4.
3723
3724Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3725
3726 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3727 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3728 * configure.in: sinclude ../common/aclocal.m4.
3729 * configure: Regenerated.
3730
3731Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3732
3733 * configure: Rebuild after change to aclocal.m4.
3734
3735Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3736
3737 * configure configure.in Makefile.in: Update to new configure
3738 scheme which is more compatible with WinGDB builds.
3739 * configure.in: Improve comment on how to run autoconf.
3740 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3741 * Makefile.in: Use autoconf substitution to install common
3742 makefile fragment.
3743
3744Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3745
3746 * gencode.c (build_instruction): Use BigEndianCPU instead of
3747 ByteSwapMem.
3748
3749Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3750
3751 * interp.c (sim_monitor): Make output to stdout visible in
3752 wingdb's I/O log window.
3753
3754Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3755
3756 * support.h: Undo previous change to SIGTRAP
3757 and SIGQUIT values.
3758
3759Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3760
3761 * interp.c (store_word, load_word): New static functions.
3762 (mips16_entry): New static function.
3763 (SignalException): Look for mips16 entry and exit instructions.
3764 (simulate): Use the correct index when setting fpr_state after
3765 doing a pending move.
3766
3767Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3768
3769 * interp.c: Fix byte-swapping code throughout to work on
3770 both little- and big-endian hosts.
3771
3772Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3773
3774 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3775 with gdb/config/i386/xm-windows.h.
3776
3777Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3778
3779 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3780 that messes up arithmetic shifts.
3781
3782Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3783
3784 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3785 SIGTRAP and SIGQUIT for _WIN32.
3786
3787Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3788
3789 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3790 force a 64 bit multiplication.
3791 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3792 destination register is 0, since that is the default mips16 nop
3793 instruction.
3794
3795Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3796
3797 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3798 (build_endian_shift): Don't check proc64.
3799 (build_instruction): Always set memval to uword64. Cast op2 to
3800 uword64 when shifting it left in memory instructions. Always use
3801 the same code for stores--don't special case proc64.
3802
3803 * gencode.c (build_mips16_operands): Fix base PC value for PC
3804 relative operands.
3805 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3806 jal instruction.
3807 * interp.c (simJALDELAYSLOT): Define.
3808 (JALDELAYSLOT): Define.
3809 (INDELAYSLOT, INJALDELAYSLOT): Define.
3810 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3811
3812Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3813
3814 * interp.c (sim_open): add flush_cache as a PMON routine
3815 (sim_monitor): handle flush_cache by ignoring it
3816
3817Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3818
3819 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3820 BigEndianMem.
3821 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3822 (BigEndianMem): Rename to ByteSwapMem and change sense.
3823 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3824 BigEndianMem references to !ByteSwapMem.
3825 (set_endianness): New function, with prototype.
3826 (sim_open): Call set_endianness.
3827 (sim_info): Use simBE instead of BigEndianMem.
3828 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3829 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3830 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3831 ifdefs, keeping the prototype declaration.
3832 (swap_word): Rewrite correctly.
3833 (ColdReset): Delete references to CONFIG. Delete endianness related
3834 code; moved to set_endianness.
72f4393d 3835
c906108c
SS		 3836Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3837
3838 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3839 * interp.c (CHECKHILO): Define away.
3840 (simSIGINT): New macro.
3841 (membank_size): Increase from 1MB to 2MB.
3842 (control_c): New function.
3843 (sim_resume): Rename parameter signal to signal_number. Add local
3844 variable prev. Call signal before and after simulate.
3845 (sim_stop_reason): Add simSIGINT support.
3846 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3847 functions always.
3848 (sim_warning): Delete call to SignalException. Do call printf_filtered
3849 if logfh is NULL.
3850 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3851 a call to sim_warning.
3852
3853Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3854
3855 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3856 16 bit instructions.
3857
3858Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3859
3860 Add support for mips16 (16 bit MIPS implementation):
3861 * gencode.c (inst_type): Add mips16 instruction encoding types.
3862 (GETDATASIZEINSN): Define.
3863 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3864 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3865 mtlo.
3866 (MIPS16_DECODE): New table, for mips16 instructions.
3867 (bitmap_val): New static function.
3868 (struct mips16_op): Define.
3869 (mips16_op_table): New table, for mips16 operands.
3870 (build_mips16_operands): New static function.
3871 (process_instructions): If PC is odd, decode a mips16
3872 instruction. Break out instruction handling into new
3873 build_instruction function.
3874 (build_instruction): New static function, broken out of
3875 process_instructions. Check modifiers rather than flags for SHIFT
3876 bit count and m[ft]{hi,lo} direction.
3877 (usage): Pass program name to fprintf.
3878 (main): Remove unused variable this_option_optind. Change
3879 ``*loptarg++'' to ``loptarg++''.
3880 (my_strtoul): Parenthesize && within ||.
3881 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3882 (simulate): If PC is odd, fetch a 16 bit instruction, and
3883 increment PC by 2 rather than 4.
3884 * configure.in: Add case for mips16*-*-*.
3885 * configure: Rebuild.
3886
3887Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3888
3889 * interp.c: Allow -t to enable tracing in standalone simulator.
3890 Fix garbage output in trace file and error messages.
3891
3892Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3893
3894 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3895 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3896 * configure.in: Simplify using macros in ../common/aclocal.m4.
3897 * configure: Regenerated.
3898 * tconfig.in: New file.
3899
3900Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3901
3902 * interp.c: Fix bugs in 64-bit port.
3903 Use ansi function declarations for msvc compiler.
3904 Initialize and test file pointer in trace code.
3905 Prevent duplicate definition of LAST_EMED_REGNUM.
3906
3907Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3908
3909 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3910
3911Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3912
3913 * interp.c (SignalException): Check for explicit terminating
3914 breakpoint value.
3915 * gencode.c: Pass instruction value through SignalException()
3916 calls for Trap, Breakpoint and Syscall.
3917
3918Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3919
3920 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3921 only used on those hosts that provide it.
3922 * configure.in: Add sqrt() to list of functions to be checked for.
3923 * config.in: Re-generated.
3924 * configure: Re-generated.
3925
3926Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3927
3928 * gencode.c (process_instructions): Call build_endian_shift when
3929 expanding STORE RIGHT, to fix swr.
3930 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3931 clear the high bits.
3932 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3933 Fix float to int conversions to produce signed values.
3934
3935Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3936
3937 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3938 (process_instructions): Correct handling of nor instruction.
3939 Correct shift count for 32 bit shift instructions. Correct sign
3940 extension for arithmetic shifts to not shift the number of bits in
3941 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3942 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3943 Fix madd.
3944 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3945 It's OK to have a mult follow a mult. What's not OK is to have a
3946 mult follow an mfhi.
3947 (Convert): Comment out incorrect rounding code.
3948
3949Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3950
3951 * interp.c (sim_monitor): Improved monitor printf
3952 simulation. Tidied up simulator warnings, and added "--log" option
3953 for directing warning message output.
3954 * gencode.c: Use sim_warning() rather than WARNING macro.
3955
3956Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3957
3958 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3959 getopt1.o, rather than on gencode.c. Link objects together.
3960 Don't link against -liberty.
3961 (gencode.o, getopt.o, getopt1.o): New targets.
3962 * gencode.c: Include <ctype.h> and "ansidecl.h".
3963 (AND): Undefine after including "ansidecl.h".
3964 (ULONG_MAX): Define if not defined.
3965 (OP_*): Don't define macros; now defined in opcode/mips.h.
3966 (main): Call my_strtoul rather than strtoul.
3967 (my_strtoul): New static function.
3968
3969Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3970
3971 * gencode.c (process_instructions): Generate word64 and uword64
3972 instead of `long long' and `unsigned long long' data types.
3973 * interp.c: #include sysdep.h to get signals, and define default
3974 for SIGBUS.
3975 * (Convert): Work around for Visual-C++ compiler bug with type
3976 conversion.
3977 * support.h: Make things compile under Visual-C++ by using
3978 __int64 instead of `long long'. Change many refs to long long
3979 into word64/uword64 typedefs.
3980
3981Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3982
72f4393d
L		 3983 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3984 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3985 (docdir): Removed.
3986 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3987 (AC_PROG_INSTALL): Added.
c906108c 3988 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3989 * configure: Rebuilt.
3990
c906108c
SS		 3991Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3992
3993 * configure.in: Define @SIMCONF@ depending on mips target.
3994 * configure: Rebuild.
3995 * Makefile.in (run): Add @SIMCONF@ to control simulator
3996 construction.
3997 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3998 * interp.c: Remove some debugging, provide more detailed error
3999 messages, update memory accesses to use LOADDRMASK.
72f4393d 4000
c906108c
SS		 4001Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
4002
4003 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
4004 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
4005 stamp-h.
4006 * configure: Rebuild.
4007 * config.in: New file, generated by autoheader.
4008 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
4009 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
4010 HAVE_ANINT and HAVE_AINT, as appropriate.
4011 * Makefile.in (run): Use @LIBS@ rather than -lm.
4012 (interp.o): Depend upon config.h.
4013 (Makefile): Just rebuild Makefile.
4014 (clean): Remove stamp-h.
4015 (mostlyclean): Make the same as clean, not as distclean.
4016 (config.h, stamp-h): New targets.
4017
4018Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
4019
4020 * interp.c (ColdReset): Fix boolean test. Make all simulator
4021 globals static.
4022
4023Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
4024
4025 * interp.c (xfer_direct_word, xfer_direct_long,
4026 swap_direct_word, swap_direct_long, xfer_big_word,
4027 xfer_big_long, xfer_little_word, xfer_little_long,
4028 swap_word,swap_long): Added.
4029 * interp.c (ColdReset): Provide function indirection to
4030 host<->simulated_target transfer routines.
4031 * interp.c (sim_store_register, sim_fetch_register): Updated to
4032 make use of indirected transfer routines.
4033
4034Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
4035
4036 * gencode.c (process_instructions): Ensure FP ABS instruction
4037 recognised.
4038 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
4039 system call support.
4040
4041Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
4042
4043 * interp.c (sim_do_command): Complain if callback structure not
4044 initialised.
4045
4046Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
4047
4048 * interp.c (Convert): Provide round-to-nearest and round-to-zero
4049 support for Sun hosts.
4050 * Makefile.in (gencode): Ensure the host compiler and libraries
4051 used for cross-hosted build.
4052
4053Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
4054
4055 * interp.c, gencode.c: Some more (TODO) tidying.
4056
4057Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
4058
4059 * gencode.c, interp.c: Replaced explicit long long references with
4060 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
4061 * support.h (SET64LO, SET64HI): Macros added.
4062
4063Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
4064
4065 * configure: Regenerate with autoconf 2.7.
4066
4067Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
4068
4069 * interp.c (LoadMemory): Enclose text following #endif in /* */.
4070 * support.h: Remove superfluous "1" from #if.
4071 * support.h (CHECKSIM): Remove stray 'a' at end of line.
4072
4073Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
4074
4075 * interp.c (StoreFPR): Control UndefinedResult() call on
4076 WARN_RESULT manifest.
4077
4078Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
4079
4080 * gencode.c: Tidied instruction decoding, and added FP instruction
4081 support.
4082
4083 * interp.c: Added dineroIII, and BSD profiling support. Also
4084 run-time FP handling.
4085
4086Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
4087
4088 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
4089 gencode.c, interp.c, support.h: created.
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