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sim: drop --enable-sim-cflags option
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
22be3fbe
MF		 12016-01-10 Mike Frysinger <vapier@gentoo.org>
2
3 * configure: Regenerate.
4
936df756
MF		 52016-01-09 Mike Frysinger <vapier@gentoo.org>
6
7 * config.in, configure: Regenerate.
8
2e3d4f4d
MF		 92016-01-06 Mike Frysinger <vapier@gentoo.org>
10
11 * interp.c (sim_open): Mark argv const.
12 (sim_create_inferior): Mark argv and env const.
13
9bbf6f91
MF		 142016-01-04 Mike Frysinger <vapier@gentoo.org>
15
16 * configure: Regenerate.
17
77cf2ef5
MF		 182016-01-03 Mike Frysinger <vapier@gentoo.org>
19
20 * interp.c (sim_open): Update sim_parse_args comment.
21
0cb8d851
MF		 222016-01-03 Mike Frysinger <vapier@gentoo.org>
23
24 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
25 * configure: Regenerate.
26
1ac72f06
MF		 272016-01-02 Mike Frysinger <vapier@gentoo.org>
28
29 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
30 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
31 * configure: Regenerate.
32 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
33
d47f5b30
MF		 342016-01-02 Mike Frysinger <vapier@gentoo.org>
35
36 * dv-tx3904cpu.c (CPU, SD): Delete.
37
e1211e55
MF		 382015-12-30 Mike Frysinger <vapier@gentoo.org>
39
40 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
41 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
42 (sim_store_register): Rename to ...
43 (mips_reg_store): ... this. Delete local cpu var.
44 Update sim_io_eprintf calls.
45 (sim_fetch_register): Rename to ...
46 (mips_reg_fetch): ... this. Delete local cpu var.
47 Update sim_io_eprintf calls.
48
5e744ef8
MF		 492015-12-27 Mike Frysinger <vapier@gentoo.org>
50
51 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
52
1b393626
MF		 532015-12-26 Mike Frysinger <vapier@gentoo.org>
54
55 * config.in, configure: Regenerate.
56
26f8bf63
MF		 572015-12-26 Mike Frysinger <vapier@gentoo.org>
58
59 * interp.c (sim_write, sim_read): Delete.
60 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
61 (load_word): Likewise.
62 * micromips.igen (cache): Likewise.
63 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
64 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
65 do_store_left, do_store_right, do_load_double, do_store_double):
66 Likewise.
67 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
68 (do_prefx): Likewise.
69 * sim-main.c (address_translation, prefetch): Delete.
70 (ifetch32, ifetch16): Delete call to AddressTranslation and set
71 paddr=vaddr.
72 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
73 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
74 (LoadMemory, StoreMemory): Delete CCA arg.
75
ef04e371
MF		 762015-12-24 Mike Frysinger <vapier@gentoo.org>
77
78 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
79 * configure: Regenerated.
80
cb379ede
MF		 812015-12-24 Mike Frysinger <vapier@gentoo.org>
82
83 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
84 * tconfig.h: Delete.
85
26936211
MF		 862015-12-24 Mike Frysinger <vapier@gentoo.org>
87
88 * tconfig.h (SIM_HANDLES_LMA): Delete.
89
84e8e361
MF		 902015-12-24 Mike Frysinger <vapier@gentoo.org>
91
92 * sim-main.h (WITH_WATCHPOINTS): Delete.
93
3cabaf66
MF		 942015-12-24 Mike Frysinger <vapier@gentoo.org>
95
96 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
97
8abe6c66
MF		 982015-12-24 Mike Frysinger <vapier@gentoo.org>
99
100 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
101
1d19cae7
DV		 1022015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
103
104 * micromips.igen (process_isa_mode): Fix left shift of negative
105 value.
106
cdf850e9
MF		 1072015-11-17 Mike Frysinger <vapier@gentoo.org>
108
109 * sim-main.h (WITH_MODULO_MEMORY): Delete.
110
797eee42
MF		 1112015-11-15 Mike Frysinger <vapier@gentoo.org>
112
113 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
114
6e4f085c
MF		 1152015-11-14 Mike Frysinger <vapier@gentoo.org>
116
117 * interp.c (sim_close): Rename to ...
118 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
119 sim_io_shutdown.
120 * sim-main.h (mips_sim_close): Declare.
121 (SIM_CLOSE_HOOK): Define.
122
8e394ffc
AB		 1232015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
124 Ali Lown <ali.lown@imgtec.com>
125
126 * Makefile.in (tmp-micromips): New rule.
127 (tmp-mach-multi): Add support for micromips.
128 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
129 that works for both mips64 and micromips64.
130 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
131 micromips32.
132 Add build support for micromips.
133 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
134 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
135 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
136 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
137 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
138 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
139 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
140 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
141 Refactored instruction code to use these functions.
142 * dsp2.igen: Refactored instruction code to use the new functions.
143 * interp.c (decode_coproc): Refactored to work with any instruction
144 encoding.
145 (isa_mode): New variable
146 (RSVD_INSTRUCTION): Changed to 0x00000039.
147 * m16.igen (BREAK16): Refactored instruction to use do_break16.
148 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
149 * micromips.dc: New file.
150 * micromips.igen: New file.
151 * micromips16.dc: New file.
152 * micromipsdsp.igen: New file.
153 * micromipsrun.c: New file.
154 * mips.igen (do_swc1): Changed to work with any instruction encoding.
155 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
156 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
157 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
158 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
159 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
160 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
161 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
162 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
163 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
164 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
165 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
166 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
167 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
168 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
169 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
170 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
171 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
172 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
173 instructions.
174 Refactored instruction code to use these functions.
175 (RSVD): Changed to use new reserved instruction.
176 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
177 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
178 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
179 do_store_double): Added micromips32 and micromips64 models.
180 Added include for micromips.igen and micromipsdsp.igen
181 Add micromips32 and micromips64 models.
182 (DecodeCoproc): Updated to use new macro definition.
183 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
184 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
185 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
186 Refactored instruction code to use these functions.
187 * sim-main.h (CP0_operation): New enum.
188 (DecodeCoproc): Updated macro.
189 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
190 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
191 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
192 ISA_MODE_MICROMIPS): New defines.
193 (sim_state): Add isa_mode field.
194
8d0978fb
MF		 1952015-06-23 Mike Frysinger <vapier@gentoo.org>
196
197 * configure: Regenerate.
198
306f4178
MF		 1992015-06-12 Mike Frysinger <vapier@gentoo.org>
200
201 * configure.ac: Change configure.in to configure.ac.
202 * configure: Regenerate.
203
a3487082
MF		 2042015-06-12 Mike Frysinger <vapier@gentoo.org>
205
206 * configure: Regenerate.
207
29bc024d
MF		 2082015-06-12 Mike Frysinger <vapier@gentoo.org>
209
210 * interp.c [TRACE]: Delete.
211 (TRACE): Change to WITH_TRACE_ANY_P.
212 [!WITH_TRACE_ANY_P] (open_trace): Define.
213 (mips_option_handler, open_trace, sim_close, dotrace):
214 Change defined(TRACE) to WITH_TRACE_ANY_P.
215 (sim_open): Delete TRACE ifdef check.
216 * sim-main.c (load_memory): Delete TRACE ifdef check.
217 (store_memory): Likewise.
218 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
219 [!WITH_TRACE_ANY_P] (dotrace): Define.
220
3ebe2863
MF		 2212015-04-18 Mike Frysinger <vapier@gentoo.org>
222
223 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
224 comments.
225
20bca71d
MF		 2262015-04-18 Mike Frysinger <vapier@gentoo.org>
227
228 * sim-main.h (SIM_CPU): Delete.
229
7e83aa92
MF		 2302015-04-18 Mike Frysinger <vapier@gentoo.org>
231
232 * sim-main.h (sim_cia): Delete.
233
034685f9
MF		 2342015-04-17 Mike Frysinger <vapier@gentoo.org>
235
236 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
237 PU_PC_GET.
238 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
239 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
240 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
241 CIA_SET to CPU_PC_SET.
242 * sim-main.h (CIA_GET, CIA_SET): Delete.
243
78e9aa70
MF		 2442015-04-15 Mike Frysinger <vapier@gentoo.org>
245
246 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
247 * sim-main.h (STATE_CPU): Delete.
248
bf12d44e
MF		 2492015-04-13 Mike Frysinger <vapier@gentoo.org>
250
251 * configure: Regenerate.
252
7bebb329
MF		 2532015-04-13 Mike Frysinger <vapier@gentoo.org>
254
255 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
256 * interp.c (mips_pc_get, mips_pc_set): New functions.
257 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
258 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
259 (sim_pc_get): Delete.
260 * sim-main.h (SIM_CPU): Define.
261 (struct sim_state): Change cpu to an array of pointers.
262 (STATE_CPU): Drop &.
263
8ac57fbd
MF		 2642015-04-13 Mike Frysinger <vapier@gentoo.org>
265
266 * interp.c (mips_option_handler, open_trace, sim_close,
267 sim_write, sim_read, sim_store_register, sim_fetch_register,
268 sim_create_inferior, pr_addr, pr_uword64): Convert old style
269 prototypes.
270 (sim_open): Convert old style prototype. Change casts with
271 sim_write to unsigned char *.
272 (fetch_str): Change null to unsigned char, and change cast to
273 unsigned char *.
274 (sim_monitor): Change c & ch to unsigned char. Change cast to
275 unsigned char *.
276
e787f858
MF		 2772015-04-12 Mike Frysinger <vapier@gentoo.org>
278
279 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
280
122bbfb5
MF		 2812015-04-06 Mike Frysinger <vapier@gentoo.org>
282
283 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
284
0fe84f3f
MF		 2852015-04-01 Mike Frysinger <vapier@gentoo.org>
286
287 * tconfig.h (SIM_HAVE_PROFILE): Delete.
288
aadc9410
MF		 2892015-03-31 Mike Frysinger <vapier@gentoo.org>
290
291 * config.in, configure: Regenerate.
292
05f53ed6
MF		 2932015-03-24 Mike Frysinger <vapier@gentoo.org>
294
295 * interp.c (sim_pc_get): New function.
296
c0931f26
MF		 2972015-03-24 Mike Frysinger <vapier@gentoo.org>
298
299 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
300 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
301
30452bbe
MF		 3022015-03-24 Mike Frysinger <vapier@gentoo.org>
303
304 * configure: Regenerate.
305
64dd13df
MF		 3062015-03-23 Mike Frysinger <vapier@gentoo.org>
307
308 * configure: Regenerate.
309
49cd1634
MF		 3102015-03-23 Mike Frysinger <vapier@gentoo.org>
311
312 * configure: Regenerate.
313 * configure.ac (mips_extra_objs): Delete.
314 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
315 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
316
3649cb06
MF		 3172015-03-23 Mike Frysinger <vapier@gentoo.org>
318
319 * configure: Regenerate.
320 * configure.ac: Delete sim_hw checks for dv-sockser.
321
ae7d0cac
MF		 3222015-03-16 Mike Frysinger <vapier@gentoo.org>
323
324 * config.in, configure: Regenerate.
325 * tconfig.in: Rename file ...
326 * tconfig.h: ... here.
327
8406bb59
MF		 3282015-03-15 Mike Frysinger <vapier@gentoo.org>
329
330 * tconfig.in: Delete includes.
331 [HAVE_DV_SOCKSER]: Delete.
332
465fb143
MF		 3332015-03-14 Mike Frysinger <vapier@gentoo.org>
334
335 * Makefile.in (SIM_RUN_OBJS): Delete.
336
5cddc23a
MF		 3372015-03-14 Mike Frysinger <vapier@gentoo.org>
338
339 * configure.ac (AC_CHECK_HEADERS): Delete.
340 * aclocal.m4, configure: Regenerate.
341
2974be62
AM		 3422014-08-19 Alan Modra <amodra@gmail.com>
343
344 * configure: Regenerate.
345
faa743bb
RM		 3462014-08-15 Roland McGrath <mcgrathr@google.com>
347
348 * configure: Regenerate.
349 * config.in: Regenerate.
350
1a8a700e
MF		 3512014-03-04 Mike Frysinger <vapier@gentoo.org>
352
353 * configure: Regenerate.
354
bf3d9781
AM		 3552013-09-23 Alan Modra <amodra@gmail.com>
356
357 * configure: Regenerate.
358
31e6ad7d
MF		 3592013-06-03 Mike Frysinger <vapier@gentoo.org>
360
361 * aclocal.m4, configure: Regenerate.
362
d3685d60
TT		 3632013-05-10 Freddie Chopin <freddie_chopin@op.pl>
364
365 * configure: Rebuild.
366
1517bd27
MF		 3672013-03-26 Mike Frysinger <vapier@gentoo.org>
368
369 * configure: Regenerate.
370
3be31516
JS		 3712013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
372
373 * configure.ac: Address use of dv-sockser.o.
374 * tconfig.in: Conditionalize use of dv_sockser_install.
375 * configure: Regenerated.
376 * config.in: Regenerated.
377
37cb8f8e
SE		 3782012-10-04 Chao-ying Fu <fu@mips.com>
379 Steve Ellcey <sellcey@mips.com>
380
381 * mips/mips3264r2.igen (rdhwr): New.
382
87c8644f
JS		 3832012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
384
385 * configure.ac: Always link against dv-sockser.o.
386 * configure: Regenerate.
387
5f3ef9d0
JB		 3882012-06-15 Joel Brobecker <brobecker@adacore.com>
389
390 * config.in, configure: Regenerate.
391
a6ff997c
NC		 3922012-05-18 Nick Clifton <nickc@redhat.com>
393
394 PR 14072
395 * interp.c: Include config.h before system header files.
396
2232061b
MF		 3972012-03-24 Mike Frysinger <vapier@gentoo.org>
398
399 * aclocal.m4, config.in, configure: Regenerate.
400
db2e4d67
MF		 4012011-12-03 Mike Frysinger <vapier@gentoo.org>
402
403 * aclocal.m4: New file.
404 * configure: Regenerate.
405
4399a56b
MF		 4062011-10-19 Mike Frysinger <vapier@gentoo.org>
407
408 * configure: Regenerate after common/acinclude.m4 update.
409
9c082ca8
MF		 4102011-10-17 Mike Frysinger <vapier@gentoo.org>
411
412 * configure.ac: Change include to common/acinclude.m4.
413
6ffe910a
MF		 4142011-10-17 Mike Frysinger <vapier@gentoo.org>
415
416 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
417 call. Replace common.m4 include with SIM_AC_COMMON.
418 * configure: Regenerate.
419
31b28250
HPN		 4202011-07-08 Hans-Peter Nilsson <hp@axis.com>
421
3faa01e3
HPN		 422 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
423 $(SIM_EXTRA_DEPS).
424 (tmp-mach-multi): Exit early when igen fails.
31b28250 425
2419798b
MF		 4262011-07-05 Mike Frysinger <vapier@gentoo.org>
427
428 * interp.c (sim_do_command): Delete.
429
d79fe0d6
MF		 4302011-02-14 Mike Frysinger <vapier@gentoo.org>
431
432 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
433 (tx3904sio_fifo_reset): Likewise.
434 * interp.c (sim_monitor): Likewise.
435
5558e7e6
MF		 4362010-04-14 Mike Frysinger <vapier@gentoo.org>
437
438 * interp.c (sim_write): Add const to buffer arg.
439
35aafff4
JB		 4402010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
441
442 * interp.c: Don't include sysdep.h
443
3725885a
RW		 4442010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
445
446 * configure: Regenerate.
447
d6416cdc
RW		 4482009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
449
81ecdfbb
RW		 450 * config.in: Regenerate.
451 * configure: Likewise.
452
d6416cdc
RW		 453 * configure: Regenerate.
454
b5bd9624
HPN		 4552008-07-11 Hans-Peter Nilsson <hp@axis.com>
456
457 * configure: Regenerate to track ../common/common.m4 changes.
458 * config.in: Ditto.
459
6efef468 4602008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 461 Daniel Jacobowitz <dan@codesourcery.com>
462 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 463
464 * configure: Regenerate.
465
60dc88db
RS		 4662007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
467
468 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
469 that unconditionally allows fmt_ps.
470 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
471 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
472 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
473 filter from 64,f to 32,f.
474 (PREFX): Change filter from 64 to 32.
475 (LDXC1, LUXC1): Provide separate mips32r2 implementations
476 that use do_load_double instead of do_load. Make both LUXC1
477 versions unpredictable if SizeFGR () != 64.
478 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
479 instead of do_store. Remove unused variable. Make both SUXC1
480 versions unpredictable if SizeFGR () != 64.
481
599ca73e
RS		 4822007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
483
484 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
485 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
486 shifts for that case.
487
2525df03
NC		 4882007-09-04 Nick Clifton <nickc@redhat.com>
489
490 * interp.c (options enum): Add OPTION_INFO_MEMORY.
491 (display_mem_info): New static variable.
492 (mips_option_handler): Handle OPTION_INFO_MEMORY.
493 (mips_options): Add info-memory and memory-info.
494 (sim_open): After processing the command line and board
495 specification, check display_mem_info. If it is set then
496 call the real handler for the --memory-info command line
497 switch.
498
35ee6e1e
JB		 4992007-08-24 Joel Brobecker <brobecker@adacore.com>
500
501 * configure.ac: Change license of multi-run.c to GPL version 3.
502 * configure: Regenerate.
503
d5fb0879
RS		 5042007-06-28 Richard Sandiford <richard@codesourcery.com>
505
506 * configure.ac, configure: Revert last patch.
507
2a2ce21b
RS		 5082007-06-26 Richard Sandiford <richard@codesourcery.com>
509
510 * configure.ac (sim_mipsisa3264_configs): New variable.
511 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
512 every configuration support all four targets, using the triplet to
513 determine the default.
514 * configure: Regenerate.
515
efdcccc9
RS		 5162007-06-25 Richard Sandiford <richard@codesourcery.com>
517
0a7692b2 518 * Makefile.in (m16run.o): New rule.
efdcccc9 519
f532a356
TS		 5202007-05-15 Thiemo Seufer <ths@mips.com>
521
522 * mips3264r2.igen (DSHD): Fix compile warning.
523
bfe9c90b
TS		 5242007-05-14 Thiemo Seufer <ths@mips.com>
525
526 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
527 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
528 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
529 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
530 for mips32r2.
531
53f4826b
TS		 5322007-03-01 Thiemo Seufer <ths@mips.com>
533
534 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
535 and mips64.
536
8bf3ddc8
TS		 5372007-02-20 Thiemo Seufer <ths@mips.com>
538
539 * dsp.igen: Update copyright notice.
540 * dsp2.igen: Fix copyright notice.
541
8b082fb1 5422007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 543 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 544
545 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
546 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
547 Add dsp2 to sim_igen_machine.
548 * configure: Regenerate.
549 * dsp.igen (do_ph_op): Add MUL support when op = 2.
550 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
551 (mulq_rs.ph): Use do_ph_mulq.
552 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
553 * mips.igen: Add dsp2 model and include dsp2.igen.
554 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
555 for *mips32r2, *mips64r2, *dsp.
556 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
557 for *mips32r2, *mips64r2, *dsp2.
558 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
559
b1004875 5602007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 561 Nigel Stephens <nigel@mips.com>
b1004875
TS		 562
563 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
564 jumps with hazard barrier.
565
f8df4c77 5662007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 567 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 568
569 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
570 after each call to sim_io_write.
571
b1004875 5722007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 573 Nigel Stephens <nigel@mips.com>
b1004875
TS		 574
575 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
576 supported by this simulator.
07802d98
TS		 577 (decode_coproc): Recognise additional CP0 Config registers
578 correctly.
579
14fb6c5a 5802007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 581 Nigel Stephens <nigel@mips.com>
582 David Ung <davidu@mips.com>
14fb6c5a
TS		 583
584 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
585 uninterpreted formats. If fmt is one of the uninterpreted types
586 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
587 fmt_word, and fmt_uninterpreted_64 like fmt_long.
588 (store_fpr): When writing an invalid odd register, set the
589 matching even register to fmt_unknown, not the following register.
590 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
591 the the memory window at offset 0 set by --memory-size command
592 line option.
593 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
594 point register.
595 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
596 register.
597 (sim_monitor): When returning the memory size to the MIPS
598 application, use the value in STATE_MEM_SIZE, not an arbitrary
599 hardcoded value.
600 (cop_lw): Don' mess around with FPR_STATE, just pass
601 fmt_uninterpreted_32 to StoreFPR.
602 (cop_sw): Similarly.
603 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
604 (cop_sd): Similarly.
605 * mips.igen (not_word_value): Single version for mips32, mips64
606 and mips16.
607
c8847145 6082007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 609 Nigel Stephens <nigel@mips.com>
c8847145
TS		 610
611 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
612 MBytes.
613
4b5d35ee
TS		 6142007-02-17 Thiemo Seufer <ths@mips.com>
615
616 * configure.ac (mips*-sde-elf*): Move in front of generic machine
617 configuration.
618 * configure: Regenerate.
619
3669427c
TS		 6202007-02-17 Thiemo Seufer <ths@mips.com>
621
622 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
623 Add mdmx to sim_igen_machine.
624 (mipsisa64*-*-*): Likewise. Remove dsp.
625 (mipsisa32*-*-*): Remove dsp.
626 * configure: Regenerate.
627
109ad085
TS		 6282007-02-13 Thiemo Seufer <ths@mips.com>
629
630 * configure.ac: Add mips*-sde-elf* target.
631 * configure: Regenerate.
632
921d7ad3
HPN		 6332006-12-21 Hans-Peter Nilsson <hp@axis.com>
634
635 * acconfig.h: Remove.
636 * config.in, configure: Regenerate.
637
02f97da7
TS		 6382006-11-07 Thiemo Seufer <ths@mips.com>
639
640 * dsp.igen (do_w_op): Fix compiler warning.
641
2d2733fc 6422006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 643 David Ung <davidu@mips.com>
2d2733fc
TS		 644
645 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
646 sim_igen_machine.
647 * configure: Regenerate.
648 * mips.igen (model): Add smartmips.
649 (MADDU): Increment ACX if carry.
650 (do_mult): Clear ACX.
651 (ROR,RORV): Add smartmips.
72f4393d 652 (include): Include smartmips.igen.
2d2733fc
TS		 653 * sim-main.h (ACX): Set to REGISTERS[89].
654 * smartmips.igen: New file.
655
d85c3a10 6562006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 657 David Ung <davidu@mips.com>
d85c3a10
TS		 658
659 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
660 mips3264r2.igen. Add missing dependency rules.
661 * m16e.igen: Support for mips16e save/restore instructions.
662
e85e3205
RE		 6632006-06-13 Richard Earnshaw <rearnsha@arm.com>
664
665 * configure: Regenerated.
666
2f0122dc
DJ		 6672006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
668
669 * configure: Regenerated.
670
20e95c23
DJ		 6712006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
672
673 * configure: Regenerated.
674
69088b17
CF		 6752006-05-15 Chao-ying Fu <fu@mips.com>
676
677 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
678
0275de4e
NC		 6792006-04-18 Nick Clifton <nickc@redhat.com>
680
681 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
682 statement.
683
b3a3ffef
HPN		 6842006-03-29 Hans-Peter Nilsson <hp@axis.com>
685
686 * configure: Regenerate.
687
40a5538e
CF		 6882005-12-14 Chao-ying Fu <fu@mips.com>
689
690 * Makefile.in (SIM_OBJS): Add dsp.o.
691 (dsp.o): New dependency.
692 (IGEN_INCLUDE): Add dsp.igen.
693 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
694 mipsisa64*-*-*): Add dsp to sim_igen_machine.
695 * configure: Regenerate.
696 * mips.igen: Add dsp model and include dsp.igen.
697 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
698 because these instructions are extended in DSP ASE.
699 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
700 adding 6 DSP accumulator registers and 1 DSP control register.
701 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
702 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
703 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
704 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
705 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
706 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
707 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
708 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
709 DSPCR_CCOND_SMASK): New define.
710 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
711 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
712
21d14896
ILT		 7132005-07-08 Ian Lance Taylor <ian@airs.com>
714
715 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
716
b16d63da 7172005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 718 Nigel Stephens <nigel@mips.com>
719
720 * mips.igen: New mips16e model and include m16e.igen.
721 (check_u64): Add mips16e tag.
722 * m16e.igen: New file for MIPS16e instructions.
723 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
724 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
725 models.
726 * configure: Regenerate.
b16d63da 727
e70cb6cd 7282005-05-26 David Ung <davidu@mips.com>
72f4393d 729
e70cb6cd
CD		 730 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
731 tags to all instructions which are applicable to the new ISAs.
732 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
733 vr.igen.
734 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 735 instructions.
e70cb6cd
CD		 736 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
737 to mips.igen.
738 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
739 * configure: Regenerate.
72f4393d 740
2b193c4a
MK		 7412005-03-23 Mark Kettenis <kettenis@gnu.org>
742
743 * configure: Regenerate.
744
35695fd6
AC		 7452005-01-14 Andrew Cagney <cagney@gnu.org>
746
747 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
748 explicit call to AC_CONFIG_HEADER.
749 * configure: Regenerate.
750
f0569246
AC		 7512005-01-12 Andrew Cagney <cagney@gnu.org>
752
753 * configure.ac: Update to use ../common/common.m4.
754 * configure: Re-generate.
755
38f48d72
AC		 7562005-01-11 Andrew Cagney <cagney@localhost.localdomain>
757
758 * configure: Regenerated to track ../common/aclocal.m4 changes.
759
b7026657
AC		 7602005-01-07 Andrew Cagney <cagney@gnu.org>
761
762 * configure.ac: Rename configure.in, require autoconf 2.59.
763 * configure: Re-generate.
764
379832de
HPN		 7652004-12-08 Hans-Peter Nilsson <hp@axis.com>
766
767 * configure: Regenerate for ../common/aclocal.m4 update.
768
cd62154c 7692004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 770
cd62154c
AC		 771 Committed by Andrew Cagney.
772 * m16.igen (CMP, CMPI): Fix assembler.
773
e5da76ec
CD		 7742004-08-18 Chris Demetriou <cgd@broadcom.com>
775
776 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
777 * configure: Regenerate.
778
139181c8
CD		 7792004-06-25 Chris Demetriou <cgd@broadcom.com>
780
781 * configure.in (sim_m16_machine): Include mipsIII.
782 * configure: Regenerate.
783
1a27f959
CD		 7842004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
785
72f4393d 786 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 787 from COP0_BADVADDR.
788 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
789
5dbb7b5a
CD		 7902004-04-10 Chris Demetriou <cgd@broadcom.com>
791
792 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
793
14234056
CD		 7942004-04-09 Chris Demetriou <cgd@broadcom.com>
795
796 * mips.igen (check_fmt): Remove.
797 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
798 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
799 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
800 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
801 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
802 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
803 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
804 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
805 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
806 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
807
c6f9085c
CD		 8082004-04-09 Chris Demetriou <cgd@broadcom.com>
809
810 * sb1.igen (check_sbx): New function.
811 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
812
11d66e66 8132004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 814 Richard Sandiford <rsandifo@redhat.com>
815
816 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
817 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
818 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
819 separate implementations for mipsIV and mipsV. Use new macros to
820 determine whether the restrictions apply.
821
b3208fb8
CD		 8222004-01-19 Chris Demetriou <cgd@broadcom.com>
823
824 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
825 (check_mult_hilo): Improve comments.
826 (check_div_hilo): Likewise. Also, fork off a new version
827 to handle mips32/mips64 (since there are no hazards to check
828 in MIPS32/MIPS64).
829
9a1d84fb
CD		 8302003-06-17 Richard Sandiford <rsandifo@redhat.com>
831
832 * mips.igen (do_dmultx): Fix check for negative operands.
833
ae451ac6
ILT		 8342003-05-16 Ian Lance Taylor <ian@airs.com>
835
836 * Makefile.in (SHELL): Make sure this is defined.
837 (various): Use $(SHELL) whenever we invoke move-if-change.
838
dd69d292
CD		 8392003-05-03 Chris Demetriou <cgd@broadcom.com>
840
841 * cp1.c: Tweak attribution slightly.
842 * cp1.h: Likewise.
843 * mdmx.c: Likewise.
844 * mdmx.igen: Likewise.
845 * mips3d.igen: Likewise.
846 * sb1.igen: Likewise.
847
bcd0068e
CD		 8482003-04-15 Richard Sandiford <rsandifo@redhat.com>
849
850 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
851 unsigned operands.
852
6b4a8935
AC		 8532003-02-27 Andrew Cagney <cagney@redhat.com>
854
601da316
AC		 855 * interp.c (sim_open): Rename _bfd to bfd.
856 (sim_create_inferior): Ditto.
6b4a8935 857
d29e330f
CD		 8582003-01-14 Chris Demetriou <cgd@broadcom.com>
859
860 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
861
a2353a08
CD		 8622003-01-14 Chris Demetriou <cgd@broadcom.com>
863
864 * mips.igen (EI, DI): Remove.
865
80551777
CD		 8662003-01-05 Richard Sandiford <rsandifo@redhat.com>
867
868 * Makefile.in (tmp-run-multi): Fix mips16 filter.
869
4c54fc26
CD		 8702003-01-04 Richard Sandiford <rsandifo@redhat.com>
871 Andrew Cagney <ac131313@redhat.com>
872 Gavin Romig-Koch <gavin@redhat.com>
873 Graydon Hoare <graydon@redhat.com>
874 Aldy Hernandez <aldyh@redhat.com>
875 Dave Brolley <brolley@redhat.com>
876 Chris Demetriou <cgd@broadcom.com>
877
878 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
879 (sim_mach_default): New variable.
880 (mips64vr-*-*, mips64vrel-*-*): New configurations.
881 Add a new simulator generator, MULTI.
882 * configure: Regenerate.
883 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
884 (multi-run.o): New dependency.
885 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
886 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
887 (tmp-multi): Combine them.
888 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
889 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
890 (distclean-extra): New rule.
891 * sim-main.h: Include bfd.h.
892 (MIPS_MACH): New macro.
893 * mips.igen (vr4120, vr5400, vr5500): New models.
894 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
895 * vr.igen: Replace with new version.
896
e6c674b8
CD		 8972003-01-04 Chris Demetriou <cgd@broadcom.com>
898
899 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
900 * configure: Regenerate.
901
28f50ac8
CD		 9022002-12-31 Chris Demetriou <cgd@broadcom.com>
903
904 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
905 * mips.igen: Remove all invocations of check_branch_bug and
906 mark_branch_bug.
907
5071ffe6
CD		 9082002-12-16 Chris Demetriou <cgd@broadcom.com>
909
72f4393d 910 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 911
06e7837e
CD		 9122002-07-30 Chris Demetriou <cgd@broadcom.com>
913
914 * mips.igen (do_load_double, do_store_double): New functions.
915 (LDC1, SDC1): Rename to...
916 (LDC1b, SDC1b): respectively.
917 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
918
2265c243
MS		 9192002-07-29 Michael Snyder <msnyder@redhat.com>
920
921 * cp1.c (fp_recip2): Modify initialization expression so that
922 GCC will recognize it as constant.
923
a2f8b4f3
CD		 9242002-06-18 Chris Demetriou <cgd@broadcom.com>
925
926 * mdmx.c (SD_): Delete.
927 (Unpredictable): Re-define, for now, to directly invoke
928 unpredictable_action().
929 (mdmx_acc_op): Fix error in .ob immediate handling.
930
b4b6c939
AC		 9312002-06-18 Andrew Cagney <cagney@redhat.com>
932
933 * interp.c (sim_firmware_command): Initialize `address'.
934
c8cca39f
AC		 9352002-06-16 Andrew Cagney <ac131313@redhat.com>
936
937 * configure: Regenerated to track ../common/aclocal.m4 changes.
938
e7e81181 9392002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 940 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 941
942 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
943 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
944 * mips.igen: Include mips3d.igen.
945 (mips3d): New model name for MIPS-3D ASE instructions.
946 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 947 instructions.
e7e81181
CD		 948 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
949 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
950 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
951 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
952 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
953 (RSquareRoot1, RSquareRoot2): New macros.
954 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
955 (fp_rsqrt2): New functions.
956 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
957 * configure: Regenerate.
958
3a2b820e 9592002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 960 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 961
962 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
963 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
964 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
965 (convert): Note that this function is not used for paired-single
966 format conversions.
967 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
968 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
969 (check_fmt_p): Enable paired-single support.
970 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
971 (PUU.PS): New instructions.
972 (CVT.S.fmt): Don't use this instruction for paired-single format
973 destinations.
974 * sim-main.h (FP_formats): New value 'fmt_ps.'
975 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
976 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
977
d18ea9c2
CD		 9782002-06-12 Chris Demetriou <cgd@broadcom.com>
979
980 * mips.igen: Fix formatting of function calls in
981 many FP operations.
982
95fd5cee
CD		 9832002-06-12 Chris Demetriou <cgd@broadcom.com>
984
985 * mips.igen (MOVN, MOVZ): Trace result.
986 (TNEI): Print "tnei" as the opcode name in traces.
987 (CEIL.W): Add disassembly string for traces.
988 (RSQRT.fmt): Make location of disassembly string consistent
989 with other instructions.
990
4f0d55ae
CD		 9912002-06-12 Chris Demetriou <cgd@broadcom.com>
992
993 * mips.igen (X): Delete unused function.
994
3c25f8c7
AC		 9952002-06-08 Andrew Cagney <cagney@redhat.com>
996
997 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
998
f3c08b7e 9992002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1000 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1001
1002 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1003 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1004 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1005 (fp_nmsub): New prototypes.
1006 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1007 (NegMultiplySub): New defines.
1008 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1009 (MADD.D, MADD.S): Replace with...
1010 (MADD.fmt): New instruction.
1011 (MSUB.D, MSUB.S): Replace with...
1012 (MSUB.fmt): New instruction.
1013 (NMADD.D, NMADD.S): Replace with...
1014 (NMADD.fmt): New instruction.
1015 (NMSUB.D, MSUB.S): Replace with...
1016 (NMSUB.fmt): New instruction.
1017
52714ff9 10182002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1019 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1020
1021 * cp1.c: Fix more comment spelling and formatting.
1022 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1023 (denorm_mode): New function.
1024 (fpu_unary, fpu_binary): Round results after operation, collect
1025 status from rounding operations, and update the FCSR.
1026 (convert): Collect status from integer conversions and rounding
1027 operations, and update the FCSR. Adjust NaN values that result
1028 from conversions. Convert to use sim_io_eprintf rather than
1029 fprintf, and remove some debugging code.
1030 * cp1.h (fenr_FS): New define.
1031
577d8c4b
CD		 10322002-06-07 Chris Demetriou <cgd@broadcom.com>
1033
1034 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1035 rounding mode to sim FP rounding mode flag conversion code into...
1036 (rounding_mode): New function.
1037
196496ed
CD		 10382002-06-07 Chris Demetriou <cgd@broadcom.com>
1039
1040 * cp1.c: Clean up formatting of a few comments.
1041 (value_fpr): Reformat switch statement.
1042
cfe9ea23 10432002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1044 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1045
1046 * cp1.h: New file.
1047 * sim-main.h: Include cp1.h.
1048 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1049 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1050 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1051 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1052 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1053 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1054 * cp1.c: Don't include sim-fpu.h; already included by
1055 sim-main.h. Clean up formatting of some comments.
1056 (NaN, Equal, Less): Remove.
1057 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1058 (fp_cmp): New functions.
1059 * mips.igen (do_c_cond_fmt): Remove.
1060 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1061 Compare. Add result tracing.
1062 (CxC1): Remove, replace with...
1063 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1064 (DMxC1): Remove, replace with...
1065 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1066 (MxC1): Remove, replace with...
1067 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1068
ee7254b0
CD		 10692002-06-04 Chris Demetriou <cgd@broadcom.com>
1070
1071 * sim-main.h (FGRIDX): Remove, replace all uses with...
1072 (FGR_BASE): New macro.
1073 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1074 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1075 (NR_FGR, FGR): Likewise.
1076 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1077 * mips.igen: Likewise.
1078
d3eb724f
CD		 10792002-06-04 Chris Demetriou <cgd@broadcom.com>
1080
1081 * cp1.c: Add an FSF Copyright notice to this file.
1082
ba46ddd0 10832002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1084 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1085
1086 * cp1.c (Infinity): Remove.
1087 * sim-main.h (Infinity): Likewise.
1088
1089 * cp1.c (fp_unary, fp_binary): New functions.
1090 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1091 (fp_sqrt): New functions, implemented in terms of the above.
1092 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1093 (Recip, SquareRoot): Remove (replaced by functions above).
1094 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1095 (fp_recip, fp_sqrt): New prototypes.
1096 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1097 (Recip, SquareRoot): Replace prototypes with #defines which
1098 invoke the functions above.
72f4393d 1099
18d8a52d
CD		 11002002-06-03 Chris Demetriou <cgd@broadcom.com>
1101
1102 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1103 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1104 file, remove PARAMS from prototypes.
1105 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1106 simulator state arguments.
1107 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1108 pass simulator state arguments.
1109 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1110 (store_fpr, convert): Remove 'sd' argument.
1111 (value_fpr): Likewise. Convert to use 'SD' instead.
1112
0f154cbd
CD		 11132002-06-03 Chris Demetriou <cgd@broadcom.com>
1114
1115 * cp1.c (Min, Max): Remove #if 0'd functions.
1116 * sim-main.h (Min, Max): Remove.
1117
e80fc152
CD		 11182002-06-03 Chris Demetriou <cgd@broadcom.com>
1119
1120 * cp1.c: fix formatting of switch case and default labels.
1121 * interp.c: Likewise.
1122 * sim-main.c: Likewise.
1123
bad673a9
CD		 11242002-06-03 Chris Demetriou <cgd@broadcom.com>
1125
1126 * cp1.c: Clean up comments which describe FP formats.
1127 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1128
7cbea089 11292002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1130 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1131
1132 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1133 Broadcom SiByte SB-1 processor configurations.
1134 * configure: Regenerate.
1135 * sb1.igen: New file.
1136 * mips.igen: Include sb1.igen.
1137 (sb1): New model.
1138 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1139 * mdmx.igen: Add "sb1" model to all appropriate functions and
1140 instructions.
1141 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1142 (ob_func, ob_acc): Reference the above.
1143 (qh_acc): Adjust to keep the same size as ob_acc.
1144 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1145 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1146
909daa82
CD		 11472002-06-03 Chris Demetriou <cgd@broadcom.com>
1148
1149 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1150
f4f1b9f1 11512002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1152 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1153
1154 * mips.igen (mdmx): New (pseudo-)model.
1155 * mdmx.c, mdmx.igen: New files.
1156 * Makefile.in (SIM_OBJS): Add mdmx.o.
1157 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1158 New typedefs.
1159 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1160 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1161 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1162 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1163 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1164 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1165 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1166 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1167 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1168 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1169 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1170 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1171 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1172 (qh_fmtsel): New macros.
1173 (_sim_cpu): New member "acc".
1174 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1175 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1176
5accf1ff
CD		 11772002-05-01 Chris Demetriou <cgd@broadcom.com>
1178
1179 * interp.c: Use 'deprecated' rather than 'depreciated.'
1180 * sim-main.h: Likewise.
1181
402586aa
CD		 11822002-05-01 Chris Demetriou <cgd@broadcom.com>
1183
1184 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1185 which wouldn't compile anyway.
1186 * sim-main.h (unpredictable_action): New function prototype.
1187 (Unpredictable): Define to call igen function unpredictable().
1188 (NotWordValue): New macro to call igen function not_word_value().
1189 (UndefinedResult): Remove.
1190 * interp.c (undefined_result): Remove.
1191 (unpredictable_action): New function.
1192 * mips.igen (not_word_value, unpredictable): New functions.
1193 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1194 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1195 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1196 NotWordValue() to check for unpredictable inputs, then
1197 Unpredictable() to handle them.
1198
c9b9995a
CD		 11992002-02-24 Chris Demetriou <cgd@broadcom.com>
1200
1201 * mips.igen: Fix formatting of calls to Unpredictable().
1202
e1015982
AC		 12032002-04-20 Andrew Cagney <ac131313@redhat.com>
1204
1205 * interp.c (sim_open): Revert previous change.
1206
b882a66b
AO		 12072002-04-18 Alexandre Oliva <aoliva@redhat.com>
1208
1209 * interp.c (sim_open): Disable chunk of code that wrote code in
1210 vector table entries.
1211
c429b7dd
CD		 12122002-03-19 Chris Demetriou <cgd@broadcom.com>
1213
1214 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1215 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1216 unused definitions.
1217
37d146fa
CD		 12182002-03-19 Chris Demetriou <cgd@broadcom.com>
1219
1220 * cp1.c: Fix many formatting issues.
1221
07892c0b
CD		 12222002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1223
1224 * cp1.c (fpu_format_name): New function to replace...
1225 (DOFMT): This. Delete, and update all callers.
1226 (fpu_rounding_mode_name): New function to replace...
1227 (RMMODE): This. Delete, and update all callers.
1228
487f79b7
CD		 12292002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1230
1231 * interp.c: Move FPU support routines from here to...
1232 * cp1.c: Here. New file.
1233 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1234 (cp1.o): New target.
1235
1e799e28
CD		 12362002-03-12 Chris Demetriou <cgd@broadcom.com>
1237
1238 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1239 * mips.igen (mips32, mips64): New models, add to all instructions
1240 and functions as appropriate.
1241 (loadstore_ea, check_u64): New variant for model mips64.
1242 (check_fmt_p): New variant for models mipsV and mips64, remove
1243 mipsV model marking fro other variant.
1244 (SLL) Rename to...
1245 (SLLa) this.
1246 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1247 for mips32 and mips64.
1248 (DCLO, DCLZ): New instructions for mips64.
1249
82f728db
CD		 12502002-03-07 Chris Demetriou <cgd@broadcom.com>
1251
1252 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1253 immediate or code as a hex value with the "%#lx" format.
1254 (ANDI): Likewise, and fix printed instruction name.
1255
b96e7ef1
CD		 12562002-03-05 Chris Demetriou <cgd@broadcom.com>
1257
1258 * sim-main.h (UndefinedResult, Unpredictable): New macros
1259 which currently do nothing.
1260
d35d4f70
CD		 12612002-03-05 Chris Demetriou <cgd@broadcom.com>
1262
1263 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1264 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1265 (status_CU3): New definitions.
1266
1267 * sim-main.h (ExceptionCause): Add new values for MIPS32
1268 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1269 for DebugBreakPoint and NMIReset to note their status in
1270 MIPS32 and MIPS64.
1271 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1272 (SignalExceptionCacheErr): New exception macros.
1273
3ad6f714
CD		 12742002-03-05 Chris Demetriou <cgd@broadcom.com>
1275
1276 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1277 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1278 is always enabled.
1279 (SignalExceptionCoProcessorUnusable): Take as argument the
1280 unusable coprocessor number.
1281
86b77b47
CD		 12822002-03-05 Chris Demetriou <cgd@broadcom.com>
1283
1284 * mips.igen: Fix formatting of all SignalException calls.
1285
97a88e93 12862002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1287
1288 * sim-main.h (SIGNEXTEND): Remove.
1289
97a88e93 12902002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1291
1292 * mips.igen: Remove gencode comment from top of file, fix
1293 spelling in another comment.
1294
97a88e93 12952002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1296
1297 * mips.igen (check_fmt, check_fmt_p): New functions to check
1298 whether specific floating point formats are usable.
1299 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1300 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1301 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1302 Use the new functions.
1303 (do_c_cond_fmt): Remove format checks...
1304 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1305
97a88e93 13062002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1307
1308 * mips.igen: Fix formatting of check_fpu calls.
1309
41774c9d
CD		 13102002-03-03 Chris Demetriou <cgd@broadcom.com>
1311
1312 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1313
4a0bd876
CD		 13142002-03-03 Chris Demetriou <cgd@broadcom.com>
1315
1316 * mips.igen: Remove whitespace at end of lines.
1317
09297648
CD		 13182002-03-02 Chris Demetriou <cgd@broadcom.com>
1319
1320 * mips.igen (loadstore_ea): New function to do effective
1321 address calculations.
1322 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1323 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1324 CACHE): Use loadstore_ea to do effective address computations.
1325
043b7057
CD		 13262002-03-02 Chris Demetriou <cgd@broadcom.com>
1327
1328 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1329 * mips.igen (LL, CxC1, MxC1): Likewise.
1330
c1e8ada4
CD		 13312002-03-02 Chris Demetriou <cgd@broadcom.com>
1332
1333 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1334 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1335 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1336 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1337 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1338 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1339 Don't split opcode fields by hand, use the opcode field values
1340 provided by igen.
1341
3e1dca16
CD		 13422002-03-01 Chris Demetriou <cgd@broadcom.com>
1343
1344 * mips.igen (do_divu): Fix spacing.
1345
1346 * mips.igen (do_dsllv): Move to be right before DSLLV,
1347 to match the rest of the do_<shift> functions.
1348
fff8d27d
CD		 13492002-03-01 Chris Demetriou <cgd@broadcom.com>
1350
1351 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1352 DSRL32, do_dsrlv): Trace inputs and results.
1353
0d3e762b
CD		 13542002-03-01 Chris Demetriou <cgd@broadcom.com>
1355
1356 * mips.igen (CACHE): Provide instruction-printing string.
1357
1358 * interp.c (signal_exception): Comment tokens after #endif.
1359
eb5fcf93
CD		 13602002-02-28 Chris Demetriou <cgd@broadcom.com>
1361
1362 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1363 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1364 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1365 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1366 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1367 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1368 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1369 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1370
bb22bd7d
CD		 13712002-02-28 Chris Demetriou <cgd@broadcom.com>
1372
1373 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1374 instruction-printing string.
1375 (LWU): Use '64' as the filter flag.
1376
91a177cf
CD		 13772002-02-28 Chris Demetriou <cgd@broadcom.com>
1378
1379 * mips.igen (SDXC1): Fix instruction-printing string.
1380
387f484a
CD		 13812002-02-28 Chris Demetriou <cgd@broadcom.com>
1382
1383 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1384 filter flags "32,f".
1385
3d81f391
CD		 13862002-02-27 Chris Demetriou <cgd@broadcom.com>
1387
1388 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1389 as the filter flag.
1390
af5107af
CD		 13912002-02-27 Chris Demetriou <cgd@broadcom.com>
1392
1393 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1394 add a comma) so that it more closely match the MIPS ISA
1395 documentation opcode partitioning.
1396 (PREF): Put useful names on opcode fields, and include
1397 instruction-printing string.
1398
ca971540
CD		 13992002-02-27 Chris Demetriou <cgd@broadcom.com>
1400
1401 * mips.igen (check_u64): New function which in the future will
1402 check whether 64-bit instructions are usable and signal an
1403 exception if not. Currently a no-op.
1404 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1405 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1406 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1407 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1408
1409 * mips.igen (check_fpu): New function which in the future will
1410 check whether FPU instructions are usable and signal an exception
1411 if not. Currently a no-op.
1412 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1413 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1414 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1415 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1416 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1417 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1418 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1419 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1420
1c47a468
CD		 14212002-02-27 Chris Demetriou <cgd@broadcom.com>
1422
1423 * mips.igen (do_load_left, do_load_right): Move to be immediately
1424 following do_load.
1425 (do_store_left, do_store_right): Move to be immediately following
1426 do_store.
1427
603a98e7
CD		 14282002-02-27 Chris Demetriou <cgd@broadcom.com>
1429
1430 * mips.igen (mipsV): New model name. Also, add it to
1431 all instructions and functions where it is appropriate.
1432
c5d00cc7
CD		 14332002-02-18 Chris Demetriou <cgd@broadcom.com>
1434
1435 * mips.igen: For all functions and instructions, list model
1436 names that support that instruction one per line.
1437
074e9cb8
CD		 14382002-02-11 Chris Demetriou <cgd@broadcom.com>
1439
1440 * mips.igen: Add some additional comments about supported
1441 models, and about which instructions go where.
1442 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1443 order as is used in the rest of the file.
1444
9805e229
CD		 14452002-02-11 Chris Demetriou <cgd@broadcom.com>
1446
1447 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1448 indicating that ALU32_END or ALU64_END are there to check
1449 for overflow.
1450 (DADD): Likewise, but also remove previous comment about
1451 overflow checking.
1452
f701dad2
CD		 14532002-02-10 Chris Demetriou <cgd@broadcom.com>
1454
1455 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1456 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1457 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1458 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1459 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1460 fields (i.e., add and move commas) so that they more closely
1461 match the MIPS ISA documentation opcode partitioning.
1462
14632002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1464
72f4393d
L		 1465 * mips.igen (ADDI): Print immediate value.
1466 (BREAK): Print code.
1467 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1468 (SLL): Print "nop" specially, and don't run the code
1469 that does the shift for the "nop" case.
20ae0098 1470
9e52972e
FF		 14712001-11-17 Fred Fish <fnf@redhat.com>
1472
1473 * sim-main.h (float_operation): Move enum declaration outside
1474 of _sim_cpu struct declaration.
1475
c0efbca4
JB		 14762001-04-12 Jim Blandy <jimb@redhat.com>
1477
1478 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1479 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1480 set of the FCSR.
1481 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1482 PENDING_FILL, and you can get the intended effect gracefully by
1483 calling PENDING_SCHED directly.
1484
fb891446
BE		 14852001-02-23 Ben Elliston <bje@redhat.com>
1486
1487 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1488 already defined elsewhere.
1489
8030f857
BE		 14902001-02-19 Ben Elliston <bje@redhat.com>
1491
1492 * sim-main.h (sim_monitor): Return an int.
1493 * interp.c (sim_monitor): Add return values.
1494 (signal_exception): Handle error conditions from sim_monitor.
1495
56b48a7a
CD		 14962001-02-08 Ben Elliston <bje@redhat.com>
1497
1498 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1499 (store_memory): Likewise, pass cia to sim_core_write*.
1500
d3ee60d9
FCE		 15012000-10-19 Frank Ch. Eigler <fche@redhat.com>
1502
1503 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1504 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1505
071da002
AC		 1506Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1507
1508 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1509 * Makefile.in: Don't delete *.igen when cleaning directory.
1510
a28c02cd
AC		 1511Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1512
1513 * m16.igen (break): Call SignalException not sim_engine_halt.
1514
80ee11fa
AC		 1515Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1516
1517 From Jason Eckhardt:
1518 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1519
673388c0
AC		 1520Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1521
1522 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1523
4c0deff4
NC		 15242000-05-24 Michael Hayes <mhayes@cygnus.com>
1525
1526 * mips.igen (do_dmultx): Fix typo.
1527
eb2d80b4
AC		 1528Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1529
1530 * configure: Regenerated to track ../common/aclocal.m4 changes.
1531
dd37a34b
AC		 1532Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1533
1534 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1535
4c0deff4
NC		 15362000-04-12 Frank Ch. Eigler <fche@redhat.com>
1537
1538 * sim-main.h (GPR_CLEAR): Define macro.
1539
e30db738
AC		 1540Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1541
1542 * interp.c (decode_coproc): Output long using %lx and not %s.
1543
cb7450ea
FCE		 15442000-03-21 Frank Ch. Eigler <fche@redhat.com>
1545
1546 * interp.c (sim_open): Sort & extend dummy memory regions for
1547 --board=jmr3904 for eCos.
1548
a3027dd7
FCE		 15492000-03-02 Frank Ch. Eigler <fche@redhat.com>
1550
1551 * configure: Regenerated.
1552
1553Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1554
1555 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1556 calls, conditional on the simulator being in verbose mode.
1557
dfcd3bfb
JM		 1558Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1559
1560 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1561 cache don't get ReservedInstruction traps.
1562
c2d11a7d
JM		 15631999-11-29 Mark Salter <msalter@cygnus.com>
1564
1565 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1566 to clear status bits in sdisr register. This is how the hardware works.
1567
1568 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1569 being used by cygmon.
1570
4ce44c66
JM		 15711999-11-11 Andrew Haley <aph@cygnus.com>
1572
1573 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1574 instructions.
1575
cff3e48b
JM		 1576Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1577
1578 * mips.igen (MULT): Correct previous mis-applied patch.
1579
d4f3574e
SS		 1580Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1581
1582 * mips.igen (delayslot32): Handle sequence like
1583 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1584 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1585 (MULT): Actually pass the third register...
1586
15871999-09-03 Mark Salter <msalter@cygnus.com>
1588
1589 * interp.c (sim_open): Added more memory aliases for additional
1590 hardware being touched by cygmon on jmr3904 board.
1591
1592Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1593
1594 * configure: Regenerated to track ../common/aclocal.m4 changes.
1595
a0b3c4fd
JM		 1596Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1597
1598 * interp.c (sim_store_register): Handle case where client - GDB -
1599 specifies that a 4 byte register is 8 bytes in size.
1600 (sim_fetch_register): Ditto.
72f4393d 1601
adf40b2e
JM		 16021999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1603
1604 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1605 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1606 (idt_monitor_base): Base address for IDT monitor traps.
1607 (pmon_monitor_base): Ditto for PMON.
1608 (lsipmon_monitor_base): Ditto for LSI PMON.
1609 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1610 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1611 (sim_firmware_command): New function.
1612 (mips_option_handler): Call it for OPTION_FIRMWARE.
1613 (sim_open): Allocate memory for idt_monitor region. If "--board"
1614 option was given, add no monitor by default. Add BREAK hooks only if
1615 monitors are also there.
72f4393d 1616
43e526b9
JM		 1617Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1618
1619 * interp.c (sim_monitor): Flush output before reading input.
1620
1621Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1622
1623 * tconfig.in (SIM_HANDLES_LMA): Always define.
1624
1625Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1626
1627 From Mark Salter <msalter@cygnus.com>:
1628 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1629 (sim_open): Add setup for BSP board.
1630
9846de1b
JM		 1631Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1632
1633 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1634 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1635 them as unimplemented.
1636
cd0fc7c3
SS		 16371999-05-08 Felix Lee <flee@cygnus.com>
1638
1639 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1640
7a292a7a
SS		 16411999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1642
1643 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1644
1645Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1646
1647 * configure.in: Any mips64vr5*-*-* target should have
1648 -DTARGET_ENABLE_FR=1.
1649 (default_endian): Any mips64vr*el-*-* target should default to
1650 LITTLE_ENDIAN.
1651 * configure: Re-generate.
1652
16531999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1654
1655 * mips.igen (ldl): Extend from _16_, not 32.
1656
1657Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1658
1659 * interp.c (sim_store_register): Force registers written to by GDB
1660 into an un-interpreted state.
1661
c906108c
SS		 16621999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1663
1664 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1665 CPU, start periodic background I/O polls.
72f4393d 1666 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1667
16681998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1669
1670 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1671
c906108c
SS		 1672Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1673
1674 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1675 case statement.
1676
16771998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1678
1679 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1680 (load_word): Call SIM_CORE_SIGNAL hook on error.
1681 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1682 starting. For exception dispatching, pass PC instead of NULL_CIA.
1683 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1684 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1685 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1686 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1687 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1688 * mips.igen (*): Replace memory-related SignalException* calls
1689 with references to SIM_CORE_SIGNAL hook.
72f4393d 1690
c906108c
SS		 1691 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1692 fix.
1693 * sim-main.c (*): Minor warning cleanups.
72f4393d 1694
c906108c
SS		 16951998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1696
1697 * m16.igen (DADDIU5): Correct type-o.
1698
1699Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1700
1701 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1702 variables.
1703
1704Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1705
1706 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1707 to include path.
1708 (interp.o): Add dependency on itable.h
1709 (oengine.c, gencode): Delete remaining references.
1710 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1711
c906108c 17121998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1713
c906108c
SS		 1714 * vr4run.c: New.
1715 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1716 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1717 tmp-run-hack) : New.
1718 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1719 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1720 Drop the "64" qualifier to get the HACK generator working.
1721 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1722 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1723 qualifier to get the hack generator working.
1724 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1725 (DSLL): Use do_dsll.
1726 (DSLLV): Use do_dsllv.
1727 (DSRA): Use do_dsra.
1728 (DSRL): Use do_dsrl.
1729 (DSRLV): Use do_dsrlv.
1730 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1731 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1732 get the HACK generator working.
1733 (MACC) Rename to get the HACK generator working.
1734 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1735
c906108c
SS		 17361998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1737
1738 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1739 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1740
c906108c
SS		 17411998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1742
1743 * mips/interp.c (DEBUG): Cleanups.
1744
17451998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1746
1747 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1748 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1749
c906108c
SS		 17501998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1751
1752 * interp.c (sim_close): Uninstall modules.
1753
1754Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1755
1756 * sim-main.h, interp.c (sim_monitor): Change to global
1757 function.
1758
1759Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1760
1761 * configure.in (vr4100): Only include vr4100 instructions in
1762 simulator.
1763 * configure: Re-generate.
1764 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1765
1766Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1767
1768 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1769 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1770 true alternative.
1771
1772 * configure.in (sim_default_gen, sim_use_gen): Replace with
1773 sim_gen.
1774 (--enable-sim-igen): Delete config option. Always using IGEN.
1775 * configure: Re-generate.
72f4393d 1776
c906108c
SS		 1777 * Makefile.in (gencode): Kill, kill, kill.
1778 * gencode.c: Ditto.
72f4393d 1779
c906108c
SS		 1780Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1781
1782 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1783 bit mips16 igen simulator.
1784 * configure: Re-generate.
1785
1786 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1787 as part of vr4100 ISA.
1788 * vr.igen: Mark all instructions as 64 bit only.
1789
1790Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1791
1792 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1793 Pacify GCC.
1794
1795Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1796
1797 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1798 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1799 * configure: Re-generate.
1800
1801 * m16.igen (BREAK): Define breakpoint instruction.
1802 (JALX32): Mark instruction as mips16 and not r3900.
1803 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1804
1805 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1806
1807Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1808
1809 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1810 insn as a debug breakpoint.
1811
1812 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1813 pending.slot_size.
1814 (PENDING_SCHED): Clean up trace statement.
1815 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1816 (PENDING_FILL): Delay write by only one cycle.
1817 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1818
1819 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1820 of pending writes.
1821 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1822 32 & 64.
1823 (pending_tick): Move incrementing of index to FOR statement.
1824 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1825
c906108c
SS		 1826 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1827 build simulator.
1828 * configure: Re-generate.
72f4393d 1829
c906108c
SS		 1830 * interp.c (sim_engine_run OLD): Delete explicit call to
1831 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1832
c906108c
SS		 1833Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1834
1835 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1836 interrupt level number to match changed SignalExceptionInterrupt
1837 macro.
1838
1839Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1840
1841 * interp.c: #include "itable.h" if WITH_IGEN.
1842 (get_insn_name): New function.
1843 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1844 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1845
1846Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1847
1848 * configure: Rebuilt to inhale new common/aclocal.m4.
1849
1850Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1851
1852 * dv-tx3904sio.c: Include sim-assert.h.
1853
1854Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1855
1856 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1857 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1858 Reorganize target-specific sim-hardware checks.
1859 * configure: rebuilt.
1860 * interp.c (sim_open): For tx39 target boards, set
1861 OPERATING_ENVIRONMENT, add tx3904sio devices.
1862 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1863 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1864
c906108c
SS		 1865 * dv-tx3904irc.c: Compiler warning clean-up.
1866 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1867 frequent hw-trace messages.
1868
1869Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1870
1871 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1872
1873Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1874
1875 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1876
1877 * vr.igen: New file.
1878 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1879 * mips.igen: Define vr4100 model. Include vr.igen.
1880Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1881
1882 * mips.igen (check_mf_hilo): Correct check.
1883
1884Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1885
1886 * sim-main.h (interrupt_event): Add prototype.
1887
1888 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1889 register_ptr, register_value.
1890 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1891
1892 * sim-main.h (tracefh): Make extern.
1893
1894Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1895
1896 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1897 Reduce unnecessarily high timer event frequency.
c906108c 1898 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1899
c906108c
SS		 1900Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1901
1902 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1903 to allay warnings.
1904 (interrupt_event): Made non-static.
72f4393d 1905
c906108c
SS		 1906 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1907 interchange of configuration values for external vs. internal
1908 clock dividers.
72f4393d 1909
c906108c
SS		 1910Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1911
72f4393d 1912 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1913 simulator-reserved break instructions.
1914 * gencode.c (build_instruction): Ditto.
1915 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1916 reserved instructions now use exception vector, rather
c906108c
SS		 1917 than halting sim.
1918 * sim-main.h: Moved magic constants to here.
1919
1920Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1921
1922 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1923 register upon non-zero interrupt event level, clear upon zero
1924 event value.
1925 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1926 by passing zero event value.
1927 (*_io_{read,write}_buffer): Endianness fixes.
1928 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1929 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1930
1931 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1932 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 1933
c906108c
SS		 1934Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1935
72f4393d 1936 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 1937 and BigEndianCPU.
1938
1939Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1940
1941 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1942 parts.
1943 * configure: Update.
1944
1945Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1946
1947 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1948 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1949 * configure.in: Include tx3904tmr in hw_device list.
1950 * configure: Rebuilt.
1951 * interp.c (sim_open): Instantiate three timer instances.
1952 Fix address typo of tx3904irc instance.
1953
1954Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1955
1956 * interp.c (signal_exception): SystemCall exception now uses
1957 the exception vector.
1958
1959Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1960
1961 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1962 to allay warnings.
1963
1964Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1965
1966 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1967
1968Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1969
1970 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1971
1972 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1973 sim-main.h. Declare a struct hw_descriptor instead of struct
1974 hw_device_descriptor.
1975
1976Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1977
1978 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1979 right bits and then re-align left hand bytes to correct byte
1980 lanes. Fix incorrect computation in do_store_left when loading
1981 bytes from second word.
1982
1983Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1984
1985 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1986 * interp.c (sim_open): Only create a device tree when HW is
1987 enabled.
1988
1989 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1990 * interp.c (signal_exception): Ditto.
1991
1992Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1993
1994 * gencode.c: Mark BEGEZALL as LIKELY.
1995
1996Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1997
1998 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1999 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2000
c906108c
SS		 2001Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2002
2003 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2004 modules. Recognize TX39 target with "mips*tx39" pattern.
2005 * configure: Rebuilt.
2006 * sim-main.h (*): Added many macros defining bits in
2007 TX39 control registers.
2008 (SignalInterrupt): Send actual PC instead of NULL.
2009 (SignalNMIReset): New exception type.
2010 * interp.c (board): New variable for future use to identify
2011 a particular board being simulated.
2012 (mips_option_handler,mips_options): Added "--board" option.
2013 (interrupt_event): Send actual PC.
2014 (sim_open): Make memory layout conditional on board setting.
2015 (signal_exception): Initial implementation of hardware interrupt
2016 handling. Accept another break instruction variant for simulator
2017 exit.
2018 (decode_coproc): Implement RFE instruction for TX39.
2019 (mips.igen): Decode RFE instruction as such.
2020 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2021 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2022 bbegin to implement memory map.
2023 * dv-tx3904cpu.c: New file.
2024 * dv-tx3904irc.c: New file.
2025
2026Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2027
2028 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2029
2030Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2031
2032 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2033 with calls to check_div_hilo.
2034
2035Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2036
2037 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2038 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2039 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2040 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2041 with calls to check_mult_hilo.
2042 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2043 with calls to check_div_hilo.
2044
2045Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2046
2047 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2048 Document a replacement.
2049
2050Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2051
2052 * interp.c (sim_monitor): Make mon_printf work.
2053
2054Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2055
2056 * sim-main.h (INSN_NAME): New arg `cpu'.
2057
2058Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2059
72f4393d 2060 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2061
2062Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2063
2064 * configure: Regenerated to track ../common/aclocal.m4 changes.
2065 * config.in: Ditto.
2066
2067Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2068
2069 * acconfig.h: New file.
2070 * configure.in: Reverted change of Apr 24; use sinclude again.
2071
2072Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2073
2074 * configure: Regenerated to track ../common/aclocal.m4 changes.
2075 * config.in: Ditto.
2076
2077Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2078
2079 * configure.in: Don't call sinclude.
2080
2081Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2082
2083 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2084
2085Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2086
2087 * mips.igen (ERET): Implement.
2088
2089 * interp.c (decode_coproc): Return sign-extended EPC.
2090
2091 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2092
2093 * interp.c (signal_exception): Do not ignore Trap.
2094 (signal_exception): On TRAP, restart at exception address.
2095 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2096 (signal_exception): Update.
2097 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2098 so that TRAP instructions are caught.
2099
2100Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2101
2102 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2103 contains HI/LO access history.
2104 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2105 (HIACCESS, LOACCESS): Delete, replace with
2106 (HIHISTORY, LOHISTORY): New macros.
2107 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2108
c906108c
SS		 2109 * gencode.c (build_instruction): Do not generate checks for
2110 correct HI/LO register usage.
2111
2112 * interp.c (old_engine_run): Delete checks for correct HI/LO
2113 register usage.
2114
2115 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2116 check_mf_cycles): New functions.
2117 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2118 do_divu, domultx, do_mult, do_multu): Use.
2119
2120 * tx.igen ("madd", "maddu"): Use.
72f4393d 2121
c906108c
SS		 2122Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2123
2124 * mips.igen (DSRAV): Use function do_dsrav.
2125 (SRAV): Use new function do_srav.
2126
2127 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2128 (B): Sign extend 11 bit immediate.
2129 (EXT-B*): Shift 16 bit immediate left by 1.
2130 (ADDIU*): Don't sign extend immediate value.
2131
2132Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2133
2134 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2135
2136 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2137 functions.
2138
2139 * mips.igen (delayslot32, nullify_next_insn): New functions.
2140 (m16.igen): Always include.
2141 (do_*): Add more tracing.
2142
2143 * m16.igen (delayslot16): Add NIA argument, could be called by a
2144 32 bit MIPS16 instruction.
72f4393d 2145
c906108c
SS		 2146 * interp.c (ifetch16): Move function from here.
2147 * sim-main.c (ifetch16): To here.
72f4393d 2148
c906108c
SS		 2149 * sim-main.c (ifetch16, ifetch32): Update to match current
2150 implementations of LH, LW.
2151 (signal_exception): Don't print out incorrect hex value of illegal
2152 instruction.
2153
2154Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2155
2156 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2157 instruction.
2158
2159 * m16.igen: Implement MIPS16 instructions.
72f4393d 2160
c906108c
SS		 2161 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2162 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2163 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2164 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2165 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2166 bodies of corresponding code from 32 bit insn to these. Also used
2167 by MIPS16 versions of functions.
72f4393d 2168
c906108c
SS		 2169 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2170 (IMEM16): Drop NR argument from macro.
2171
2172Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2173
2174 * Makefile.in (SIM_OBJS): Add sim-main.o.
2175
2176 * sim-main.h (address_translation, load_memory, store_memory,
2177 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2178 as INLINE_SIM_MAIN.
2179 (pr_addr, pr_uword64): Declare.
2180 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2181
c906108c
SS		 2182 * interp.c (address_translation, load_memory, store_memory,
2183 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2184 from here.
2185 * sim-main.c: To here. Fix compilation problems.
72f4393d 2186
c906108c
SS		 2187 * configure.in: Enable inlining.
2188 * configure: Re-config.
2189
2190Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2191
2192 * configure: Regenerated to track ../common/aclocal.m4 changes.
2193
2194Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2195
2196 * mips.igen: Include tx.igen.
2197 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2198 * tx.igen: New file, contains MADD and MADDU.
2199
2200 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2201 the hardwired constant `7'.
2202 (store_memory): Ditto.
2203 (LOADDRMASK): Move definition to sim-main.h.
2204
2205 mips.igen (MTC0): Enable for r3900.
2206 (ADDU): Add trace.
2207
2208 mips.igen (do_load_byte): Delete.
2209 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2210 do_store_right): New functions.
2211 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2212
2213 configure.in: Let the tx39 use igen again.
2214 configure: Update.
72f4393d 2215
c906108c
SS		 2216Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2217
2218 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2219 not an address sized quantity. Return zero for cache sizes.
2220
2221Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2222
2223 * mips.igen (r3900): r3900 does not support 64 bit integer
2224 operations.
2225
2226Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2227
2228 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2229 than igen one.
2230 * configure : Rebuild.
72f4393d 2231
c906108c
SS		 2232Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2233
2234 * configure: Regenerated to track ../common/aclocal.m4 changes.
2235
2236Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2237
2238 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2239
2240Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2241
2242 * configure: Regenerated to track ../common/aclocal.m4 changes.
2243 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2244
2245Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2246
2247 * configure: Regenerated to track ../common/aclocal.m4 changes.
2248
2249Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2250
2251 * interp.c (Max, Min): Comment out functions. Not yet used.
2252
2253Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2254
2255 * configure: Regenerated to track ../common/aclocal.m4 changes.
2256
2257Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2258
2259 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2260 configurable settings for stand-alone simulator.
72f4393d 2261
c906108c 2262 * configure.in: Added X11 search, just in case.
72f4393d 2263
c906108c
SS		 2264 * configure: Regenerated.
2265
2266Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2267
2268 * interp.c (sim_write, sim_read, load_memory, store_memory):
2269 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2270
2271Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2272
2273 * sim-main.h (GETFCC): Return an unsigned value.
2274
2275Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2276
2277 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2278 (DADD): Result destination is RD not RT.
2279
2280Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2281
2282 * sim-main.h (HIACCESS, LOACCESS): Always define.
2283
2284 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2285
2286 * interp.c (sim_info): Delete.
2287
2288Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2289
2290 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2291 (mips_option_handler): New argument `cpu'.
2292 (sim_open): Update call to sim_add_option_table.
2293
2294Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2295
2296 * mips.igen (CxC1): Add tracing.
2297
2298Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2299
2300 * sim-main.h (Max, Min): Declare.
2301
2302 * interp.c (Max, Min): New functions.
2303
2304 * mips.igen (BC1): Add tracing.
72f4393d 2305
c906108c 2306Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2307
c906108c 2308 * interp.c Added memory map for stack in vr4100
72f4393d 2309
c906108c
SS		 2310Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2311
2312 * interp.c (load_memory): Add missing "break"'s.
2313
2314Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2315
2316 * interp.c (sim_store_register, sim_fetch_register): Pass in
2317 length parameter. Return -1.
2318
2319Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2320
2321 * interp.c: Added hardware init hook, fixed warnings.
2322
2323Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2324
2325 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2326
2327Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2328
2329 * interp.c (ifetch16): New function.
2330
2331 * sim-main.h (IMEM32): Rename IMEM.
2332 (IMEM16_IMMED): Define.
2333 (IMEM16): Define.
2334 (DELAY_SLOT): Update.
72f4393d 2335
c906108c 2336 * m16run.c (sim_engine_run): New file.
72f4393d 2337
c906108c
SS		 2338 * m16.igen: All instructions except LB.
2339 (LB): Call do_load_byte.
2340 * mips.igen (do_load_byte): New function.
2341 (LB): Call do_load_byte.
2342
2343 * mips.igen: Move spec for insn bit size and high bit from here.
2344 * Makefile.in (tmp-igen, tmp-m16): To here.
2345
2346 * m16.dc: New file, decode mips16 instructions.
2347
2348 * Makefile.in (SIM_NO_ALL): Define.
2349 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2350
2351Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2352
2353 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2354 point unit to 32 bit registers.
2355 * configure: Re-generate.
2356
2357Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2358
2359 * configure.in (sim_use_gen): Make IGEN the default simulator
2360 generator for generic 32 and 64 bit mips targets.
2361 * configure: Re-generate.
2362
2363Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2364
2365 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2366 bitsize.
2367
2368 * interp.c (sim_fetch_register, sim_store_register): Read/write
2369 FGR from correct location.
2370 (sim_open): Set size of FGR's according to
2371 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2372
c906108c
SS		 2373 * sim-main.h (FGR): Store floating point registers in a separate
2374 array.
2375
2376Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2377
2378 * configure: Regenerated to track ../common/aclocal.m4 changes.
2379
2380Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2381
2382 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2383
2384 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2385
2386 * interp.c (pending_tick): New function. Deliver pending writes.
2387
2388 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2389 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2390 it can handle mixed sized quantites and single bits.
72f4393d 2391
c906108c
SS		 2392Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2393
2394 * interp.c (oengine.h): Do not include when building with IGEN.
2395 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2396 (sim_info): Ditto for PROCESSOR_64BIT.
2397 (sim_monitor): Replace ut_reg with unsigned_word.
2398 (*): Ditto for t_reg.
2399 (LOADDRMASK): Define.
2400 (sim_open): Remove defunct check that host FP is IEEE compliant,
2401 using software to emulate floating point.
2402 (value_fpr, ...): Always compile, was conditional on HASFPU.
2403
2404Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2405
2406 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2407 size.
2408
2409 * interp.c (SD, CPU): Define.
2410 (mips_option_handler): Set flags in each CPU.
2411 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2412 (sim_close): Do not clear STATE, deleted anyway.
2413 (sim_write, sim_read): Assume CPU zero's vm should be used for
2414 data transfers.
2415 (sim_create_inferior): Set the PC for all processors.
2416 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2417 argument.
2418 (mips16_entry): Pass correct nr of args to store_word, load_word.
2419 (ColdReset): Cold reset all cpu's.
2420 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2421 (sim_monitor, load_memory, store_memory, signal_exception): Use
2422 `CPU' instead of STATE_CPU.
2423
2424
2425 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2426 SD or CPU_.
72f4393d 2427
c906108c
SS		 2428 * sim-main.h (signal_exception): Add sim_cpu arg.
2429 (SignalException*): Pass both SD and CPU to signal_exception.
2430 * interp.c (signal_exception): Update.
72f4393d 2431
c906108c
SS		 2432 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2433 Ditto
2434 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2435 address_translation): Ditto
2436 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2437
c906108c
SS		 2438Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2439
2440 * configure: Regenerated to track ../common/aclocal.m4 changes.
2441
2442Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2443
2444 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2445
72f4393d 2446 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2447
2448 * sim-main.h (CPU_CIA): Delete.
2449 (SET_CIA, GET_CIA): Define
2450
2451Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2452
2453 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2454 regiser.
2455
2456 * configure.in (default_endian): Configure a big-endian simulator
2457 by default.
2458 * configure: Re-generate.
72f4393d 2459
c906108c
SS		 2460Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2461
2462 * configure: Regenerated to track ../common/aclocal.m4 changes.
2463
2464Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2465
2466 * interp.c (sim_monitor): Handle Densan monitor outbyte
2467 and inbyte functions.
2468
24691997-12-29 Felix Lee <flee@cygnus.com>
2470
2471 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2472
2473Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2474
2475 * Makefile.in (tmp-igen): Arrange for $zero to always be
2476 reset to zero after every instruction.
2477
2478Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2479
2480 * configure: Regenerated to track ../common/aclocal.m4 changes.
2481 * config.in: Ditto.
2482
2483Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2484
2485 * mips.igen (MSUB): Fix to work like MADD.
2486 * gencode.c (MSUB): Similarly.
2487
2488Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2489
2490 * configure: Regenerated to track ../common/aclocal.m4 changes.
2491
2492Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2493
2494 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2495
2496Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2497
2498 * sim-main.h (sim-fpu.h): Include.
2499
2500 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2501 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2502 using host independant sim_fpu module.
2503
2504Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2505
2506 * interp.c (signal_exception): Report internal errors with SIGABRT
2507 not SIGQUIT.
2508
2509 * sim-main.h (C0_CONFIG): New register.
2510 (signal.h): No longer include.
2511
2512 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2513
2514Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2515
2516 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2517
2518Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2519
2520 * mips.igen: Tag vr5000 instructions.
2521 (ANDI): Was missing mipsIV model, fix assembler syntax.
2522 (do_c_cond_fmt): New function.
2523 (C.cond.fmt): Handle mips I-III which do not support CC field
2524 separatly.
2525 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2526 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2527 in IV3.2 spec.
2528 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2529 vr5000 which saves LO in a GPR separatly.
72f4393d 2530
c906108c
SS		 2531 * configure.in (enable-sim-igen): For vr5000, select vr5000
2532 specific instructions.
2533 * configure: Re-generate.
72f4393d 2534
c906108c
SS		 2535Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2536
2537 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2538
2539 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2540 fmt_uninterpreted_64 bit cases to switch. Convert to
2541 fmt_formatted,
2542
2543 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2544
2545 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2546 as specified in IV3.2 spec.
2547 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2548
2549Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2550
2551 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2552 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2553 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2554 PENDING_FILL versions of instructions. Simplify.
2555 (X): New function.
2556 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2557 instructions.
2558 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2559 a signed value.
2560 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2561
c906108c
SS		 2562 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2563 global.
2564 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2565
2566Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2567
2568 * gencode.c (build_mips16_operands): Replace IPC with cia.
2569
2570 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2571 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2572 IPC to `cia'.
2573 (UndefinedResult): Replace function with macro/function
2574 combination.
2575 (sim_engine_run): Don't save PC in IPC.
2576
2577 * sim-main.h (IPC): Delete.
2578
2579
2580 * interp.c (signal_exception, store_word, load_word,
2581 address_translation, load_memory, store_memory, cache_op,
2582 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2583 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2584 current instruction address - cia - argument.
2585 (sim_read, sim_write): Call address_translation directly.
2586 (sim_engine_run): Rename variable vaddr to cia.
2587 (signal_exception): Pass cia to sim_monitor
72f4393d 2588
c906108c
SS		 2589 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2590 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2591 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2592
2593 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2594 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2595 SIM_ASSERT.
72f4393d 2596
c906108c
SS		 2597 * interp.c (signal_exception): Pass restart address to
2598 sim_engine_restart.
2599
2600 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2601 idecode.o): Add dependency.
2602
2603 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2604 Delete definitions
2605 (DELAY_SLOT): Update NIA not PC with branch address.
2606 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2607
2608 * mips.igen: Use CIA not PC in branch calculations.
2609 (illegal): Call SignalException.
2610 (BEQ, ADDIU): Fix assembler.
2611
2612Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2613
2614 * m16.igen (JALX): Was missing.
2615
2616 * configure.in (enable-sim-igen): New configuration option.
2617 * configure: Re-generate.
72f4393d 2618
c906108c
SS		 2619 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2620
2621 * interp.c (load_memory, store_memory): Delete parameter RAW.
2622 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2623 bypassing {load,store}_memory.
2624
2625 * sim-main.h (ByteSwapMem): Delete definition.
2626
2627 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2628
2629 * interp.c (sim_do_command, sim_commands): Delete mips specific
2630 commands. Handled by module sim-options.
72f4393d 2631
c906108c
SS		 2632 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2633 (WITH_MODULO_MEMORY): Define.
2634
2635 * interp.c (sim_info): Delete code printing memory size.
2636
2637 * interp.c (mips_size): Nee sim_size, delete function.
2638 (power2): Delete.
2639 (monitor, monitor_base, monitor_size): Delete global variables.
2640 (sim_open, sim_close): Delete code creating monitor and other
2641 memory regions. Use sim-memopts module, via sim_do_commandf, to
2642 manage memory regions.
2643 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2644
c906108c
SS		 2645 * interp.c (address_translation): Delete all memory map code
2646 except line forcing 32 bit addresses.
2647
2648Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2649
2650 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2651 trace options.
2652
2653 * interp.c (logfh, logfile): Delete globals.
2654 (sim_open, sim_close): Delete code opening & closing log file.
2655 (mips_option_handler): Delete -l and -n options.
2656 (OPTION mips_options): Ditto.
2657
2658 * interp.c (OPTION mips_options): Rename option trace to dinero.
2659 (mips_option_handler): Update.
2660
2661Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2662
2663 * interp.c (fetch_str): New function.
2664 (sim_monitor): Rewrite using sim_read & sim_write.
2665 (sim_open): Check magic number.
2666 (sim_open): Write monitor vectors into memory using sim_write.
2667 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2668 (sim_read, sim_write): Simplify - transfer data one byte at a
2669 time.
2670 (load_memory, store_memory): Clarify meaning of parameter RAW.
2671
2672 * sim-main.h (isHOST): Defete definition.
2673 (isTARGET): Mark as depreciated.
2674 (address_translation): Delete parameter HOST.
2675
2676 * interp.c (address_translation): Delete parameter HOST.
2677
2678Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2679
72f4393d 2680 * mips.igen:
c906108c
SS		 2681
2682 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2683 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2684
2685Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2686
2687 * mips.igen: Add model filter field to records.
2688
2689Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2690
2691 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2692
c906108c
SS		 2693 interp.c (sim_engine_run): Do not compile function sim_engine_run
2694 when WITH_IGEN == 1.
2695
2696 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2697 target architecture.
2698
2699 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2700 igen. Replace with configuration variables sim_igen_flags /
2701 sim_m16_flags.
2702
2703 * m16.igen: New file. Copy mips16 insns here.
2704 * mips.igen: From here.
2705
2706Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2707
2708 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2709 to top.
2710 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2711
2712Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2713
2714 * gencode.c (build_instruction): Follow sim_write's lead in using
2715 BigEndianMem instead of !ByteSwapMem.
2716
2717Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2718
2719 * configure.in (sim_gen): Dependent on target, select type of
2720 generator. Always select old style generator.
2721
2722 configure: Re-generate.
2723
2724 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2725 targets.
2726 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2727 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2728 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2729 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2730 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2731
c906108c
SS		 2732Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2733
2734 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2735
2736 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2737 CURRENT_FLOATING_POINT instead.
2738
2739 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2740 (address_translation): Raise exception InstructionFetch when
2741 translation fails and isINSTRUCTION.
72f4393d 2742
c906108c
SS		 2743 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2744 sim_engine_run): Change type of of vaddr and paddr to
2745 address_word.
2746 (address_translation, prefetch, load_memory, store_memory,
2747 cache_op): Change type of vAddr and pAddr to address_word.
2748
2749 * gencode.c (build_instruction): Change type of vaddr and paddr to
2750 address_word.
2751
2752Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2753
2754 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2755 macro to obtain result of ALU op.
2756
2757Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2758
2759 * interp.c (sim_info): Call profile_print.
2760
2761Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2762
2763 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2764
2765 * sim-main.h (WITH_PROFILE): Do not define, defined in
2766 common/sim-config.h. Use sim-profile module.
2767 (simPROFILE): Delete defintion.
2768
2769 * interp.c (PROFILE): Delete definition.
2770 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2771 (sim_close): Delete code writing profile histogram.
2772 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2773 Delete.
2774 (sim_engine_run): Delete code profiling the PC.
2775
2776Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2777
2778 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2779
2780 * interp.c (sim_monitor): Make register pointers of type
2781 unsigned_word*.
2782
2783 * sim-main.h: Make registers of type unsigned_word not
2784 signed_word.
2785
2786Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2787
2788 * interp.c (sync_operation): Rename from SyncOperation, make
2789 global, add SD argument.
2790 (prefetch): Rename from Prefetch, make global, add SD argument.
2791 (decode_coproc): Make global.
2792
2793 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2794
2795 * gencode.c (build_instruction): Generate DecodeCoproc not
2796 decode_coproc calls.
2797
2798 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2799 (SizeFGR): Move to sim-main.h
2800 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2801 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2802 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2803 sim-main.h.
2804 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2805 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2806 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2807 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2808 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2809 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2810
c906108c
SS		 2811 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2812 exception.
2813 (sim-alu.h): Include.
2814 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2815 (sim_cia): Typedef to instruction_address.
72f4393d 2816
c906108c
SS		 2817Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2818
2819 * Makefile.in (interp.o): Rename generated file engine.c to
2820 oengine.c.
72f4393d 2821
c906108c 2822 * interp.c: Update.
72f4393d 2823
c906108c
SS		 2824Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2825
2826 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2827
c906108c
SS		 2828Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2829
2830 * gencode.c (build_instruction): For "FPSQRT", output correct
2831 number of arguments to Recip.
72f4393d 2832
c906108c
SS		 2833Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2834
2835 * Makefile.in (interp.o): Depends on sim-main.h
2836
2837 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2838
2839 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2840 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2841 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2842 STATE, DSSTATE): Define
2843 (GPR, FGRIDX, ..): Define.
2844
2845 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2846 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2847 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2848
c906108c 2849 * interp.c: Update names to match defines from sim-main.h
72f4393d 2850
c906108c
SS		 2851Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2852
2853 * interp.c (sim_monitor): Add SD argument.
2854 (sim_warning): Delete. Replace calls with calls to
2855 sim_io_eprintf.
2856 (sim_error): Delete. Replace calls with sim_io_error.
2857 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2858 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2859 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2860 argument.
2861 (mips_size): Rename from sim_size. Add SD argument.
2862
2863 * interp.c (simulator): Delete global variable.
2864 (callback): Delete global variable.
2865 (mips_option_handler, sim_open, sim_write, sim_read,
2866 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2867 sim_size,sim_monitor): Use sim_io_* not callback->*.
2868 (sim_open): ZALLOC simulator struct.
2869 (PROFILE): Do not define.
2870
2871Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2872
2873 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2874 support.h with corresponding code.
2875
2876 * sim-main.h (word64, uword64), support.h: Move definition to
2877 sim-main.h.
2878 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2879
2880 * support.h: Delete
2881 * Makefile.in: Update dependencies
2882 * interp.c: Do not include.
72f4393d 2883
c906108c
SS		 2884Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2885
2886 * interp.c (address_translation, load_memory, store_memory,
2887 cache_op): Rename to from AddressTranslation et.al., make global,
2888 add SD argument
72f4393d 2889
c906108c
SS		 2890 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2891 CacheOp): Define.
72f4393d 2892
c906108c
SS		 2893 * interp.c (SignalException): Rename to signal_exception, make
2894 global.
2895
2896 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2897
c906108c
SS		 2898 * sim-main.h (SignalException, SignalExceptionInterrupt,
2899 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2900 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2901 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2902 Define.
72f4393d 2903
c906108c 2904 * interp.c, support.h: Use.
72f4393d 2905
c906108c
SS		 2906Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2907
2908 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2909 to value_fpr / store_fpr. Add SD argument.
2910 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2911 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2912
2913 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2914
c906108c
SS		 2915Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2916
2917 * interp.c (sim_engine_run): Check consistency between configure
2918 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2919 and HASFPU.
2920
2921 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 2922 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 2923 (mips_endian): Configure WITH_TARGET_ENDIAN.
2924 * configure: Update.
2925
2926Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2927
2928 * configure: Regenerated to track ../common/aclocal.m4 changes.
2929
2930Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2931
2932 * configure: Regenerated.
2933
2934Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2935
2936 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2937
2938Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2939
2940 * gencode.c (print_igen_insn_models): Assume certain architectures
2941 include all mips* instructions.
2942 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2943 instruction.
2944
2945 * Makefile.in (tmp.igen): Add target. Generate igen input from
2946 gencode file.
2947
2948 * gencode.c (FEATURE_IGEN): Define.
2949 (main): Add --igen option. Generate output in igen format.
2950 (process_instructions): Format output according to igen option.
2951 (print_igen_insn_format): New function.
2952 (print_igen_insn_models): New function.
2953 (process_instructions): Only issue warnings and ignore
2954 instructions when no FEATURE_IGEN.
2955
2956Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2957
2958 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2959 MIPS targets.
2960
2961Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2962
2963 * configure: Regenerated to track ../common/aclocal.m4 changes.
2964
2965Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2966
2967 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2968 SIM_RESERVED_BITS): Delete, moved to common.
2969 (SIM_EXTRA_CFLAGS): Update.
72f4393d 2970
c906108c
SS		 2971Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2972
2973 * configure.in: Configure non-strict memory alignment.
2974 * configure: Regenerated to track ../common/aclocal.m4 changes.
2975
2976Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2977
2978 * configure: Regenerated to track ../common/aclocal.m4 changes.
2979
2980Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2981
2982 * gencode.c (SDBBP,DERET): Added (3900) insns.
2983 (RFE): Turn on for 3900.
2984 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2985 (dsstate): Made global.
2986 (SUBTARGET_R3900): Added.
2987 (CANCELDELAYSLOT): New.
2988 (SignalException): Ignore SystemCall rather than ignore and
2989 terminate. Add DebugBreakPoint handling.
2990 (decode_coproc): New insns RFE, DERET; and new registers Debug
2991 and DEPC protected by SUBTARGET_R3900.
2992 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2993 bits explicitly.
2994 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 2995 * configure: Update.
c906108c
SS		 2996
2997Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2998
2999 * gencode.c: Add r3900 (tx39).
72f4393d 3000
c906108c
SS		 3001
3002Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3003
3004 * gencode.c (build_instruction): Don't need to subtract 4 for
3005 JALR, just 2.
3006
3007Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3008
3009 * interp.c: Correct some HASFPU problems.
3010
3011Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3012
3013 * configure: Regenerated to track ../common/aclocal.m4 changes.
3014
3015Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3016
3017 * interp.c (mips_options): Fix samples option short form, should
3018 be `x'.
3019
3020Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3021
3022 * interp.c (sim_info): Enable info code. Was just returning.
3023
3024Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3025
3026 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3027 MFC0.
3028
3029Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3030
3031 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3032 constants.
3033 (build_instruction): Ditto for LL.
3034
3035Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3036
3037 * configure: Regenerated to track ../common/aclocal.m4 changes.
3038
3039Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3040
3041 * configure: Regenerated to track ../common/aclocal.m4 changes.
3042 * config.in: Ditto.
3043
3044Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3045
3046 * interp.c (sim_open): Add call to sim_analyze_program, update
3047 call to sim_config.
3048
3049Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3050
3051 * interp.c (sim_kill): Delete.
3052 (sim_create_inferior): Add ABFD argument. Set PC from same.
3053 (sim_load): Move code initializing trap handlers from here.
3054 (sim_open): To here.
3055 (sim_load): Delete, use sim-hload.c.
3056
3057 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3058
3059Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3060
3061 * configure: Regenerated to track ../common/aclocal.m4 changes.
3062 * config.in: Ditto.
3063
3064Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3065
3066 * interp.c (sim_open): Add ABFD argument.
3067 (sim_load): Move call to sim_config from here.
3068 (sim_open): To here. Check return status.
3069
3070Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3071
c906108c
SS		 3072 * gencode.c (build_instruction): Two arg MADD should
3073 not assign result to $0.
72f4393d 3074
c906108c
SS		 3075Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3076
3077 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3078 * sim/mips/configure.in: Regenerate.
3079
3080Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3081
3082 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3083 signed8, unsigned8 et.al. types.
3084
3085 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3086 hosts when selecting subreg.
3087
3088Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3089
3090 * interp.c (sim_engine_run): Reset the ZERO register to zero
3091 regardless of FEATURE_WARN_ZERO.
3092 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3093
3094Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3095
3096 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3097 (SignalException): For BreakPoints ignore any mode bits and just
3098 save the PC.
3099 (SignalException): Always set the CAUSE register.
3100
3101Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3102
3103 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3104 exception has been taken.
3105
3106 * interp.c: Implement the ERET and mt/f sr instructions.
3107
3108Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3109
3110 * interp.c (SignalException): Don't bother restarting an
3111 interrupt.
3112
3113Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3114
3115 * interp.c (SignalException): Really take an interrupt.
3116 (interrupt_event): Only deliver interrupts when enabled.
3117
3118Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3119
3120 * interp.c (sim_info): Only print info when verbose.
3121 (sim_info) Use sim_io_printf for output.
72f4393d 3122
c906108c
SS		 3123Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3124
3125 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3126 mips architectures.
3127
3128Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3129
3130 * interp.c (sim_do_command): Check for common commands if a
3131 simulator specific command fails.
3132
3133Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3134
3135 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3136 and simBE when DEBUG is defined.
3137
3138Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3139
3140 * interp.c (interrupt_event): New function. Pass exception event
3141 onto exception handler.
3142
3143 * configure.in: Check for stdlib.h.
3144 * configure: Regenerate.
3145
3146 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3147 variable declaration.
3148 (build_instruction): Initialize memval1.
3149 (build_instruction): Add UNUSED attribute to byte, bigend,
3150 reverse.
3151 (build_operands): Ditto.
3152
3153 * interp.c: Fix GCC warnings.
3154 (sim_get_quit_code): Delete.
3155
3156 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3157 * Makefile.in: Ditto.
3158 * configure: Re-generate.
72f4393d 3159
c906108c
SS		 3160 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3161
3162Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3163
3164 * interp.c (mips_option_handler): New function parse argumes using
3165 sim-options.
3166 (myname): Replace with STATE_MY_NAME.
3167 (sim_open): Delete check for host endianness - performed by
3168 sim_config.
3169 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3170 (sim_open): Move much of the initialization from here.
3171 (sim_load): To here. After the image has been loaded and
3172 endianness set.
3173 (sim_open): Move ColdReset from here.
3174 (sim_create_inferior): To here.
3175 (sim_open): Make FP check less dependant on host endianness.
3176
3177 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3178 run.
3179 * interp.c (sim_set_callbacks): Delete.
3180
3181 * interp.c (membank, membank_base, membank_size): Replace with
3182 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3183 (sim_open): Remove call to callback->init. gdb/run do this.
3184
3185 * interp.c: Update
3186
3187 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3188
3189 * interp.c (big_endian_p): Delete, replaced by
3190 current_target_byte_order.
3191
3192Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3193
3194 * interp.c (host_read_long, host_read_word, host_swap_word,
3195 host_swap_long): Delete. Using common sim-endian.
3196 (sim_fetch_register, sim_store_register): Use H2T.
3197 (pipeline_ticks): Delete. Handled by sim-events.
3198 (sim_info): Update.
3199 (sim_engine_run): Update.
3200
3201Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3202
3203 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3204 reason from here.
3205 (SignalException): To here. Signal using sim_engine_halt.
3206 (sim_stop_reason): Delete, moved to common.
72f4393d 3207
c906108c
SS		 3208Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3209
3210 * interp.c (sim_open): Add callback argument.
3211 (sim_set_callbacks): Delete SIM_DESC argument.
3212 (sim_size): Ditto.
3213
3214Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3215
3216 * Makefile.in (SIM_OBJS): Add common modules.
3217
3218 * interp.c (sim_set_callbacks): Also set SD callback.
3219 (set_endianness, xfer_*, swap_*): Delete.
3220 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3221 Change to functions using sim-endian macros.
3222 (control_c, sim_stop): Delete, use common version.
3223 (simulate): Convert into.
3224 (sim_engine_run): This function.
3225 (sim_resume): Delete.
72f4393d 3226
c906108c
SS		 3227 * interp.c (simulation): New variable - the simulator object.
3228 (sim_kind): Delete global - merged into simulation.
3229 (sim_load): Cleanup. Move PC assignment from here.
3230 (sim_create_inferior): To here.
3231
3232 * sim-main.h: New file.
3233 * interp.c (sim-main.h): Include.
72f4393d 3234
c906108c
SS		 3235Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3236
3237 * configure: Regenerated to track ../common/aclocal.m4 changes.
3238
3239Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3240
3241 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3242
3243Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3244
72f4393d
L		 3245 * gencode.c (build_instruction): DIV instructions: check
3246 for division by zero and integer overflow before using
c906108c
SS		 3247 host's division operation.
3248
3249Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3250
3251 * Makefile.in (SIM_OBJS): Add sim-load.o.
3252 * interp.c: #include bfd.h.
3253 (target_byte_order): Delete.
3254 (sim_kind, myname, big_endian_p): New static locals.
3255 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3256 after argument parsing. Recognize -E arg, set endianness accordingly.
3257 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3258 load file into simulator. Set PC from bfd.
3259 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3260 (set_endianness): Use big_endian_p instead of target_byte_order.
3261
3262Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3263
3264 * interp.c (sim_size): Delete prototype - conflicts with
3265 definition in remote-sim.h. Correct definition.
3266
3267Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3268
3269 * configure: Regenerated to track ../common/aclocal.m4 changes.
3270 * config.in: Ditto.
3271
3272Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3273
3274 * interp.c (sim_open): New arg `kind'.
3275
3276 * configure: Regenerated to track ../common/aclocal.m4 changes.
3277
3278Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3279
3280 * configure: Regenerated to track ../common/aclocal.m4 changes.
3281
3282Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3283
3284 * interp.c (sim_open): Set optind to 0 before calling getopt.
3285
3286Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3287
3288 * configure: Regenerated to track ../common/aclocal.m4 changes.
3289
3290Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3291
3292 * interp.c : Replace uses of pr_addr with pr_uword64
3293 where the bit length is always 64 independent of SIM_ADDR.
3294 (pr_uword64) : added.
3295
3296Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3297
3298 * configure: Re-generate.
3299
3300Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3301
3302 * configure: Regenerate to track ../common/aclocal.m4 changes.
3303
3304Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3305
3306 * interp.c (sim_open): New SIM_DESC result. Argument is now
3307 in argv form.
3308 (other sim_*): New SIM_DESC argument.
3309
3310Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3311
3312 * interp.c: Fix printing of addresses for non-64-bit targets.
3313 (pr_addr): Add function to print address based on size.
3314
3315Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3316
3317 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3318
3319Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3320
3321 * gencode.c (build_mips16_operands): Correct computation of base
3322 address for extended PC relative instruction.
3323
3324Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3325
3326 * interp.c (mips16_entry): Add support for floating point cases.
3327 (SignalException): Pass floating point cases to mips16_entry.
3328 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3329 registers.
3330 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3331 or fmt_word.
3332 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3333 and then set the state to fmt_uninterpreted.
3334 (COP_SW): Temporarily set the state to fmt_word while calling
3335 ValueFPR.
3336
3337Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3338
3339 * gencode.c (build_instruction): The high order may be set in the
3340 comparison flags at any ISA level, not just ISA 4.
3341
3342Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3343
3344 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3345 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3346 * configure.in: sinclude ../common/aclocal.m4.
3347 * configure: Regenerated.
3348
3349Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3350
3351 * configure: Rebuild after change to aclocal.m4.
3352
3353Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3354
3355 * configure configure.in Makefile.in: Update to new configure
3356 scheme which is more compatible with WinGDB builds.
3357 * configure.in: Improve comment on how to run autoconf.
3358 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3359 * Makefile.in: Use autoconf substitution to install common
3360 makefile fragment.
3361
3362Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3363
3364 * gencode.c (build_instruction): Use BigEndianCPU instead of
3365 ByteSwapMem.
3366
3367Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3368
3369 * interp.c (sim_monitor): Make output to stdout visible in
3370 wingdb's I/O log window.
3371
3372Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3373
3374 * support.h: Undo previous change to SIGTRAP
3375 and SIGQUIT values.
3376
3377Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3378
3379 * interp.c (store_word, load_word): New static functions.
3380 (mips16_entry): New static function.
3381 (SignalException): Look for mips16 entry and exit instructions.
3382 (simulate): Use the correct index when setting fpr_state after
3383 doing a pending move.
3384
3385Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3386
3387 * interp.c: Fix byte-swapping code throughout to work on
3388 both little- and big-endian hosts.
3389
3390Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3391
3392 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3393 with gdb/config/i386/xm-windows.h.
3394
3395Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3396
3397 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3398 that messes up arithmetic shifts.
3399
3400Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3401
3402 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3403 SIGTRAP and SIGQUIT for _WIN32.
3404
3405Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3406
3407 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3408 force a 64 bit multiplication.
3409 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3410 destination register is 0, since that is the default mips16 nop
3411 instruction.
3412
3413Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3414
3415 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3416 (build_endian_shift): Don't check proc64.
3417 (build_instruction): Always set memval to uword64. Cast op2 to
3418 uword64 when shifting it left in memory instructions. Always use
3419 the same code for stores--don't special case proc64.
3420
3421 * gencode.c (build_mips16_operands): Fix base PC value for PC
3422 relative operands.
3423 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3424 jal instruction.
3425 * interp.c (simJALDELAYSLOT): Define.
3426 (JALDELAYSLOT): Define.
3427 (INDELAYSLOT, INJALDELAYSLOT): Define.
3428 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3429
3430Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3431
3432 * interp.c (sim_open): add flush_cache as a PMON routine
3433 (sim_monitor): handle flush_cache by ignoring it
3434
3435Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3436
3437 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3438 BigEndianMem.
3439 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3440 (BigEndianMem): Rename to ByteSwapMem and change sense.
3441 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3442 BigEndianMem references to !ByteSwapMem.
3443 (set_endianness): New function, with prototype.
3444 (sim_open): Call set_endianness.
3445 (sim_info): Use simBE instead of BigEndianMem.
3446 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3447 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3448 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3449 ifdefs, keeping the prototype declaration.
3450 (swap_word): Rewrite correctly.
3451 (ColdReset): Delete references to CONFIG. Delete endianness related
3452 code; moved to set_endianness.
72f4393d 3453
c906108c
SS		 3454Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3455
3456 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3457 * interp.c (CHECKHILO): Define away.
3458 (simSIGINT): New macro.
3459 (membank_size): Increase from 1MB to 2MB.
3460 (control_c): New function.
3461 (sim_resume): Rename parameter signal to signal_number. Add local
3462 variable prev. Call signal before and after simulate.
3463 (sim_stop_reason): Add simSIGINT support.
3464 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3465 functions always.
3466 (sim_warning): Delete call to SignalException. Do call printf_filtered
3467 if logfh is NULL.
3468 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3469 a call to sim_warning.
3470
3471Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3472
3473 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3474 16 bit instructions.
3475
3476Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3477
3478 Add support for mips16 (16 bit MIPS implementation):
3479 * gencode.c (inst_type): Add mips16 instruction encoding types.
3480 (GETDATASIZEINSN): Define.
3481 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3482 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3483 mtlo.
3484 (MIPS16_DECODE): New table, for mips16 instructions.
3485 (bitmap_val): New static function.
3486 (struct mips16_op): Define.
3487 (mips16_op_table): New table, for mips16 operands.
3488 (build_mips16_operands): New static function.
3489 (process_instructions): If PC is odd, decode a mips16
3490 instruction. Break out instruction handling into new
3491 build_instruction function.
3492 (build_instruction): New static function, broken out of
3493 process_instructions. Check modifiers rather than flags for SHIFT
3494 bit count and m[ft]{hi,lo} direction.
3495 (usage): Pass program name to fprintf.
3496 (main): Remove unused variable this_option_optind. Change
3497 ``*loptarg++'' to ``loptarg++''.
3498 (my_strtoul): Parenthesize && within ||.
3499 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3500 (simulate): If PC is odd, fetch a 16 bit instruction, and
3501 increment PC by 2 rather than 4.
3502 * configure.in: Add case for mips16*-*-*.
3503 * configure: Rebuild.
3504
3505Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3506
3507 * interp.c: Allow -t to enable tracing in standalone simulator.
3508 Fix garbage output in trace file and error messages.
3509
3510Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3511
3512 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3513 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3514 * configure.in: Simplify using macros in ../common/aclocal.m4.
3515 * configure: Regenerated.
3516 * tconfig.in: New file.
3517
3518Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3519
3520 * interp.c: Fix bugs in 64-bit port.
3521 Use ansi function declarations for msvc compiler.
3522 Initialize and test file pointer in trace code.
3523 Prevent duplicate definition of LAST_EMED_REGNUM.
3524
3525Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3526
3527 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3528
3529Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3530
3531 * interp.c (SignalException): Check for explicit terminating
3532 breakpoint value.
3533 * gencode.c: Pass instruction value through SignalException()
3534 calls for Trap, Breakpoint and Syscall.
3535
3536Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3537
3538 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3539 only used on those hosts that provide it.
3540 * configure.in: Add sqrt() to list of functions to be checked for.
3541 * config.in: Re-generated.
3542 * configure: Re-generated.
3543
3544Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3545
3546 * gencode.c (process_instructions): Call build_endian_shift when
3547 expanding STORE RIGHT, to fix swr.
3548 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3549 clear the high bits.
3550 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3551 Fix float to int conversions to produce signed values.
3552
3553Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3554
3555 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3556 (process_instructions): Correct handling of nor instruction.
3557 Correct shift count for 32 bit shift instructions. Correct sign
3558 extension for arithmetic shifts to not shift the number of bits in
3559 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3560 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3561 Fix madd.
3562 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3563 It's OK to have a mult follow a mult. What's not OK is to have a
3564 mult follow an mfhi.
3565 (Convert): Comment out incorrect rounding code.
3566
3567Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3568
3569 * interp.c (sim_monitor): Improved monitor printf
3570 simulation. Tidied up simulator warnings, and added "--log" option
3571 for directing warning message output.
3572 * gencode.c: Use sim_warning() rather than WARNING macro.
3573
3574Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3575
3576 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3577 getopt1.o, rather than on gencode.c. Link objects together.
3578 Don't link against -liberty.
3579 (gencode.o, getopt.o, getopt1.o): New targets.
3580 * gencode.c: Include <ctype.h> and "ansidecl.h".
3581 (AND): Undefine after including "ansidecl.h".
3582 (ULONG_MAX): Define if not defined.
3583 (OP_*): Don't define macros; now defined in opcode/mips.h.
3584 (main): Call my_strtoul rather than strtoul.
3585 (my_strtoul): New static function.
3586
3587Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3588
3589 * gencode.c (process_instructions): Generate word64 and uword64
3590 instead of `long long' and `unsigned long long' data types.
3591 * interp.c: #include sysdep.h to get signals, and define default
3592 for SIGBUS.
3593 * (Convert): Work around for Visual-C++ compiler bug with type
3594 conversion.
3595 * support.h: Make things compile under Visual-C++ by using
3596 __int64 instead of `long long'. Change many refs to long long
3597 into word64/uword64 typedefs.
3598
3599Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3600
72f4393d
L		 3601 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3602 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3603 (docdir): Removed.
3604 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3605 (AC_PROG_INSTALL): Added.
c906108c 3606 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3607 * configure: Rebuilt.
3608
c906108c
SS		 3609Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3610
3611 * configure.in: Define @SIMCONF@ depending on mips target.
3612 * configure: Rebuild.
3613 * Makefile.in (run): Add @SIMCONF@ to control simulator
3614 construction.
3615 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3616 * interp.c: Remove some debugging, provide more detailed error
3617 messages, update memory accesses to use LOADDRMASK.
72f4393d 3618
c906108c
SS		 3619Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3620
3621 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3622 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3623 stamp-h.
3624 * configure: Rebuild.
3625 * config.in: New file, generated by autoheader.
3626 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3627 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3628 HAVE_ANINT and HAVE_AINT, as appropriate.
3629 * Makefile.in (run): Use @LIBS@ rather than -lm.
3630 (interp.o): Depend upon config.h.
3631 (Makefile): Just rebuild Makefile.
3632 (clean): Remove stamp-h.
3633 (mostlyclean): Make the same as clean, not as distclean.
3634 (config.h, stamp-h): New targets.
3635
3636Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3637
3638 * interp.c (ColdReset): Fix boolean test. Make all simulator
3639 globals static.
3640
3641Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3642
3643 * interp.c (xfer_direct_word, xfer_direct_long,
3644 swap_direct_word, swap_direct_long, xfer_big_word,
3645 xfer_big_long, xfer_little_word, xfer_little_long,
3646 swap_word,swap_long): Added.
3647 * interp.c (ColdReset): Provide function indirection to
3648 host<->simulated_target transfer routines.
3649 * interp.c (sim_store_register, sim_fetch_register): Updated to
3650 make use of indirected transfer routines.
3651
3652Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3653
3654 * gencode.c (process_instructions): Ensure FP ABS instruction
3655 recognised.
3656 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3657 system call support.
3658
3659Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3660
3661 * interp.c (sim_do_command): Complain if callback structure not
3662 initialised.
3663
3664Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3665
3666 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3667 support for Sun hosts.
3668 * Makefile.in (gencode): Ensure the host compiler and libraries
3669 used for cross-hosted build.
3670
3671Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3672
3673 * interp.c, gencode.c: Some more (TODO) tidying.
3674
3675Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3676
3677 * gencode.c, interp.c: Replaced explicit long long references with
3678 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3679 * support.h (SET64LO, SET64HI): Macros added.
3680
3681Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3682
3683 * configure: Regenerate with autoconf 2.7.
3684
3685Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3686
3687 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3688 * support.h: Remove superfluous "1" from #if.
3689 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3690
3691Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3692
3693 * interp.c (StoreFPR): Control UndefinedResult() call on
3694 WARN_RESULT manifest.
3695
3696Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3697
3698 * gencode.c: Tidied instruction decoding, and added FP instruction
3699 support.
3700
3701 * interp.c: Added dineroIII, and BSD profiling support. Also
3702 run-time FP handling.
3703
3704Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3705
3706 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3707 gencode.c, interp.c, support.h: created.
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