sim: rx: cast bfd_vma when printing
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
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9d903352
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12021-04-23 Mike Frysinger <vapier@gentoo.org>
2
3 * configure.ac (hw_enabled): Delete.
4 (SIM_AC_OPTION_HARDWARE): Delete first two args.
5 * configure: Regenerate.
6
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72021-04-22 Tom Tromey <tom@tromey.com>
8
9 * configure, config.in: Rebuild.
10
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112021-04-22 Tom Tromey <tom@tromey.com>
12
13 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
14 Remove.
15 (SIM_EXTRA_DEPS): New variable.
16
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172021-04-22 Tom Tromey <tom@tromey.com>
18
19 * configure: Rebuild.
20
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212021-04-21 Mike Frysinger <vapier@gentoo.org>
22
23 * aclocal.m4: Regenerate.
24
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252021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
26
27 * configure: Regenerate.
28
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292021-04-18 Mike Frysinger <vapier@gentoo.org>
30
31 * configure: Regenerate.
32
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332021-04-12 Mike Frysinger <vapier@gentoo.org>
34
35 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
36
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372021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
38
39 * Makefile.in: Set ASAN_OPTIONS when running igen.
40
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412021-04-04 Steve Ellcey <sellcey@mips.com>
42 Faraz Shahbazker <fshahbazker@wavecomp.com>
43
44 * interp.c (sim_monitor): Add switch entries for unlink (13),
45 lseek (14), and stat (15).
46
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472021-04-02 Mike Frysinger <vapier@gentoo.org>
48
49 * Makefile.in (../igen/igen): Delete rule.
50 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
51
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522021-04-02 Mike Frysinger <vapier@gentoo.org>
53
54 * aclocal.m4, configure: Regenerate.
55
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562021-02-28 Mike Frysinger <vapier@gentoo.org>
57
58 * configure: Regenerate.
59
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602021-02-27 Mike Frysinger <vapier@gentoo.org>
61
62 * Makefile.in (SIM_EXTRA_ALL): Delete.
63 (all): New target.
64
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652021-02-21 Mike Frysinger <vapier@gentoo.org>
66
67 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
68 * aclocal.m4, configure: Regenerate.
69
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702021-02-13 Mike Frysinger <vapier@gentoo.org>
71
72 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
73 * aclocal.m4, configure: Regenerate.
74
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752021-02-06 Mike Frysinger <vapier@gentoo.org>
76
77 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
78
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792021-02-06 Mike Frysinger <vapier@gentoo.org>
80
81 * configure: Regenerate.
82
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832021-01-30 Mike Frysinger <vapier@gentoo.org>
84
85 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
86
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872021-01-11 Mike Frysinger <vapier@gentoo.org>
88
89 * config.in, configure: Regenerate.
90 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
91 and strings.h include.
92
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932021-01-09 Mike Frysinger <vapier@gentoo.org>
94
95 * configure: Regenerate.
96
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972021-01-09 Mike Frysinger <vapier@gentoo.org>
98
99 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
100 * configure: Regenerate.
101
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1022021-01-08 Mike Frysinger <vapier@gentoo.org>
103
104 * configure: Regenerate.
105
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1062021-01-04 Mike Frysinger <vapier@gentoo.org>
107
108 * configure: Regenerate.
109
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1102020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
111
112 * sim-main.c: Include <stdlib.h>.
113
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1142020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
115
116 * cp1.c: Include <stdlib.h>.
117
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1182020-07-29 Simon Marchi <simon.marchi@efficios.com>
119
120 * configure: Re-generate.
121
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1222017-09-06 John Baldwin <jhb@FreeBSD.org>
123
124 * configure: Regenerate.
125
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1262016-11-11 Mike Frysinger <vapier@gentoo.org>
127
6cb2202b 128 PR sim/20808
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129 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
130 and SD to sd.
131
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1322016-11-11 Mike Frysinger <vapier@gentoo.org>
133
6cb2202b 134 PR sim/20809
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135 * mips.igen (check_u64): Enable for `r3900'.
136
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1372016-02-05 Mike Frysinger <vapier@gentoo.org>
138
139 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
140 STATE_PROG_BFD (sd).
141 * configure: Regenerate.
142
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1432016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
144 Maciej W. Rozycki <macro@imgtec.com>
145
146 PR sim/19441
147 * micromips.igen (delayslot_micromips): Enable for `micromips32',
148 `micromips64' and `micromipsdsp' only.
149 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
150 (do_micromips_jalr, do_micromips_jal): Likewise.
151 (compute_movep_src_reg): Likewise.
152 (compute_andi16_imm): Likewise.
153 (convert_fmt_micromips): Likewise.
154 (convert_fmt_micromips_cvt_d): Likewise.
155 (convert_fmt_micromips_cvt_s): Likewise.
156 (FMT_MICROMIPS): Likewise.
157 (FMT_MICROMIPS_CVT_D): Likewise.
158 (FMT_MICROMIPS_CVT_S): Likewise.
159
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1602016-01-12 Mike Frysinger <vapier@gentoo.org>
161
162 * interp.c: Include elf-bfd.h.
163 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
164 ELFCLASS32.
165
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1662016-01-10 Mike Frysinger <vapier@gentoo.org>
167
168 * config.in, configure: Regenerate.
169
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1702016-01-10 Mike Frysinger <vapier@gentoo.org>
171
172 * configure: Regenerate.
173
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1742016-01-10 Mike Frysinger <vapier@gentoo.org>
175
176 * configure: Regenerate.
177
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1782016-01-10 Mike Frysinger <vapier@gentoo.org>
179
180 * configure: Regenerate.
181
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1822016-01-10 Mike Frysinger <vapier@gentoo.org>
183
184 * configure: Regenerate.
185
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1862016-01-10 Mike Frysinger <vapier@gentoo.org>
187
188 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
189 * configure: Regenerate.
190
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1912016-01-10 Mike Frysinger <vapier@gentoo.org>
192
193 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
194 * configure: Regenerate.
195
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1962016-01-10 Mike Frysinger <vapier@gentoo.org>
197
198 * configure: Regenerate.
199
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2002016-01-10 Mike Frysinger <vapier@gentoo.org>
201
202 * configure: Regenerate.
203
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2042016-01-09 Mike Frysinger <vapier@gentoo.org>
205
206 * config.in, configure: Regenerate.
207
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2082016-01-06 Mike Frysinger <vapier@gentoo.org>
209
210 * interp.c (sim_open): Mark argv const.
211 (sim_create_inferior): Mark argv and env const.
212
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2132016-01-04 Mike Frysinger <vapier@gentoo.org>
214
215 * configure: Regenerate.
216
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2172016-01-03 Mike Frysinger <vapier@gentoo.org>
218
219 * interp.c (sim_open): Update sim_parse_args comment.
220
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2212016-01-03 Mike Frysinger <vapier@gentoo.org>
222
223 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
224 * configure: Regenerate.
225
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2262016-01-02 Mike Frysinger <vapier@gentoo.org>
227
228 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
229 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
230 * configure: Regenerate.
231 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
232
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2332016-01-02 Mike Frysinger <vapier@gentoo.org>
234
235 * dv-tx3904cpu.c (CPU, SD): Delete.
236
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2372015-12-30 Mike Frysinger <vapier@gentoo.org>
238
239 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
240 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
241 (sim_store_register): Rename to ...
242 (mips_reg_store): ... this. Delete local cpu var.
243 Update sim_io_eprintf calls.
244 (sim_fetch_register): Rename to ...
245 (mips_reg_fetch): ... this. Delete local cpu var.
246 Update sim_io_eprintf calls.
247
5e744ef8
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2482015-12-27 Mike Frysinger <vapier@gentoo.org>
249
250 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
251
1b393626
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2522015-12-26 Mike Frysinger <vapier@gentoo.org>
253
254 * config.in, configure: Regenerate.
255
26f8bf63
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2562015-12-26 Mike Frysinger <vapier@gentoo.org>
257
258 * interp.c (sim_write, sim_read): Delete.
259 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
260 (load_word): Likewise.
261 * micromips.igen (cache): Likewise.
262 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
263 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
264 do_store_left, do_store_right, do_load_double, do_store_double):
265 Likewise.
266 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
267 (do_prefx): Likewise.
268 * sim-main.c (address_translation, prefetch): Delete.
269 (ifetch32, ifetch16): Delete call to AddressTranslation and set
270 paddr=vaddr.
271 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
272 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
273 (LoadMemory, StoreMemory): Delete CCA arg.
274
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2752015-12-24 Mike Frysinger <vapier@gentoo.org>
276
277 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
278 * configure: Regenerated.
279
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2802015-12-24 Mike Frysinger <vapier@gentoo.org>
281
282 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
283 * tconfig.h: Delete.
284
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2852015-12-24 Mike Frysinger <vapier@gentoo.org>
286
287 * tconfig.h (SIM_HANDLES_LMA): Delete.
288
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2892015-12-24 Mike Frysinger <vapier@gentoo.org>
290
291 * sim-main.h (WITH_WATCHPOINTS): Delete.
292
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2932015-12-24 Mike Frysinger <vapier@gentoo.org>
294
295 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
296
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2972015-12-24 Mike Frysinger <vapier@gentoo.org>
298
299 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
300
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3012015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
302
303 * micromips.igen (process_isa_mode): Fix left shift of negative
304 value.
305
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3062015-11-17 Mike Frysinger <vapier@gentoo.org>
307
308 * sim-main.h (WITH_MODULO_MEMORY): Delete.
309
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3102015-11-15 Mike Frysinger <vapier@gentoo.org>
311
312 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
313
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3142015-11-14 Mike Frysinger <vapier@gentoo.org>
315
316 * interp.c (sim_close): Rename to ...
317 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
318 sim_io_shutdown.
319 * sim-main.h (mips_sim_close): Declare.
320 (SIM_CLOSE_HOOK): Define.
321
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3222015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
323 Ali Lown <ali.lown@imgtec.com>
324
325 * Makefile.in (tmp-micromips): New rule.
326 (tmp-mach-multi): Add support for micromips.
327 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
328 that works for both mips64 and micromips64.
329 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
330 micromips32.
331 Add build support for micromips.
332 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
333 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
334 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
335 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
336 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
337 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
338 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
339 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
340 Refactored instruction code to use these functions.
341 * dsp2.igen: Refactored instruction code to use the new functions.
342 * interp.c (decode_coproc): Refactored to work with any instruction
343 encoding.
344 (isa_mode): New variable
345 (RSVD_INSTRUCTION): Changed to 0x00000039.
346 * m16.igen (BREAK16): Refactored instruction to use do_break16.
347 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
348 * micromips.dc: New file.
349 * micromips.igen: New file.
350 * micromips16.dc: New file.
351 * micromipsdsp.igen: New file.
352 * micromipsrun.c: New file.
353 * mips.igen (do_swc1): Changed to work with any instruction encoding.
354 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
355 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
356 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
357 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
358 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
359 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
360 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
361 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
362 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
363 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
364 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
365 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
366 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
367 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
368 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
369 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
370 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
371 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
372 instructions.
373 Refactored instruction code to use these functions.
374 (RSVD): Changed to use new reserved instruction.
375 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
376 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
377 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
378 do_store_double): Added micromips32 and micromips64 models.
379 Added include for micromips.igen and micromipsdsp.igen
380 Add micromips32 and micromips64 models.
381 (DecodeCoproc): Updated to use new macro definition.
382 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
383 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
384 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
385 Refactored instruction code to use these functions.
386 * sim-main.h (CP0_operation): New enum.
387 (DecodeCoproc): Updated macro.
388 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
389 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
390 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
391 ISA_MODE_MICROMIPS): New defines.
392 (sim_state): Add isa_mode field.
393
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3942015-06-23 Mike Frysinger <vapier@gentoo.org>
395
396 * configure: Regenerate.
397
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3982015-06-12 Mike Frysinger <vapier@gentoo.org>
399
400 * configure.ac: Change configure.in to configure.ac.
401 * configure: Regenerate.
402
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4032015-06-12 Mike Frysinger <vapier@gentoo.org>
404
405 * configure: Regenerate.
406
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4072015-06-12 Mike Frysinger <vapier@gentoo.org>
408
409 * interp.c [TRACE]: Delete.
410 (TRACE): Change to WITH_TRACE_ANY_P.
411 [!WITH_TRACE_ANY_P] (open_trace): Define.
412 (mips_option_handler, open_trace, sim_close, dotrace):
413 Change defined(TRACE) to WITH_TRACE_ANY_P.
414 (sim_open): Delete TRACE ifdef check.
415 * sim-main.c (load_memory): Delete TRACE ifdef check.
416 (store_memory): Likewise.
417 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
418 [!WITH_TRACE_ANY_P] (dotrace): Define.
419
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4202015-04-18 Mike Frysinger <vapier@gentoo.org>
421
422 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
423 comments.
424
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4252015-04-18 Mike Frysinger <vapier@gentoo.org>
426
427 * sim-main.h (SIM_CPU): Delete.
428
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4292015-04-18 Mike Frysinger <vapier@gentoo.org>
430
431 * sim-main.h (sim_cia): Delete.
432
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4332015-04-17 Mike Frysinger <vapier@gentoo.org>
434
435 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
436 PU_PC_GET.
437 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
438 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
439 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
440 CIA_SET to CPU_PC_SET.
441 * sim-main.h (CIA_GET, CIA_SET): Delete.
442
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4432015-04-15 Mike Frysinger <vapier@gentoo.org>
444
445 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
446 * sim-main.h (STATE_CPU): Delete.
447
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4482015-04-13 Mike Frysinger <vapier@gentoo.org>
449
450 * configure: Regenerate.
451
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4522015-04-13 Mike Frysinger <vapier@gentoo.org>
453
454 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
455 * interp.c (mips_pc_get, mips_pc_set): New functions.
456 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
457 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
458 (sim_pc_get): Delete.
459 * sim-main.h (SIM_CPU): Define.
460 (struct sim_state): Change cpu to an array of pointers.
461 (STATE_CPU): Drop &.
462
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4632015-04-13 Mike Frysinger <vapier@gentoo.org>
464
465 * interp.c (mips_option_handler, open_trace, sim_close,
466 sim_write, sim_read, sim_store_register, sim_fetch_register,
467 sim_create_inferior, pr_addr, pr_uword64): Convert old style
468 prototypes.
469 (sim_open): Convert old style prototype. Change casts with
470 sim_write to unsigned char *.
471 (fetch_str): Change null to unsigned char, and change cast to
472 unsigned char *.
473 (sim_monitor): Change c & ch to unsigned char. Change cast to
474 unsigned char *.
475
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4762015-04-12 Mike Frysinger <vapier@gentoo.org>
477
478 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
479
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4802015-04-06 Mike Frysinger <vapier@gentoo.org>
481
482 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
483
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4842015-04-01 Mike Frysinger <vapier@gentoo.org>
485
486 * tconfig.h (SIM_HAVE_PROFILE): Delete.
487
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4882015-03-31 Mike Frysinger <vapier@gentoo.org>
489
490 * config.in, configure: Regenerate.
491
05f53ed6
MF
4922015-03-24 Mike Frysinger <vapier@gentoo.org>
493
494 * interp.c (sim_pc_get): New function.
495
c0931f26
MF
4962015-03-24 Mike Frysinger <vapier@gentoo.org>
497
498 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
499 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
500
30452bbe
MF
5012015-03-24 Mike Frysinger <vapier@gentoo.org>
502
503 * configure: Regenerate.
504
64dd13df
MF
5052015-03-23 Mike Frysinger <vapier@gentoo.org>
506
507 * configure: Regenerate.
508
49cd1634
MF
5092015-03-23 Mike Frysinger <vapier@gentoo.org>
510
511 * configure: Regenerate.
512 * configure.ac (mips_extra_objs): Delete.
513 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
514 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
515
3649cb06
MF
5162015-03-23 Mike Frysinger <vapier@gentoo.org>
517
518 * configure: Regenerate.
519 * configure.ac: Delete sim_hw checks for dv-sockser.
520
ae7d0cac
MF
5212015-03-16 Mike Frysinger <vapier@gentoo.org>
522
523 * config.in, configure: Regenerate.
524 * tconfig.in: Rename file ...
525 * tconfig.h: ... here.
526
8406bb59
MF
5272015-03-15 Mike Frysinger <vapier@gentoo.org>
528
529 * tconfig.in: Delete includes.
530 [HAVE_DV_SOCKSER]: Delete.
531
465fb143
MF
5322015-03-14 Mike Frysinger <vapier@gentoo.org>
533
534 * Makefile.in (SIM_RUN_OBJS): Delete.
535
5cddc23a
MF
5362015-03-14 Mike Frysinger <vapier@gentoo.org>
537
538 * configure.ac (AC_CHECK_HEADERS): Delete.
539 * aclocal.m4, configure: Regenerate.
540
2974be62
AM
5412014-08-19 Alan Modra <amodra@gmail.com>
542
543 * configure: Regenerate.
544
faa743bb
RM
5452014-08-15 Roland McGrath <mcgrathr@google.com>
546
547 * configure: Regenerate.
548 * config.in: Regenerate.
549
1a8a700e
MF
5502014-03-04 Mike Frysinger <vapier@gentoo.org>
551
552 * configure: Regenerate.
553
bf3d9781
AM
5542013-09-23 Alan Modra <amodra@gmail.com>
555
556 * configure: Regenerate.
557
31e6ad7d
MF
5582013-06-03 Mike Frysinger <vapier@gentoo.org>
559
560 * aclocal.m4, configure: Regenerate.
561
d3685d60
TT
5622013-05-10 Freddie Chopin <freddie_chopin@op.pl>
563
564 * configure: Rebuild.
565
1517bd27
MF
5662013-03-26 Mike Frysinger <vapier@gentoo.org>
567
568 * configure: Regenerate.
569
3be31516
JS
5702013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
571
572 * configure.ac: Address use of dv-sockser.o.
573 * tconfig.in: Conditionalize use of dv_sockser_install.
574 * configure: Regenerated.
575 * config.in: Regenerated.
576
37cb8f8e
SE
5772012-10-04 Chao-ying Fu <fu@mips.com>
578 Steve Ellcey <sellcey@mips.com>
579
580 * mips/mips3264r2.igen (rdhwr): New.
581
87c8644f
JS
5822012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
583
584 * configure.ac: Always link against dv-sockser.o.
585 * configure: Regenerate.
586
5f3ef9d0
JB
5872012-06-15 Joel Brobecker <brobecker@adacore.com>
588
589 * config.in, configure: Regenerate.
590
a6ff997c
NC
5912012-05-18 Nick Clifton <nickc@redhat.com>
592
593 PR 14072
594 * interp.c: Include config.h before system header files.
595
2232061b
MF
5962012-03-24 Mike Frysinger <vapier@gentoo.org>
597
598 * aclocal.m4, config.in, configure: Regenerate.
599
db2e4d67
MF
6002011-12-03 Mike Frysinger <vapier@gentoo.org>
601
602 * aclocal.m4: New file.
603 * configure: Regenerate.
604
4399a56b
MF
6052011-10-19 Mike Frysinger <vapier@gentoo.org>
606
607 * configure: Regenerate after common/acinclude.m4 update.
608
9c082ca8
MF
6092011-10-17 Mike Frysinger <vapier@gentoo.org>
610
611 * configure.ac: Change include to common/acinclude.m4.
612
6ffe910a
MF
6132011-10-17 Mike Frysinger <vapier@gentoo.org>
614
615 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
616 call. Replace common.m4 include with SIM_AC_COMMON.
617 * configure: Regenerate.
618
31b28250
HPN
6192011-07-08 Hans-Peter Nilsson <hp@axis.com>
620
3faa01e3
HPN
621 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
622 $(SIM_EXTRA_DEPS).
623 (tmp-mach-multi): Exit early when igen fails.
31b28250 624
2419798b
MF
6252011-07-05 Mike Frysinger <vapier@gentoo.org>
626
627 * interp.c (sim_do_command): Delete.
628
d79fe0d6
MF
6292011-02-14 Mike Frysinger <vapier@gentoo.org>
630
631 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
632 (tx3904sio_fifo_reset): Likewise.
633 * interp.c (sim_monitor): Likewise.
634
5558e7e6
MF
6352010-04-14 Mike Frysinger <vapier@gentoo.org>
636
637 * interp.c (sim_write): Add const to buffer arg.
638
35aafff4
JB
6392010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
640
641 * interp.c: Don't include sysdep.h
642
3725885a
RW
6432010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
644
645 * configure: Regenerate.
646
d6416cdc
RW
6472009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
648
81ecdfbb
RW
649 * config.in: Regenerate.
650 * configure: Likewise.
651
d6416cdc
RW
652 * configure: Regenerate.
653
b5bd9624
HPN
6542008-07-11 Hans-Peter Nilsson <hp@axis.com>
655
656 * configure: Regenerate to track ../common/common.m4 changes.
657 * config.in: Ditto.
658
6efef468 6592008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L
660 Daniel Jacobowitz <dan@codesourcery.com>
661 Joseph Myers <joseph@codesourcery.com>
6efef468
JM
662
663 * configure: Regenerate.
664
60dc88db
RS
6652007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
666
667 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
668 that unconditionally allows fmt_ps.
669 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
670 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
671 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
672 filter from 64,f to 32,f.
673 (PREFX): Change filter from 64 to 32.
674 (LDXC1, LUXC1): Provide separate mips32r2 implementations
675 that use do_load_double instead of do_load. Make both LUXC1
676 versions unpredictable if SizeFGR () != 64.
677 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
678 instead of do_store. Remove unused variable. Make both SUXC1
679 versions unpredictable if SizeFGR () != 64.
680
599ca73e
RS
6812007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
682
683 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
684 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
685 shifts for that case.
686
2525df03
NC
6872007-09-04 Nick Clifton <nickc@redhat.com>
688
689 * interp.c (options enum): Add OPTION_INFO_MEMORY.
690 (display_mem_info): New static variable.
691 (mips_option_handler): Handle OPTION_INFO_MEMORY.
692 (mips_options): Add info-memory and memory-info.
693 (sim_open): After processing the command line and board
694 specification, check display_mem_info. If it is set then
695 call the real handler for the --memory-info command line
696 switch.
697
35ee6e1e
JB
6982007-08-24 Joel Brobecker <brobecker@adacore.com>
699
700 * configure.ac: Change license of multi-run.c to GPL version 3.
701 * configure: Regenerate.
702
d5fb0879
RS
7032007-06-28 Richard Sandiford <richard@codesourcery.com>
704
705 * configure.ac, configure: Revert last patch.
706
2a2ce21b
RS
7072007-06-26 Richard Sandiford <richard@codesourcery.com>
708
709 * configure.ac (sim_mipsisa3264_configs): New variable.
710 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
711 every configuration support all four targets, using the triplet to
712 determine the default.
713 * configure: Regenerate.
714
efdcccc9
RS
7152007-06-25 Richard Sandiford <richard@codesourcery.com>
716
0a7692b2 717 * Makefile.in (m16run.o): New rule.
efdcccc9 718
f532a356
TS
7192007-05-15 Thiemo Seufer <ths@mips.com>
720
721 * mips3264r2.igen (DSHD): Fix compile warning.
722
bfe9c90b
TS
7232007-05-14 Thiemo Seufer <ths@mips.com>
724
725 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
726 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
727 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
728 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
729 for mips32r2.
730
53f4826b
TS
7312007-03-01 Thiemo Seufer <ths@mips.com>
732
733 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
734 and mips64.
735
8bf3ddc8
TS
7362007-02-20 Thiemo Seufer <ths@mips.com>
737
738 * dsp.igen: Update copyright notice.
739 * dsp2.igen: Fix copyright notice.
740
8b082fb1 7412007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 742 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS
743
744 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
745 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
746 Add dsp2 to sim_igen_machine.
747 * configure: Regenerate.
748 * dsp.igen (do_ph_op): Add MUL support when op = 2.
749 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
750 (mulq_rs.ph): Use do_ph_mulq.
751 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
752 * mips.igen: Add dsp2 model and include dsp2.igen.
753 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
754 for *mips32r2, *mips64r2, *dsp.
755 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
756 for *mips32r2, *mips64r2, *dsp2.
757 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
758
b1004875 7592007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 760 Nigel Stephens <nigel@mips.com>
b1004875
TS
761
762 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
763 jumps with hazard barrier.
764
f8df4c77 7652007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 766 Nigel Stephens <nigel@mips.com>
f8df4c77
TS
767
768 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
769 after each call to sim_io_write.
770
b1004875 7712007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 772 Nigel Stephens <nigel@mips.com>
b1004875
TS
773
774 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
775 supported by this simulator.
07802d98
TS
776 (decode_coproc): Recognise additional CP0 Config registers
777 correctly.
778
14fb6c5a 7792007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L
780 Nigel Stephens <nigel@mips.com>
781 David Ung <davidu@mips.com>
14fb6c5a
TS
782
783 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
784 uninterpreted formats. If fmt is one of the uninterpreted types
785 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
786 fmt_word, and fmt_uninterpreted_64 like fmt_long.
787 (store_fpr): When writing an invalid odd register, set the
788 matching even register to fmt_unknown, not the following register.
789 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
790 the the memory window at offset 0 set by --memory-size command
791 line option.
792 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
793 point register.
794 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
795 register.
796 (sim_monitor): When returning the memory size to the MIPS
797 application, use the value in STATE_MEM_SIZE, not an arbitrary
798 hardcoded value.
799 (cop_lw): Don' mess around with FPR_STATE, just pass
800 fmt_uninterpreted_32 to StoreFPR.
801 (cop_sw): Similarly.
802 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
803 (cop_sd): Similarly.
804 * mips.igen (not_word_value): Single version for mips32, mips64
805 and mips16.
806
c8847145 8072007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 808 Nigel Stephens <nigel@mips.com>
c8847145
TS
809
810 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
811 MBytes.
812
4b5d35ee
TS
8132007-02-17 Thiemo Seufer <ths@mips.com>
814
815 * configure.ac (mips*-sde-elf*): Move in front of generic machine
816 configuration.
817 * configure: Regenerate.
818
3669427c
TS
8192007-02-17 Thiemo Seufer <ths@mips.com>
820
821 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
822 Add mdmx to sim_igen_machine.
823 (mipsisa64*-*-*): Likewise. Remove dsp.
824 (mipsisa32*-*-*): Remove dsp.
825 * configure: Regenerate.
826
109ad085
TS
8272007-02-13 Thiemo Seufer <ths@mips.com>
828
829 * configure.ac: Add mips*-sde-elf* target.
830 * configure: Regenerate.
831
921d7ad3
HPN
8322006-12-21 Hans-Peter Nilsson <hp@axis.com>
833
834 * acconfig.h: Remove.
835 * config.in, configure: Regenerate.
836
02f97da7
TS
8372006-11-07 Thiemo Seufer <ths@mips.com>
838
839 * dsp.igen (do_w_op): Fix compiler warning.
840
2d2733fc 8412006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 842 David Ung <davidu@mips.com>
2d2733fc
TS
843
844 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
845 sim_igen_machine.
846 * configure: Regenerate.
847 * mips.igen (model): Add smartmips.
848 (MADDU): Increment ACX if carry.
849 (do_mult): Clear ACX.
850 (ROR,RORV): Add smartmips.
72f4393d 851 (include): Include smartmips.igen.
2d2733fc
TS
852 * sim-main.h (ACX): Set to REGISTERS[89].
853 * smartmips.igen: New file.
854
d85c3a10 8552006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 856 David Ung <davidu@mips.com>
d85c3a10
TS
857
858 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
859 mips3264r2.igen. Add missing dependency rules.
860 * m16e.igen: Support for mips16e save/restore instructions.
861
e85e3205
RE
8622006-06-13 Richard Earnshaw <rearnsha@arm.com>
863
864 * configure: Regenerated.
865
2f0122dc
DJ
8662006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
867
868 * configure: Regenerated.
869
20e95c23
DJ
8702006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
871
872 * configure: Regenerated.
873
69088b17
CF
8742006-05-15 Chao-ying Fu <fu@mips.com>
875
876 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
877
0275de4e
NC
8782006-04-18 Nick Clifton <nickc@redhat.com>
879
880 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
881 statement.
882
b3a3ffef
HPN
8832006-03-29 Hans-Peter Nilsson <hp@axis.com>
884
885 * configure: Regenerate.
886
40a5538e
CF
8872005-12-14 Chao-ying Fu <fu@mips.com>
888
889 * Makefile.in (SIM_OBJS): Add dsp.o.
890 (dsp.o): New dependency.
891 (IGEN_INCLUDE): Add dsp.igen.
892 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
893 mipsisa64*-*-*): Add dsp to sim_igen_machine.
894 * configure: Regenerate.
895 * mips.igen: Add dsp model and include dsp.igen.
896 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
897 because these instructions are extended in DSP ASE.
898 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
899 adding 6 DSP accumulator registers and 1 DSP control register.
900 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
901 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
902 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
903 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
904 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
905 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
906 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
907 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
908 DSPCR_CCOND_SMASK): New define.
909 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
910 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
911
21d14896
ILT
9122005-07-08 Ian Lance Taylor <ian@airs.com>
913
914 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
915
b16d63da 9162005-06-16 David Ung <davidu@mips.com>
72f4393d
L
917 Nigel Stephens <nigel@mips.com>
918
919 * mips.igen: New mips16e model and include m16e.igen.
920 (check_u64): Add mips16e tag.
921 * m16e.igen: New file for MIPS16e instructions.
922 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
923 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
924 models.
925 * configure: Regenerate.
b16d63da 926
e70cb6cd 9272005-05-26 David Ung <davidu@mips.com>
72f4393d 928
e70cb6cd
CD
929 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
930 tags to all instructions which are applicable to the new ISAs.
931 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
932 vr.igen.
933 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 934 instructions.
e70cb6cd
CD
935 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
936 to mips.igen.
937 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
938 * configure: Regenerate.
72f4393d 939
2b193c4a
MK
9402005-03-23 Mark Kettenis <kettenis@gnu.org>
941
942 * configure: Regenerate.
943
35695fd6
AC
9442005-01-14 Andrew Cagney <cagney@gnu.org>
945
946 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
947 explicit call to AC_CONFIG_HEADER.
948 * configure: Regenerate.
949
f0569246
AC
9502005-01-12 Andrew Cagney <cagney@gnu.org>
951
952 * configure.ac: Update to use ../common/common.m4.
953 * configure: Re-generate.
954
38f48d72
AC
9552005-01-11 Andrew Cagney <cagney@localhost.localdomain>
956
957 * configure: Regenerated to track ../common/aclocal.m4 changes.
958
b7026657
AC
9592005-01-07 Andrew Cagney <cagney@gnu.org>
960
961 * configure.ac: Rename configure.in, require autoconf 2.59.
962 * configure: Re-generate.
963
379832de
HPN
9642004-12-08 Hans-Peter Nilsson <hp@axis.com>
965
966 * configure: Regenerate for ../common/aclocal.m4 update.
967
cd62154c 9682004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 969
cd62154c
AC
970 Committed by Andrew Cagney.
971 * m16.igen (CMP, CMPI): Fix assembler.
972
e5da76ec
CD
9732004-08-18 Chris Demetriou <cgd@broadcom.com>
974
975 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
976 * configure: Regenerate.
977
139181c8
CD
9782004-06-25 Chris Demetriou <cgd@broadcom.com>
979
980 * configure.in (sim_m16_machine): Include mipsIII.
981 * configure: Regenerate.
982
1a27f959
CD
9832004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
984
72f4393d 985 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD
986 from COP0_BADVADDR.
987 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
988
5dbb7b5a
CD
9892004-04-10 Chris Demetriou <cgd@broadcom.com>
990
991 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
992
14234056
CD
9932004-04-09 Chris Demetriou <cgd@broadcom.com>
994
995 * mips.igen (check_fmt): Remove.
996 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
997 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
998 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
999 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1000 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1001 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1002 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1003 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1004 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1005 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1006
c6f9085c
CD
10072004-04-09 Chris Demetriou <cgd@broadcom.com>
1008
1009 * sb1.igen (check_sbx): New function.
1010 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1011
11d66e66 10122004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS
1013 Richard Sandiford <rsandifo@redhat.com>
1014
1015 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1016 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1017 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1018 separate implementations for mipsIV and mipsV. Use new macros to
1019 determine whether the restrictions apply.
1020
b3208fb8
CD
10212004-01-19 Chris Demetriou <cgd@broadcom.com>
1022
1023 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1024 (check_mult_hilo): Improve comments.
1025 (check_div_hilo): Likewise. Also, fork off a new version
1026 to handle mips32/mips64 (since there are no hazards to check
1027 in MIPS32/MIPS64).
1028
9a1d84fb
CD
10292003-06-17 Richard Sandiford <rsandifo@redhat.com>
1030
1031 * mips.igen (do_dmultx): Fix check for negative operands.
1032
ae451ac6
ILT
10332003-05-16 Ian Lance Taylor <ian@airs.com>
1034
1035 * Makefile.in (SHELL): Make sure this is defined.
1036 (various): Use $(SHELL) whenever we invoke move-if-change.
1037
dd69d292
CD
10382003-05-03 Chris Demetriou <cgd@broadcom.com>
1039
1040 * cp1.c: Tweak attribution slightly.
1041 * cp1.h: Likewise.
1042 * mdmx.c: Likewise.
1043 * mdmx.igen: Likewise.
1044 * mips3d.igen: Likewise.
1045 * sb1.igen: Likewise.
1046
bcd0068e
CD
10472003-04-15 Richard Sandiford <rsandifo@redhat.com>
1048
1049 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1050 unsigned operands.
1051
6b4a8935
AC
10522003-02-27 Andrew Cagney <cagney@redhat.com>
1053
601da316
AC
1054 * interp.c (sim_open): Rename _bfd to bfd.
1055 (sim_create_inferior): Ditto.
6b4a8935 1056
d29e330f
CD
10572003-01-14 Chris Demetriou <cgd@broadcom.com>
1058
1059 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1060
a2353a08
CD
10612003-01-14 Chris Demetriou <cgd@broadcom.com>
1062
1063 * mips.igen (EI, DI): Remove.
1064
80551777
CD
10652003-01-05 Richard Sandiford <rsandifo@redhat.com>
1066
1067 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1068
4c54fc26
CD
10692003-01-04 Richard Sandiford <rsandifo@redhat.com>
1070 Andrew Cagney <ac131313@redhat.com>
1071 Gavin Romig-Koch <gavin@redhat.com>
1072 Graydon Hoare <graydon@redhat.com>
1073 Aldy Hernandez <aldyh@redhat.com>
1074 Dave Brolley <brolley@redhat.com>
1075 Chris Demetriou <cgd@broadcom.com>
1076
1077 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1078 (sim_mach_default): New variable.
1079 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1080 Add a new simulator generator, MULTI.
1081 * configure: Regenerate.
1082 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1083 (multi-run.o): New dependency.
1084 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1085 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1086 (tmp-multi): Combine them.
1087 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1088 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1089 (distclean-extra): New rule.
1090 * sim-main.h: Include bfd.h.
1091 (MIPS_MACH): New macro.
1092 * mips.igen (vr4120, vr5400, vr5500): New models.
1093 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1094 * vr.igen: Replace with new version.
1095
e6c674b8
CD
10962003-01-04 Chris Demetriou <cgd@broadcom.com>
1097
1098 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1099 * configure: Regenerate.
1100
28f50ac8
CD
11012002-12-31 Chris Demetriou <cgd@broadcom.com>
1102
1103 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1104 * mips.igen: Remove all invocations of check_branch_bug and
1105 mark_branch_bug.
1106
5071ffe6
CD
11072002-12-16 Chris Demetriou <cgd@broadcom.com>
1108
72f4393d 1109 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1110
06e7837e
CD
11112002-07-30 Chris Demetriou <cgd@broadcom.com>
1112
1113 * mips.igen (do_load_double, do_store_double): New functions.
1114 (LDC1, SDC1): Rename to...
1115 (LDC1b, SDC1b): respectively.
1116 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1117
2265c243
MS
11182002-07-29 Michael Snyder <msnyder@redhat.com>
1119
1120 * cp1.c (fp_recip2): Modify initialization expression so that
1121 GCC will recognize it as constant.
1122
a2f8b4f3
CD
11232002-06-18 Chris Demetriou <cgd@broadcom.com>
1124
1125 * mdmx.c (SD_): Delete.
1126 (Unpredictable): Re-define, for now, to directly invoke
1127 unpredictable_action().
1128 (mdmx_acc_op): Fix error in .ob immediate handling.
1129
b4b6c939
AC
11302002-06-18 Andrew Cagney <cagney@redhat.com>
1131
1132 * interp.c (sim_firmware_command): Initialize `address'.
1133
c8cca39f
AC
11342002-06-16 Andrew Cagney <ac131313@redhat.com>
1135
1136 * configure: Regenerated to track ../common/aclocal.m4 changes.
1137
e7e81181 11382002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1139 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD
1140
1141 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1142 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1143 * mips.igen: Include mips3d.igen.
1144 (mips3d): New model name for MIPS-3D ASE instructions.
1145 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1146 instructions.
e7e81181
CD
1147 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1148 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1149 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1150 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1151 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1152 (RSquareRoot1, RSquareRoot2): New macros.
1153 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1154 (fp_rsqrt2): New functions.
1155 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1156 * configure: Regenerate.
1157
3a2b820e 11582002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1159 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD
1160
1161 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1162 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1163 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1164 (convert): Note that this function is not used for paired-single
1165 format conversions.
1166 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1167 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1168 (check_fmt_p): Enable paired-single support.
1169 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1170 (PUU.PS): New instructions.
1171 (CVT.S.fmt): Don't use this instruction for paired-single format
1172 destinations.
1173 * sim-main.h (FP_formats): New value 'fmt_ps.'
1174 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1175 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1176
d18ea9c2
CD
11772002-06-12 Chris Demetriou <cgd@broadcom.com>
1178
1179 * mips.igen: Fix formatting of function calls in
1180 many FP operations.
1181
95fd5cee
CD
11822002-06-12 Chris Demetriou <cgd@broadcom.com>
1183
1184 * mips.igen (MOVN, MOVZ): Trace result.
1185 (TNEI): Print "tnei" as the opcode name in traces.
1186 (CEIL.W): Add disassembly string for traces.
1187 (RSQRT.fmt): Make location of disassembly string consistent
1188 with other instructions.
1189
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CD
11902002-06-12 Chris Demetriou <cgd@broadcom.com>
1191
1192 * mips.igen (X): Delete unused function.
1193
3c25f8c7
AC
11942002-06-08 Andrew Cagney <cagney@redhat.com>
1195
1196 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1197
f3c08b7e 11982002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1199 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD
1200
1201 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1202 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1203 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1204 (fp_nmsub): New prototypes.
1205 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1206 (NegMultiplySub): New defines.
1207 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1208 (MADD.D, MADD.S): Replace with...
1209 (MADD.fmt): New instruction.
1210 (MSUB.D, MSUB.S): Replace with...
1211 (MSUB.fmt): New instruction.
1212 (NMADD.D, NMADD.S): Replace with...
1213 (NMADD.fmt): New instruction.
1214 (NMSUB.D, MSUB.S): Replace with...
1215 (NMSUB.fmt): New instruction.
1216
52714ff9 12172002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1218 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD
1219
1220 * cp1.c: Fix more comment spelling and formatting.
1221 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1222 (denorm_mode): New function.
1223 (fpu_unary, fpu_binary): Round results after operation, collect
1224 status from rounding operations, and update the FCSR.
1225 (convert): Collect status from integer conversions and rounding
1226 operations, and update the FCSR. Adjust NaN values that result
1227 from conversions. Convert to use sim_io_eprintf rather than
1228 fprintf, and remove some debugging code.
1229 * cp1.h (fenr_FS): New define.
1230
577d8c4b
CD
12312002-06-07 Chris Demetriou <cgd@broadcom.com>
1232
1233 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1234 rounding mode to sim FP rounding mode flag conversion code into...
1235 (rounding_mode): New function.
1236
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CD
12372002-06-07 Chris Demetriou <cgd@broadcom.com>
1238
1239 * cp1.c: Clean up formatting of a few comments.
1240 (value_fpr): Reformat switch statement.
1241
cfe9ea23 12422002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1243 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD
1244
1245 * cp1.h: New file.
1246 * sim-main.h: Include cp1.h.
1247 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1248 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1249 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1250 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1251 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1252 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1253 * cp1.c: Don't include sim-fpu.h; already included by
1254 sim-main.h. Clean up formatting of some comments.
1255 (NaN, Equal, Less): Remove.
1256 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1257 (fp_cmp): New functions.
1258 * mips.igen (do_c_cond_fmt): Remove.
1259 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1260 Compare. Add result tracing.
1261 (CxC1): Remove, replace with...
1262 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1263 (DMxC1): Remove, replace with...
1264 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L
1265 (MxC1): Remove, replace with...
1266 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1267
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CD
12682002-06-04 Chris Demetriou <cgd@broadcom.com>
1269
1270 * sim-main.h (FGRIDX): Remove, replace all uses with...
1271 (FGR_BASE): New macro.
1272 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1273 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1274 (NR_FGR, FGR): Likewise.
1275 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1276 * mips.igen: Likewise.
1277
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CD
12782002-06-04 Chris Demetriou <cgd@broadcom.com>
1279
1280 * cp1.c: Add an FSF Copyright notice to this file.
1281
ba46ddd0 12822002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1283 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD
1284
1285 * cp1.c (Infinity): Remove.
1286 * sim-main.h (Infinity): Likewise.
1287
1288 * cp1.c (fp_unary, fp_binary): New functions.
1289 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1290 (fp_sqrt): New functions, implemented in terms of the above.
1291 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1292 (Recip, SquareRoot): Remove (replaced by functions above).
1293 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1294 (fp_recip, fp_sqrt): New prototypes.
1295 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1296 (Recip, SquareRoot): Replace prototypes with #defines which
1297 invoke the functions above.
72f4393d 1298
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CD
12992002-06-03 Chris Demetriou <cgd@broadcom.com>
1300
1301 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1302 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1303 file, remove PARAMS from prototypes.
1304 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1305 simulator state arguments.
1306 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1307 pass simulator state arguments.
1308 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1309 (store_fpr, convert): Remove 'sd' argument.
1310 (value_fpr): Likewise. Convert to use 'SD' instead.
1311
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CD
13122002-06-03 Chris Demetriou <cgd@broadcom.com>
1313
1314 * cp1.c (Min, Max): Remove #if 0'd functions.
1315 * sim-main.h (Min, Max): Remove.
1316
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CD
13172002-06-03 Chris Demetriou <cgd@broadcom.com>
1318
1319 * cp1.c: fix formatting of switch case and default labels.
1320 * interp.c: Likewise.
1321 * sim-main.c: Likewise.
1322
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CD
13232002-06-03 Chris Demetriou <cgd@broadcom.com>
1324
1325 * cp1.c: Clean up comments which describe FP formats.
1326 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1327
7cbea089 13282002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1329 Ed Satterthwaite <ehs@broadcom.com>
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CD
1330
1331 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1332 Broadcom SiByte SB-1 processor configurations.
1333 * configure: Regenerate.
1334 * sb1.igen: New file.
1335 * mips.igen: Include sb1.igen.
1336 (sb1): New model.
1337 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1338 * mdmx.igen: Add "sb1" model to all appropriate functions and
1339 instructions.
1340 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1341 (ob_func, ob_acc): Reference the above.
1342 (qh_acc): Adjust to keep the same size as ob_acc.
1343 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1344 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1345
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CD
13462002-06-03 Chris Demetriou <cgd@broadcom.com>
1347
1348 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1349
f4f1b9f1 13502002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1351 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD
1352
1353 * mips.igen (mdmx): New (pseudo-)model.
1354 * mdmx.c, mdmx.igen: New files.
1355 * Makefile.in (SIM_OBJS): Add mdmx.o.
1356 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1357 New typedefs.
1358 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1359 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1360 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1361 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1362 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1363 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1364 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1365 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1366 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1367 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1368 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1369 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1370 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1371 (qh_fmtsel): New macros.
1372 (_sim_cpu): New member "acc".
1373 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1374 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1375
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CD
13762002-05-01 Chris Demetriou <cgd@broadcom.com>
1377
1378 * interp.c: Use 'deprecated' rather than 'depreciated.'
1379 * sim-main.h: Likewise.
1380
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CD
13812002-05-01 Chris Demetriou <cgd@broadcom.com>
1382
1383 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1384 which wouldn't compile anyway.
1385 * sim-main.h (unpredictable_action): New function prototype.
1386 (Unpredictable): Define to call igen function unpredictable().
1387 (NotWordValue): New macro to call igen function not_word_value().
1388 (UndefinedResult): Remove.
1389 * interp.c (undefined_result): Remove.
1390 (unpredictable_action): New function.
1391 * mips.igen (not_word_value, unpredictable): New functions.
1392 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1393 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1394 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1395 NotWordValue() to check for unpredictable inputs, then
1396 Unpredictable() to handle them.
1397
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CD
13982002-02-24 Chris Demetriou <cgd@broadcom.com>
1399
1400 * mips.igen: Fix formatting of calls to Unpredictable().
1401
e1015982
AC
14022002-04-20 Andrew Cagney <ac131313@redhat.com>
1403
1404 * interp.c (sim_open): Revert previous change.
1405
b882a66b
AO
14062002-04-18 Alexandre Oliva <aoliva@redhat.com>
1407
1408 * interp.c (sim_open): Disable chunk of code that wrote code in
1409 vector table entries.
1410
c429b7dd
CD
14112002-03-19 Chris Demetriou <cgd@broadcom.com>
1412
1413 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1414 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1415 unused definitions.
1416
37d146fa
CD
14172002-03-19 Chris Demetriou <cgd@broadcom.com>
1418
1419 * cp1.c: Fix many formatting issues.
1420
07892c0b
CD
14212002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1422
1423 * cp1.c (fpu_format_name): New function to replace...
1424 (DOFMT): This. Delete, and update all callers.
1425 (fpu_rounding_mode_name): New function to replace...
1426 (RMMODE): This. Delete, and update all callers.
1427
487f79b7
CD
14282002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1429
1430 * interp.c: Move FPU support routines from here to...
1431 * cp1.c: Here. New file.
1432 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1433 (cp1.o): New target.
1434
1e799e28
CD
14352002-03-12 Chris Demetriou <cgd@broadcom.com>
1436
1437 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1438 * mips.igen (mips32, mips64): New models, add to all instructions
1439 and functions as appropriate.
1440 (loadstore_ea, check_u64): New variant for model mips64.
1441 (check_fmt_p): New variant for models mipsV and mips64, remove
1442 mipsV model marking fro other variant.
1443 (SLL) Rename to...
1444 (SLLa) this.
1445 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1446 for mips32 and mips64.
1447 (DCLO, DCLZ): New instructions for mips64.
1448
82f728db
CD
14492002-03-07 Chris Demetriou <cgd@broadcom.com>
1450
1451 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1452 immediate or code as a hex value with the "%#lx" format.
1453 (ANDI): Likewise, and fix printed instruction name.
1454
b96e7ef1
CD
14552002-03-05 Chris Demetriou <cgd@broadcom.com>
1456
1457 * sim-main.h (UndefinedResult, Unpredictable): New macros
1458 which currently do nothing.
1459
d35d4f70
CD
14602002-03-05 Chris Demetriou <cgd@broadcom.com>
1461
1462 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1463 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1464 (status_CU3): New definitions.
1465
1466 * sim-main.h (ExceptionCause): Add new values for MIPS32
1467 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1468 for DebugBreakPoint and NMIReset to note their status in
1469 MIPS32 and MIPS64.
1470 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1471 (SignalExceptionCacheErr): New exception macros.
1472
3ad6f714
CD
14732002-03-05 Chris Demetriou <cgd@broadcom.com>
1474
1475 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1476 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1477 is always enabled.
1478 (SignalExceptionCoProcessorUnusable): Take as argument the
1479 unusable coprocessor number.
1480
86b77b47
CD
14812002-03-05 Chris Demetriou <cgd@broadcom.com>
1482
1483 * mips.igen: Fix formatting of all SignalException calls.
1484
97a88e93 14852002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD
1486
1487 * sim-main.h (SIGNEXTEND): Remove.
1488
97a88e93 14892002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD
1490
1491 * mips.igen: Remove gencode comment from top of file, fix
1492 spelling in another comment.
1493
97a88e93 14942002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD
1495
1496 * mips.igen (check_fmt, check_fmt_p): New functions to check
1497 whether specific floating point formats are usable.
1498 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1499 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1500 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1501 Use the new functions.
1502 (do_c_cond_fmt): Remove format checks...
1503 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1504
97a88e93 15052002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD
1506
1507 * mips.igen: Fix formatting of check_fpu calls.
1508
41774c9d
CD
15092002-03-03 Chris Demetriou <cgd@broadcom.com>
1510
1511 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1512
4a0bd876
CD
15132002-03-03 Chris Demetriou <cgd@broadcom.com>
1514
1515 * mips.igen: Remove whitespace at end of lines.
1516
09297648
CD
15172002-03-02 Chris Demetriou <cgd@broadcom.com>
1518
1519 * mips.igen (loadstore_ea): New function to do effective
1520 address calculations.
1521 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1522 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1523 CACHE): Use loadstore_ea to do effective address computations.
1524
043b7057
CD
15252002-03-02 Chris Demetriou <cgd@broadcom.com>
1526
1527 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1528 * mips.igen (LL, CxC1, MxC1): Likewise.
1529
c1e8ada4
CD
15302002-03-02 Chris Demetriou <cgd@broadcom.com>
1531
1532 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1533 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1534 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1535 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1536 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1537 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1538 Don't split opcode fields by hand, use the opcode field values
1539 provided by igen.
1540
3e1dca16
CD
15412002-03-01 Chris Demetriou <cgd@broadcom.com>
1542
1543 * mips.igen (do_divu): Fix spacing.
1544
1545 * mips.igen (do_dsllv): Move to be right before DSLLV,
1546 to match the rest of the do_<shift> functions.
1547
fff8d27d
CD
15482002-03-01 Chris Demetriou <cgd@broadcom.com>
1549
1550 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1551 DSRL32, do_dsrlv): Trace inputs and results.
1552
0d3e762b
CD
15532002-03-01 Chris Demetriou <cgd@broadcom.com>
1554
1555 * mips.igen (CACHE): Provide instruction-printing string.
1556
1557 * interp.c (signal_exception): Comment tokens after #endif.
1558
eb5fcf93
CD
15592002-02-28 Chris Demetriou <cgd@broadcom.com>
1560
1561 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L
1562 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1563 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1564 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1565 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1566 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1567 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD
1568 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1569
bb22bd7d
CD
15702002-02-28 Chris Demetriou <cgd@broadcom.com>
1571
1572 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1573 instruction-printing string.
1574 (LWU): Use '64' as the filter flag.
1575
91a177cf
CD
15762002-02-28 Chris Demetriou <cgd@broadcom.com>
1577
1578 * mips.igen (SDXC1): Fix instruction-printing string.
1579
387f484a
CD
15802002-02-28 Chris Demetriou <cgd@broadcom.com>
1581
1582 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1583 filter flags "32,f".
1584
3d81f391
CD
15852002-02-27 Chris Demetriou <cgd@broadcom.com>
1586
1587 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1588 as the filter flag.
1589
af5107af
CD
15902002-02-27 Chris Demetriou <cgd@broadcom.com>
1591
1592 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1593 add a comma) so that it more closely match the MIPS ISA
1594 documentation opcode partitioning.
1595 (PREF): Put useful names on opcode fields, and include
1596 instruction-printing string.
1597
ca971540
CD
15982002-02-27 Chris Demetriou <cgd@broadcom.com>
1599
1600 * mips.igen (check_u64): New function which in the future will
1601 check whether 64-bit instructions are usable and signal an
1602 exception if not. Currently a no-op.
1603 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1604 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1605 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1606 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1607
1608 * mips.igen (check_fpu): New function which in the future will
1609 check whether FPU instructions are usable and signal an exception
1610 if not. Currently a no-op.
1611 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1612 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1613 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1614 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1615 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1616 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1617 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1618 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1619
1c47a468
CD
16202002-02-27 Chris Demetriou <cgd@broadcom.com>
1621
1622 * mips.igen (do_load_left, do_load_right): Move to be immediately
1623 following do_load.
1624 (do_store_left, do_store_right): Move to be immediately following
1625 do_store.
1626
603a98e7
CD
16272002-02-27 Chris Demetriou <cgd@broadcom.com>
1628
1629 * mips.igen (mipsV): New model name. Also, add it to
1630 all instructions and functions where it is appropriate.
1631
c5d00cc7
CD
16322002-02-18 Chris Demetriou <cgd@broadcom.com>
1633
1634 * mips.igen: For all functions and instructions, list model
1635 names that support that instruction one per line.
1636
074e9cb8
CD
16372002-02-11 Chris Demetriou <cgd@broadcom.com>
1638
1639 * mips.igen: Add some additional comments about supported
1640 models, and about which instructions go where.
1641 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1642 order as is used in the rest of the file.
1643
9805e229
CD
16442002-02-11 Chris Demetriou <cgd@broadcom.com>
1645
1646 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1647 indicating that ALU32_END or ALU64_END are there to check
1648 for overflow.
1649 (DADD): Likewise, but also remove previous comment about
1650 overflow checking.
1651
f701dad2
CD
16522002-02-10 Chris Demetriou <cgd@broadcom.com>
1653
1654 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1655 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1656 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1657 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1658 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1659 fields (i.e., add and move commas) so that they more closely
1660 match the MIPS ISA documentation opcode partitioning.
1661
16622002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1663
72f4393d
L
1664 * mips.igen (ADDI): Print immediate value.
1665 (BREAK): Print code.
1666 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1667 (SLL): Print "nop" specially, and don't run the code
1668 that does the shift for the "nop" case.
20ae0098 1669
9e52972e
FF
16702001-11-17 Fred Fish <fnf@redhat.com>
1671
1672 * sim-main.h (float_operation): Move enum declaration outside
1673 of _sim_cpu struct declaration.
1674
c0efbca4
JB
16752001-04-12 Jim Blandy <jimb@redhat.com>
1676
1677 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1678 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1679 set of the FCSR.
1680 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1681 PENDING_FILL, and you can get the intended effect gracefully by
1682 calling PENDING_SCHED directly.
1683
fb891446
BE
16842001-02-23 Ben Elliston <bje@redhat.com>
1685
1686 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1687 already defined elsewhere.
1688
8030f857
BE
16892001-02-19 Ben Elliston <bje@redhat.com>
1690
1691 * sim-main.h (sim_monitor): Return an int.
1692 * interp.c (sim_monitor): Add return values.
1693 (signal_exception): Handle error conditions from sim_monitor.
1694
56b48a7a
CD
16952001-02-08 Ben Elliston <bje@redhat.com>
1696
1697 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1698 (store_memory): Likewise, pass cia to sim_core_write*.
1699
d3ee60d9
FCE
17002000-10-19 Frank Ch. Eigler <fche@redhat.com>
1701
1702 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1703 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1704
071da002
AC
1705Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1706
1707 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1708 * Makefile.in: Don't delete *.igen when cleaning directory.
1709
a28c02cd
AC
1710Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1711
1712 * m16.igen (break): Call SignalException not sim_engine_halt.
1713
80ee11fa
AC
1714Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1715
1716 From Jason Eckhardt:
1717 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1718
673388c0
AC
1719Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1720
1721 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1722
4c0deff4
NC
17232000-05-24 Michael Hayes <mhayes@cygnus.com>
1724
1725 * mips.igen (do_dmultx): Fix typo.
1726
eb2d80b4
AC
1727Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1728
1729 * configure: Regenerated to track ../common/aclocal.m4 changes.
1730
dd37a34b
AC
1731Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1732
1733 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1734
4c0deff4
NC
17352000-04-12 Frank Ch. Eigler <fche@redhat.com>
1736
1737 * sim-main.h (GPR_CLEAR): Define macro.
1738
e30db738
AC
1739Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1740
1741 * interp.c (decode_coproc): Output long using %lx and not %s.
1742
cb7450ea
FCE
17432000-03-21 Frank Ch. Eigler <fche@redhat.com>
1744
1745 * interp.c (sim_open): Sort & extend dummy memory regions for
1746 --board=jmr3904 for eCos.
1747
a3027dd7
FCE
17482000-03-02 Frank Ch. Eigler <fche@redhat.com>
1749
1750 * configure: Regenerated.
1751
1752Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1753
1754 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1755 calls, conditional on the simulator being in verbose mode.
1756
dfcd3bfb
JM
1757Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1758
1759 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1760 cache don't get ReservedInstruction traps.
1761
c2d11a7d
JM
17621999-11-29 Mark Salter <msalter@cygnus.com>
1763
1764 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1765 to clear status bits in sdisr register. This is how the hardware works.
1766
1767 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1768 being used by cygmon.
1769
4ce44c66
JM
17701999-11-11 Andrew Haley <aph@cygnus.com>
1771
1772 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1773 instructions.
1774
cff3e48b
JM
1775Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1776
1777 * mips.igen (MULT): Correct previous mis-applied patch.
1778
d4f3574e
SS
1779Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1780
1781 * mips.igen (delayslot32): Handle sequence like
1782 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1783 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1784 (MULT): Actually pass the third register...
1785
17861999-09-03 Mark Salter <msalter@cygnus.com>
1787
1788 * interp.c (sim_open): Added more memory aliases for additional
1789 hardware being touched by cygmon on jmr3904 board.
1790
1791Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1792
1793 * configure: Regenerated to track ../common/aclocal.m4 changes.
1794
a0b3c4fd
JM
1795Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1796
1797 * interp.c (sim_store_register): Handle case where client - GDB -
1798 specifies that a 4 byte register is 8 bytes in size.
1799 (sim_fetch_register): Ditto.
72f4393d 1800
adf40b2e
JM
18011999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1802
1803 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1804 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1805 (idt_monitor_base): Base address for IDT monitor traps.
1806 (pmon_monitor_base): Ditto for PMON.
1807 (lsipmon_monitor_base): Ditto for LSI PMON.
1808 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1809 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1810 (sim_firmware_command): New function.
1811 (mips_option_handler): Call it for OPTION_FIRMWARE.
1812 (sim_open): Allocate memory for idt_monitor region. If "--board"
1813 option was given, add no monitor by default. Add BREAK hooks only if
1814 monitors are also there.
72f4393d 1815
43e526b9
JM
1816Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1817
1818 * interp.c (sim_monitor): Flush output before reading input.
1819
1820Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1821
1822 * tconfig.in (SIM_HANDLES_LMA): Always define.
1823
1824Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1825
1826 From Mark Salter <msalter@cygnus.com>:
1827 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1828 (sim_open): Add setup for BSP board.
1829
9846de1b
JM
1830Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1831
1832 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1833 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1834 them as unimplemented.
1835
cd0fc7c3
SS
18361999-05-08 Felix Lee <flee@cygnus.com>
1837
1838 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1839
7a292a7a
SS
18401999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1841
1842 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1843
1844Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1845
1846 * configure.in: Any mips64vr5*-*-* target should have
1847 -DTARGET_ENABLE_FR=1.
1848 (default_endian): Any mips64vr*el-*-* target should default to
1849 LITTLE_ENDIAN.
1850 * configure: Re-generate.
1851
18521999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1853
1854 * mips.igen (ldl): Extend from _16_, not 32.
1855
1856Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1857
1858 * interp.c (sim_store_register): Force registers written to by GDB
1859 into an un-interpreted state.
1860
c906108c
SS
18611999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1862
1863 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1864 CPU, start periodic background I/O polls.
72f4393d 1865 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS
1866
18671998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1868
1869 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1870
c906108c
SS
1871Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1872
1873 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1874 case statement.
1875
18761998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L
1877
1878 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS
1879 (load_word): Call SIM_CORE_SIGNAL hook on error.
1880 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1881 starting. For exception dispatching, pass PC instead of NULL_CIA.
1882 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1883 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS
1884 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1885 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1886 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS
1887 * mips.igen (*): Replace memory-related SignalException* calls
1888 with references to SIM_CORE_SIGNAL hook.
72f4393d 1889
c906108c
SS
1890 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1891 fix.
1892 * sim-main.c (*): Minor warning cleanups.
72f4393d 1893
c906108c
SS
18941998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1895
1896 * m16.igen (DADDIU5): Correct type-o.
1897
1898Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1899
1900 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1901 variables.
1902
1903Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1904
1905 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1906 to include path.
1907 (interp.o): Add dependency on itable.h
1908 (oengine.c, gencode): Delete remaining references.
1909 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1910
c906108c 19111998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1912
c906108c
SS
1913 * vr4run.c: New.
1914 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1915 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1916 tmp-run-hack) : New.
1917 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1918 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS
1919 Drop the "64" qualifier to get the HACK generator working.
1920 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1921 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1922 qualifier to get the hack generator working.
1923 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1924 (DSLL): Use do_dsll.
1925 (DSLLV): Use do_dsllv.
1926 (DSRA): Use do_dsra.
1927 (DSRL): Use do_dsrl.
1928 (DSRLV): Use do_dsrlv.
1929 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1930 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS
1931 get the HACK generator working.
1932 (MACC) Rename to get the HACK generator working.
1933 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1934
c906108c
SS
19351998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1936
1937 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1938 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1939
c906108c
SS
19401998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1941
1942 * mips/interp.c (DEBUG): Cleanups.
1943
19441998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1945
1946 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1947 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1948
c906108c
SS
19491998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1950
1951 * interp.c (sim_close): Uninstall modules.
1952
1953Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1954
1955 * sim-main.h, interp.c (sim_monitor): Change to global
1956 function.
1957
1958Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1959
1960 * configure.in (vr4100): Only include vr4100 instructions in
1961 simulator.
1962 * configure: Re-generate.
1963 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1964
1965Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1966
1967 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1968 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1969 true alternative.
1970
1971 * configure.in (sim_default_gen, sim_use_gen): Replace with
1972 sim_gen.
1973 (--enable-sim-igen): Delete config option. Always using IGEN.
1974 * configure: Re-generate.
72f4393d 1975
c906108c
SS
1976 * Makefile.in (gencode): Kill, kill, kill.
1977 * gencode.c: Ditto.
72f4393d 1978
c906108c
SS
1979Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1980
1981 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1982 bit mips16 igen simulator.
1983 * configure: Re-generate.
1984
1985 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1986 as part of vr4100 ISA.
1987 * vr.igen: Mark all instructions as 64 bit only.
1988
1989Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1990
1991 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1992 Pacify GCC.
1993
1994Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1995
1996 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1997 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1998 * configure: Re-generate.
1999
2000 * m16.igen (BREAK): Define breakpoint instruction.
2001 (JALX32): Mark instruction as mips16 and not r3900.
2002 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2003
2004 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2005
2006Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2007
2008 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2009 insn as a debug breakpoint.
2010
2011 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2012 pending.slot_size.
2013 (PENDING_SCHED): Clean up trace statement.
2014 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2015 (PENDING_FILL): Delay write by only one cycle.
2016 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2017
2018 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2019 of pending writes.
2020 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2021 32 & 64.
2022 (pending_tick): Move incrementing of index to FOR statement.
2023 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2024
c906108c
SS
2025 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2026 build simulator.
2027 * configure: Re-generate.
72f4393d 2028
c906108c
SS
2029 * interp.c (sim_engine_run OLD): Delete explicit call to
2030 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2031
c906108c
SS
2032Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2033
2034 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2035 interrupt level number to match changed SignalExceptionInterrupt
2036 macro.
2037
2038Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2039
2040 * interp.c: #include "itable.h" if WITH_IGEN.
2041 (get_insn_name): New function.
2042 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2043 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2044
2045Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2046
2047 * configure: Rebuilt to inhale new common/aclocal.m4.
2048
2049Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2050
2051 * dv-tx3904sio.c: Include sim-assert.h.
2052
2053Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2054
2055 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2056 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2057 Reorganize target-specific sim-hardware checks.
2058 * configure: rebuilt.
2059 * interp.c (sim_open): For tx39 target boards, set
2060 OPERATING_ENVIRONMENT, add tx3904sio devices.
2061 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2062 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2063
c906108c
SS
2064 * dv-tx3904irc.c: Compiler warning clean-up.
2065 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2066 frequent hw-trace messages.
2067
2068Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2069
2070 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2071
2072Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2073
2074 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2075
2076 * vr.igen: New file.
2077 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2078 * mips.igen: Define vr4100 model. Include vr.igen.
2079Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2080
2081 * mips.igen (check_mf_hilo): Correct check.
2082
2083Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2084
2085 * sim-main.h (interrupt_event): Add prototype.
2086
2087 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2088 register_ptr, register_value.
2089 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2090
2091 * sim-main.h (tracefh): Make extern.
2092
2093Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2094
2095 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2096 Reduce unnecessarily high timer event frequency.
c906108c 2097 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2098
c906108c
SS
2099Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2100
2101 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2102 to allay warnings.
2103 (interrupt_event): Made non-static.
72f4393d 2104
c906108c
SS
2105 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2106 interchange of configuration values for external vs. internal
2107 clock dividers.
72f4393d 2108
c906108c
SS
2109Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2110
72f4393d 2111 * mips.igen (BREAK): Moved code to here for
c906108c
SS
2112 simulator-reserved break instructions.
2113 * gencode.c (build_instruction): Ditto.
2114 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2115 reserved instructions now use exception vector, rather
c906108c
SS
2116 than halting sim.
2117 * sim-main.h: Moved magic constants to here.
2118
2119Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2120
2121 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2122 register upon non-zero interrupt event level, clear upon zero
2123 event value.
2124 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2125 by passing zero event value.
2126 (*_io_{read,write}_buffer): Endianness fixes.
2127 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2128 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2129
2130 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2131 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2132
c906108c
SS
2133Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2134
72f4393d 2135 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS
2136 and BigEndianCPU.
2137
2138Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2139
2140 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2141 parts.
2142 * configure: Update.
2143
2144Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2145
2146 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2147 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2148 * configure.in: Include tx3904tmr in hw_device list.
2149 * configure: Rebuilt.
2150 * interp.c (sim_open): Instantiate three timer instances.
2151 Fix address typo of tx3904irc instance.
2152
2153Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2154
2155 * interp.c (signal_exception): SystemCall exception now uses
2156 the exception vector.
2157
2158Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2159
2160 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2161 to allay warnings.
2162
2163Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2164
2165 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2166
2167Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2168
2169 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2170
2171 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2172 sim-main.h. Declare a struct hw_descriptor instead of struct
2173 hw_device_descriptor.
2174
2175Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2176
2177 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2178 right bits and then re-align left hand bytes to correct byte
2179 lanes. Fix incorrect computation in do_store_left when loading
2180 bytes from second word.
2181
2182Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2183
2184 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2185 * interp.c (sim_open): Only create a device tree when HW is
2186 enabled.
2187
2188 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2189 * interp.c (signal_exception): Ditto.
2190
2191Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2192
2193 * gencode.c: Mark BEGEZALL as LIKELY.
2194
2195Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2196
2197 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2198 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2199
c906108c
SS
2200Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2201
2202 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2203 modules. Recognize TX39 target with "mips*tx39" pattern.
2204 * configure: Rebuilt.
2205 * sim-main.h (*): Added many macros defining bits in
2206 TX39 control registers.
2207 (SignalInterrupt): Send actual PC instead of NULL.
2208 (SignalNMIReset): New exception type.
2209 * interp.c (board): New variable for future use to identify
2210 a particular board being simulated.
2211 (mips_option_handler,mips_options): Added "--board" option.
2212 (interrupt_event): Send actual PC.
2213 (sim_open): Make memory layout conditional on board setting.
2214 (signal_exception): Initial implementation of hardware interrupt
2215 handling. Accept another break instruction variant for simulator
2216 exit.
2217 (decode_coproc): Implement RFE instruction for TX39.
2218 (mips.igen): Decode RFE instruction as such.
2219 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2220 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2221 bbegin to implement memory map.
2222 * dv-tx3904cpu.c: New file.
2223 * dv-tx3904irc.c: New file.
2224
2225Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2226
2227 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2228
2229Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2230
2231 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2232 with calls to check_div_hilo.
2233
2234Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2235
2236 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2237 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2238 Add special r3900 version of do_mult_hilo.
c906108c
SS
2239 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2240 with calls to check_mult_hilo.
2241 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2242 with calls to check_div_hilo.
2243
2244Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2245
2246 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2247 Document a replacement.
2248
2249Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2250
2251 * interp.c (sim_monitor): Make mon_printf work.
2252
2253Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2254
2255 * sim-main.h (INSN_NAME): New arg `cpu'.
2256
2257Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2258
72f4393d 2259 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS
2260
2261Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2262
2263 * configure: Regenerated to track ../common/aclocal.m4 changes.
2264 * config.in: Ditto.
2265
2266Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2267
2268 * acconfig.h: New file.
2269 * configure.in: Reverted change of Apr 24; use sinclude again.
2270
2271Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2272
2273 * configure: Regenerated to track ../common/aclocal.m4 changes.
2274 * config.in: Ditto.
2275
2276Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2277
2278 * configure.in: Don't call sinclude.
2279
2280Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2281
2282 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2283
2284Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2285
2286 * mips.igen (ERET): Implement.
2287
2288 * interp.c (decode_coproc): Return sign-extended EPC.
2289
2290 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2291
2292 * interp.c (signal_exception): Do not ignore Trap.
2293 (signal_exception): On TRAP, restart at exception address.
2294 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2295 (signal_exception): Update.
2296 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2297 so that TRAP instructions are caught.
2298
2299Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2300
2301 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2302 contains HI/LO access history.
2303 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2304 (HIACCESS, LOACCESS): Delete, replace with
2305 (HIHISTORY, LOHISTORY): New macros.
2306 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2307
c906108c
SS
2308 * gencode.c (build_instruction): Do not generate checks for
2309 correct HI/LO register usage.
2310
2311 * interp.c (old_engine_run): Delete checks for correct HI/LO
2312 register usage.
2313
2314 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2315 check_mf_cycles): New functions.
2316 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2317 do_divu, domultx, do_mult, do_multu): Use.
2318
2319 * tx.igen ("madd", "maddu"): Use.
72f4393d 2320
c906108c
SS
2321Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2322
2323 * mips.igen (DSRAV): Use function do_dsrav.
2324 (SRAV): Use new function do_srav.
2325
2326 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2327 (B): Sign extend 11 bit immediate.
2328 (EXT-B*): Shift 16 bit immediate left by 1.
2329 (ADDIU*): Don't sign extend immediate value.
2330
2331Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2332
2333 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2334
2335 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2336 functions.
2337
2338 * mips.igen (delayslot32, nullify_next_insn): New functions.
2339 (m16.igen): Always include.
2340 (do_*): Add more tracing.
2341
2342 * m16.igen (delayslot16): Add NIA argument, could be called by a
2343 32 bit MIPS16 instruction.
72f4393d 2344
c906108c
SS
2345 * interp.c (ifetch16): Move function from here.
2346 * sim-main.c (ifetch16): To here.
72f4393d 2347
c906108c
SS
2348 * sim-main.c (ifetch16, ifetch32): Update to match current
2349 implementations of LH, LW.
2350 (signal_exception): Don't print out incorrect hex value of illegal
2351 instruction.
2352
2353Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2354
2355 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2356 instruction.
2357
2358 * m16.igen: Implement MIPS16 instructions.
72f4393d 2359
c906108c
SS
2360 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2361 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2362 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2363 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2364 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2365 bodies of corresponding code from 32 bit insn to these. Also used
2366 by MIPS16 versions of functions.
72f4393d 2367
c906108c
SS
2368 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2369 (IMEM16): Drop NR argument from macro.
2370
2371Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2372
2373 * Makefile.in (SIM_OBJS): Add sim-main.o.
2374
2375 * sim-main.h (address_translation, load_memory, store_memory,
2376 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2377 as INLINE_SIM_MAIN.
2378 (pr_addr, pr_uword64): Declare.
2379 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2380
c906108c
SS
2381 * interp.c (address_translation, load_memory, store_memory,
2382 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2383 from here.
2384 * sim-main.c: To here. Fix compilation problems.
72f4393d 2385
c906108c
SS
2386 * configure.in: Enable inlining.
2387 * configure: Re-config.
2388
2389Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2390
2391 * configure: Regenerated to track ../common/aclocal.m4 changes.
2392
2393Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2394
2395 * mips.igen: Include tx.igen.
2396 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2397 * tx.igen: New file, contains MADD and MADDU.
2398
2399 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2400 the hardwired constant `7'.
2401 (store_memory): Ditto.
2402 (LOADDRMASK): Move definition to sim-main.h.
2403
2404 mips.igen (MTC0): Enable for r3900.
2405 (ADDU): Add trace.
2406
2407 mips.igen (do_load_byte): Delete.
2408 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2409 do_store_right): New functions.
2410 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2411
2412 configure.in: Let the tx39 use igen again.
2413 configure: Update.
72f4393d 2414
c906108c
SS
2415Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2416
2417 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2418 not an address sized quantity. Return zero for cache sizes.
2419
2420Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2421
2422 * mips.igen (r3900): r3900 does not support 64 bit integer
2423 operations.
2424
2425Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2426
2427 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2428 than igen one.
2429 * configure : Rebuild.
72f4393d 2430
c906108c
SS
2431Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2432
2433 * configure: Regenerated to track ../common/aclocal.m4 changes.
2434
2435Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2436
2437 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2438
2439Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2440
2441 * configure: Regenerated to track ../common/aclocal.m4 changes.
2442 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2443
2444Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2445
2446 * configure: Regenerated to track ../common/aclocal.m4 changes.
2447
2448Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2449
2450 * interp.c (Max, Min): Comment out functions. Not yet used.
2451
2452Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2453
2454 * configure: Regenerated to track ../common/aclocal.m4 changes.
2455
2456Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2457
2458 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2459 configurable settings for stand-alone simulator.
72f4393d 2460
c906108c 2461 * configure.in: Added X11 search, just in case.
72f4393d 2462
c906108c
SS
2463 * configure: Regenerated.
2464
2465Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2466
2467 * interp.c (sim_write, sim_read, load_memory, store_memory):
2468 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2469
2470Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2471
2472 * sim-main.h (GETFCC): Return an unsigned value.
2473
2474Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2475
2476 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2477 (DADD): Result destination is RD not RT.
2478
2479Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2480
2481 * sim-main.h (HIACCESS, LOACCESS): Always define.
2482
2483 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2484
2485 * interp.c (sim_info): Delete.
2486
2487Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2488
2489 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2490 (mips_option_handler): New argument `cpu'.
2491 (sim_open): Update call to sim_add_option_table.
2492
2493Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2494
2495 * mips.igen (CxC1): Add tracing.
2496
2497Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2498
2499 * sim-main.h (Max, Min): Declare.
2500
2501 * interp.c (Max, Min): New functions.
2502
2503 * mips.igen (BC1): Add tracing.
72f4393d 2504
c906108c 2505Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2506
c906108c 2507 * interp.c Added memory map for stack in vr4100
72f4393d 2508
c906108c
SS
2509Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2510
2511 * interp.c (load_memory): Add missing "break"'s.
2512
2513Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2514
2515 * interp.c (sim_store_register, sim_fetch_register): Pass in
2516 length parameter. Return -1.
2517
2518Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2519
2520 * interp.c: Added hardware init hook, fixed warnings.
2521
2522Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2523
2524 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2525
2526Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2527
2528 * interp.c (ifetch16): New function.
2529
2530 * sim-main.h (IMEM32): Rename IMEM.
2531 (IMEM16_IMMED): Define.
2532 (IMEM16): Define.
2533 (DELAY_SLOT): Update.
72f4393d 2534
c906108c 2535 * m16run.c (sim_engine_run): New file.
72f4393d 2536
c906108c
SS
2537 * m16.igen: All instructions except LB.
2538 (LB): Call do_load_byte.
2539 * mips.igen (do_load_byte): New function.
2540 (LB): Call do_load_byte.
2541
2542 * mips.igen: Move spec for insn bit size and high bit from here.
2543 * Makefile.in (tmp-igen, tmp-m16): To here.
2544
2545 * m16.dc: New file, decode mips16 instructions.
2546
2547 * Makefile.in (SIM_NO_ALL): Define.
2548 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2549
2550Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2551
2552 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2553 point unit to 32 bit registers.
2554 * configure: Re-generate.
2555
2556Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2557
2558 * configure.in (sim_use_gen): Make IGEN the default simulator
2559 generator for generic 32 and 64 bit mips targets.
2560 * configure: Re-generate.
2561
2562Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2563
2564 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2565 bitsize.
2566
2567 * interp.c (sim_fetch_register, sim_store_register): Read/write
2568 FGR from correct location.
2569 (sim_open): Set size of FGR's according to
2570 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2571
c906108c
SS
2572 * sim-main.h (FGR): Store floating point registers in a separate
2573 array.
2574
2575Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2576
2577 * configure: Regenerated to track ../common/aclocal.m4 changes.
2578
2579Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2580
2581 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2582
2583 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2584
2585 * interp.c (pending_tick): New function. Deliver pending writes.
2586
2587 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2588 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2589 it can handle mixed sized quantites and single bits.
72f4393d 2590
c906108c
SS
2591Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2592
2593 * interp.c (oengine.h): Do not include when building with IGEN.
2594 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2595 (sim_info): Ditto for PROCESSOR_64BIT.
2596 (sim_monitor): Replace ut_reg with unsigned_word.
2597 (*): Ditto for t_reg.
2598 (LOADDRMASK): Define.
2599 (sim_open): Remove defunct check that host FP is IEEE compliant,
2600 using software to emulate floating point.
2601 (value_fpr, ...): Always compile, was conditional on HASFPU.
2602
2603Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2604
2605 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2606 size.
2607
2608 * interp.c (SD, CPU): Define.
2609 (mips_option_handler): Set flags in each CPU.
2610 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2611 (sim_close): Do not clear STATE, deleted anyway.
2612 (sim_write, sim_read): Assume CPU zero's vm should be used for
2613 data transfers.
2614 (sim_create_inferior): Set the PC for all processors.
2615 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2616 argument.
2617 (mips16_entry): Pass correct nr of args to store_word, load_word.
2618 (ColdReset): Cold reset all cpu's.
2619 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2620 (sim_monitor, load_memory, store_memory, signal_exception): Use
2621 `CPU' instead of STATE_CPU.
2622
2623
2624 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2625 SD or CPU_.
72f4393d 2626
c906108c
SS
2627 * sim-main.h (signal_exception): Add sim_cpu arg.
2628 (SignalException*): Pass both SD and CPU to signal_exception.
2629 * interp.c (signal_exception): Update.
72f4393d 2630
c906108c
SS
2631 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2632 Ditto
2633 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2634 address_translation): Ditto
2635 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2636
c906108c
SS
2637Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2638
2639 * configure: Regenerated to track ../common/aclocal.m4 changes.
2640
2641Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2642
2643 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2644
72f4393d 2645 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS
2646
2647 * sim-main.h (CPU_CIA): Delete.
2648 (SET_CIA, GET_CIA): Define
2649
2650Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2651
2652 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2653 regiser.
2654
2655 * configure.in (default_endian): Configure a big-endian simulator
2656 by default.
2657 * configure: Re-generate.
72f4393d 2658
c906108c
SS
2659Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2660
2661 * configure: Regenerated to track ../common/aclocal.m4 changes.
2662
2663Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2664
2665 * interp.c (sim_monitor): Handle Densan monitor outbyte
2666 and inbyte functions.
2667
26681997-12-29 Felix Lee <flee@cygnus.com>
2669
2670 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2671
2672Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2673
2674 * Makefile.in (tmp-igen): Arrange for $zero to always be
2675 reset to zero after every instruction.
2676
2677Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2678
2679 * configure: Regenerated to track ../common/aclocal.m4 changes.
2680 * config.in: Ditto.
2681
2682Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2683
2684 * mips.igen (MSUB): Fix to work like MADD.
2685 * gencode.c (MSUB): Similarly.
2686
2687Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2688
2689 * configure: Regenerated to track ../common/aclocal.m4 changes.
2690
2691Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2692
2693 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2694
2695Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2696
2697 * sim-main.h (sim-fpu.h): Include.
2698
2699 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2700 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2701 using host independant sim_fpu module.
2702
2703Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2704
2705 * interp.c (signal_exception): Report internal errors with SIGABRT
2706 not SIGQUIT.
2707
2708 * sim-main.h (C0_CONFIG): New register.
2709 (signal.h): No longer include.
2710
2711 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2712
2713Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2714
2715 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2716
2717Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2718
2719 * mips.igen: Tag vr5000 instructions.
2720 (ANDI): Was missing mipsIV model, fix assembler syntax.
2721 (do_c_cond_fmt): New function.
2722 (C.cond.fmt): Handle mips I-III which do not support CC field
2723 separatly.
2724 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2725 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2726 in IV3.2 spec.
2727 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2728 vr5000 which saves LO in a GPR separatly.
72f4393d 2729
c906108c
SS
2730 * configure.in (enable-sim-igen): For vr5000, select vr5000
2731 specific instructions.
2732 * configure: Re-generate.
72f4393d 2733
c906108c
SS
2734Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2735
2736 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2737
2738 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2739 fmt_uninterpreted_64 bit cases to switch. Convert to
2740 fmt_formatted,
2741
2742 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2743
2744 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2745 as specified in IV3.2 spec.
2746 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2747
2748Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2749
2750 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2751 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2752 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2753 PENDING_FILL versions of instructions. Simplify.
2754 (X): New function.
2755 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2756 instructions.
2757 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2758 a signed value.
2759 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2760
c906108c
SS
2761 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2762 global.
2763 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2764
2765Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2766
2767 * gencode.c (build_mips16_operands): Replace IPC with cia.
2768
2769 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2770 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2771 IPC to `cia'.
2772 (UndefinedResult): Replace function with macro/function
2773 combination.
2774 (sim_engine_run): Don't save PC in IPC.
2775
2776 * sim-main.h (IPC): Delete.
2777
2778
2779 * interp.c (signal_exception, store_word, load_word,
2780 address_translation, load_memory, store_memory, cache_op,
2781 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2782 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2783 current instruction address - cia - argument.
2784 (sim_read, sim_write): Call address_translation directly.
2785 (sim_engine_run): Rename variable vaddr to cia.
2786 (signal_exception): Pass cia to sim_monitor
72f4393d 2787
c906108c
SS
2788 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2789 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2790 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2791
2792 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2793 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2794 SIM_ASSERT.
72f4393d 2795
c906108c
SS
2796 * interp.c (signal_exception): Pass restart address to
2797 sim_engine_restart.
2798
2799 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2800 idecode.o): Add dependency.
2801
2802 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2803 Delete definitions
2804 (DELAY_SLOT): Update NIA not PC with branch address.
2805 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2806
2807 * mips.igen: Use CIA not PC in branch calculations.
2808 (illegal): Call SignalException.
2809 (BEQ, ADDIU): Fix assembler.
2810
2811Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2812
2813 * m16.igen (JALX): Was missing.
2814
2815 * configure.in (enable-sim-igen): New configuration option.
2816 * configure: Re-generate.
72f4393d 2817
c906108c
SS
2818 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2819
2820 * interp.c (load_memory, store_memory): Delete parameter RAW.
2821 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2822 bypassing {load,store}_memory.
2823
2824 * sim-main.h (ByteSwapMem): Delete definition.
2825
2826 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2827
2828 * interp.c (sim_do_command, sim_commands): Delete mips specific
2829 commands. Handled by module sim-options.
72f4393d 2830
c906108c
SS
2831 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2832 (WITH_MODULO_MEMORY): Define.
2833
2834 * interp.c (sim_info): Delete code printing memory size.
2835
2836 * interp.c (mips_size): Nee sim_size, delete function.
2837 (power2): Delete.
2838 (monitor, monitor_base, monitor_size): Delete global variables.
2839 (sim_open, sim_close): Delete code creating monitor and other
2840 memory regions. Use sim-memopts module, via sim_do_commandf, to
2841 manage memory regions.
2842 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2843
c906108c
SS
2844 * interp.c (address_translation): Delete all memory map code
2845 except line forcing 32 bit addresses.
2846
2847Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2848
2849 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2850 trace options.
2851
2852 * interp.c (logfh, logfile): Delete globals.
2853 (sim_open, sim_close): Delete code opening & closing log file.
2854 (mips_option_handler): Delete -l and -n options.
2855 (OPTION mips_options): Ditto.
2856
2857 * interp.c (OPTION mips_options): Rename option trace to dinero.
2858 (mips_option_handler): Update.
2859
2860Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2861
2862 * interp.c (fetch_str): New function.
2863 (sim_monitor): Rewrite using sim_read & sim_write.
2864 (sim_open): Check magic number.
2865 (sim_open): Write monitor vectors into memory using sim_write.
2866 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2867 (sim_read, sim_write): Simplify - transfer data one byte at a
2868 time.
2869 (load_memory, store_memory): Clarify meaning of parameter RAW.
2870
2871 * sim-main.h (isHOST): Defete definition.
2872 (isTARGET): Mark as depreciated.
2873 (address_translation): Delete parameter HOST.
2874
2875 * interp.c (address_translation): Delete parameter HOST.
2876
2877Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2878
72f4393d 2879 * mips.igen:
c906108c
SS
2880
2881 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2882 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2883
2884Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2885
2886 * mips.igen: Add model filter field to records.
2887
2888Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2889
2890 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2891
c906108c
SS
2892 interp.c (sim_engine_run): Do not compile function sim_engine_run
2893 when WITH_IGEN == 1.
2894
2895 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2896 target architecture.
2897
2898 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2899 igen. Replace with configuration variables sim_igen_flags /
2900 sim_m16_flags.
2901
2902 * m16.igen: New file. Copy mips16 insns here.
2903 * mips.igen: From here.
2904
2905Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2906
2907 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2908 to top.
2909 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2910
2911Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2912
2913 * gencode.c (build_instruction): Follow sim_write's lead in using
2914 BigEndianMem instead of !ByteSwapMem.
2915
2916Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2917
2918 * configure.in (sim_gen): Dependent on target, select type of
2919 generator. Always select old style generator.
2920
2921 configure: Re-generate.
2922
2923 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2924 targets.
2925 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2926 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2927 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2928 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2929 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2930
c906108c
SS
2931Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2932
2933 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2934
2935 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2936 CURRENT_FLOATING_POINT instead.
2937
2938 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2939 (address_translation): Raise exception InstructionFetch when
2940 translation fails and isINSTRUCTION.
72f4393d 2941
c906108c
SS
2942 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2943 sim_engine_run): Change type of of vaddr and paddr to
2944 address_word.
2945 (address_translation, prefetch, load_memory, store_memory,
2946 cache_op): Change type of vAddr and pAddr to address_word.
2947
2948 * gencode.c (build_instruction): Change type of vaddr and paddr to
2949 address_word.
2950
2951Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2952
2953 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2954 macro to obtain result of ALU op.
2955
2956Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2957
2958 * interp.c (sim_info): Call profile_print.
2959
2960Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2961
2962 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2963
2964 * sim-main.h (WITH_PROFILE): Do not define, defined in
2965 common/sim-config.h. Use sim-profile module.
2966 (simPROFILE): Delete defintion.
2967
2968 * interp.c (PROFILE): Delete definition.
2969 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2970 (sim_close): Delete code writing profile histogram.
2971 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2972 Delete.
2973 (sim_engine_run): Delete code profiling the PC.
2974
2975Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2976
2977 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2978
2979 * interp.c (sim_monitor): Make register pointers of type
2980 unsigned_word*.
2981
2982 * sim-main.h: Make registers of type unsigned_word not
2983 signed_word.
2984
2985Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2986
2987 * interp.c (sync_operation): Rename from SyncOperation, make
2988 global, add SD argument.
2989 (prefetch): Rename from Prefetch, make global, add SD argument.
2990 (decode_coproc): Make global.
2991
2992 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2993
2994 * gencode.c (build_instruction): Generate DecodeCoproc not
2995 decode_coproc calls.
2996
2997 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2998 (SizeFGR): Move to sim-main.h
2999 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3000 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3001 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3002 sim-main.h.
3003 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3004 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3005 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3006 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3007 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3008 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3009
c906108c
SS
3010 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3011 exception.
3012 (sim-alu.h): Include.
3013 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3014 (sim_cia): Typedef to instruction_address.
72f4393d 3015
c906108c
SS
3016Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3017
3018 * Makefile.in (interp.o): Rename generated file engine.c to
3019 oengine.c.
72f4393d 3020
c906108c 3021 * interp.c: Update.
72f4393d 3022
c906108c
SS
3023Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3024
3025 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3026
c906108c
SS
3027Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3028
3029 * gencode.c (build_instruction): For "FPSQRT", output correct
3030 number of arguments to Recip.
72f4393d 3031
c906108c
SS
3032Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3033
3034 * Makefile.in (interp.o): Depends on sim-main.h
3035
3036 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3037
3038 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3039 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3040 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3041 STATE, DSSTATE): Define
3042 (GPR, FGRIDX, ..): Define.
3043
3044 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3045 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3046 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3047
c906108c 3048 * interp.c: Update names to match defines from sim-main.h
72f4393d 3049
c906108c
SS
3050Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3051
3052 * interp.c (sim_monitor): Add SD argument.
3053 (sim_warning): Delete. Replace calls with calls to
3054 sim_io_eprintf.
3055 (sim_error): Delete. Replace calls with sim_io_error.
3056 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3057 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3058 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3059 argument.
3060 (mips_size): Rename from sim_size. Add SD argument.
3061
3062 * interp.c (simulator): Delete global variable.
3063 (callback): Delete global variable.
3064 (mips_option_handler, sim_open, sim_write, sim_read,
3065 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3066 sim_size,sim_monitor): Use sim_io_* not callback->*.
3067 (sim_open): ZALLOC simulator struct.
3068 (PROFILE): Do not define.
3069
3070Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3071
3072 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3073 support.h with corresponding code.
3074
3075 * sim-main.h (word64, uword64), support.h: Move definition to
3076 sim-main.h.
3077 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3078
3079 * support.h: Delete
3080 * Makefile.in: Update dependencies
3081 * interp.c: Do not include.
72f4393d 3082
c906108c
SS
3083Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3084
3085 * interp.c (address_translation, load_memory, store_memory,
3086 cache_op): Rename to from AddressTranslation et.al., make global,
3087 add SD argument
72f4393d 3088
c906108c
SS
3089 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3090 CacheOp): Define.
72f4393d 3091
c906108c
SS
3092 * interp.c (SignalException): Rename to signal_exception, make
3093 global.
3094
3095 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3096
c906108c
SS
3097 * sim-main.h (SignalException, SignalExceptionInterrupt,
3098 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3099 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3100 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3101 Define.
72f4393d 3102
c906108c 3103 * interp.c, support.h: Use.
72f4393d 3104
c906108c
SS
3105Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3106
3107 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3108 to value_fpr / store_fpr. Add SD argument.
3109 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3110 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3111
3112 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3113
c906108c
SS
3114Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3115
3116 * interp.c (sim_engine_run): Check consistency between configure
3117 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3118 and HASFPU.
3119
3120 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3121 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS
3122 (mips_endian): Configure WITH_TARGET_ENDIAN.
3123 * configure: Update.
3124
3125Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3126
3127 * configure: Regenerated to track ../common/aclocal.m4 changes.
3128
3129Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3130
3131 * configure: Regenerated.
3132
3133Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3134
3135 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3136
3137Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3138
3139 * gencode.c (print_igen_insn_models): Assume certain architectures
3140 include all mips* instructions.
3141 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3142 instruction.
3143
3144 * Makefile.in (tmp.igen): Add target. Generate igen input from
3145 gencode file.
3146
3147 * gencode.c (FEATURE_IGEN): Define.
3148 (main): Add --igen option. Generate output in igen format.
3149 (process_instructions): Format output according to igen option.
3150 (print_igen_insn_format): New function.
3151 (print_igen_insn_models): New function.
3152 (process_instructions): Only issue warnings and ignore
3153 instructions when no FEATURE_IGEN.
3154
3155Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3156
3157 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3158 MIPS targets.
3159
3160Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3161
3162 * configure: Regenerated to track ../common/aclocal.m4 changes.
3163
3164Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3165
3166 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3167 SIM_RESERVED_BITS): Delete, moved to common.
3168 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3169
c906108c
SS
3170Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3171
3172 * configure.in: Configure non-strict memory alignment.
3173 * configure: Regenerated to track ../common/aclocal.m4 changes.
3174
3175Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3176
3177 * configure: Regenerated to track ../common/aclocal.m4 changes.
3178
3179Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3180
3181 * gencode.c (SDBBP,DERET): Added (3900) insns.
3182 (RFE): Turn on for 3900.
3183 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3184 (dsstate): Made global.
3185 (SUBTARGET_R3900): Added.
3186 (CANCELDELAYSLOT): New.
3187 (SignalException): Ignore SystemCall rather than ignore and
3188 terminate. Add DebugBreakPoint handling.
3189 (decode_coproc): New insns RFE, DERET; and new registers Debug
3190 and DEPC protected by SUBTARGET_R3900.
3191 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3192 bits explicitly.
3193 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3194 * configure: Update.
c906108c
SS
3195
3196Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3197
3198 * gencode.c: Add r3900 (tx39).
72f4393d 3199
c906108c
SS
3200
3201Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3202
3203 * gencode.c (build_instruction): Don't need to subtract 4 for
3204 JALR, just 2.
3205
3206Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3207
3208 * interp.c: Correct some HASFPU problems.
3209
3210Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3211
3212 * configure: Regenerated to track ../common/aclocal.m4 changes.
3213
3214Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3215
3216 * interp.c (mips_options): Fix samples option short form, should
3217 be `x'.
3218
3219Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3220
3221 * interp.c (sim_info): Enable info code. Was just returning.
3222
3223Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3224
3225 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3226 MFC0.
3227
3228Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3229
3230 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3231 constants.
3232 (build_instruction): Ditto for LL.
3233
3234Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3235
3236 * configure: Regenerated to track ../common/aclocal.m4 changes.
3237
3238Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3239
3240 * configure: Regenerated to track ../common/aclocal.m4 changes.
3241 * config.in: Ditto.
3242
3243Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3244
3245 * interp.c (sim_open): Add call to sim_analyze_program, update
3246 call to sim_config.
3247
3248Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3249
3250 * interp.c (sim_kill): Delete.
3251 (sim_create_inferior): Add ABFD argument. Set PC from same.
3252 (sim_load): Move code initializing trap handlers from here.
3253 (sim_open): To here.
3254 (sim_load): Delete, use sim-hload.c.
3255
3256 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3257
3258Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3259
3260 * configure: Regenerated to track ../common/aclocal.m4 changes.
3261 * config.in: Ditto.
3262
3263Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3264
3265 * interp.c (sim_open): Add ABFD argument.
3266 (sim_load): Move call to sim_config from here.
3267 (sim_open): To here. Check return status.
3268
3269Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3270
c906108c
SS
3271 * gencode.c (build_instruction): Two arg MADD should
3272 not assign result to $0.
72f4393d 3273
c906108c
SS
3274Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3275
3276 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3277 * sim/mips/configure.in: Regenerate.
3278
3279Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3280
3281 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3282 signed8, unsigned8 et.al. types.
3283
3284 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3285 hosts when selecting subreg.
3286
3287Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3288
3289 * interp.c (sim_engine_run): Reset the ZERO register to zero
3290 regardless of FEATURE_WARN_ZERO.
3291 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3292
3293Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3294
3295 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3296 (SignalException): For BreakPoints ignore any mode bits and just
3297 save the PC.
3298 (SignalException): Always set the CAUSE register.
3299
3300Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3301
3302 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3303 exception has been taken.
3304
3305 * interp.c: Implement the ERET and mt/f sr instructions.
3306
3307Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3308
3309 * interp.c (SignalException): Don't bother restarting an
3310 interrupt.
3311
3312Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3313
3314 * interp.c (SignalException): Really take an interrupt.
3315 (interrupt_event): Only deliver interrupts when enabled.
3316
3317Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3318
3319 * interp.c (sim_info): Only print info when verbose.
3320 (sim_info) Use sim_io_printf for output.
72f4393d 3321
c906108c
SS
3322Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3323
3324 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3325 mips architectures.
3326
3327Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3328
3329 * interp.c (sim_do_command): Check for common commands if a
3330 simulator specific command fails.
3331
3332Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3333
3334 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3335 and simBE when DEBUG is defined.
3336
3337Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3338
3339 * interp.c (interrupt_event): New function. Pass exception event
3340 onto exception handler.
3341
3342 * configure.in: Check for stdlib.h.
3343 * configure: Regenerate.
3344
3345 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3346 variable declaration.
3347 (build_instruction): Initialize memval1.
3348 (build_instruction): Add UNUSED attribute to byte, bigend,
3349 reverse.
3350 (build_operands): Ditto.
3351
3352 * interp.c: Fix GCC warnings.
3353 (sim_get_quit_code): Delete.
3354
3355 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3356 * Makefile.in: Ditto.
3357 * configure: Re-generate.
72f4393d 3358
c906108c
SS
3359 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3360
3361Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3362
3363 * interp.c (mips_option_handler): New function parse argumes using
3364 sim-options.
3365 (myname): Replace with STATE_MY_NAME.
3366 (sim_open): Delete check for host endianness - performed by
3367 sim_config.
3368 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3369 (sim_open): Move much of the initialization from here.
3370 (sim_load): To here. After the image has been loaded and
3371 endianness set.
3372 (sim_open): Move ColdReset from here.
3373 (sim_create_inferior): To here.
3374 (sim_open): Make FP check less dependant on host endianness.
3375
3376 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3377 run.
3378 * interp.c (sim_set_callbacks): Delete.
3379
3380 * interp.c (membank, membank_base, membank_size): Replace with
3381 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3382 (sim_open): Remove call to callback->init. gdb/run do this.
3383
3384 * interp.c: Update
3385
3386 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3387
3388 * interp.c (big_endian_p): Delete, replaced by
3389 current_target_byte_order.
3390
3391Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3392
3393 * interp.c (host_read_long, host_read_word, host_swap_word,
3394 host_swap_long): Delete. Using common sim-endian.
3395 (sim_fetch_register, sim_store_register): Use H2T.
3396 (pipeline_ticks): Delete. Handled by sim-events.
3397 (sim_info): Update.
3398 (sim_engine_run): Update.
3399
3400Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3401
3402 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3403 reason from here.
3404 (SignalException): To here. Signal using sim_engine_halt.
3405 (sim_stop_reason): Delete, moved to common.
72f4393d 3406
c906108c
SS
3407Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3408
3409 * interp.c (sim_open): Add callback argument.
3410 (sim_set_callbacks): Delete SIM_DESC argument.
3411 (sim_size): Ditto.
3412
3413Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3414
3415 * Makefile.in (SIM_OBJS): Add common modules.
3416
3417 * interp.c (sim_set_callbacks): Also set SD callback.
3418 (set_endianness, xfer_*, swap_*): Delete.
3419 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3420 Change to functions using sim-endian macros.
3421 (control_c, sim_stop): Delete, use common version.
3422 (simulate): Convert into.
3423 (sim_engine_run): This function.
3424 (sim_resume): Delete.
72f4393d 3425
c906108c
SS
3426 * interp.c (simulation): New variable - the simulator object.
3427 (sim_kind): Delete global - merged into simulation.
3428 (sim_load): Cleanup. Move PC assignment from here.
3429 (sim_create_inferior): To here.
3430
3431 * sim-main.h: New file.
3432 * interp.c (sim-main.h): Include.
72f4393d 3433
c906108c
SS
3434Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3435
3436 * configure: Regenerated to track ../common/aclocal.m4 changes.
3437
3438Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3439
3440 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3441
3442Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3443
72f4393d
L
3444 * gencode.c (build_instruction): DIV instructions: check
3445 for division by zero and integer overflow before using
c906108c
SS
3446 host's division operation.
3447
3448Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3449
3450 * Makefile.in (SIM_OBJS): Add sim-load.o.
3451 * interp.c: #include bfd.h.
3452 (target_byte_order): Delete.
3453 (sim_kind, myname, big_endian_p): New static locals.
3454 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3455 after argument parsing. Recognize -E arg, set endianness accordingly.
3456 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3457 load file into simulator. Set PC from bfd.
3458 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3459 (set_endianness): Use big_endian_p instead of target_byte_order.
3460
3461Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3462
3463 * interp.c (sim_size): Delete prototype - conflicts with
3464 definition in remote-sim.h. Correct definition.
3465
3466Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3467
3468 * configure: Regenerated to track ../common/aclocal.m4 changes.
3469 * config.in: Ditto.
3470
3471Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3472
3473 * interp.c (sim_open): New arg `kind'.
3474
3475 * configure: Regenerated to track ../common/aclocal.m4 changes.
3476
3477Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3478
3479 * configure: Regenerated to track ../common/aclocal.m4 changes.
3480
3481Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3482
3483 * interp.c (sim_open): Set optind to 0 before calling getopt.
3484
3485Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3486
3487 * configure: Regenerated to track ../common/aclocal.m4 changes.
3488
3489Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3490
3491 * interp.c : Replace uses of pr_addr with pr_uword64
3492 where the bit length is always 64 independent of SIM_ADDR.
3493 (pr_uword64) : added.
3494
3495Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3496
3497 * configure: Re-generate.
3498
3499Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3500
3501 * configure: Regenerate to track ../common/aclocal.m4 changes.
3502
3503Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3504
3505 * interp.c (sim_open): New SIM_DESC result. Argument is now
3506 in argv form.
3507 (other sim_*): New SIM_DESC argument.
3508
3509Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3510
3511 * interp.c: Fix printing of addresses for non-64-bit targets.
3512 (pr_addr): Add function to print address based on size.
3513
3514Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3515
3516 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3517
3518Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3519
3520 * gencode.c (build_mips16_operands): Correct computation of base
3521 address for extended PC relative instruction.
3522
3523Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3524
3525 * interp.c (mips16_entry): Add support for floating point cases.
3526 (SignalException): Pass floating point cases to mips16_entry.
3527 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3528 registers.
3529 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3530 or fmt_word.
3531 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3532 and then set the state to fmt_uninterpreted.
3533 (COP_SW): Temporarily set the state to fmt_word while calling
3534 ValueFPR.
3535
3536Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3537
3538 * gencode.c (build_instruction): The high order may be set in the
3539 comparison flags at any ISA level, not just ISA 4.
3540
3541Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3542
3543 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3544 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3545 * configure.in: sinclude ../common/aclocal.m4.
3546 * configure: Regenerated.
3547
3548Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3549
3550 * configure: Rebuild after change to aclocal.m4.
3551
3552Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3553
3554 * configure configure.in Makefile.in: Update to new configure
3555 scheme which is more compatible with WinGDB builds.
3556 * configure.in: Improve comment on how to run autoconf.
3557 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3558 * Makefile.in: Use autoconf substitution to install common
3559 makefile fragment.
3560
3561Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3562
3563 * gencode.c (build_instruction): Use BigEndianCPU instead of
3564 ByteSwapMem.
3565
3566Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3567
3568 * interp.c (sim_monitor): Make output to stdout visible in
3569 wingdb's I/O log window.
3570
3571Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3572
3573 * support.h: Undo previous change to SIGTRAP
3574 and SIGQUIT values.
3575
3576Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3577
3578 * interp.c (store_word, load_word): New static functions.
3579 (mips16_entry): New static function.
3580 (SignalException): Look for mips16 entry and exit instructions.
3581 (simulate): Use the correct index when setting fpr_state after
3582 doing a pending move.
3583
3584Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3585
3586 * interp.c: Fix byte-swapping code throughout to work on
3587 both little- and big-endian hosts.
3588
3589Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3590
3591 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3592 with gdb/config/i386/xm-windows.h.
3593
3594Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3595
3596 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3597 that messes up arithmetic shifts.
3598
3599Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3600
3601 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3602 SIGTRAP and SIGQUIT for _WIN32.
3603
3604Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3605
3606 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3607 force a 64 bit multiplication.
3608 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3609 destination register is 0, since that is the default mips16 nop
3610 instruction.
3611
3612Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3613
3614 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3615 (build_endian_shift): Don't check proc64.
3616 (build_instruction): Always set memval to uword64. Cast op2 to
3617 uword64 when shifting it left in memory instructions. Always use
3618 the same code for stores--don't special case proc64.
3619
3620 * gencode.c (build_mips16_operands): Fix base PC value for PC
3621 relative operands.
3622 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3623 jal instruction.
3624 * interp.c (simJALDELAYSLOT): Define.
3625 (JALDELAYSLOT): Define.
3626 (INDELAYSLOT, INJALDELAYSLOT): Define.
3627 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3628
3629Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3630
3631 * interp.c (sim_open): add flush_cache as a PMON routine
3632 (sim_monitor): handle flush_cache by ignoring it
3633
3634Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3635
3636 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3637 BigEndianMem.
3638 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3639 (BigEndianMem): Rename to ByteSwapMem and change sense.
3640 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3641 BigEndianMem references to !ByteSwapMem.
3642 (set_endianness): New function, with prototype.
3643 (sim_open): Call set_endianness.
3644 (sim_info): Use simBE instead of BigEndianMem.
3645 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3646 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3647 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3648 ifdefs, keeping the prototype declaration.
3649 (swap_word): Rewrite correctly.
3650 (ColdReset): Delete references to CONFIG. Delete endianness related
3651 code; moved to set_endianness.
72f4393d 3652
c906108c
SS
3653Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3654
3655 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3656 * interp.c (CHECKHILO): Define away.
3657 (simSIGINT): New macro.
3658 (membank_size): Increase from 1MB to 2MB.
3659 (control_c): New function.
3660 (sim_resume): Rename parameter signal to signal_number. Add local
3661 variable prev. Call signal before and after simulate.
3662 (sim_stop_reason): Add simSIGINT support.
3663 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3664 functions always.
3665 (sim_warning): Delete call to SignalException. Do call printf_filtered
3666 if logfh is NULL.
3667 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3668 a call to sim_warning.
3669
3670Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3671
3672 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3673 16 bit instructions.
3674
3675Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3676
3677 Add support for mips16 (16 bit MIPS implementation):
3678 * gencode.c (inst_type): Add mips16 instruction encoding types.
3679 (GETDATASIZEINSN): Define.
3680 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3681 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3682 mtlo.
3683 (MIPS16_DECODE): New table, for mips16 instructions.
3684 (bitmap_val): New static function.
3685 (struct mips16_op): Define.
3686 (mips16_op_table): New table, for mips16 operands.
3687 (build_mips16_operands): New static function.
3688 (process_instructions): If PC is odd, decode a mips16
3689 instruction. Break out instruction handling into new
3690 build_instruction function.
3691 (build_instruction): New static function, broken out of
3692 process_instructions. Check modifiers rather than flags for SHIFT
3693 bit count and m[ft]{hi,lo} direction.
3694 (usage): Pass program name to fprintf.
3695 (main): Remove unused variable this_option_optind. Change
3696 ``*loptarg++'' to ``loptarg++''.
3697 (my_strtoul): Parenthesize && within ||.
3698 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3699 (simulate): If PC is odd, fetch a 16 bit instruction, and
3700 increment PC by 2 rather than 4.
3701 * configure.in: Add case for mips16*-*-*.
3702 * configure: Rebuild.
3703
3704Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3705
3706 * interp.c: Allow -t to enable tracing in standalone simulator.
3707 Fix garbage output in trace file and error messages.
3708
3709Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3710
3711 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3712 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3713 * configure.in: Simplify using macros in ../common/aclocal.m4.
3714 * configure: Regenerated.
3715 * tconfig.in: New file.
3716
3717Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3718
3719 * interp.c: Fix bugs in 64-bit port.
3720 Use ansi function declarations for msvc compiler.
3721 Initialize and test file pointer in trace code.
3722 Prevent duplicate definition of LAST_EMED_REGNUM.
3723
3724Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3725
3726 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3727
3728Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3729
3730 * interp.c (SignalException): Check for explicit terminating
3731 breakpoint value.
3732 * gencode.c: Pass instruction value through SignalException()
3733 calls for Trap, Breakpoint and Syscall.
3734
3735Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3736
3737 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3738 only used on those hosts that provide it.
3739 * configure.in: Add sqrt() to list of functions to be checked for.
3740 * config.in: Re-generated.
3741 * configure: Re-generated.
3742
3743Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3744
3745 * gencode.c (process_instructions): Call build_endian_shift when
3746 expanding STORE RIGHT, to fix swr.
3747 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3748 clear the high bits.
3749 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3750 Fix float to int conversions to produce signed values.
3751
3752Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3753
3754 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3755 (process_instructions): Correct handling of nor instruction.
3756 Correct shift count for 32 bit shift instructions. Correct sign
3757 extension for arithmetic shifts to not shift the number of bits in
3758 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3759 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3760 Fix madd.
3761 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3762 It's OK to have a mult follow a mult. What's not OK is to have a
3763 mult follow an mfhi.
3764 (Convert): Comment out incorrect rounding code.
3765
3766Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3767
3768 * interp.c (sim_monitor): Improved monitor printf
3769 simulation. Tidied up simulator warnings, and added "--log" option
3770 for directing warning message output.
3771 * gencode.c: Use sim_warning() rather than WARNING macro.
3772
3773Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3774
3775 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3776 getopt1.o, rather than on gencode.c. Link objects together.
3777 Don't link against -liberty.
3778 (gencode.o, getopt.o, getopt1.o): New targets.
3779 * gencode.c: Include <ctype.h> and "ansidecl.h".
3780 (AND): Undefine after including "ansidecl.h".
3781 (ULONG_MAX): Define if not defined.
3782 (OP_*): Don't define macros; now defined in opcode/mips.h.
3783 (main): Call my_strtoul rather than strtoul.
3784 (my_strtoul): New static function.
3785
3786Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3787
3788 * gencode.c (process_instructions): Generate word64 and uword64
3789 instead of `long long' and `unsigned long long' data types.
3790 * interp.c: #include sysdep.h to get signals, and define default
3791 for SIGBUS.
3792 * (Convert): Work around for Visual-C++ compiler bug with type
3793 conversion.
3794 * support.h: Make things compile under Visual-C++ by using
3795 __int64 instead of `long long'. Change many refs to long long
3796 into word64/uword64 typedefs.
3797
3798Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3799
72f4393d
L
3800 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3801 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3802 (docdir): Removed.
3803 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3804 (AC_PROG_INSTALL): Added.
c906108c 3805 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L
3806 * configure: Rebuilt.
3807
c906108c
SS
3808Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3809
3810 * configure.in: Define @SIMCONF@ depending on mips target.
3811 * configure: Rebuild.
3812 * Makefile.in (run): Add @SIMCONF@ to control simulator
3813 construction.
3814 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3815 * interp.c: Remove some debugging, provide more detailed error
3816 messages, update memory accesses to use LOADDRMASK.
72f4393d 3817
c906108c
SS
3818Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3819
3820 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3821 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3822 stamp-h.
3823 * configure: Rebuild.
3824 * config.in: New file, generated by autoheader.
3825 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3826 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3827 HAVE_ANINT and HAVE_AINT, as appropriate.
3828 * Makefile.in (run): Use @LIBS@ rather than -lm.
3829 (interp.o): Depend upon config.h.
3830 (Makefile): Just rebuild Makefile.
3831 (clean): Remove stamp-h.
3832 (mostlyclean): Make the same as clean, not as distclean.
3833 (config.h, stamp-h): New targets.
3834
3835Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3836
3837 * interp.c (ColdReset): Fix boolean test. Make all simulator
3838 globals static.
3839
3840Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3841
3842 * interp.c (xfer_direct_word, xfer_direct_long,
3843 swap_direct_word, swap_direct_long, xfer_big_word,
3844 xfer_big_long, xfer_little_word, xfer_little_long,
3845 swap_word,swap_long): Added.
3846 * interp.c (ColdReset): Provide function indirection to
3847 host<->simulated_target transfer routines.
3848 * interp.c (sim_store_register, sim_fetch_register): Updated to
3849 make use of indirected transfer routines.
3850
3851Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3852
3853 * gencode.c (process_instructions): Ensure FP ABS instruction
3854 recognised.
3855 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3856 system call support.
3857
3858Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3859
3860 * interp.c (sim_do_command): Complain if callback structure not
3861 initialised.
3862
3863Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3864
3865 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3866 support for Sun hosts.
3867 * Makefile.in (gencode): Ensure the host compiler and libraries
3868 used for cross-hosted build.
3869
3870Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3871
3872 * interp.c, gencode.c: Some more (TODO) tidying.
3873
3874Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3875
3876 * gencode.c, interp.c: Replaced explicit long long references with
3877 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3878 * support.h (SET64LO, SET64HI): Macros added.
3879
3880Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3881
3882 * configure: Regenerate with autoconf 2.7.
3883
3884Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3885
3886 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3887 * support.h: Remove superfluous "1" from #if.
3888 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3889
3890Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3891
3892 * interp.c (StoreFPR): Control UndefinedResult() call on
3893 WARN_RESULT manifest.
3894
3895Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3896
3897 * gencode.c: Tidied instruction decoding, and added FP instruction
3898 support.
3899
3900 * interp.c: Added dineroIII, and BSD profiling support. Also
3901 run-time FP handling.
3902
3903Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3904
3905 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3906 gencode.c, interp.c, support.h: created.
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