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[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
d4e3adda
MF		 12021-01-30 Mike Frysinger <vapier@gentoo.org>
2
3 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
4
68ed2854
MF		 52021-01-11 Mike Frysinger <vapier@gentoo.org>
6
7 * config.in, configure: Regenerate.
8 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
9 and strings.h include.
10
50df264d
MF		 112021-01-09 Mike Frysinger <vapier@gentoo.org>
12
13 * configure: Regenerate.
14
bf470982
MF		 152021-01-09 Mike Frysinger <vapier@gentoo.org>
16
17 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
18 * configure: Regenerate.
19
46f900c0
MF		 202021-01-08 Mike Frysinger <vapier@gentoo.org>
21
22 * configure: Regenerate.
23
dfb856ba
MF		 242021-01-04 Mike Frysinger <vapier@gentoo.org>
25
26 * configure: Regenerate.
27
382bc56b
PK		 282020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
29
30 * sim-main.c: Include <stdlib.h>.
31
ad9675dd
PK		 322020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
33
34 * cp1.c: Include <stdlib.h>.
35
f693213d
SM		 362020-07-29 Simon Marchi <simon.marchi@efficios.com>
37
38 * configure: Re-generate.
39
5c887dd5
JB		 402017-09-06 John Baldwin <jhb@FreeBSD.org>
41
42 * configure: Regenerate.
43
91588b3a
MF		 442016-11-11 Mike Frysinger <vapier@gentoo.org>
45
6cb2202b 46 PR sim/20808
91588b3a
MF		 47 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
48 and SD to sd.
49
e04659e8
MF		 502016-11-11 Mike Frysinger <vapier@gentoo.org>
51
6cb2202b 52 PR sim/20809
e04659e8
MF		 53 * mips.igen (check_u64): Enable for `r3900'.
54
1554f758
MF		 552016-02-05 Mike Frysinger <vapier@gentoo.org>
56
57 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
58 STATE_PROG_BFD (sd).
59 * configure: Regenerate.
60
3d304f48
AB		 612016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
62 Maciej W. Rozycki <macro@imgtec.com>
63
64 PR sim/19441
65 * micromips.igen (delayslot_micromips): Enable for `micromips32',
66 `micromips64' and `micromipsdsp' only.
67 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
68 (do_micromips_jalr, do_micromips_jal): Likewise.
69 (compute_movep_src_reg): Likewise.
70 (compute_andi16_imm): Likewise.
71 (convert_fmt_micromips): Likewise.
72 (convert_fmt_micromips_cvt_d): Likewise.
73 (convert_fmt_micromips_cvt_s): Likewise.
74 (FMT_MICROMIPS): Likewise.
75 (FMT_MICROMIPS_CVT_D): Likewise.
76 (FMT_MICROMIPS_CVT_S): Likewise.
77
b36d953b
MF		 782016-01-12 Mike Frysinger <vapier@gentoo.org>
79
80 * interp.c: Include elf-bfd.h.
81 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
82 ELFCLASS32.
83
ce39bd38
MF		 842016-01-10 Mike Frysinger <vapier@gentoo.org>
85
86 * config.in, configure: Regenerate.
87
99d8e879
MF		 882016-01-10 Mike Frysinger <vapier@gentoo.org>
89
90 * configure: Regenerate.
91
35656e95
MF		 922016-01-10 Mike Frysinger <vapier@gentoo.org>
93
94 * configure: Regenerate.
95
16f7876d
MF		 962016-01-10 Mike Frysinger <vapier@gentoo.org>
97
98 * configure: Regenerate.
99
e19418e0
MF		 1002016-01-10 Mike Frysinger <vapier@gentoo.org>
101
102 * configure: Regenerate.
103
6d90347b
MF		 1042016-01-10 Mike Frysinger <vapier@gentoo.org>
105
106 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
107 * configure: Regenerate.
108
347fe5bb
MF		 1092016-01-10 Mike Frysinger <vapier@gentoo.org>
110
111 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
112 * configure: Regenerate.
113
22be3fbe
MF		 1142016-01-10 Mike Frysinger <vapier@gentoo.org>
115
116 * configure: Regenerate.
117
0dc73ef7
MF		 1182016-01-10 Mike Frysinger <vapier@gentoo.org>
119
120 * configure: Regenerate.
121
936df756
MF		 1222016-01-09 Mike Frysinger <vapier@gentoo.org>
123
124 * config.in, configure: Regenerate.
125
2e3d4f4d
MF		 1262016-01-06 Mike Frysinger <vapier@gentoo.org>
127
128 * interp.c (sim_open): Mark argv const.
129 (sim_create_inferior): Mark argv and env const.
130
9bbf6f91
MF		 1312016-01-04 Mike Frysinger <vapier@gentoo.org>
132
133 * configure: Regenerate.
134
77cf2ef5
MF		 1352016-01-03 Mike Frysinger <vapier@gentoo.org>
136
137 * interp.c (sim_open): Update sim_parse_args comment.
138
0cb8d851
MF		 1392016-01-03 Mike Frysinger <vapier@gentoo.org>
140
141 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
142 * configure: Regenerate.
143
1ac72f06
MF		 1442016-01-02 Mike Frysinger <vapier@gentoo.org>
145
146 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
147 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
148 * configure: Regenerate.
149 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
150
d47f5b30
MF		 1512016-01-02 Mike Frysinger <vapier@gentoo.org>
152
153 * dv-tx3904cpu.c (CPU, SD): Delete.
154
e1211e55
MF		 1552015-12-30 Mike Frysinger <vapier@gentoo.org>
156
157 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
158 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
159 (sim_store_register): Rename to ...
160 (mips_reg_store): ... this. Delete local cpu var.
161 Update sim_io_eprintf calls.
162 (sim_fetch_register): Rename to ...
163 (mips_reg_fetch): ... this. Delete local cpu var.
164 Update sim_io_eprintf calls.
165
5e744ef8
MF		 1662015-12-27 Mike Frysinger <vapier@gentoo.org>
167
168 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
169
1b393626
MF		 1702015-12-26 Mike Frysinger <vapier@gentoo.org>
171
172 * config.in, configure: Regenerate.
173
26f8bf63
MF		 1742015-12-26 Mike Frysinger <vapier@gentoo.org>
175
176 * interp.c (sim_write, sim_read): Delete.
177 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
178 (load_word): Likewise.
179 * micromips.igen (cache): Likewise.
180 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
181 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
182 do_store_left, do_store_right, do_load_double, do_store_double):
183 Likewise.
184 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
185 (do_prefx): Likewise.
186 * sim-main.c (address_translation, prefetch): Delete.
187 (ifetch32, ifetch16): Delete call to AddressTranslation and set
188 paddr=vaddr.
189 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
190 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
191 (LoadMemory, StoreMemory): Delete CCA arg.
192
ef04e371
MF		 1932015-12-24 Mike Frysinger <vapier@gentoo.org>
194
195 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
196 * configure: Regenerated.
197
cb379ede
MF		 1982015-12-24 Mike Frysinger <vapier@gentoo.org>
199
200 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
201 * tconfig.h: Delete.
202
26936211
MF		 2032015-12-24 Mike Frysinger <vapier@gentoo.org>
204
205 * tconfig.h (SIM_HANDLES_LMA): Delete.
206
84e8e361
MF		 2072015-12-24 Mike Frysinger <vapier@gentoo.org>
208
209 * sim-main.h (WITH_WATCHPOINTS): Delete.
210
3cabaf66
MF		 2112015-12-24 Mike Frysinger <vapier@gentoo.org>
212
213 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
214
8abe6c66
MF		 2152015-12-24 Mike Frysinger <vapier@gentoo.org>
216
217 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
218
1d19cae7
DV		 2192015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
220
221 * micromips.igen (process_isa_mode): Fix left shift of negative
222 value.
223
cdf850e9
MF		 2242015-11-17 Mike Frysinger <vapier@gentoo.org>
225
226 * sim-main.h (WITH_MODULO_MEMORY): Delete.
227
797eee42
MF		 2282015-11-15 Mike Frysinger <vapier@gentoo.org>
229
230 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
231
6e4f085c
MF		 2322015-11-14 Mike Frysinger <vapier@gentoo.org>
233
234 * interp.c (sim_close): Rename to ...
235 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
236 sim_io_shutdown.
237 * sim-main.h (mips_sim_close): Declare.
238 (SIM_CLOSE_HOOK): Define.
239
8e394ffc
AB		 2402015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
241 Ali Lown <ali.lown@imgtec.com>
242
243 * Makefile.in (tmp-micromips): New rule.
244 (tmp-mach-multi): Add support for micromips.
245 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
246 that works for both mips64 and micromips64.
247 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
248 micromips32.
249 Add build support for micromips.
250 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
251 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
252 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
253 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
254 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
255 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
256 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
257 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
258 Refactored instruction code to use these functions.
259 * dsp2.igen: Refactored instruction code to use the new functions.
260 * interp.c (decode_coproc): Refactored to work with any instruction
261 encoding.
262 (isa_mode): New variable
263 (RSVD_INSTRUCTION): Changed to 0x00000039.
264 * m16.igen (BREAK16): Refactored instruction to use do_break16.
265 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
266 * micromips.dc: New file.
267 * micromips.igen: New file.
268 * micromips16.dc: New file.
269 * micromipsdsp.igen: New file.
270 * micromipsrun.c: New file.
271 * mips.igen (do_swc1): Changed to work with any instruction encoding.
272 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
273 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
274 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
275 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
276 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
277 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
278 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
279 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
280 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
281 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
282 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
283 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
284 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
285 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
286 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
287 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
288 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
289 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
290 instructions.
291 Refactored instruction code to use these functions.
292 (RSVD): Changed to use new reserved instruction.
293 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
294 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
295 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
296 do_store_double): Added micromips32 and micromips64 models.
297 Added include for micromips.igen and micromipsdsp.igen
298 Add micromips32 and micromips64 models.
299 (DecodeCoproc): Updated to use new macro definition.
300 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
301 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
302 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
303 Refactored instruction code to use these functions.
304 * sim-main.h (CP0_operation): New enum.
305 (DecodeCoproc): Updated macro.
306 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
307 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
308 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
309 ISA_MODE_MICROMIPS): New defines.
310 (sim_state): Add isa_mode field.
311
8d0978fb
MF		 3122015-06-23 Mike Frysinger <vapier@gentoo.org>
313
314 * configure: Regenerate.
315
306f4178
MF		 3162015-06-12 Mike Frysinger <vapier@gentoo.org>
317
318 * configure.ac: Change configure.in to configure.ac.
319 * configure: Regenerate.
320
a3487082
MF		 3212015-06-12 Mike Frysinger <vapier@gentoo.org>
322
323 * configure: Regenerate.
324
29bc024d
MF		 3252015-06-12 Mike Frysinger <vapier@gentoo.org>
326
327 * interp.c [TRACE]: Delete.
328 (TRACE): Change to WITH_TRACE_ANY_P.
329 [!WITH_TRACE_ANY_P] (open_trace): Define.
330 (mips_option_handler, open_trace, sim_close, dotrace):
331 Change defined(TRACE) to WITH_TRACE_ANY_P.
332 (sim_open): Delete TRACE ifdef check.
333 * sim-main.c (load_memory): Delete TRACE ifdef check.
334 (store_memory): Likewise.
335 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
336 [!WITH_TRACE_ANY_P] (dotrace): Define.
337
3ebe2863
MF		 3382015-04-18 Mike Frysinger <vapier@gentoo.org>
339
340 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
341 comments.
342
20bca71d
MF		 3432015-04-18 Mike Frysinger <vapier@gentoo.org>
344
345 * sim-main.h (SIM_CPU): Delete.
346
7e83aa92
MF		 3472015-04-18 Mike Frysinger <vapier@gentoo.org>
348
349 * sim-main.h (sim_cia): Delete.
350
034685f9
MF		 3512015-04-17 Mike Frysinger <vapier@gentoo.org>
352
353 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
354 PU_PC_GET.
355 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
356 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
357 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
358 CIA_SET to CPU_PC_SET.
359 * sim-main.h (CIA_GET, CIA_SET): Delete.
360
78e9aa70
MF		 3612015-04-15 Mike Frysinger <vapier@gentoo.org>
362
363 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
364 * sim-main.h (STATE_CPU): Delete.
365
bf12d44e
MF		 3662015-04-13 Mike Frysinger <vapier@gentoo.org>
367
368 * configure: Regenerate.
369
7bebb329
MF		 3702015-04-13 Mike Frysinger <vapier@gentoo.org>
371
372 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
373 * interp.c (mips_pc_get, mips_pc_set): New functions.
374 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
375 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
376 (sim_pc_get): Delete.
377 * sim-main.h (SIM_CPU): Define.
378 (struct sim_state): Change cpu to an array of pointers.
379 (STATE_CPU): Drop &.
380
8ac57fbd
MF		 3812015-04-13 Mike Frysinger <vapier@gentoo.org>
382
383 * interp.c (mips_option_handler, open_trace, sim_close,
384 sim_write, sim_read, sim_store_register, sim_fetch_register,
385 sim_create_inferior, pr_addr, pr_uword64): Convert old style
386 prototypes.
387 (sim_open): Convert old style prototype. Change casts with
388 sim_write to unsigned char *.
389 (fetch_str): Change null to unsigned char, and change cast to
390 unsigned char *.
391 (sim_monitor): Change c & ch to unsigned char. Change cast to
392 unsigned char *.
393
e787f858
MF		 3942015-04-12 Mike Frysinger <vapier@gentoo.org>
395
396 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
397
122bbfb5
MF		 3982015-04-06 Mike Frysinger <vapier@gentoo.org>
399
400 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
401
0fe84f3f
MF		 4022015-04-01 Mike Frysinger <vapier@gentoo.org>
403
404 * tconfig.h (SIM_HAVE_PROFILE): Delete.
405
aadc9410
MF		 4062015-03-31 Mike Frysinger <vapier@gentoo.org>
407
408 * config.in, configure: Regenerate.
409
05f53ed6
MF		 4102015-03-24 Mike Frysinger <vapier@gentoo.org>
411
412 * interp.c (sim_pc_get): New function.
413
c0931f26
MF		 4142015-03-24 Mike Frysinger <vapier@gentoo.org>
415
416 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
417 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
418
30452bbe
MF		 4192015-03-24 Mike Frysinger <vapier@gentoo.org>
420
421 * configure: Regenerate.
422
64dd13df
MF		 4232015-03-23 Mike Frysinger <vapier@gentoo.org>
424
425 * configure: Regenerate.
426
49cd1634
MF		 4272015-03-23 Mike Frysinger <vapier@gentoo.org>
428
429 * configure: Regenerate.
430 * configure.ac (mips_extra_objs): Delete.
431 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
432 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
433
3649cb06
MF		 4342015-03-23 Mike Frysinger <vapier@gentoo.org>
435
436 * configure: Regenerate.
437 * configure.ac: Delete sim_hw checks for dv-sockser.
438
ae7d0cac
MF		 4392015-03-16 Mike Frysinger <vapier@gentoo.org>
440
441 * config.in, configure: Regenerate.
442 * tconfig.in: Rename file ...
443 * tconfig.h: ... here.
444
8406bb59
MF		 4452015-03-15 Mike Frysinger <vapier@gentoo.org>
446
447 * tconfig.in: Delete includes.
448 [HAVE_DV_SOCKSER]: Delete.
449
465fb143
MF		 4502015-03-14 Mike Frysinger <vapier@gentoo.org>
451
452 * Makefile.in (SIM_RUN_OBJS): Delete.
453
5cddc23a
MF		 4542015-03-14 Mike Frysinger <vapier@gentoo.org>
455
456 * configure.ac (AC_CHECK_HEADERS): Delete.
457 * aclocal.m4, configure: Regenerate.
458
2974be62
AM		 4592014-08-19 Alan Modra <amodra@gmail.com>
460
461 * configure: Regenerate.
462
faa743bb
RM		 4632014-08-15 Roland McGrath <mcgrathr@google.com>
464
465 * configure: Regenerate.
466 * config.in: Regenerate.
467
1a8a700e
MF		 4682014-03-04 Mike Frysinger <vapier@gentoo.org>
469
470 * configure: Regenerate.
471
bf3d9781
AM		 4722013-09-23 Alan Modra <amodra@gmail.com>
473
474 * configure: Regenerate.
475
31e6ad7d
MF		 4762013-06-03 Mike Frysinger <vapier@gentoo.org>
477
478 * aclocal.m4, configure: Regenerate.
479
d3685d60
TT		 4802013-05-10 Freddie Chopin <freddie_chopin@op.pl>
481
482 * configure: Rebuild.
483
1517bd27
MF		 4842013-03-26 Mike Frysinger <vapier@gentoo.org>
485
486 * configure: Regenerate.
487
3be31516
JS		 4882013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
489
490 * configure.ac: Address use of dv-sockser.o.
491 * tconfig.in: Conditionalize use of dv_sockser_install.
492 * configure: Regenerated.
493 * config.in: Regenerated.
494
37cb8f8e
SE		 4952012-10-04 Chao-ying Fu <fu@mips.com>
496 Steve Ellcey <sellcey@mips.com>
497
498 * mips/mips3264r2.igen (rdhwr): New.
499
87c8644f
JS		 5002012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
501
502 * configure.ac: Always link against dv-sockser.o.
503 * configure: Regenerate.
504
5f3ef9d0
JB		 5052012-06-15 Joel Brobecker <brobecker@adacore.com>
506
507 * config.in, configure: Regenerate.
508
a6ff997c
NC		 5092012-05-18 Nick Clifton <nickc@redhat.com>
510
511 PR 14072
512 * interp.c: Include config.h before system header files.
513
2232061b
MF		 5142012-03-24 Mike Frysinger <vapier@gentoo.org>
515
516 * aclocal.m4, config.in, configure: Regenerate.
517
db2e4d67
MF		 5182011-12-03 Mike Frysinger <vapier@gentoo.org>
519
520 * aclocal.m4: New file.
521 * configure: Regenerate.
522
4399a56b
MF		 5232011-10-19 Mike Frysinger <vapier@gentoo.org>
524
525 * configure: Regenerate after common/acinclude.m4 update.
526
9c082ca8
MF		 5272011-10-17 Mike Frysinger <vapier@gentoo.org>
528
529 * configure.ac: Change include to common/acinclude.m4.
530
6ffe910a
MF		 5312011-10-17 Mike Frysinger <vapier@gentoo.org>
532
533 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
534 call. Replace common.m4 include with SIM_AC_COMMON.
535 * configure: Regenerate.
536
31b28250
HPN		 5372011-07-08 Hans-Peter Nilsson <hp@axis.com>
538
3faa01e3
HPN		 539 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
540 $(SIM_EXTRA_DEPS).
541 (tmp-mach-multi): Exit early when igen fails.
31b28250 542
2419798b
MF		 5432011-07-05 Mike Frysinger <vapier@gentoo.org>
544
545 * interp.c (sim_do_command): Delete.
546
d79fe0d6
MF		 5472011-02-14 Mike Frysinger <vapier@gentoo.org>
548
549 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
550 (tx3904sio_fifo_reset): Likewise.
551 * interp.c (sim_monitor): Likewise.
552
5558e7e6
MF		 5532010-04-14 Mike Frysinger <vapier@gentoo.org>
554
555 * interp.c (sim_write): Add const to buffer arg.
556
35aafff4
JB		 5572010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
558
559 * interp.c: Don't include sysdep.h
560
3725885a
RW		 5612010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
562
563 * configure: Regenerate.
564
d6416cdc
RW		 5652009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
566
81ecdfbb
RW		 567 * config.in: Regenerate.
568 * configure: Likewise.
569
d6416cdc
RW		 570 * configure: Regenerate.
571
b5bd9624
HPN		 5722008-07-11 Hans-Peter Nilsson <hp@axis.com>
573
574 * configure: Regenerate to track ../common/common.m4 changes.
575 * config.in: Ditto.
576
6efef468 5772008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 578 Daniel Jacobowitz <dan@codesourcery.com>
579 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 580
581 * configure: Regenerate.
582
60dc88db
RS		 5832007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
584
585 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
586 that unconditionally allows fmt_ps.
587 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
588 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
589 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
590 filter from 64,f to 32,f.
591 (PREFX): Change filter from 64 to 32.
592 (LDXC1, LUXC1): Provide separate mips32r2 implementations
593 that use do_load_double instead of do_load. Make both LUXC1
594 versions unpredictable if SizeFGR () != 64.
595 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
596 instead of do_store. Remove unused variable. Make both SUXC1
597 versions unpredictable if SizeFGR () != 64.
598
599ca73e
RS		 5992007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
600
601 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
602 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
603 shifts for that case.
604
2525df03
NC		 6052007-09-04 Nick Clifton <nickc@redhat.com>
606
607 * interp.c (options enum): Add OPTION_INFO_MEMORY.
608 (display_mem_info): New static variable.
609 (mips_option_handler): Handle OPTION_INFO_MEMORY.
610 (mips_options): Add info-memory and memory-info.
611 (sim_open): After processing the command line and board
612 specification, check display_mem_info. If it is set then
613 call the real handler for the --memory-info command line
614 switch.
615
35ee6e1e
JB		 6162007-08-24 Joel Brobecker <brobecker@adacore.com>
617
618 * configure.ac: Change license of multi-run.c to GPL version 3.
619 * configure: Regenerate.
620
d5fb0879
RS		 6212007-06-28 Richard Sandiford <richard@codesourcery.com>
622
623 * configure.ac, configure: Revert last patch.
624
2a2ce21b
RS		 6252007-06-26 Richard Sandiford <richard@codesourcery.com>
626
627 * configure.ac (sim_mipsisa3264_configs): New variable.
628 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
629 every configuration support all four targets, using the triplet to
630 determine the default.
631 * configure: Regenerate.
632
efdcccc9
RS		 6332007-06-25 Richard Sandiford <richard@codesourcery.com>
634
0a7692b2 635 * Makefile.in (m16run.o): New rule.
efdcccc9 636
f532a356
TS		 6372007-05-15 Thiemo Seufer <ths@mips.com>
638
639 * mips3264r2.igen (DSHD): Fix compile warning.
640
bfe9c90b
TS		 6412007-05-14 Thiemo Seufer <ths@mips.com>
642
643 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
644 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
645 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
646 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
647 for mips32r2.
648
53f4826b
TS		 6492007-03-01 Thiemo Seufer <ths@mips.com>
650
651 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
652 and mips64.
653
8bf3ddc8
TS		 6542007-02-20 Thiemo Seufer <ths@mips.com>
655
656 * dsp.igen: Update copyright notice.
657 * dsp2.igen: Fix copyright notice.
658
8b082fb1 6592007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 660 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 661
662 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
663 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
664 Add dsp2 to sim_igen_machine.
665 * configure: Regenerate.
666 * dsp.igen (do_ph_op): Add MUL support when op = 2.
667 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
668 (mulq_rs.ph): Use do_ph_mulq.
669 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
670 * mips.igen: Add dsp2 model and include dsp2.igen.
671 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
672 for *mips32r2, *mips64r2, *dsp.
673 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
674 for *mips32r2, *mips64r2, *dsp2.
675 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
676
b1004875 6772007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 678 Nigel Stephens <nigel@mips.com>
b1004875
TS		 679
680 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
681 jumps with hazard barrier.
682
f8df4c77 6832007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 684 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 685
686 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
687 after each call to sim_io_write.
688
b1004875 6892007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 690 Nigel Stephens <nigel@mips.com>
b1004875
TS		 691
692 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
693 supported by this simulator.
07802d98
TS		 694 (decode_coproc): Recognise additional CP0 Config registers
695 correctly.
696
14fb6c5a 6972007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 698 Nigel Stephens <nigel@mips.com>
699 David Ung <davidu@mips.com>
14fb6c5a
TS		 700
701 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
702 uninterpreted formats. If fmt is one of the uninterpreted types
703 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
704 fmt_word, and fmt_uninterpreted_64 like fmt_long.
705 (store_fpr): When writing an invalid odd register, set the
706 matching even register to fmt_unknown, not the following register.
707 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
708 the the memory window at offset 0 set by --memory-size command
709 line option.
710 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
711 point register.
712 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
713 register.
714 (sim_monitor): When returning the memory size to the MIPS
715 application, use the value in STATE_MEM_SIZE, not an arbitrary
716 hardcoded value.
717 (cop_lw): Don' mess around with FPR_STATE, just pass
718 fmt_uninterpreted_32 to StoreFPR.
719 (cop_sw): Similarly.
720 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
721 (cop_sd): Similarly.
722 * mips.igen (not_word_value): Single version for mips32, mips64
723 and mips16.
724
c8847145 7252007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 726 Nigel Stephens <nigel@mips.com>
c8847145
TS		 727
728 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
729 MBytes.
730
4b5d35ee
TS		 7312007-02-17 Thiemo Seufer <ths@mips.com>
732
733 * configure.ac (mips*-sde-elf*): Move in front of generic machine
734 configuration.
735 * configure: Regenerate.
736
3669427c
TS		 7372007-02-17 Thiemo Seufer <ths@mips.com>
738
739 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
740 Add mdmx to sim_igen_machine.
741 (mipsisa64*-*-*): Likewise. Remove dsp.
742 (mipsisa32*-*-*): Remove dsp.
743 * configure: Regenerate.
744
109ad085
TS		 7452007-02-13 Thiemo Seufer <ths@mips.com>
746
747 * configure.ac: Add mips*-sde-elf* target.
748 * configure: Regenerate.
749
921d7ad3
HPN		 7502006-12-21 Hans-Peter Nilsson <hp@axis.com>
751
752 * acconfig.h: Remove.
753 * config.in, configure: Regenerate.
754
02f97da7
TS		 7552006-11-07 Thiemo Seufer <ths@mips.com>
756
757 * dsp.igen (do_w_op): Fix compiler warning.
758
2d2733fc 7592006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 760 David Ung <davidu@mips.com>
2d2733fc
TS		 761
762 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
763 sim_igen_machine.
764 * configure: Regenerate.
765 * mips.igen (model): Add smartmips.
766 (MADDU): Increment ACX if carry.
767 (do_mult): Clear ACX.
768 (ROR,RORV): Add smartmips.
72f4393d 769 (include): Include smartmips.igen.
2d2733fc
TS		 770 * sim-main.h (ACX): Set to REGISTERS[89].
771 * smartmips.igen: New file.
772
d85c3a10 7732006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 774 David Ung <davidu@mips.com>
d85c3a10
TS		 775
776 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
777 mips3264r2.igen. Add missing dependency rules.
778 * m16e.igen: Support for mips16e save/restore instructions.
779
e85e3205
RE		 7802006-06-13 Richard Earnshaw <rearnsha@arm.com>
781
782 * configure: Regenerated.
783
2f0122dc
DJ		 7842006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
785
786 * configure: Regenerated.
787
20e95c23
DJ		 7882006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
789
790 * configure: Regenerated.
791
69088b17
CF		 7922006-05-15 Chao-ying Fu <fu@mips.com>
793
794 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
795
0275de4e
NC		 7962006-04-18 Nick Clifton <nickc@redhat.com>
797
798 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
799 statement.
800
b3a3ffef
HPN		 8012006-03-29 Hans-Peter Nilsson <hp@axis.com>
802
803 * configure: Regenerate.
804
40a5538e
CF		 8052005-12-14 Chao-ying Fu <fu@mips.com>
806
807 * Makefile.in (SIM_OBJS): Add dsp.o.
808 (dsp.o): New dependency.
809 (IGEN_INCLUDE): Add dsp.igen.
810 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
811 mipsisa64*-*-*): Add dsp to sim_igen_machine.
812 * configure: Regenerate.
813 * mips.igen: Add dsp model and include dsp.igen.
814 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
815 because these instructions are extended in DSP ASE.
816 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
817 adding 6 DSP accumulator registers and 1 DSP control register.
818 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
819 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
820 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
821 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
822 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
823 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
824 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
825 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
826 DSPCR_CCOND_SMASK): New define.
827 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
828 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
829
21d14896
ILT		 8302005-07-08 Ian Lance Taylor <ian@airs.com>
831
832 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
833
b16d63da 8342005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 835 Nigel Stephens <nigel@mips.com>
836
837 * mips.igen: New mips16e model and include m16e.igen.
838 (check_u64): Add mips16e tag.
839 * m16e.igen: New file for MIPS16e instructions.
840 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
841 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
842 models.
843 * configure: Regenerate.
b16d63da 844
e70cb6cd 8452005-05-26 David Ung <davidu@mips.com>
72f4393d 846
e70cb6cd
CD		 847 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
848 tags to all instructions which are applicable to the new ISAs.
849 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
850 vr.igen.
851 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 852 instructions.
e70cb6cd
CD		 853 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
854 to mips.igen.
855 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
856 * configure: Regenerate.
72f4393d 857
2b193c4a
MK		 8582005-03-23 Mark Kettenis <kettenis@gnu.org>
859
860 * configure: Regenerate.
861
35695fd6
AC		 8622005-01-14 Andrew Cagney <cagney@gnu.org>
863
864 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
865 explicit call to AC_CONFIG_HEADER.
866 * configure: Regenerate.
867
f0569246
AC		 8682005-01-12 Andrew Cagney <cagney@gnu.org>
869
870 * configure.ac: Update to use ../common/common.m4.
871 * configure: Re-generate.
872
38f48d72
AC		 8732005-01-11 Andrew Cagney <cagney@localhost.localdomain>
874
875 * configure: Regenerated to track ../common/aclocal.m4 changes.
876
b7026657
AC		 8772005-01-07 Andrew Cagney <cagney@gnu.org>
878
879 * configure.ac: Rename configure.in, require autoconf 2.59.
880 * configure: Re-generate.
881
379832de
HPN		 8822004-12-08 Hans-Peter Nilsson <hp@axis.com>
883
884 * configure: Regenerate for ../common/aclocal.m4 update.
885
cd62154c 8862004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 887
cd62154c
AC		 888 Committed by Andrew Cagney.
889 * m16.igen (CMP, CMPI): Fix assembler.
890
e5da76ec
CD		 8912004-08-18 Chris Demetriou <cgd@broadcom.com>
892
893 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
894 * configure: Regenerate.
895
139181c8
CD		 8962004-06-25 Chris Demetriou <cgd@broadcom.com>
897
898 * configure.in (sim_m16_machine): Include mipsIII.
899 * configure: Regenerate.
900
1a27f959
CD		 9012004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
902
72f4393d 903 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 904 from COP0_BADVADDR.
905 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
906
5dbb7b5a
CD		 9072004-04-10 Chris Demetriou <cgd@broadcom.com>
908
909 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
910
14234056
CD		 9112004-04-09 Chris Demetriou <cgd@broadcom.com>
912
913 * mips.igen (check_fmt): Remove.
914 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
915 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
916 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
917 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
918 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
919 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
920 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
921 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
922 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
923 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
924
c6f9085c
CD		 9252004-04-09 Chris Demetriou <cgd@broadcom.com>
926
927 * sb1.igen (check_sbx): New function.
928 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
929
11d66e66 9302004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 931 Richard Sandiford <rsandifo@redhat.com>
932
933 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
934 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
935 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
936 separate implementations for mipsIV and mipsV. Use new macros to
937 determine whether the restrictions apply.
938
b3208fb8
CD		 9392004-01-19 Chris Demetriou <cgd@broadcom.com>
940
941 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
942 (check_mult_hilo): Improve comments.
943 (check_div_hilo): Likewise. Also, fork off a new version
944 to handle mips32/mips64 (since there are no hazards to check
945 in MIPS32/MIPS64).
946
9a1d84fb
CD		 9472003-06-17 Richard Sandiford <rsandifo@redhat.com>
948
949 * mips.igen (do_dmultx): Fix check for negative operands.
950
ae451ac6
ILT		 9512003-05-16 Ian Lance Taylor <ian@airs.com>
952
953 * Makefile.in (SHELL): Make sure this is defined.
954 (various): Use $(SHELL) whenever we invoke move-if-change.
955
dd69d292
CD		 9562003-05-03 Chris Demetriou <cgd@broadcom.com>
957
958 * cp1.c: Tweak attribution slightly.
959 * cp1.h: Likewise.
960 * mdmx.c: Likewise.
961 * mdmx.igen: Likewise.
962 * mips3d.igen: Likewise.
963 * sb1.igen: Likewise.
964
bcd0068e
CD		 9652003-04-15 Richard Sandiford <rsandifo@redhat.com>
966
967 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
968 unsigned operands.
969
6b4a8935
AC		 9702003-02-27 Andrew Cagney <cagney@redhat.com>
971
601da316
AC		 972 * interp.c (sim_open): Rename _bfd to bfd.
973 (sim_create_inferior): Ditto.
6b4a8935 974
d29e330f
CD		 9752003-01-14 Chris Demetriou <cgd@broadcom.com>
976
977 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
978
a2353a08
CD		 9792003-01-14 Chris Demetriou <cgd@broadcom.com>
980
981 * mips.igen (EI, DI): Remove.
982
80551777
CD		 9832003-01-05 Richard Sandiford <rsandifo@redhat.com>
984
985 * Makefile.in (tmp-run-multi): Fix mips16 filter.
986
4c54fc26
CD		 9872003-01-04 Richard Sandiford <rsandifo@redhat.com>
988 Andrew Cagney <ac131313@redhat.com>
989 Gavin Romig-Koch <gavin@redhat.com>
990 Graydon Hoare <graydon@redhat.com>
991 Aldy Hernandez <aldyh@redhat.com>
992 Dave Brolley <brolley@redhat.com>
993 Chris Demetriou <cgd@broadcom.com>
994
995 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
996 (sim_mach_default): New variable.
997 (mips64vr-*-*, mips64vrel-*-*): New configurations.
998 Add a new simulator generator, MULTI.
999 * configure: Regenerate.
1000 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1001 (multi-run.o): New dependency.
1002 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1003 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1004 (tmp-multi): Combine them.
1005 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1006 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1007 (distclean-extra): New rule.
1008 * sim-main.h: Include bfd.h.
1009 (MIPS_MACH): New macro.
1010 * mips.igen (vr4120, vr5400, vr5500): New models.
1011 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1012 * vr.igen: Replace with new version.
1013
e6c674b8
CD		 10142003-01-04 Chris Demetriou <cgd@broadcom.com>
1015
1016 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1017 * configure: Regenerate.
1018
28f50ac8
CD		 10192002-12-31 Chris Demetriou <cgd@broadcom.com>
1020
1021 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1022 * mips.igen: Remove all invocations of check_branch_bug and
1023 mark_branch_bug.
1024
5071ffe6
CD		 10252002-12-16 Chris Demetriou <cgd@broadcom.com>
1026
72f4393d 1027 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1028
06e7837e
CD		 10292002-07-30 Chris Demetriou <cgd@broadcom.com>
1030
1031 * mips.igen (do_load_double, do_store_double): New functions.
1032 (LDC1, SDC1): Rename to...
1033 (LDC1b, SDC1b): respectively.
1034 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1035
2265c243
MS		 10362002-07-29 Michael Snyder <msnyder@redhat.com>
1037
1038 * cp1.c (fp_recip2): Modify initialization expression so that
1039 GCC will recognize it as constant.
1040
a2f8b4f3
CD		 10412002-06-18 Chris Demetriou <cgd@broadcom.com>
1042
1043 * mdmx.c (SD_): Delete.
1044 (Unpredictable): Re-define, for now, to directly invoke
1045 unpredictable_action().
1046 (mdmx_acc_op): Fix error in .ob immediate handling.
1047
b4b6c939
AC		 10482002-06-18 Andrew Cagney <cagney@redhat.com>
1049
1050 * interp.c (sim_firmware_command): Initialize `address'.
1051
c8cca39f
AC		 10522002-06-16 Andrew Cagney <ac131313@redhat.com>
1053
1054 * configure: Regenerated to track ../common/aclocal.m4 changes.
1055
e7e81181 10562002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1057 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1058
1059 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1060 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1061 * mips.igen: Include mips3d.igen.
1062 (mips3d): New model name for MIPS-3D ASE instructions.
1063 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1064 instructions.
e7e81181
CD		 1065 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1066 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1067 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1068 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1069 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1070 (RSquareRoot1, RSquareRoot2): New macros.
1071 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1072 (fp_rsqrt2): New functions.
1073 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1074 * configure: Regenerate.
1075
3a2b820e 10762002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1077 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1078
1079 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1080 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1081 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1082 (convert): Note that this function is not used for paired-single
1083 format conversions.
1084 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1085 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1086 (check_fmt_p): Enable paired-single support.
1087 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1088 (PUU.PS): New instructions.
1089 (CVT.S.fmt): Don't use this instruction for paired-single format
1090 destinations.
1091 * sim-main.h (FP_formats): New value 'fmt_ps.'
1092 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1093 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1094
d18ea9c2
CD		 10952002-06-12 Chris Demetriou <cgd@broadcom.com>
1096
1097 * mips.igen: Fix formatting of function calls in
1098 many FP operations.
1099
95fd5cee
CD		 11002002-06-12 Chris Demetriou <cgd@broadcom.com>
1101
1102 * mips.igen (MOVN, MOVZ): Trace result.
1103 (TNEI): Print "tnei" as the opcode name in traces.
1104 (CEIL.W): Add disassembly string for traces.
1105 (RSQRT.fmt): Make location of disassembly string consistent
1106 with other instructions.
1107
4f0d55ae
CD		 11082002-06-12 Chris Demetriou <cgd@broadcom.com>
1109
1110 * mips.igen (X): Delete unused function.
1111
3c25f8c7
AC		 11122002-06-08 Andrew Cagney <cagney@redhat.com>
1113
1114 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1115
f3c08b7e 11162002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1117 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1118
1119 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1120 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1121 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1122 (fp_nmsub): New prototypes.
1123 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1124 (NegMultiplySub): New defines.
1125 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1126 (MADD.D, MADD.S): Replace with...
1127 (MADD.fmt): New instruction.
1128 (MSUB.D, MSUB.S): Replace with...
1129 (MSUB.fmt): New instruction.
1130 (NMADD.D, NMADD.S): Replace with...
1131 (NMADD.fmt): New instruction.
1132 (NMSUB.D, MSUB.S): Replace with...
1133 (NMSUB.fmt): New instruction.
1134
52714ff9 11352002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1136 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1137
1138 * cp1.c: Fix more comment spelling and formatting.
1139 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1140 (denorm_mode): New function.
1141 (fpu_unary, fpu_binary): Round results after operation, collect
1142 status from rounding operations, and update the FCSR.
1143 (convert): Collect status from integer conversions and rounding
1144 operations, and update the FCSR. Adjust NaN values that result
1145 from conversions. Convert to use sim_io_eprintf rather than
1146 fprintf, and remove some debugging code.
1147 * cp1.h (fenr_FS): New define.
1148
577d8c4b
CD		 11492002-06-07 Chris Demetriou <cgd@broadcom.com>
1150
1151 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1152 rounding mode to sim FP rounding mode flag conversion code into...
1153 (rounding_mode): New function.
1154
196496ed
CD		 11552002-06-07 Chris Demetriou <cgd@broadcom.com>
1156
1157 * cp1.c: Clean up formatting of a few comments.
1158 (value_fpr): Reformat switch statement.
1159
cfe9ea23 11602002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1161 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1162
1163 * cp1.h: New file.
1164 * sim-main.h: Include cp1.h.
1165 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1166 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1167 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1168 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1169 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1170 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1171 * cp1.c: Don't include sim-fpu.h; already included by
1172 sim-main.h. Clean up formatting of some comments.
1173 (NaN, Equal, Less): Remove.
1174 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1175 (fp_cmp): New functions.
1176 * mips.igen (do_c_cond_fmt): Remove.
1177 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1178 Compare. Add result tracing.
1179 (CxC1): Remove, replace with...
1180 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1181 (DMxC1): Remove, replace with...
1182 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1183 (MxC1): Remove, replace with...
1184 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1185
ee7254b0
CD		 11862002-06-04 Chris Demetriou <cgd@broadcom.com>
1187
1188 * sim-main.h (FGRIDX): Remove, replace all uses with...
1189 (FGR_BASE): New macro.
1190 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1191 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1192 (NR_FGR, FGR): Likewise.
1193 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1194 * mips.igen: Likewise.
1195
d3eb724f
CD		 11962002-06-04 Chris Demetriou <cgd@broadcom.com>
1197
1198 * cp1.c: Add an FSF Copyright notice to this file.
1199
ba46ddd0 12002002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1201 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1202
1203 * cp1.c (Infinity): Remove.
1204 * sim-main.h (Infinity): Likewise.
1205
1206 * cp1.c (fp_unary, fp_binary): New functions.
1207 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1208 (fp_sqrt): New functions, implemented in terms of the above.
1209 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1210 (Recip, SquareRoot): Remove (replaced by functions above).
1211 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1212 (fp_recip, fp_sqrt): New prototypes.
1213 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1214 (Recip, SquareRoot): Replace prototypes with #defines which
1215 invoke the functions above.
72f4393d 1216
18d8a52d
CD		 12172002-06-03 Chris Demetriou <cgd@broadcom.com>
1218
1219 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1220 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1221 file, remove PARAMS from prototypes.
1222 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1223 simulator state arguments.
1224 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1225 pass simulator state arguments.
1226 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1227 (store_fpr, convert): Remove 'sd' argument.
1228 (value_fpr): Likewise. Convert to use 'SD' instead.
1229
0f154cbd
CD		 12302002-06-03 Chris Demetriou <cgd@broadcom.com>
1231
1232 * cp1.c (Min, Max): Remove #if 0'd functions.
1233 * sim-main.h (Min, Max): Remove.
1234
e80fc152
CD		 12352002-06-03 Chris Demetriou <cgd@broadcom.com>
1236
1237 * cp1.c: fix formatting of switch case and default labels.
1238 * interp.c: Likewise.
1239 * sim-main.c: Likewise.
1240
bad673a9
CD		 12412002-06-03 Chris Demetriou <cgd@broadcom.com>
1242
1243 * cp1.c: Clean up comments which describe FP formats.
1244 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1245
7cbea089 12462002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1247 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1248
1249 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1250 Broadcom SiByte SB-1 processor configurations.
1251 * configure: Regenerate.
1252 * sb1.igen: New file.
1253 * mips.igen: Include sb1.igen.
1254 (sb1): New model.
1255 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1256 * mdmx.igen: Add "sb1" model to all appropriate functions and
1257 instructions.
1258 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1259 (ob_func, ob_acc): Reference the above.
1260 (qh_acc): Adjust to keep the same size as ob_acc.
1261 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1262 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1263
909daa82
CD		 12642002-06-03 Chris Demetriou <cgd@broadcom.com>
1265
1266 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1267
f4f1b9f1 12682002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1269 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1270
1271 * mips.igen (mdmx): New (pseudo-)model.
1272 * mdmx.c, mdmx.igen: New files.
1273 * Makefile.in (SIM_OBJS): Add mdmx.o.
1274 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1275 New typedefs.
1276 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1277 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1278 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1279 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1280 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1281 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1282 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1283 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1284 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1285 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1286 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1287 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1288 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1289 (qh_fmtsel): New macros.
1290 (_sim_cpu): New member "acc".
1291 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1292 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1293
5accf1ff
CD		 12942002-05-01 Chris Demetriou <cgd@broadcom.com>
1295
1296 * interp.c: Use 'deprecated' rather than 'depreciated.'
1297 * sim-main.h: Likewise.
1298
402586aa
CD		 12992002-05-01 Chris Demetriou <cgd@broadcom.com>
1300
1301 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1302 which wouldn't compile anyway.
1303 * sim-main.h (unpredictable_action): New function prototype.
1304 (Unpredictable): Define to call igen function unpredictable().
1305 (NotWordValue): New macro to call igen function not_word_value().
1306 (UndefinedResult): Remove.
1307 * interp.c (undefined_result): Remove.
1308 (unpredictable_action): New function.
1309 * mips.igen (not_word_value, unpredictable): New functions.
1310 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1311 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1312 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1313 NotWordValue() to check for unpredictable inputs, then
1314 Unpredictable() to handle them.
1315
c9b9995a
CD		 13162002-02-24 Chris Demetriou <cgd@broadcom.com>
1317
1318 * mips.igen: Fix formatting of calls to Unpredictable().
1319
e1015982
AC		 13202002-04-20 Andrew Cagney <ac131313@redhat.com>
1321
1322 * interp.c (sim_open): Revert previous change.
1323
b882a66b
AO		 13242002-04-18 Alexandre Oliva <aoliva@redhat.com>
1325
1326 * interp.c (sim_open): Disable chunk of code that wrote code in
1327 vector table entries.
1328
c429b7dd
CD		 13292002-03-19 Chris Demetriou <cgd@broadcom.com>
1330
1331 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1332 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1333 unused definitions.
1334
37d146fa
CD		 13352002-03-19 Chris Demetriou <cgd@broadcom.com>
1336
1337 * cp1.c: Fix many formatting issues.
1338
07892c0b
CD		 13392002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1340
1341 * cp1.c (fpu_format_name): New function to replace...
1342 (DOFMT): This. Delete, and update all callers.
1343 (fpu_rounding_mode_name): New function to replace...
1344 (RMMODE): This. Delete, and update all callers.
1345
487f79b7
CD		 13462002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1347
1348 * interp.c: Move FPU support routines from here to...
1349 * cp1.c: Here. New file.
1350 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1351 (cp1.o): New target.
1352
1e799e28
CD		 13532002-03-12 Chris Demetriou <cgd@broadcom.com>
1354
1355 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1356 * mips.igen (mips32, mips64): New models, add to all instructions
1357 and functions as appropriate.
1358 (loadstore_ea, check_u64): New variant for model mips64.
1359 (check_fmt_p): New variant for models mipsV and mips64, remove
1360 mipsV model marking fro other variant.
1361 (SLL) Rename to...
1362 (SLLa) this.
1363 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1364 for mips32 and mips64.
1365 (DCLO, DCLZ): New instructions for mips64.
1366
82f728db
CD		 13672002-03-07 Chris Demetriou <cgd@broadcom.com>
1368
1369 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1370 immediate or code as a hex value with the "%#lx" format.
1371 (ANDI): Likewise, and fix printed instruction name.
1372
b96e7ef1
CD		 13732002-03-05 Chris Demetriou <cgd@broadcom.com>
1374
1375 * sim-main.h (UndefinedResult, Unpredictable): New macros
1376 which currently do nothing.
1377
d35d4f70
CD		 13782002-03-05 Chris Demetriou <cgd@broadcom.com>
1379
1380 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1381 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1382 (status_CU3): New definitions.
1383
1384 * sim-main.h (ExceptionCause): Add new values for MIPS32
1385 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1386 for DebugBreakPoint and NMIReset to note their status in
1387 MIPS32 and MIPS64.
1388 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1389 (SignalExceptionCacheErr): New exception macros.
1390
3ad6f714
CD		 13912002-03-05 Chris Demetriou <cgd@broadcom.com>
1392
1393 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1394 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1395 is always enabled.
1396 (SignalExceptionCoProcessorUnusable): Take as argument the
1397 unusable coprocessor number.
1398
86b77b47
CD		 13992002-03-05 Chris Demetriou <cgd@broadcom.com>
1400
1401 * mips.igen: Fix formatting of all SignalException calls.
1402
97a88e93 14032002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1404
1405 * sim-main.h (SIGNEXTEND): Remove.
1406
97a88e93 14072002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1408
1409 * mips.igen: Remove gencode comment from top of file, fix
1410 spelling in another comment.
1411
97a88e93 14122002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1413
1414 * mips.igen (check_fmt, check_fmt_p): New functions to check
1415 whether specific floating point formats are usable.
1416 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1417 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1418 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1419 Use the new functions.
1420 (do_c_cond_fmt): Remove format checks...
1421 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1422
97a88e93 14232002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1424
1425 * mips.igen: Fix formatting of check_fpu calls.
1426
41774c9d
CD		 14272002-03-03 Chris Demetriou <cgd@broadcom.com>
1428
1429 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1430
4a0bd876
CD		 14312002-03-03 Chris Demetriou <cgd@broadcom.com>
1432
1433 * mips.igen: Remove whitespace at end of lines.
1434
09297648
CD		 14352002-03-02 Chris Demetriou <cgd@broadcom.com>
1436
1437 * mips.igen (loadstore_ea): New function to do effective
1438 address calculations.
1439 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1440 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1441 CACHE): Use loadstore_ea to do effective address computations.
1442
043b7057
CD		 14432002-03-02 Chris Demetriou <cgd@broadcom.com>
1444
1445 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1446 * mips.igen (LL, CxC1, MxC1): Likewise.
1447
c1e8ada4
CD		 14482002-03-02 Chris Demetriou <cgd@broadcom.com>
1449
1450 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1451 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1452 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1453 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1454 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1455 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1456 Don't split opcode fields by hand, use the opcode field values
1457 provided by igen.
1458
3e1dca16
CD		 14592002-03-01 Chris Demetriou <cgd@broadcom.com>
1460
1461 * mips.igen (do_divu): Fix spacing.
1462
1463 * mips.igen (do_dsllv): Move to be right before DSLLV,
1464 to match the rest of the do_<shift> functions.
1465
fff8d27d
CD		 14662002-03-01 Chris Demetriou <cgd@broadcom.com>
1467
1468 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1469 DSRL32, do_dsrlv): Trace inputs and results.
1470
0d3e762b
CD		 14712002-03-01 Chris Demetriou <cgd@broadcom.com>
1472
1473 * mips.igen (CACHE): Provide instruction-printing string.
1474
1475 * interp.c (signal_exception): Comment tokens after #endif.
1476
eb5fcf93
CD		 14772002-02-28 Chris Demetriou <cgd@broadcom.com>
1478
1479 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1480 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1481 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1482 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1483 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1484 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1485 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1486 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1487
bb22bd7d
CD		 14882002-02-28 Chris Demetriou <cgd@broadcom.com>
1489
1490 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1491 instruction-printing string.
1492 (LWU): Use '64' as the filter flag.
1493
91a177cf
CD		 14942002-02-28 Chris Demetriou <cgd@broadcom.com>
1495
1496 * mips.igen (SDXC1): Fix instruction-printing string.
1497
387f484a
CD		 14982002-02-28 Chris Demetriou <cgd@broadcom.com>
1499
1500 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1501 filter flags "32,f".
1502
3d81f391
CD		 15032002-02-27 Chris Demetriou <cgd@broadcom.com>
1504
1505 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1506 as the filter flag.
1507
af5107af
CD		 15082002-02-27 Chris Demetriou <cgd@broadcom.com>
1509
1510 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1511 add a comma) so that it more closely match the MIPS ISA
1512 documentation opcode partitioning.
1513 (PREF): Put useful names on opcode fields, and include
1514 instruction-printing string.
1515
ca971540
CD		 15162002-02-27 Chris Demetriou <cgd@broadcom.com>
1517
1518 * mips.igen (check_u64): New function which in the future will
1519 check whether 64-bit instructions are usable and signal an
1520 exception if not. Currently a no-op.
1521 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1522 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1523 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1524 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1525
1526 * mips.igen (check_fpu): New function which in the future will
1527 check whether FPU instructions are usable and signal an exception
1528 if not. Currently a no-op.
1529 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1530 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1531 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1532 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1533 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1534 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1535 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1536 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1537
1c47a468
CD		 15382002-02-27 Chris Demetriou <cgd@broadcom.com>
1539
1540 * mips.igen (do_load_left, do_load_right): Move to be immediately
1541 following do_load.
1542 (do_store_left, do_store_right): Move to be immediately following
1543 do_store.
1544
603a98e7
CD		 15452002-02-27 Chris Demetriou <cgd@broadcom.com>
1546
1547 * mips.igen (mipsV): New model name. Also, add it to
1548 all instructions and functions where it is appropriate.
1549
c5d00cc7
CD		 15502002-02-18 Chris Demetriou <cgd@broadcom.com>
1551
1552 * mips.igen: For all functions and instructions, list model
1553 names that support that instruction one per line.
1554
074e9cb8
CD		 15552002-02-11 Chris Demetriou <cgd@broadcom.com>
1556
1557 * mips.igen: Add some additional comments about supported
1558 models, and about which instructions go where.
1559 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1560 order as is used in the rest of the file.
1561
9805e229
CD		 15622002-02-11 Chris Demetriou <cgd@broadcom.com>
1563
1564 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1565 indicating that ALU32_END or ALU64_END are there to check
1566 for overflow.
1567 (DADD): Likewise, but also remove previous comment about
1568 overflow checking.
1569
f701dad2
CD		 15702002-02-10 Chris Demetriou <cgd@broadcom.com>
1571
1572 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1573 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1574 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1575 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1576 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1577 fields (i.e., add and move commas) so that they more closely
1578 match the MIPS ISA documentation opcode partitioning.
1579
15802002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1581
72f4393d
L		 1582 * mips.igen (ADDI): Print immediate value.
1583 (BREAK): Print code.
1584 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1585 (SLL): Print "nop" specially, and don't run the code
1586 that does the shift for the "nop" case.
20ae0098 1587
9e52972e
FF		 15882001-11-17 Fred Fish <fnf@redhat.com>
1589
1590 * sim-main.h (float_operation): Move enum declaration outside
1591 of _sim_cpu struct declaration.
1592
c0efbca4
JB		 15932001-04-12 Jim Blandy <jimb@redhat.com>
1594
1595 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1596 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1597 set of the FCSR.
1598 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1599 PENDING_FILL, and you can get the intended effect gracefully by
1600 calling PENDING_SCHED directly.
1601
fb891446
BE		 16022001-02-23 Ben Elliston <bje@redhat.com>
1603
1604 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1605 already defined elsewhere.
1606
8030f857
BE		 16072001-02-19 Ben Elliston <bje@redhat.com>
1608
1609 * sim-main.h (sim_monitor): Return an int.
1610 * interp.c (sim_monitor): Add return values.
1611 (signal_exception): Handle error conditions from sim_monitor.
1612
56b48a7a
CD		 16132001-02-08 Ben Elliston <bje@redhat.com>
1614
1615 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1616 (store_memory): Likewise, pass cia to sim_core_write*.
1617
d3ee60d9
FCE		 16182000-10-19 Frank Ch. Eigler <fche@redhat.com>
1619
1620 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1621 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1622
071da002
AC		 1623Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1624
1625 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1626 * Makefile.in: Don't delete *.igen when cleaning directory.
1627
a28c02cd
AC		 1628Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1629
1630 * m16.igen (break): Call SignalException not sim_engine_halt.
1631
80ee11fa
AC		 1632Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1633
1634 From Jason Eckhardt:
1635 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1636
673388c0
AC		 1637Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1638
1639 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1640
4c0deff4
NC		 16412000-05-24 Michael Hayes <mhayes@cygnus.com>
1642
1643 * mips.igen (do_dmultx): Fix typo.
1644
eb2d80b4
AC		 1645Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1646
1647 * configure: Regenerated to track ../common/aclocal.m4 changes.
1648
dd37a34b
AC		 1649Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1650
1651 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1652
4c0deff4
NC		 16532000-04-12 Frank Ch. Eigler <fche@redhat.com>
1654
1655 * sim-main.h (GPR_CLEAR): Define macro.
1656
e30db738
AC		 1657Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1658
1659 * interp.c (decode_coproc): Output long using %lx and not %s.
1660
cb7450ea
FCE		 16612000-03-21 Frank Ch. Eigler <fche@redhat.com>
1662
1663 * interp.c (sim_open): Sort & extend dummy memory regions for
1664 --board=jmr3904 for eCos.
1665
a3027dd7
FCE		 16662000-03-02 Frank Ch. Eigler <fche@redhat.com>
1667
1668 * configure: Regenerated.
1669
1670Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1671
1672 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1673 calls, conditional on the simulator being in verbose mode.
1674
dfcd3bfb
JM		 1675Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1676
1677 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1678 cache don't get ReservedInstruction traps.
1679
c2d11a7d
JM		 16801999-11-29 Mark Salter <msalter@cygnus.com>
1681
1682 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1683 to clear status bits in sdisr register. This is how the hardware works.
1684
1685 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1686 being used by cygmon.
1687
4ce44c66
JM		 16881999-11-11 Andrew Haley <aph@cygnus.com>
1689
1690 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1691 instructions.
1692
cff3e48b
JM		 1693Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1694
1695 * mips.igen (MULT): Correct previous mis-applied patch.
1696
d4f3574e
SS		 1697Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1698
1699 * mips.igen (delayslot32): Handle sequence like
1700 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1701 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1702 (MULT): Actually pass the third register...
1703
17041999-09-03 Mark Salter <msalter@cygnus.com>
1705
1706 * interp.c (sim_open): Added more memory aliases for additional
1707 hardware being touched by cygmon on jmr3904 board.
1708
1709Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1710
1711 * configure: Regenerated to track ../common/aclocal.m4 changes.
1712
a0b3c4fd
JM		 1713Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1714
1715 * interp.c (sim_store_register): Handle case where client - GDB -
1716 specifies that a 4 byte register is 8 bytes in size.
1717 (sim_fetch_register): Ditto.
72f4393d 1718
adf40b2e
JM		 17191999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1720
1721 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1722 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1723 (idt_monitor_base): Base address for IDT monitor traps.
1724 (pmon_monitor_base): Ditto for PMON.
1725 (lsipmon_monitor_base): Ditto for LSI PMON.
1726 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1727 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1728 (sim_firmware_command): New function.
1729 (mips_option_handler): Call it for OPTION_FIRMWARE.
1730 (sim_open): Allocate memory for idt_monitor region. If "--board"
1731 option was given, add no monitor by default. Add BREAK hooks only if
1732 monitors are also there.
72f4393d 1733
43e526b9
JM		 1734Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1735
1736 * interp.c (sim_monitor): Flush output before reading input.
1737
1738Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1739
1740 * tconfig.in (SIM_HANDLES_LMA): Always define.
1741
1742Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1743
1744 From Mark Salter <msalter@cygnus.com>:
1745 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1746 (sim_open): Add setup for BSP board.
1747
9846de1b
JM		 1748Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1749
1750 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1751 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1752 them as unimplemented.
1753
cd0fc7c3
SS		 17541999-05-08 Felix Lee <flee@cygnus.com>
1755
1756 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1757
7a292a7a
SS		 17581999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1759
1760 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1761
1762Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1763
1764 * configure.in: Any mips64vr5*-*-* target should have
1765 -DTARGET_ENABLE_FR=1.
1766 (default_endian): Any mips64vr*el-*-* target should default to
1767 LITTLE_ENDIAN.
1768 * configure: Re-generate.
1769
17701999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1771
1772 * mips.igen (ldl): Extend from _16_, not 32.
1773
1774Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1775
1776 * interp.c (sim_store_register): Force registers written to by GDB
1777 into an un-interpreted state.
1778
c906108c
SS		 17791999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1780
1781 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1782 CPU, start periodic background I/O polls.
72f4393d 1783 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1784
17851998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1786
1787 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1788
c906108c
SS		 1789Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1790
1791 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1792 case statement.
1793
17941998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1795
1796 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1797 (load_word): Call SIM_CORE_SIGNAL hook on error.
1798 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1799 starting. For exception dispatching, pass PC instead of NULL_CIA.
1800 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1801 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1802 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1803 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1804 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1805 * mips.igen (*): Replace memory-related SignalException* calls
1806 with references to SIM_CORE_SIGNAL hook.
72f4393d 1807
c906108c
SS		 1808 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1809 fix.
1810 * sim-main.c (*): Minor warning cleanups.
72f4393d 1811
c906108c
SS		 18121998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1813
1814 * m16.igen (DADDIU5): Correct type-o.
1815
1816Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1817
1818 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1819 variables.
1820
1821Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1822
1823 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1824 to include path.
1825 (interp.o): Add dependency on itable.h
1826 (oengine.c, gencode): Delete remaining references.
1827 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1828
c906108c 18291998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1830
c906108c
SS		 1831 * vr4run.c: New.
1832 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1833 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1834 tmp-run-hack) : New.
1835 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1836 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1837 Drop the "64" qualifier to get the HACK generator working.
1838 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1839 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1840 qualifier to get the hack generator working.
1841 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1842 (DSLL): Use do_dsll.
1843 (DSLLV): Use do_dsllv.
1844 (DSRA): Use do_dsra.
1845 (DSRL): Use do_dsrl.
1846 (DSRLV): Use do_dsrlv.
1847 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1848 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1849 get the HACK generator working.
1850 (MACC) Rename to get the HACK generator working.
1851 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1852
c906108c
SS		 18531998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1854
1855 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1856 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1857
c906108c
SS		 18581998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1859
1860 * mips/interp.c (DEBUG): Cleanups.
1861
18621998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1863
1864 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1865 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1866
c906108c
SS		 18671998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1868
1869 * interp.c (sim_close): Uninstall modules.
1870
1871Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1872
1873 * sim-main.h, interp.c (sim_monitor): Change to global
1874 function.
1875
1876Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1877
1878 * configure.in (vr4100): Only include vr4100 instructions in
1879 simulator.
1880 * configure: Re-generate.
1881 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1882
1883Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1884
1885 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1886 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1887 true alternative.
1888
1889 * configure.in (sim_default_gen, sim_use_gen): Replace with
1890 sim_gen.
1891 (--enable-sim-igen): Delete config option. Always using IGEN.
1892 * configure: Re-generate.
72f4393d 1893
c906108c
SS		 1894 * Makefile.in (gencode): Kill, kill, kill.
1895 * gencode.c: Ditto.
72f4393d 1896
c906108c
SS		 1897Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1898
1899 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1900 bit mips16 igen simulator.
1901 * configure: Re-generate.
1902
1903 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1904 as part of vr4100 ISA.
1905 * vr.igen: Mark all instructions as 64 bit only.
1906
1907Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1908
1909 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1910 Pacify GCC.
1911
1912Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1913
1914 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1915 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1916 * configure: Re-generate.
1917
1918 * m16.igen (BREAK): Define breakpoint instruction.
1919 (JALX32): Mark instruction as mips16 and not r3900.
1920 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1921
1922 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1923
1924Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1925
1926 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1927 insn as a debug breakpoint.
1928
1929 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1930 pending.slot_size.
1931 (PENDING_SCHED): Clean up trace statement.
1932 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1933 (PENDING_FILL): Delay write by only one cycle.
1934 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1935
1936 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1937 of pending writes.
1938 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1939 32 & 64.
1940 (pending_tick): Move incrementing of index to FOR statement.
1941 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1942
c906108c
SS		 1943 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1944 build simulator.
1945 * configure: Re-generate.
72f4393d 1946
c906108c
SS		 1947 * interp.c (sim_engine_run OLD): Delete explicit call to
1948 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1949
c906108c
SS		 1950Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1951
1952 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1953 interrupt level number to match changed SignalExceptionInterrupt
1954 macro.
1955
1956Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1957
1958 * interp.c: #include "itable.h" if WITH_IGEN.
1959 (get_insn_name): New function.
1960 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1961 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1962
1963Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1964
1965 * configure: Rebuilt to inhale new common/aclocal.m4.
1966
1967Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1968
1969 * dv-tx3904sio.c: Include sim-assert.h.
1970
1971Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1972
1973 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1974 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1975 Reorganize target-specific sim-hardware checks.
1976 * configure: rebuilt.
1977 * interp.c (sim_open): For tx39 target boards, set
1978 OPERATING_ENVIRONMENT, add tx3904sio devices.
1979 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1980 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1981
c906108c
SS		 1982 * dv-tx3904irc.c: Compiler warning clean-up.
1983 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1984 frequent hw-trace messages.
1985
1986Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1987
1988 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1989
1990Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1991
1992 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1993
1994 * vr.igen: New file.
1995 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1996 * mips.igen: Define vr4100 model. Include vr.igen.
1997Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1998
1999 * mips.igen (check_mf_hilo): Correct check.
2000
2001Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2002
2003 * sim-main.h (interrupt_event): Add prototype.
2004
2005 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2006 register_ptr, register_value.
2007 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2008
2009 * sim-main.h (tracefh): Make extern.
2010
2011Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2012
2013 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2014 Reduce unnecessarily high timer event frequency.
c906108c 2015 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2016
c906108c
SS		 2017Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2018
2019 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2020 to allay warnings.
2021 (interrupt_event): Made non-static.
72f4393d 2022
c906108c
SS		 2023 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2024 interchange of configuration values for external vs. internal
2025 clock dividers.
72f4393d 2026
c906108c
SS		 2027Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2028
72f4393d 2029 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2030 simulator-reserved break instructions.
2031 * gencode.c (build_instruction): Ditto.
2032 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2033 reserved instructions now use exception vector, rather
c906108c
SS		 2034 than halting sim.
2035 * sim-main.h: Moved magic constants to here.
2036
2037Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2038
2039 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2040 register upon non-zero interrupt event level, clear upon zero
2041 event value.
2042 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2043 by passing zero event value.
2044 (*_io_{read,write}_buffer): Endianness fixes.
2045 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2046 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2047
2048 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2049 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2050
c906108c
SS		 2051Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2052
72f4393d 2053 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2054 and BigEndianCPU.
2055
2056Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2057
2058 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2059 parts.
2060 * configure: Update.
2061
2062Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2063
2064 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2065 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2066 * configure.in: Include tx3904tmr in hw_device list.
2067 * configure: Rebuilt.
2068 * interp.c (sim_open): Instantiate three timer instances.
2069 Fix address typo of tx3904irc instance.
2070
2071Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2072
2073 * interp.c (signal_exception): SystemCall exception now uses
2074 the exception vector.
2075
2076Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2077
2078 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2079 to allay warnings.
2080
2081Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2082
2083 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2084
2085Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2086
2087 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2088
2089 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2090 sim-main.h. Declare a struct hw_descriptor instead of struct
2091 hw_device_descriptor.
2092
2093Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2094
2095 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2096 right bits and then re-align left hand bytes to correct byte
2097 lanes. Fix incorrect computation in do_store_left when loading
2098 bytes from second word.
2099
2100Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2101
2102 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2103 * interp.c (sim_open): Only create a device tree when HW is
2104 enabled.
2105
2106 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2107 * interp.c (signal_exception): Ditto.
2108
2109Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2110
2111 * gencode.c: Mark BEGEZALL as LIKELY.
2112
2113Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2114
2115 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2116 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2117
c906108c
SS		 2118Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2119
2120 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2121 modules. Recognize TX39 target with "mips*tx39" pattern.
2122 * configure: Rebuilt.
2123 * sim-main.h (*): Added many macros defining bits in
2124 TX39 control registers.
2125 (SignalInterrupt): Send actual PC instead of NULL.
2126 (SignalNMIReset): New exception type.
2127 * interp.c (board): New variable for future use to identify
2128 a particular board being simulated.
2129 (mips_option_handler,mips_options): Added "--board" option.
2130 (interrupt_event): Send actual PC.
2131 (sim_open): Make memory layout conditional on board setting.
2132 (signal_exception): Initial implementation of hardware interrupt
2133 handling. Accept another break instruction variant for simulator
2134 exit.
2135 (decode_coproc): Implement RFE instruction for TX39.
2136 (mips.igen): Decode RFE instruction as such.
2137 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2138 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2139 bbegin to implement memory map.
2140 * dv-tx3904cpu.c: New file.
2141 * dv-tx3904irc.c: New file.
2142
2143Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2144
2145 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2146
2147Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2148
2149 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2150 with calls to check_div_hilo.
2151
2152Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2153
2154 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2155 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2156 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2157 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2158 with calls to check_mult_hilo.
2159 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2160 with calls to check_div_hilo.
2161
2162Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2163
2164 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2165 Document a replacement.
2166
2167Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2168
2169 * interp.c (sim_monitor): Make mon_printf work.
2170
2171Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2172
2173 * sim-main.h (INSN_NAME): New arg `cpu'.
2174
2175Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2176
72f4393d 2177 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2178
2179Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2180
2181 * configure: Regenerated to track ../common/aclocal.m4 changes.
2182 * config.in: Ditto.
2183
2184Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2185
2186 * acconfig.h: New file.
2187 * configure.in: Reverted change of Apr 24; use sinclude again.
2188
2189Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2190
2191 * configure: Regenerated to track ../common/aclocal.m4 changes.
2192 * config.in: Ditto.
2193
2194Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2195
2196 * configure.in: Don't call sinclude.
2197
2198Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2199
2200 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2201
2202Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2203
2204 * mips.igen (ERET): Implement.
2205
2206 * interp.c (decode_coproc): Return sign-extended EPC.
2207
2208 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2209
2210 * interp.c (signal_exception): Do not ignore Trap.
2211 (signal_exception): On TRAP, restart at exception address.
2212 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2213 (signal_exception): Update.
2214 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2215 so that TRAP instructions are caught.
2216
2217Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2218
2219 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2220 contains HI/LO access history.
2221 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2222 (HIACCESS, LOACCESS): Delete, replace with
2223 (HIHISTORY, LOHISTORY): New macros.
2224 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2225
c906108c
SS		 2226 * gencode.c (build_instruction): Do not generate checks for
2227 correct HI/LO register usage.
2228
2229 * interp.c (old_engine_run): Delete checks for correct HI/LO
2230 register usage.
2231
2232 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2233 check_mf_cycles): New functions.
2234 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2235 do_divu, domultx, do_mult, do_multu): Use.
2236
2237 * tx.igen ("madd", "maddu"): Use.
72f4393d 2238
c906108c
SS		 2239Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2240
2241 * mips.igen (DSRAV): Use function do_dsrav.
2242 (SRAV): Use new function do_srav.
2243
2244 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2245 (B): Sign extend 11 bit immediate.
2246 (EXT-B*): Shift 16 bit immediate left by 1.
2247 (ADDIU*): Don't sign extend immediate value.
2248
2249Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2250
2251 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2252
2253 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2254 functions.
2255
2256 * mips.igen (delayslot32, nullify_next_insn): New functions.
2257 (m16.igen): Always include.
2258 (do_*): Add more tracing.
2259
2260 * m16.igen (delayslot16): Add NIA argument, could be called by a
2261 32 bit MIPS16 instruction.
72f4393d 2262
c906108c
SS		 2263 * interp.c (ifetch16): Move function from here.
2264 * sim-main.c (ifetch16): To here.
72f4393d 2265
c906108c
SS		 2266 * sim-main.c (ifetch16, ifetch32): Update to match current
2267 implementations of LH, LW.
2268 (signal_exception): Don't print out incorrect hex value of illegal
2269 instruction.
2270
2271Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2272
2273 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2274 instruction.
2275
2276 * m16.igen: Implement MIPS16 instructions.
72f4393d 2277
c906108c
SS		 2278 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2279 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2280 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2281 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2282 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2283 bodies of corresponding code from 32 bit insn to these. Also used
2284 by MIPS16 versions of functions.
72f4393d 2285
c906108c
SS		 2286 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2287 (IMEM16): Drop NR argument from macro.
2288
2289Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2290
2291 * Makefile.in (SIM_OBJS): Add sim-main.o.
2292
2293 * sim-main.h (address_translation, load_memory, store_memory,
2294 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2295 as INLINE_SIM_MAIN.
2296 (pr_addr, pr_uword64): Declare.
2297 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2298
c906108c
SS		 2299 * interp.c (address_translation, load_memory, store_memory,
2300 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2301 from here.
2302 * sim-main.c: To here. Fix compilation problems.
72f4393d 2303
c906108c
SS		 2304 * configure.in: Enable inlining.
2305 * configure: Re-config.
2306
2307Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2308
2309 * configure: Regenerated to track ../common/aclocal.m4 changes.
2310
2311Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2312
2313 * mips.igen: Include tx.igen.
2314 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2315 * tx.igen: New file, contains MADD and MADDU.
2316
2317 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2318 the hardwired constant `7'.
2319 (store_memory): Ditto.
2320 (LOADDRMASK): Move definition to sim-main.h.
2321
2322 mips.igen (MTC0): Enable for r3900.
2323 (ADDU): Add trace.
2324
2325 mips.igen (do_load_byte): Delete.
2326 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2327 do_store_right): New functions.
2328 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2329
2330 configure.in: Let the tx39 use igen again.
2331 configure: Update.
72f4393d 2332
c906108c
SS		 2333Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2334
2335 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2336 not an address sized quantity. Return zero for cache sizes.
2337
2338Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2339
2340 * mips.igen (r3900): r3900 does not support 64 bit integer
2341 operations.
2342
2343Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2344
2345 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2346 than igen one.
2347 * configure : Rebuild.
72f4393d 2348
c906108c
SS		 2349Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2350
2351 * configure: Regenerated to track ../common/aclocal.m4 changes.
2352
2353Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2354
2355 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2356
2357Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2358
2359 * configure: Regenerated to track ../common/aclocal.m4 changes.
2360 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2361
2362Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2363
2364 * configure: Regenerated to track ../common/aclocal.m4 changes.
2365
2366Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2367
2368 * interp.c (Max, Min): Comment out functions. Not yet used.
2369
2370Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2371
2372 * configure: Regenerated to track ../common/aclocal.m4 changes.
2373
2374Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2375
2376 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2377 configurable settings for stand-alone simulator.
72f4393d 2378
c906108c 2379 * configure.in: Added X11 search, just in case.
72f4393d 2380
c906108c
SS		 2381 * configure: Regenerated.
2382
2383Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2384
2385 * interp.c (sim_write, sim_read, load_memory, store_memory):
2386 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2387
2388Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2389
2390 * sim-main.h (GETFCC): Return an unsigned value.
2391
2392Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2393
2394 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2395 (DADD): Result destination is RD not RT.
2396
2397Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2398
2399 * sim-main.h (HIACCESS, LOACCESS): Always define.
2400
2401 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2402
2403 * interp.c (sim_info): Delete.
2404
2405Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2406
2407 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2408 (mips_option_handler): New argument `cpu'.
2409 (sim_open): Update call to sim_add_option_table.
2410
2411Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2412
2413 * mips.igen (CxC1): Add tracing.
2414
2415Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2416
2417 * sim-main.h (Max, Min): Declare.
2418
2419 * interp.c (Max, Min): New functions.
2420
2421 * mips.igen (BC1): Add tracing.
72f4393d 2422
c906108c 2423Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2424
c906108c 2425 * interp.c Added memory map for stack in vr4100
72f4393d 2426
c906108c
SS		 2427Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2428
2429 * interp.c (load_memory): Add missing "break"'s.
2430
2431Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2432
2433 * interp.c (sim_store_register, sim_fetch_register): Pass in
2434 length parameter. Return -1.
2435
2436Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2437
2438 * interp.c: Added hardware init hook, fixed warnings.
2439
2440Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2441
2442 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2443
2444Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2445
2446 * interp.c (ifetch16): New function.
2447
2448 * sim-main.h (IMEM32): Rename IMEM.
2449 (IMEM16_IMMED): Define.
2450 (IMEM16): Define.
2451 (DELAY_SLOT): Update.
72f4393d 2452
c906108c 2453 * m16run.c (sim_engine_run): New file.
72f4393d 2454
c906108c
SS		 2455 * m16.igen: All instructions except LB.
2456 (LB): Call do_load_byte.
2457 * mips.igen (do_load_byte): New function.
2458 (LB): Call do_load_byte.
2459
2460 * mips.igen: Move spec for insn bit size and high bit from here.
2461 * Makefile.in (tmp-igen, tmp-m16): To here.
2462
2463 * m16.dc: New file, decode mips16 instructions.
2464
2465 * Makefile.in (SIM_NO_ALL): Define.
2466 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2467
2468Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2469
2470 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2471 point unit to 32 bit registers.
2472 * configure: Re-generate.
2473
2474Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2475
2476 * configure.in (sim_use_gen): Make IGEN the default simulator
2477 generator for generic 32 and 64 bit mips targets.
2478 * configure: Re-generate.
2479
2480Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2481
2482 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2483 bitsize.
2484
2485 * interp.c (sim_fetch_register, sim_store_register): Read/write
2486 FGR from correct location.
2487 (sim_open): Set size of FGR's according to
2488 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2489
c906108c
SS		 2490 * sim-main.h (FGR): Store floating point registers in a separate
2491 array.
2492
2493Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2494
2495 * configure: Regenerated to track ../common/aclocal.m4 changes.
2496
2497Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2498
2499 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2500
2501 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2502
2503 * interp.c (pending_tick): New function. Deliver pending writes.
2504
2505 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2506 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2507 it can handle mixed sized quantites and single bits.
72f4393d 2508
c906108c
SS		 2509Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2510
2511 * interp.c (oengine.h): Do not include when building with IGEN.
2512 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2513 (sim_info): Ditto for PROCESSOR_64BIT.
2514 (sim_monitor): Replace ut_reg with unsigned_word.
2515 (*): Ditto for t_reg.
2516 (LOADDRMASK): Define.
2517 (sim_open): Remove defunct check that host FP is IEEE compliant,
2518 using software to emulate floating point.
2519 (value_fpr, ...): Always compile, was conditional on HASFPU.
2520
2521Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2522
2523 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2524 size.
2525
2526 * interp.c (SD, CPU): Define.
2527 (mips_option_handler): Set flags in each CPU.
2528 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2529 (sim_close): Do not clear STATE, deleted anyway.
2530 (sim_write, sim_read): Assume CPU zero's vm should be used for
2531 data transfers.
2532 (sim_create_inferior): Set the PC for all processors.
2533 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2534 argument.
2535 (mips16_entry): Pass correct nr of args to store_word, load_word.
2536 (ColdReset): Cold reset all cpu's.
2537 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2538 (sim_monitor, load_memory, store_memory, signal_exception): Use
2539 `CPU' instead of STATE_CPU.
2540
2541
2542 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2543 SD or CPU_.
72f4393d 2544
c906108c
SS		 2545 * sim-main.h (signal_exception): Add sim_cpu arg.
2546 (SignalException*): Pass both SD and CPU to signal_exception.
2547 * interp.c (signal_exception): Update.
72f4393d 2548
c906108c
SS		 2549 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2550 Ditto
2551 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2552 address_translation): Ditto
2553 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2554
c906108c
SS		 2555Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2556
2557 * configure: Regenerated to track ../common/aclocal.m4 changes.
2558
2559Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2560
2561 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2562
72f4393d 2563 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2564
2565 * sim-main.h (CPU_CIA): Delete.
2566 (SET_CIA, GET_CIA): Define
2567
2568Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2569
2570 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2571 regiser.
2572
2573 * configure.in (default_endian): Configure a big-endian simulator
2574 by default.
2575 * configure: Re-generate.
72f4393d 2576
c906108c
SS		 2577Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2578
2579 * configure: Regenerated to track ../common/aclocal.m4 changes.
2580
2581Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2582
2583 * interp.c (sim_monitor): Handle Densan monitor outbyte
2584 and inbyte functions.
2585
25861997-12-29 Felix Lee <flee@cygnus.com>
2587
2588 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2589
2590Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2591
2592 * Makefile.in (tmp-igen): Arrange for $zero to always be
2593 reset to zero after every instruction.
2594
2595Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2596
2597 * configure: Regenerated to track ../common/aclocal.m4 changes.
2598 * config.in: Ditto.
2599
2600Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2601
2602 * mips.igen (MSUB): Fix to work like MADD.
2603 * gencode.c (MSUB): Similarly.
2604
2605Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2606
2607 * configure: Regenerated to track ../common/aclocal.m4 changes.
2608
2609Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2610
2611 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2612
2613Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2614
2615 * sim-main.h (sim-fpu.h): Include.
2616
2617 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2618 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2619 using host independant sim_fpu module.
2620
2621Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2622
2623 * interp.c (signal_exception): Report internal errors with SIGABRT
2624 not SIGQUIT.
2625
2626 * sim-main.h (C0_CONFIG): New register.
2627 (signal.h): No longer include.
2628
2629 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2630
2631Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2632
2633 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2634
2635Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2636
2637 * mips.igen: Tag vr5000 instructions.
2638 (ANDI): Was missing mipsIV model, fix assembler syntax.
2639 (do_c_cond_fmt): New function.
2640 (C.cond.fmt): Handle mips I-III which do not support CC field
2641 separatly.
2642 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2643 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2644 in IV3.2 spec.
2645 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2646 vr5000 which saves LO in a GPR separatly.
72f4393d 2647
c906108c
SS		 2648 * configure.in (enable-sim-igen): For vr5000, select vr5000
2649 specific instructions.
2650 * configure: Re-generate.
72f4393d 2651
c906108c
SS		 2652Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2653
2654 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2655
2656 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2657 fmt_uninterpreted_64 bit cases to switch. Convert to
2658 fmt_formatted,
2659
2660 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2661
2662 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2663 as specified in IV3.2 spec.
2664 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2665
2666Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2667
2668 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2669 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2670 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2671 PENDING_FILL versions of instructions. Simplify.
2672 (X): New function.
2673 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2674 instructions.
2675 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2676 a signed value.
2677 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2678
c906108c
SS		 2679 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2680 global.
2681 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2682
2683Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2684
2685 * gencode.c (build_mips16_operands): Replace IPC with cia.
2686
2687 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2688 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2689 IPC to `cia'.
2690 (UndefinedResult): Replace function with macro/function
2691 combination.
2692 (sim_engine_run): Don't save PC in IPC.
2693
2694 * sim-main.h (IPC): Delete.
2695
2696
2697 * interp.c (signal_exception, store_word, load_word,
2698 address_translation, load_memory, store_memory, cache_op,
2699 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2700 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2701 current instruction address - cia - argument.
2702 (sim_read, sim_write): Call address_translation directly.
2703 (sim_engine_run): Rename variable vaddr to cia.
2704 (signal_exception): Pass cia to sim_monitor
72f4393d 2705
c906108c
SS		 2706 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2707 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2708 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2709
2710 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2711 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2712 SIM_ASSERT.
72f4393d 2713
c906108c
SS		 2714 * interp.c (signal_exception): Pass restart address to
2715 sim_engine_restart.
2716
2717 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2718 idecode.o): Add dependency.
2719
2720 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2721 Delete definitions
2722 (DELAY_SLOT): Update NIA not PC with branch address.
2723 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2724
2725 * mips.igen: Use CIA not PC in branch calculations.
2726 (illegal): Call SignalException.
2727 (BEQ, ADDIU): Fix assembler.
2728
2729Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2730
2731 * m16.igen (JALX): Was missing.
2732
2733 * configure.in (enable-sim-igen): New configuration option.
2734 * configure: Re-generate.
72f4393d 2735
c906108c
SS		 2736 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2737
2738 * interp.c (load_memory, store_memory): Delete parameter RAW.
2739 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2740 bypassing {load,store}_memory.
2741
2742 * sim-main.h (ByteSwapMem): Delete definition.
2743
2744 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2745
2746 * interp.c (sim_do_command, sim_commands): Delete mips specific
2747 commands. Handled by module sim-options.
72f4393d 2748
c906108c
SS		 2749 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2750 (WITH_MODULO_MEMORY): Define.
2751
2752 * interp.c (sim_info): Delete code printing memory size.
2753
2754 * interp.c (mips_size): Nee sim_size, delete function.
2755 (power2): Delete.
2756 (monitor, monitor_base, monitor_size): Delete global variables.
2757 (sim_open, sim_close): Delete code creating monitor and other
2758 memory regions. Use sim-memopts module, via sim_do_commandf, to
2759 manage memory regions.
2760 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2761
c906108c
SS		 2762 * interp.c (address_translation): Delete all memory map code
2763 except line forcing 32 bit addresses.
2764
2765Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2766
2767 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2768 trace options.
2769
2770 * interp.c (logfh, logfile): Delete globals.
2771 (sim_open, sim_close): Delete code opening & closing log file.
2772 (mips_option_handler): Delete -l and -n options.
2773 (OPTION mips_options): Ditto.
2774
2775 * interp.c (OPTION mips_options): Rename option trace to dinero.
2776 (mips_option_handler): Update.
2777
2778Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2779
2780 * interp.c (fetch_str): New function.
2781 (sim_monitor): Rewrite using sim_read & sim_write.
2782 (sim_open): Check magic number.
2783 (sim_open): Write monitor vectors into memory using sim_write.
2784 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2785 (sim_read, sim_write): Simplify - transfer data one byte at a
2786 time.
2787 (load_memory, store_memory): Clarify meaning of parameter RAW.
2788
2789 * sim-main.h (isHOST): Defete definition.
2790 (isTARGET): Mark as depreciated.
2791 (address_translation): Delete parameter HOST.
2792
2793 * interp.c (address_translation): Delete parameter HOST.
2794
2795Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2796
72f4393d 2797 * mips.igen:
c906108c
SS		 2798
2799 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2800 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2801
2802Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2803
2804 * mips.igen: Add model filter field to records.
2805
2806Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2807
2808 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2809
c906108c
SS		 2810 interp.c (sim_engine_run): Do not compile function sim_engine_run
2811 when WITH_IGEN == 1.
2812
2813 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2814 target architecture.
2815
2816 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2817 igen. Replace with configuration variables sim_igen_flags /
2818 sim_m16_flags.
2819
2820 * m16.igen: New file. Copy mips16 insns here.
2821 * mips.igen: From here.
2822
2823Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2824
2825 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2826 to top.
2827 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2828
2829Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2830
2831 * gencode.c (build_instruction): Follow sim_write's lead in using
2832 BigEndianMem instead of !ByteSwapMem.
2833
2834Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2835
2836 * configure.in (sim_gen): Dependent on target, select type of
2837 generator. Always select old style generator.
2838
2839 configure: Re-generate.
2840
2841 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2842 targets.
2843 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2844 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2845 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2846 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2847 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2848
c906108c
SS		 2849Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2850
2851 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2852
2853 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2854 CURRENT_FLOATING_POINT instead.
2855
2856 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2857 (address_translation): Raise exception InstructionFetch when
2858 translation fails and isINSTRUCTION.
72f4393d 2859
c906108c
SS		 2860 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2861 sim_engine_run): Change type of of vaddr and paddr to
2862 address_word.
2863 (address_translation, prefetch, load_memory, store_memory,
2864 cache_op): Change type of vAddr and pAddr to address_word.
2865
2866 * gencode.c (build_instruction): Change type of vaddr and paddr to
2867 address_word.
2868
2869Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2870
2871 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2872 macro to obtain result of ALU op.
2873
2874Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2875
2876 * interp.c (sim_info): Call profile_print.
2877
2878Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2879
2880 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2881
2882 * sim-main.h (WITH_PROFILE): Do not define, defined in
2883 common/sim-config.h. Use sim-profile module.
2884 (simPROFILE): Delete defintion.
2885
2886 * interp.c (PROFILE): Delete definition.
2887 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2888 (sim_close): Delete code writing profile histogram.
2889 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2890 Delete.
2891 (sim_engine_run): Delete code profiling the PC.
2892
2893Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2894
2895 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2896
2897 * interp.c (sim_monitor): Make register pointers of type
2898 unsigned_word*.
2899
2900 * sim-main.h: Make registers of type unsigned_word not
2901 signed_word.
2902
2903Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2904
2905 * interp.c (sync_operation): Rename from SyncOperation, make
2906 global, add SD argument.
2907 (prefetch): Rename from Prefetch, make global, add SD argument.
2908 (decode_coproc): Make global.
2909
2910 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2911
2912 * gencode.c (build_instruction): Generate DecodeCoproc not
2913 decode_coproc calls.
2914
2915 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2916 (SizeFGR): Move to sim-main.h
2917 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2918 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2919 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2920 sim-main.h.
2921 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2922 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2923 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2924 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2925 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2926 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2927
c906108c
SS		 2928 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2929 exception.
2930 (sim-alu.h): Include.
2931 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2932 (sim_cia): Typedef to instruction_address.
72f4393d 2933
c906108c
SS		 2934Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2935
2936 * Makefile.in (interp.o): Rename generated file engine.c to
2937 oengine.c.
72f4393d 2938
c906108c 2939 * interp.c: Update.
72f4393d 2940
c906108c
SS		 2941Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2942
2943 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2944
c906108c
SS		 2945Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2946
2947 * gencode.c (build_instruction): For "FPSQRT", output correct
2948 number of arguments to Recip.
72f4393d 2949
c906108c
SS		 2950Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2951
2952 * Makefile.in (interp.o): Depends on sim-main.h
2953
2954 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2955
2956 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2957 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2958 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2959 STATE, DSSTATE): Define
2960 (GPR, FGRIDX, ..): Define.
2961
2962 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2963 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2964 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2965
c906108c 2966 * interp.c: Update names to match defines from sim-main.h
72f4393d 2967
c906108c
SS		 2968Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2969
2970 * interp.c (sim_monitor): Add SD argument.
2971 (sim_warning): Delete. Replace calls with calls to
2972 sim_io_eprintf.
2973 (sim_error): Delete. Replace calls with sim_io_error.
2974 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2975 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2976 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2977 argument.
2978 (mips_size): Rename from sim_size. Add SD argument.
2979
2980 * interp.c (simulator): Delete global variable.
2981 (callback): Delete global variable.
2982 (mips_option_handler, sim_open, sim_write, sim_read,
2983 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2984 sim_size,sim_monitor): Use sim_io_* not callback->*.
2985 (sim_open): ZALLOC simulator struct.
2986 (PROFILE): Do not define.
2987
2988Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2989
2990 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2991 support.h with corresponding code.
2992
2993 * sim-main.h (word64, uword64), support.h: Move definition to
2994 sim-main.h.
2995 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2996
2997 * support.h: Delete
2998 * Makefile.in: Update dependencies
2999 * interp.c: Do not include.
72f4393d 3000
c906108c
SS		 3001Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3002
3003 * interp.c (address_translation, load_memory, store_memory,
3004 cache_op): Rename to from AddressTranslation et.al., make global,
3005 add SD argument
72f4393d 3006
c906108c
SS		 3007 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3008 CacheOp): Define.
72f4393d 3009
c906108c
SS		 3010 * interp.c (SignalException): Rename to signal_exception, make
3011 global.
3012
3013 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3014
c906108c
SS		 3015 * sim-main.h (SignalException, SignalExceptionInterrupt,
3016 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3017 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3018 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3019 Define.
72f4393d 3020
c906108c 3021 * interp.c, support.h: Use.
72f4393d 3022
c906108c
SS		 3023Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3024
3025 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3026 to value_fpr / store_fpr. Add SD argument.
3027 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3028 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3029
3030 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3031
c906108c
SS		 3032Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3033
3034 * interp.c (sim_engine_run): Check consistency between configure
3035 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3036 and HASFPU.
3037
3038 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3039 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3040 (mips_endian): Configure WITH_TARGET_ENDIAN.
3041 * configure: Update.
3042
3043Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3044
3045 * configure: Regenerated to track ../common/aclocal.m4 changes.
3046
3047Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3048
3049 * configure: Regenerated.
3050
3051Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3052
3053 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3054
3055Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3056
3057 * gencode.c (print_igen_insn_models): Assume certain architectures
3058 include all mips* instructions.
3059 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3060 instruction.
3061
3062 * Makefile.in (tmp.igen): Add target. Generate igen input from
3063 gencode file.
3064
3065 * gencode.c (FEATURE_IGEN): Define.
3066 (main): Add --igen option. Generate output in igen format.
3067 (process_instructions): Format output according to igen option.
3068 (print_igen_insn_format): New function.
3069 (print_igen_insn_models): New function.
3070 (process_instructions): Only issue warnings and ignore
3071 instructions when no FEATURE_IGEN.
3072
3073Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3074
3075 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3076 MIPS targets.
3077
3078Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3079
3080 * configure: Regenerated to track ../common/aclocal.m4 changes.
3081
3082Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3083
3084 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3085 SIM_RESERVED_BITS): Delete, moved to common.
3086 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3087
c906108c
SS		 3088Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3089
3090 * configure.in: Configure non-strict memory alignment.
3091 * configure: Regenerated to track ../common/aclocal.m4 changes.
3092
3093Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3094
3095 * configure: Regenerated to track ../common/aclocal.m4 changes.
3096
3097Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3098
3099 * gencode.c (SDBBP,DERET): Added (3900) insns.
3100 (RFE): Turn on for 3900.
3101 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3102 (dsstate): Made global.
3103 (SUBTARGET_R3900): Added.
3104 (CANCELDELAYSLOT): New.
3105 (SignalException): Ignore SystemCall rather than ignore and
3106 terminate. Add DebugBreakPoint handling.
3107 (decode_coproc): New insns RFE, DERET; and new registers Debug
3108 and DEPC protected by SUBTARGET_R3900.
3109 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3110 bits explicitly.
3111 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3112 * configure: Update.
c906108c
SS		 3113
3114Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3115
3116 * gencode.c: Add r3900 (tx39).
72f4393d 3117
c906108c
SS		 3118
3119Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3120
3121 * gencode.c (build_instruction): Don't need to subtract 4 for
3122 JALR, just 2.
3123
3124Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3125
3126 * interp.c: Correct some HASFPU problems.
3127
3128Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3129
3130 * configure: Regenerated to track ../common/aclocal.m4 changes.
3131
3132Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3133
3134 * interp.c (mips_options): Fix samples option short form, should
3135 be `x'.
3136
3137Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3138
3139 * interp.c (sim_info): Enable info code. Was just returning.
3140
3141Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3142
3143 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3144 MFC0.
3145
3146Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3147
3148 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3149 constants.
3150 (build_instruction): Ditto for LL.
3151
3152Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3153
3154 * configure: Regenerated to track ../common/aclocal.m4 changes.
3155
3156Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3157
3158 * configure: Regenerated to track ../common/aclocal.m4 changes.
3159 * config.in: Ditto.
3160
3161Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3162
3163 * interp.c (sim_open): Add call to sim_analyze_program, update
3164 call to sim_config.
3165
3166Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3167
3168 * interp.c (sim_kill): Delete.
3169 (sim_create_inferior): Add ABFD argument. Set PC from same.
3170 (sim_load): Move code initializing trap handlers from here.
3171 (sim_open): To here.
3172 (sim_load): Delete, use sim-hload.c.
3173
3174 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3175
3176Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3177
3178 * configure: Regenerated to track ../common/aclocal.m4 changes.
3179 * config.in: Ditto.
3180
3181Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3182
3183 * interp.c (sim_open): Add ABFD argument.
3184 (sim_load): Move call to sim_config from here.
3185 (sim_open): To here. Check return status.
3186
3187Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3188
c906108c
SS		 3189 * gencode.c (build_instruction): Two arg MADD should
3190 not assign result to $0.
72f4393d 3191
c906108c
SS		 3192Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3193
3194 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3195 * sim/mips/configure.in: Regenerate.
3196
3197Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3198
3199 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3200 signed8, unsigned8 et.al. types.
3201
3202 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3203 hosts when selecting subreg.
3204
3205Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3206
3207 * interp.c (sim_engine_run): Reset the ZERO register to zero
3208 regardless of FEATURE_WARN_ZERO.
3209 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3210
3211Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3212
3213 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3214 (SignalException): For BreakPoints ignore any mode bits and just
3215 save the PC.
3216 (SignalException): Always set the CAUSE register.
3217
3218Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3219
3220 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3221 exception has been taken.
3222
3223 * interp.c: Implement the ERET and mt/f sr instructions.
3224
3225Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3226
3227 * interp.c (SignalException): Don't bother restarting an
3228 interrupt.
3229
3230Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3231
3232 * interp.c (SignalException): Really take an interrupt.
3233 (interrupt_event): Only deliver interrupts when enabled.
3234
3235Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3236
3237 * interp.c (sim_info): Only print info when verbose.
3238 (sim_info) Use sim_io_printf for output.
72f4393d 3239
c906108c
SS		 3240Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3241
3242 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3243 mips architectures.
3244
3245Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3246
3247 * interp.c (sim_do_command): Check for common commands if a
3248 simulator specific command fails.
3249
3250Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3251
3252 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3253 and simBE when DEBUG is defined.
3254
3255Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3256
3257 * interp.c (interrupt_event): New function. Pass exception event
3258 onto exception handler.
3259
3260 * configure.in: Check for stdlib.h.
3261 * configure: Regenerate.
3262
3263 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3264 variable declaration.
3265 (build_instruction): Initialize memval1.
3266 (build_instruction): Add UNUSED attribute to byte, bigend,
3267 reverse.
3268 (build_operands): Ditto.
3269
3270 * interp.c: Fix GCC warnings.
3271 (sim_get_quit_code): Delete.
3272
3273 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3274 * Makefile.in: Ditto.
3275 * configure: Re-generate.
72f4393d 3276
c906108c
SS		 3277 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3278
3279Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3280
3281 * interp.c (mips_option_handler): New function parse argumes using
3282 sim-options.
3283 (myname): Replace with STATE_MY_NAME.
3284 (sim_open): Delete check for host endianness - performed by
3285 sim_config.
3286 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3287 (sim_open): Move much of the initialization from here.
3288 (sim_load): To here. After the image has been loaded and
3289 endianness set.
3290 (sim_open): Move ColdReset from here.
3291 (sim_create_inferior): To here.
3292 (sim_open): Make FP check less dependant on host endianness.
3293
3294 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3295 run.
3296 * interp.c (sim_set_callbacks): Delete.
3297
3298 * interp.c (membank, membank_base, membank_size): Replace with
3299 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3300 (sim_open): Remove call to callback->init. gdb/run do this.
3301
3302 * interp.c: Update
3303
3304 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3305
3306 * interp.c (big_endian_p): Delete, replaced by
3307 current_target_byte_order.
3308
3309Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3310
3311 * interp.c (host_read_long, host_read_word, host_swap_word,
3312 host_swap_long): Delete. Using common sim-endian.
3313 (sim_fetch_register, sim_store_register): Use H2T.
3314 (pipeline_ticks): Delete. Handled by sim-events.
3315 (sim_info): Update.
3316 (sim_engine_run): Update.
3317
3318Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3319
3320 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3321 reason from here.
3322 (SignalException): To here. Signal using sim_engine_halt.
3323 (sim_stop_reason): Delete, moved to common.
72f4393d 3324
c906108c
SS		 3325Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3326
3327 * interp.c (sim_open): Add callback argument.
3328 (sim_set_callbacks): Delete SIM_DESC argument.
3329 (sim_size): Ditto.
3330
3331Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3332
3333 * Makefile.in (SIM_OBJS): Add common modules.
3334
3335 * interp.c (sim_set_callbacks): Also set SD callback.
3336 (set_endianness, xfer_*, swap_*): Delete.
3337 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3338 Change to functions using sim-endian macros.
3339 (control_c, sim_stop): Delete, use common version.
3340 (simulate): Convert into.
3341 (sim_engine_run): This function.
3342 (sim_resume): Delete.
72f4393d 3343
c906108c
SS		 3344 * interp.c (simulation): New variable - the simulator object.
3345 (sim_kind): Delete global - merged into simulation.
3346 (sim_load): Cleanup. Move PC assignment from here.
3347 (sim_create_inferior): To here.
3348
3349 * sim-main.h: New file.
3350 * interp.c (sim-main.h): Include.
72f4393d 3351
c906108c
SS		 3352Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3353
3354 * configure: Regenerated to track ../common/aclocal.m4 changes.
3355
3356Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3357
3358 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3359
3360Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3361
72f4393d
L		 3362 * gencode.c (build_instruction): DIV instructions: check
3363 for division by zero and integer overflow before using
c906108c
SS		 3364 host's division operation.
3365
3366Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3367
3368 * Makefile.in (SIM_OBJS): Add sim-load.o.
3369 * interp.c: #include bfd.h.
3370 (target_byte_order): Delete.
3371 (sim_kind, myname, big_endian_p): New static locals.
3372 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3373 after argument parsing. Recognize -E arg, set endianness accordingly.
3374 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3375 load file into simulator. Set PC from bfd.
3376 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3377 (set_endianness): Use big_endian_p instead of target_byte_order.
3378
3379Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3380
3381 * interp.c (sim_size): Delete prototype - conflicts with
3382 definition in remote-sim.h. Correct definition.
3383
3384Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3385
3386 * configure: Regenerated to track ../common/aclocal.m4 changes.
3387 * config.in: Ditto.
3388
3389Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3390
3391 * interp.c (sim_open): New arg `kind'.
3392
3393 * configure: Regenerated to track ../common/aclocal.m4 changes.
3394
3395Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3396
3397 * configure: Regenerated to track ../common/aclocal.m4 changes.
3398
3399Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3400
3401 * interp.c (sim_open): Set optind to 0 before calling getopt.
3402
3403Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3404
3405 * configure: Regenerated to track ../common/aclocal.m4 changes.
3406
3407Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3408
3409 * interp.c : Replace uses of pr_addr with pr_uword64
3410 where the bit length is always 64 independent of SIM_ADDR.
3411 (pr_uword64) : added.
3412
3413Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3414
3415 * configure: Re-generate.
3416
3417Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3418
3419 * configure: Regenerate to track ../common/aclocal.m4 changes.
3420
3421Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3422
3423 * interp.c (sim_open): New SIM_DESC result. Argument is now
3424 in argv form.
3425 (other sim_*): New SIM_DESC argument.
3426
3427Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3428
3429 * interp.c: Fix printing of addresses for non-64-bit targets.
3430 (pr_addr): Add function to print address based on size.
3431
3432Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3433
3434 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3435
3436Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3437
3438 * gencode.c (build_mips16_operands): Correct computation of base
3439 address for extended PC relative instruction.
3440
3441Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3442
3443 * interp.c (mips16_entry): Add support for floating point cases.
3444 (SignalException): Pass floating point cases to mips16_entry.
3445 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3446 registers.
3447 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3448 or fmt_word.
3449 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3450 and then set the state to fmt_uninterpreted.
3451 (COP_SW): Temporarily set the state to fmt_word while calling
3452 ValueFPR.
3453
3454Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3455
3456 * gencode.c (build_instruction): The high order may be set in the
3457 comparison flags at any ISA level, not just ISA 4.
3458
3459Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3460
3461 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3462 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3463 * configure.in: sinclude ../common/aclocal.m4.
3464 * configure: Regenerated.
3465
3466Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3467
3468 * configure: Rebuild after change to aclocal.m4.
3469
3470Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3471
3472 * configure configure.in Makefile.in: Update to new configure
3473 scheme which is more compatible with WinGDB builds.
3474 * configure.in: Improve comment on how to run autoconf.
3475 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3476 * Makefile.in: Use autoconf substitution to install common
3477 makefile fragment.
3478
3479Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3480
3481 * gencode.c (build_instruction): Use BigEndianCPU instead of
3482 ByteSwapMem.
3483
3484Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3485
3486 * interp.c (sim_monitor): Make output to stdout visible in
3487 wingdb's I/O log window.
3488
3489Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3490
3491 * support.h: Undo previous change to SIGTRAP
3492 and SIGQUIT values.
3493
3494Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3495
3496 * interp.c (store_word, load_word): New static functions.
3497 (mips16_entry): New static function.
3498 (SignalException): Look for mips16 entry and exit instructions.
3499 (simulate): Use the correct index when setting fpr_state after
3500 doing a pending move.
3501
3502Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3503
3504 * interp.c: Fix byte-swapping code throughout to work on
3505 both little- and big-endian hosts.
3506
3507Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3508
3509 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3510 with gdb/config/i386/xm-windows.h.
3511
3512Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3513
3514 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3515 that messes up arithmetic shifts.
3516
3517Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3518
3519 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3520 SIGTRAP and SIGQUIT for _WIN32.
3521
3522Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3523
3524 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3525 force a 64 bit multiplication.
3526 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3527 destination register is 0, since that is the default mips16 nop
3528 instruction.
3529
3530Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3531
3532 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3533 (build_endian_shift): Don't check proc64.
3534 (build_instruction): Always set memval to uword64. Cast op2 to
3535 uword64 when shifting it left in memory instructions. Always use
3536 the same code for stores--don't special case proc64.
3537
3538 * gencode.c (build_mips16_operands): Fix base PC value for PC
3539 relative operands.
3540 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3541 jal instruction.
3542 * interp.c (simJALDELAYSLOT): Define.
3543 (JALDELAYSLOT): Define.
3544 (INDELAYSLOT, INJALDELAYSLOT): Define.
3545 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3546
3547Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3548
3549 * interp.c (sim_open): add flush_cache as a PMON routine
3550 (sim_monitor): handle flush_cache by ignoring it
3551
3552Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3553
3554 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3555 BigEndianMem.
3556 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3557 (BigEndianMem): Rename to ByteSwapMem and change sense.
3558 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3559 BigEndianMem references to !ByteSwapMem.
3560 (set_endianness): New function, with prototype.
3561 (sim_open): Call set_endianness.
3562 (sim_info): Use simBE instead of BigEndianMem.
3563 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3564 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3565 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3566 ifdefs, keeping the prototype declaration.
3567 (swap_word): Rewrite correctly.
3568 (ColdReset): Delete references to CONFIG. Delete endianness related
3569 code; moved to set_endianness.
72f4393d 3570
c906108c
SS		 3571Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3572
3573 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3574 * interp.c (CHECKHILO): Define away.
3575 (simSIGINT): New macro.
3576 (membank_size): Increase from 1MB to 2MB.
3577 (control_c): New function.
3578 (sim_resume): Rename parameter signal to signal_number. Add local
3579 variable prev. Call signal before and after simulate.
3580 (sim_stop_reason): Add simSIGINT support.
3581 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3582 functions always.
3583 (sim_warning): Delete call to SignalException. Do call printf_filtered
3584 if logfh is NULL.
3585 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3586 a call to sim_warning.
3587
3588Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3589
3590 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3591 16 bit instructions.
3592
3593Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3594
3595 Add support for mips16 (16 bit MIPS implementation):
3596 * gencode.c (inst_type): Add mips16 instruction encoding types.
3597 (GETDATASIZEINSN): Define.
3598 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3599 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3600 mtlo.
3601 (MIPS16_DECODE): New table, for mips16 instructions.
3602 (bitmap_val): New static function.
3603 (struct mips16_op): Define.
3604 (mips16_op_table): New table, for mips16 operands.
3605 (build_mips16_operands): New static function.
3606 (process_instructions): If PC is odd, decode a mips16
3607 instruction. Break out instruction handling into new
3608 build_instruction function.
3609 (build_instruction): New static function, broken out of
3610 process_instructions. Check modifiers rather than flags for SHIFT
3611 bit count and m[ft]{hi,lo} direction.
3612 (usage): Pass program name to fprintf.
3613 (main): Remove unused variable this_option_optind. Change
3614 ``*loptarg++'' to ``loptarg++''.
3615 (my_strtoul): Parenthesize && within ||.
3616 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3617 (simulate): If PC is odd, fetch a 16 bit instruction, and
3618 increment PC by 2 rather than 4.
3619 * configure.in: Add case for mips16*-*-*.
3620 * configure: Rebuild.
3621
3622Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3623
3624 * interp.c: Allow -t to enable tracing in standalone simulator.
3625 Fix garbage output in trace file and error messages.
3626
3627Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3628
3629 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3630 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3631 * configure.in: Simplify using macros in ../common/aclocal.m4.
3632 * configure: Regenerated.
3633 * tconfig.in: New file.
3634
3635Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3636
3637 * interp.c: Fix bugs in 64-bit port.
3638 Use ansi function declarations for msvc compiler.
3639 Initialize and test file pointer in trace code.
3640 Prevent duplicate definition of LAST_EMED_REGNUM.
3641
3642Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3643
3644 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3645
3646Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3647
3648 * interp.c (SignalException): Check for explicit terminating
3649 breakpoint value.
3650 * gencode.c: Pass instruction value through SignalException()
3651 calls for Trap, Breakpoint and Syscall.
3652
3653Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3654
3655 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3656 only used on those hosts that provide it.
3657 * configure.in: Add sqrt() to list of functions to be checked for.
3658 * config.in: Re-generated.
3659 * configure: Re-generated.
3660
3661Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3662
3663 * gencode.c (process_instructions): Call build_endian_shift when
3664 expanding STORE RIGHT, to fix swr.
3665 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3666 clear the high bits.
3667 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3668 Fix float to int conversions to produce signed values.
3669
3670Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3671
3672 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3673 (process_instructions): Correct handling of nor instruction.
3674 Correct shift count for 32 bit shift instructions. Correct sign
3675 extension for arithmetic shifts to not shift the number of bits in
3676 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3677 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3678 Fix madd.
3679 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3680 It's OK to have a mult follow a mult. What's not OK is to have a
3681 mult follow an mfhi.
3682 (Convert): Comment out incorrect rounding code.
3683
3684Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3685
3686 * interp.c (sim_monitor): Improved monitor printf
3687 simulation. Tidied up simulator warnings, and added "--log" option
3688 for directing warning message output.
3689 * gencode.c: Use sim_warning() rather than WARNING macro.
3690
3691Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3692
3693 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3694 getopt1.o, rather than on gencode.c. Link objects together.
3695 Don't link against -liberty.
3696 (gencode.o, getopt.o, getopt1.o): New targets.
3697 * gencode.c: Include <ctype.h> and "ansidecl.h".
3698 (AND): Undefine after including "ansidecl.h".
3699 (ULONG_MAX): Define if not defined.
3700 (OP_*): Don't define macros; now defined in opcode/mips.h.
3701 (main): Call my_strtoul rather than strtoul.
3702 (my_strtoul): New static function.
3703
3704Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3705
3706 * gencode.c (process_instructions): Generate word64 and uword64
3707 instead of `long long' and `unsigned long long' data types.
3708 * interp.c: #include sysdep.h to get signals, and define default
3709 for SIGBUS.
3710 * (Convert): Work around for Visual-C++ compiler bug with type
3711 conversion.
3712 * support.h: Make things compile under Visual-C++ by using
3713 __int64 instead of `long long'. Change many refs to long long
3714 into word64/uword64 typedefs.
3715
3716Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3717
72f4393d
L		 3718 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3719 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3720 (docdir): Removed.
3721 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3722 (AC_PROG_INSTALL): Added.
c906108c 3723 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3724 * configure: Rebuilt.
3725
c906108c
SS		 3726Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3727
3728 * configure.in: Define @SIMCONF@ depending on mips target.
3729 * configure: Rebuild.
3730 * Makefile.in (run): Add @SIMCONF@ to control simulator
3731 construction.
3732 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3733 * interp.c: Remove some debugging, provide more detailed error
3734 messages, update memory accesses to use LOADDRMASK.
72f4393d 3735
c906108c
SS		 3736Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3737
3738 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3739 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3740 stamp-h.
3741 * configure: Rebuild.
3742 * config.in: New file, generated by autoheader.
3743 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3744 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3745 HAVE_ANINT and HAVE_AINT, as appropriate.
3746 * Makefile.in (run): Use @LIBS@ rather than -lm.
3747 (interp.o): Depend upon config.h.
3748 (Makefile): Just rebuild Makefile.
3749 (clean): Remove stamp-h.
3750 (mostlyclean): Make the same as clean, not as distclean.
3751 (config.h, stamp-h): New targets.
3752
3753Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3754
3755 * interp.c (ColdReset): Fix boolean test. Make all simulator
3756 globals static.
3757
3758Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3759
3760 * interp.c (xfer_direct_word, xfer_direct_long,
3761 swap_direct_word, swap_direct_long, xfer_big_word,
3762 xfer_big_long, xfer_little_word, xfer_little_long,
3763 swap_word,swap_long): Added.
3764 * interp.c (ColdReset): Provide function indirection to
3765 host<->simulated_target transfer routines.
3766 * interp.c (sim_store_register, sim_fetch_register): Updated to
3767 make use of indirected transfer routines.
3768
3769Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3770
3771 * gencode.c (process_instructions): Ensure FP ABS instruction
3772 recognised.
3773 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3774 system call support.
3775
3776Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3777
3778 * interp.c (sim_do_command): Complain if callback structure not
3779 initialised.
3780
3781Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3782
3783 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3784 support for Sun hosts.
3785 * Makefile.in (gencode): Ensure the host compiler and libraries
3786 used for cross-hosted build.
3787
3788Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3789
3790 * interp.c, gencode.c: Some more (TODO) tidying.
3791
3792Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3793
3794 * gencode.c, interp.c: Replaced explicit long long references with
3795 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3796 * support.h (SET64LO, SET64HI): Macros added.
3797
3798Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3799
3800 * configure: Regenerate with autoconf 2.7.
3801
3802Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3803
3804 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3805 * support.h: Remove superfluous "1" from #if.
3806 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3807
3808Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3809
3810 * interp.c (StoreFPR): Control UndefinedResult() call on
3811 WARN_RESULT manifest.
3812
3813Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3814
3815 * gencode.c: Tidied instruction decoding, and added FP instruction
3816 support.
3817
3818 * interp.c: Added dineroIII, and BSD profiling support. Also
3819 run-time FP handling.
3820
3821Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3822
3823 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3824 gencode.c, interp.c, support.h: created.
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