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sim: dv-sockser: add stub funcs when not available
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
3649cb06
MF		 12015-03-23 Mike Frysinger <vapier@gentoo.org>
2
3 * configure: Regenerate.
4 * configure.ac: Delete sim_hw checks for dv-sockser.
5
ae7d0cac
MF		 62015-03-16 Mike Frysinger <vapier@gentoo.org>
7
8 * config.in, configure: Regenerate.
9 * tconfig.in: Rename file ...
10 * tconfig.h: ... here.
11
8406bb59
MF		 122015-03-15 Mike Frysinger <vapier@gentoo.org>
13
14 * tconfig.in: Delete includes.
15 [HAVE_DV_SOCKSER]: Delete.
16
465fb143
MF		 172015-03-14 Mike Frysinger <vapier@gentoo.org>
18
19 * Makefile.in (SIM_RUN_OBJS): Delete.
20
5cddc23a
MF		 212015-03-14 Mike Frysinger <vapier@gentoo.org>
22
23 * configure.ac (AC_CHECK_HEADERS): Delete.
24 * aclocal.m4, configure: Regenerate.
25
2974be62
AM		 262014-08-19 Alan Modra <amodra@gmail.com>
27
28 * configure: Regenerate.
29
faa743bb
RM		 302014-08-15 Roland McGrath <mcgrathr@google.com>
31
32 * configure: Regenerate.
33 * config.in: Regenerate.
34
1a8a700e
MF		 352014-03-04 Mike Frysinger <vapier@gentoo.org>
36
37 * configure: Regenerate.
38
bf3d9781
AM		 392013-09-23 Alan Modra <amodra@gmail.com>
40
41 * configure: Regenerate.
42
31e6ad7d
MF		 432013-06-03 Mike Frysinger <vapier@gentoo.org>
44
45 * aclocal.m4, configure: Regenerate.
46
d3685d60
TT		 472013-05-10 Freddie Chopin <freddie_chopin@op.pl>
48
49 * configure: Rebuild.
50
1517bd27
MF		 512013-03-26 Mike Frysinger <vapier@gentoo.org>
52
53 * configure: Regenerate.
54
3be31516
JS		 552013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
56
57 * configure.ac: Address use of dv-sockser.o.
58 * tconfig.in: Conditionalize use of dv_sockser_install.
59 * configure: Regenerated.
60 * config.in: Regenerated.
61
37cb8f8e
SE		 622012-10-04 Chao-ying Fu <fu@mips.com>
63 Steve Ellcey <sellcey@mips.com>
64
65 * mips/mips3264r2.igen (rdhwr): New.
66
87c8644f
JS		 672012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
68
69 * configure.ac: Always link against dv-sockser.o.
70 * configure: Regenerate.
71
5f3ef9d0
JB		 722012-06-15 Joel Brobecker <brobecker@adacore.com>
73
74 * config.in, configure: Regenerate.
75
a6ff997c
NC		 762012-05-18 Nick Clifton <nickc@redhat.com>
77
78 PR 14072
79 * interp.c: Include config.h before system header files.
80
2232061b
MF		 812012-03-24 Mike Frysinger <vapier@gentoo.org>
82
83 * aclocal.m4, config.in, configure: Regenerate.
84
db2e4d67
MF		 852011-12-03 Mike Frysinger <vapier@gentoo.org>
86
87 * aclocal.m4: New file.
88 * configure: Regenerate.
89
4399a56b
MF		 902011-10-19 Mike Frysinger <vapier@gentoo.org>
91
92 * configure: Regenerate after common/acinclude.m4 update.
93
9c082ca8
MF		 942011-10-17 Mike Frysinger <vapier@gentoo.org>
95
96 * configure.ac: Change include to common/acinclude.m4.
97
6ffe910a
MF		 982011-10-17 Mike Frysinger <vapier@gentoo.org>
99
100 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
101 call. Replace common.m4 include with SIM_AC_COMMON.
102 * configure: Regenerate.
103
31b28250
HPN		 1042011-07-08 Hans-Peter Nilsson <hp@axis.com>
105
3faa01e3
HPN		 106 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
107 $(SIM_EXTRA_DEPS).
108 (tmp-mach-multi): Exit early when igen fails.
31b28250 109
2419798b
MF		 1102011-07-05 Mike Frysinger <vapier@gentoo.org>
111
112 * interp.c (sim_do_command): Delete.
113
d79fe0d6
MF		 1142011-02-14 Mike Frysinger <vapier@gentoo.org>
115
116 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
117 (tx3904sio_fifo_reset): Likewise.
118 * interp.c (sim_monitor): Likewise.
119
5558e7e6
MF		 1202010-04-14 Mike Frysinger <vapier@gentoo.org>
121
122 * interp.c (sim_write): Add const to buffer arg.
123
35aafff4
JB		 1242010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
125
126 * interp.c: Don't include sysdep.h
127
3725885a
RW		 1282010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
129
130 * configure: Regenerate.
131
d6416cdc
RW		 1322009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
133
81ecdfbb
RW		 134 * config.in: Regenerate.
135 * configure: Likewise.
136
d6416cdc
RW		 137 * configure: Regenerate.
138
b5bd9624
HPN		 1392008-07-11 Hans-Peter Nilsson <hp@axis.com>
140
141 * configure: Regenerate to track ../common/common.m4 changes.
142 * config.in: Ditto.
143
6efef468
JM		 1442008-06-06 Vladimir Prus <vladimir@codesourcery.com>
145 Daniel Jacobowitz <dan@codesourcery.com>
146 Joseph Myers <joseph@codesourcery.com>
147
148 * configure: Regenerate.
149
60dc88db
RS		 1502007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
151
152 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
153 that unconditionally allows fmt_ps.
154 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
155 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
156 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
157 filter from 64,f to 32,f.
158 (PREFX): Change filter from 64 to 32.
159 (LDXC1, LUXC1): Provide separate mips32r2 implementations
160 that use do_load_double instead of do_load. Make both LUXC1
161 versions unpredictable if SizeFGR () != 64.
162 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
163 instead of do_store. Remove unused variable. Make both SUXC1
164 versions unpredictable if SizeFGR () != 64.
165
599ca73e
RS		 1662007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
167
168 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
169 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
170 shifts for that case.
171
2525df03
NC		 1722007-09-04 Nick Clifton <nickc@redhat.com>
173
174 * interp.c (options enum): Add OPTION_INFO_MEMORY.
175 (display_mem_info): New static variable.
176 (mips_option_handler): Handle OPTION_INFO_MEMORY.
177 (mips_options): Add info-memory and memory-info.
178 (sim_open): After processing the command line and board
179 specification, check display_mem_info. If it is set then
180 call the real handler for the --memory-info command line
181 switch.
182
35ee6e1e
JB		 1832007-08-24 Joel Brobecker <brobecker@adacore.com>
184
185 * configure.ac: Change license of multi-run.c to GPL version 3.
186 * configure: Regenerate.
187
d5fb0879
RS		 1882007-06-28 Richard Sandiford <richard@codesourcery.com>
189
190 * configure.ac, configure: Revert last patch.
191
2a2ce21b
RS		 1922007-06-26 Richard Sandiford <richard@codesourcery.com>
193
194 * configure.ac (sim_mipsisa3264_configs): New variable.
195 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
196 every configuration support all four targets, using the triplet to
197 determine the default.
198 * configure: Regenerate.
199
efdcccc9
RS		 2002007-06-25 Richard Sandiford <richard@codesourcery.com>
201
0a7692b2 202 * Makefile.in (m16run.o): New rule.
efdcccc9 203
f532a356
TS		 2042007-05-15 Thiemo Seufer <ths@mips.com>
205
206 * mips3264r2.igen (DSHD): Fix compile warning.
207
bfe9c90b
TS		 2082007-05-14 Thiemo Seufer <ths@mips.com>
209
210 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
211 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
212 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
213 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
214 for mips32r2.
215
53f4826b
TS		 2162007-03-01 Thiemo Seufer <ths@mips.com>
217
218 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
219 and mips64.
220
8bf3ddc8
TS		 2212007-02-20 Thiemo Seufer <ths@mips.com>
222
223 * dsp.igen: Update copyright notice.
224 * dsp2.igen: Fix copyright notice.
225
8b082fb1
TS		 2262007-02-20 Thiemo Seufer <ths@mips.com>
227 Chao-Ying Fu <fu@mips.com>
228
229 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
230 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
231 Add dsp2 to sim_igen_machine.
232 * configure: Regenerate.
233 * dsp.igen (do_ph_op): Add MUL support when op = 2.
234 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
235 (mulq_rs.ph): Use do_ph_mulq.
236 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
237 * mips.igen: Add dsp2 model and include dsp2.igen.
238 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
239 for *mips32r2, *mips64r2, *dsp.
240 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
241 for *mips32r2, *mips64r2, *dsp2.
242 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
243
b1004875
TS		 2442007-02-19 Thiemo Seufer <ths@mips.com>
245 Nigel Stephens <nigel@mips.com>
246
247 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
248 jumps with hazard barrier.
249
f8df4c77
TS		 2502007-02-19 Thiemo Seufer <ths@mips.com>
251 Nigel Stephens <nigel@mips.com>
252
253 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
254 after each call to sim_io_write.
255
b1004875 2562007-02-19 Thiemo Seufer <ths@mips.com>
07802d98 257 Nigel Stephens <nigel@mips.com>
b1004875
TS		 258
259 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
260 supported by this simulator.
07802d98
TS		 261 (decode_coproc): Recognise additional CP0 Config registers
262 correctly.
263
14fb6c5a
TS		 2642007-02-19 Thiemo Seufer <ths@mips.com>
265 Nigel Stephens <nigel@mips.com>
266 David Ung <davidu@mips.com>
267
268 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
269 uninterpreted formats. If fmt is one of the uninterpreted types
270 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
271 fmt_word, and fmt_uninterpreted_64 like fmt_long.
272 (store_fpr): When writing an invalid odd register, set the
273 matching even register to fmt_unknown, not the following register.
274 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
275 the the memory window at offset 0 set by --memory-size command
276 line option.
277 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
278 point register.
279 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
280 register.
281 (sim_monitor): When returning the memory size to the MIPS
282 application, use the value in STATE_MEM_SIZE, not an arbitrary
283 hardcoded value.
284 (cop_lw): Don' mess around with FPR_STATE, just pass
285 fmt_uninterpreted_32 to StoreFPR.
286 (cop_sw): Similarly.
287 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
288 (cop_sd): Similarly.
289 * mips.igen (not_word_value): Single version for mips32, mips64
290 and mips16.
291
c8847145
TS		 2922007-02-19 Thiemo Seufer <ths@mips.com>
293 Nigel Stephens <nigel@mips.com>
294
295 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
296 MBytes.
297
4b5d35ee
TS		 2982007-02-17 Thiemo Seufer <ths@mips.com>
299
300 * configure.ac (mips*-sde-elf*): Move in front of generic machine
301 configuration.
302 * configure: Regenerate.
303
3669427c
TS		 3042007-02-17 Thiemo Seufer <ths@mips.com>
305
306 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
307 Add mdmx to sim_igen_machine.
308 (mipsisa64*-*-*): Likewise. Remove dsp.
309 (mipsisa32*-*-*): Remove dsp.
310 * configure: Regenerate.
311
109ad085
TS		 3122007-02-13 Thiemo Seufer <ths@mips.com>
313
314 * configure.ac: Add mips*-sde-elf* target.
315 * configure: Regenerate.
316
921d7ad3
HPN		 3172006-12-21 Hans-Peter Nilsson <hp@axis.com>
318
319 * acconfig.h: Remove.
320 * config.in, configure: Regenerate.
321
02f97da7
TS		 3222006-11-07 Thiemo Seufer <ths@mips.com>
323
324 * dsp.igen (do_w_op): Fix compiler warning.
325
2d2733fc
TS		 3262006-08-29 Thiemo Seufer <ths@mips.com>
327 David Ung <davidu@mips.com>
328
329 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
330 sim_igen_machine.
331 * configure: Regenerate.
332 * mips.igen (model): Add smartmips.
333 (MADDU): Increment ACX if carry.
334 (do_mult): Clear ACX.
335 (ROR,RORV): Add smartmips.
336 (include): Include smartmips.igen.
337 * sim-main.h (ACX): Set to REGISTERS[89].
338 * smartmips.igen: New file.
339
d85c3a10
TS		 3402006-08-29 Thiemo Seufer <ths@mips.com>
341 David Ung <davidu@mips.com>
342
343 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
344 mips3264r2.igen. Add missing dependency rules.
345 * m16e.igen: Support for mips16e save/restore instructions.
346
e85e3205
RE		 3472006-06-13 Richard Earnshaw <rearnsha@arm.com>
348
349 * configure: Regenerated.
350
2f0122dc
DJ		 3512006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
352
353 * configure: Regenerated.
354
20e95c23
DJ		 3552006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
356
357 * configure: Regenerated.
358
69088b17
CF		 3592006-05-15 Chao-ying Fu <fu@mips.com>
360
361 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
362
0275de4e
NC		 3632006-04-18 Nick Clifton <nickc@redhat.com>
364
365 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
366 statement.
367
b3a3ffef
HPN		 3682006-03-29 Hans-Peter Nilsson <hp@axis.com>
369
370 * configure: Regenerate.
371
40a5538e
CF		 3722005-12-14 Chao-ying Fu <fu@mips.com>
373
374 * Makefile.in (SIM_OBJS): Add dsp.o.
375 (dsp.o): New dependency.
376 (IGEN_INCLUDE): Add dsp.igen.
377 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
378 mipsisa64*-*-*): Add dsp to sim_igen_machine.
379 * configure: Regenerate.
380 * mips.igen: Add dsp model and include dsp.igen.
381 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
382 because these instructions are extended in DSP ASE.
383 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
384 adding 6 DSP accumulator registers and 1 DSP control register.
385 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
386 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
387 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
388 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
389 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
390 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
391 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
392 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
393 DSPCR_CCOND_SMASK): New define.
394 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
395 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
396
21d14896
ILT		 3972005-07-08 Ian Lance Taylor <ian@airs.com>
398
399 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
400
b16d63da
DU		 4012005-06-16 David Ung <davidu@mips.com>
402 Nigel Stephens <nigel@mips.com>
403
404 * mips.igen: New mips16e model and include m16e.igen.
405 (check_u64): Add mips16e tag.
406 * m16e.igen: New file for MIPS16e instructions.
407 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
408 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
409 models.
410 * configure: Regenerate.
411
e70cb6cd
CD		 4122005-05-26 David Ung <davidu@mips.com>
413
414 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
415 tags to all instructions which are applicable to the new ISAs.
416 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
417 vr.igen.
418 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
419 instructions.
420 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
421 to mips.igen.
422 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
423 * configure: Regenerate.
424
2b193c4a
MK		 4252005-03-23 Mark Kettenis <kettenis@gnu.org>
426
427 * configure: Regenerate.
428
35695fd6
AC		 4292005-01-14 Andrew Cagney <cagney@gnu.org>
430
431 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
432 explicit call to AC_CONFIG_HEADER.
433 * configure: Regenerate.
434
f0569246
AC		 4352005-01-12 Andrew Cagney <cagney@gnu.org>
436
437 * configure.ac: Update to use ../common/common.m4.
438 * configure: Re-generate.
439
38f48d72
AC		 4402005-01-11 Andrew Cagney <cagney@localhost.localdomain>
441
442 * configure: Regenerated to track ../common/aclocal.m4 changes.
443
b7026657
AC		 4442005-01-07 Andrew Cagney <cagney@gnu.org>
445
446 * configure.ac: Rename configure.in, require autoconf 2.59.
447 * configure: Re-generate.
448
379832de
HPN		 4492004-12-08 Hans-Peter Nilsson <hp@axis.com>
450
451 * configure: Regenerate for ../common/aclocal.m4 update.
452
cd62154c
AC		 4532004-09-24 Monika Chaddha <monika@acmet.com>
454
455 Committed by Andrew Cagney.
456 * m16.igen (CMP, CMPI): Fix assembler.
457
e5da76ec
CD		 4582004-08-18 Chris Demetriou <cgd@broadcom.com>
459
460 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
461 * configure: Regenerate.
462
139181c8
CD		 4632004-06-25 Chris Demetriou <cgd@broadcom.com>
464
465 * configure.in (sim_m16_machine): Include mipsIII.
466 * configure: Regenerate.
467
1a27f959
CD		 4682004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
469
470 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
471 from COP0_BADVADDR.
472 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
473
5dbb7b5a
CD		 4742004-04-10 Chris Demetriou <cgd@broadcom.com>
475
476 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
477
14234056
CD		 4782004-04-09 Chris Demetriou <cgd@broadcom.com>
479
480 * mips.igen (check_fmt): Remove.
481 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
482 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
483 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
484 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
485 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
486 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
487 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
488 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
489 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
490 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
491
c6f9085c
CD		 4922004-04-09 Chris Demetriou <cgd@broadcom.com>
493
494 * sb1.igen (check_sbx): New function.
495 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
496
11d66e66 4972004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 498 Richard Sandiford <rsandifo@redhat.com>
499
500 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
501 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
502 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
503 separate implementations for mipsIV and mipsV. Use new macros to
504 determine whether the restrictions apply.
505
b3208fb8
CD		 5062004-01-19 Chris Demetriou <cgd@broadcom.com>
507
508 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
509 (check_mult_hilo): Improve comments.
510 (check_div_hilo): Likewise. Also, fork off a new version
511 to handle mips32/mips64 (since there are no hazards to check
512 in MIPS32/MIPS64).
513
9a1d84fb
CD		 5142003-06-17 Richard Sandiford <rsandifo@redhat.com>
515
516 * mips.igen (do_dmultx): Fix check for negative operands.
517
ae451ac6
ILT		 5182003-05-16 Ian Lance Taylor <ian@airs.com>
519
520 * Makefile.in (SHELL): Make sure this is defined.
521 (various): Use $(SHELL) whenever we invoke move-if-change.
522
dd69d292
CD		 5232003-05-03 Chris Demetriou <cgd@broadcom.com>
524
525 * cp1.c: Tweak attribution slightly.
526 * cp1.h: Likewise.
527 * mdmx.c: Likewise.
528 * mdmx.igen: Likewise.
529 * mips3d.igen: Likewise.
530 * sb1.igen: Likewise.
531
bcd0068e
CD		 5322003-04-15 Richard Sandiford <rsandifo@redhat.com>
533
534 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
535 unsigned operands.
536
6b4a8935
AC		 5372003-02-27 Andrew Cagney <cagney@redhat.com>
538
601da316
AC		 539 * interp.c (sim_open): Rename _bfd to bfd.
540 (sim_create_inferior): Ditto.
6b4a8935 541
d29e330f
CD		 5422003-01-14 Chris Demetriou <cgd@broadcom.com>
543
544 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
545
a2353a08
CD		 5462003-01-14 Chris Demetriou <cgd@broadcom.com>
547
548 * mips.igen (EI, DI): Remove.
549
80551777
CD		 5502003-01-05 Richard Sandiford <rsandifo@redhat.com>
551
552 * Makefile.in (tmp-run-multi): Fix mips16 filter.
553
4c54fc26
CD		 5542003-01-04 Richard Sandiford <rsandifo@redhat.com>
555 Andrew Cagney <ac131313@redhat.com>
556 Gavin Romig-Koch <gavin@redhat.com>
557 Graydon Hoare <graydon@redhat.com>
558 Aldy Hernandez <aldyh@redhat.com>
559 Dave Brolley <brolley@redhat.com>
560 Chris Demetriou <cgd@broadcom.com>
561
562 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
563 (sim_mach_default): New variable.
564 (mips64vr-*-*, mips64vrel-*-*): New configurations.
565 Add a new simulator generator, MULTI.
566 * configure: Regenerate.
567 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
568 (multi-run.o): New dependency.
569 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
570 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
571 (tmp-multi): Combine them.
572 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
573 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
574 (distclean-extra): New rule.
575 * sim-main.h: Include bfd.h.
576 (MIPS_MACH): New macro.
577 * mips.igen (vr4120, vr5400, vr5500): New models.
578 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
579 * vr.igen: Replace with new version.
580
e6c674b8
CD		 5812003-01-04 Chris Demetriou <cgd@broadcom.com>
582
583 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
584 * configure: Regenerate.
585
28f50ac8
CD		 5862002-12-31 Chris Demetriou <cgd@broadcom.com>
587
588 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
589 * mips.igen: Remove all invocations of check_branch_bug and
590 mark_branch_bug.
591
5071ffe6
CD		 5922002-12-16 Chris Demetriou <cgd@broadcom.com>
593
594 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
595
06e7837e
CD		 5962002-07-30 Chris Demetriou <cgd@broadcom.com>
597
598 * mips.igen (do_load_double, do_store_double): New functions.
599 (LDC1, SDC1): Rename to...
600 (LDC1b, SDC1b): respectively.
601 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
602
2265c243
MS		 6032002-07-29 Michael Snyder <msnyder@redhat.com>
604
605 * cp1.c (fp_recip2): Modify initialization expression so that
606 GCC will recognize it as constant.
607
a2f8b4f3
CD		 6082002-06-18 Chris Demetriou <cgd@broadcom.com>
609
610 * mdmx.c (SD_): Delete.
611 (Unpredictable): Re-define, for now, to directly invoke
612 unpredictable_action().
613 (mdmx_acc_op): Fix error in .ob immediate handling.
614
b4b6c939
AC		 6152002-06-18 Andrew Cagney <cagney@redhat.com>
616
617 * interp.c (sim_firmware_command): Initialize `address'.
618
c8cca39f
AC		 6192002-06-16 Andrew Cagney <ac131313@redhat.com>
620
621 * configure: Regenerated to track ../common/aclocal.m4 changes.
622
e7e81181
CD		 6232002-06-14 Chris Demetriou <cgd@broadcom.com>
624 Ed Satterthwaite <ehs@broadcom.com>
625
626 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
627 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
628 * mips.igen: Include mips3d.igen.
629 (mips3d): New model name for MIPS-3D ASE instructions.
630 (CVT.W.fmt): Don't use this instruction for word (source) format
631 instructions.
632 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
633 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
634 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
635 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
636 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
637 (RSquareRoot1, RSquareRoot2): New macros.
638 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
639 (fp_rsqrt2): New functions.
640 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
641 * configure: Regenerate.
642
3a2b820e 6432002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 644 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 645
646 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
647 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
648 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
649 (convert): Note that this function is not used for paired-single
650 format conversions.
651 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
652 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
653 (check_fmt_p): Enable paired-single support.
654 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
655 (PUU.PS): New instructions.
656 (CVT.S.fmt): Don't use this instruction for paired-single format
657 destinations.
658 * sim-main.h (FP_formats): New value 'fmt_ps.'
659 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
660 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
661
d18ea9c2
CD		 6622002-06-12 Chris Demetriou <cgd@broadcom.com>
663
664 * mips.igen: Fix formatting of function calls in
665 many FP operations.
666
95fd5cee
CD		 6672002-06-12 Chris Demetriou <cgd@broadcom.com>
668
669 * mips.igen (MOVN, MOVZ): Trace result.
670 (TNEI): Print "tnei" as the opcode name in traces.
671 (CEIL.W): Add disassembly string for traces.
672 (RSQRT.fmt): Make location of disassembly string consistent
673 with other instructions.
674
4f0d55ae
CD		 6752002-06-12 Chris Demetriou <cgd@broadcom.com>
676
677 * mips.igen (X): Delete unused function.
678
3c25f8c7
AC		 6792002-06-08 Andrew Cagney <cagney@redhat.com>
680
681 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
682
f3c08b7e
CD		 6832002-06-07 Chris Demetriou <cgd@broadcom.com>
684 Ed Satterthwaite <ehs@broadcom.com>
685
686 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
687 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
688 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
689 (fp_nmsub): New prototypes.
690 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
691 (NegMultiplySub): New defines.
692 * mips.igen (RSQRT.fmt): Use RSquareRoot().
693 (MADD.D, MADD.S): Replace with...
694 (MADD.fmt): New instruction.
695 (MSUB.D, MSUB.S): Replace with...
696 (MSUB.fmt): New instruction.
697 (NMADD.D, NMADD.S): Replace with...
698 (NMADD.fmt): New instruction.
699 (NMSUB.D, MSUB.S): Replace with...
700 (NMSUB.fmt): New instruction.
701
52714ff9
CD		 7022002-06-07 Chris Demetriou <cgd@broadcom.com>
703 Ed Satterthwaite <ehs@broadcom.com>
704
705 * cp1.c: Fix more comment spelling and formatting.
706 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
707 (denorm_mode): New function.
708 (fpu_unary, fpu_binary): Round results after operation, collect
709 status from rounding operations, and update the FCSR.
710 (convert): Collect status from integer conversions and rounding
711 operations, and update the FCSR. Adjust NaN values that result
712 from conversions. Convert to use sim_io_eprintf rather than
713 fprintf, and remove some debugging code.
714 * cp1.h (fenr_FS): New define.
715
577d8c4b
CD		 7162002-06-07 Chris Demetriou <cgd@broadcom.com>
717
718 * cp1.c (convert): Remove unusable debugging code, and move MIPS
719 rounding mode to sim FP rounding mode flag conversion code into...
720 (rounding_mode): New function.
721
196496ed
CD		 7222002-06-07 Chris Demetriou <cgd@broadcom.com>
723
724 * cp1.c: Clean up formatting of a few comments.
725 (value_fpr): Reformat switch statement.
726
cfe9ea23
CD		 7272002-06-06 Chris Demetriou <cgd@broadcom.com>
728 Ed Satterthwaite <ehs@broadcom.com>
729
730 * cp1.h: New file.
731 * sim-main.h: Include cp1.h.
732 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
733 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
734 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
735 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
736 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
737 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
738 * cp1.c: Don't include sim-fpu.h; already included by
739 sim-main.h. Clean up formatting of some comments.
740 (NaN, Equal, Less): Remove.
741 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
742 (fp_cmp): New functions.
743 * mips.igen (do_c_cond_fmt): Remove.
744 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
745 Compare. Add result tracing.
746 (CxC1): Remove, replace with...
747 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
748 (DMxC1): Remove, replace with...
749 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
750 (MxC1): Remove, replace with...
751 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
752
ee7254b0
CD		 7532002-06-04 Chris Demetriou <cgd@broadcom.com>
754
755 * sim-main.h (FGRIDX): Remove, replace all uses with...
756 (FGR_BASE): New macro.
757 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
758 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
759 (NR_FGR, FGR): Likewise.
760 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
761 * mips.igen: Likewise.
762
d3eb724f
CD		 7632002-06-04 Chris Demetriou <cgd@broadcom.com>
764
765 * cp1.c: Add an FSF Copyright notice to this file.
766
ba46ddd0
CD		 7672002-06-04 Chris Demetriou <cgd@broadcom.com>
768 Ed Satterthwaite <ehs@broadcom.com>
769
770 * cp1.c (Infinity): Remove.
771 * sim-main.h (Infinity): Likewise.
772
773 * cp1.c (fp_unary, fp_binary): New functions.
774 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
775 (fp_sqrt): New functions, implemented in terms of the above.
776 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
777 (Recip, SquareRoot): Remove (replaced by functions above).
778 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
779 (fp_recip, fp_sqrt): New prototypes.
780 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
781 (Recip, SquareRoot): Replace prototypes with #defines which
782 invoke the functions above.
783
18d8a52d
CD		 7842002-06-03 Chris Demetriou <cgd@broadcom.com>
785
786 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
787 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
788 file, remove PARAMS from prototypes.
789 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
790 simulator state arguments.
791 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
792 pass simulator state arguments.
793 * cp1.c (SD): Redefine as CPU_STATE(cpu).
794 (store_fpr, convert): Remove 'sd' argument.
795 (value_fpr): Likewise. Convert to use 'SD' instead.
796
0f154cbd
CD		 7972002-06-03 Chris Demetriou <cgd@broadcom.com>
798
799 * cp1.c (Min, Max): Remove #if 0'd functions.
800 * sim-main.h (Min, Max): Remove.
801
e80fc152
CD		 8022002-06-03 Chris Demetriou <cgd@broadcom.com>
803
804 * cp1.c: fix formatting of switch case and default labels.
805 * interp.c: Likewise.
806 * sim-main.c: Likewise.
807
bad673a9
CD		 8082002-06-03 Chris Demetriou <cgd@broadcom.com>
809
810 * cp1.c: Clean up comments which describe FP formats.
811 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
812
7cbea089
CD		 8132002-06-03 Chris Demetriou <cgd@broadcom.com>
814 Ed Satterthwaite <ehs@broadcom.com>
815
816 * configure.in (mipsisa64sb1*-*-*): New target for supporting
817 Broadcom SiByte SB-1 processor configurations.
818 * configure: Regenerate.
819 * sb1.igen: New file.
820 * mips.igen: Include sb1.igen.
821 (sb1): New model.
822 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
823 * mdmx.igen: Add "sb1" model to all appropriate functions and
824 instructions.
825 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
826 (ob_func, ob_acc): Reference the above.
827 (qh_acc): Adjust to keep the same size as ob_acc.
828 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
829 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
830
909daa82
CD		 8312002-06-03 Chris Demetriou <cgd@broadcom.com>
832
833 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
834
f4f1b9f1
CD		 8352002-06-02 Chris Demetriou <cgd@broadcom.com>
836 Ed Satterthwaite <ehs@broadcom.com>
837
838 * mips.igen (mdmx): New (pseudo-)model.
839 * mdmx.c, mdmx.igen: New files.
840 * Makefile.in (SIM_OBJS): Add mdmx.o.
841 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
842 New typedefs.
843 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
844 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
845 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
846 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
847 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
848 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
849 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
850 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
851 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
852 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
853 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
854 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
855 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
856 (qh_fmtsel): New macros.
857 (_sim_cpu): New member "acc".
858 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
859 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
860
5accf1ff
CD		 8612002-05-01 Chris Demetriou <cgd@broadcom.com>
862
863 * interp.c: Use 'deprecated' rather than 'depreciated.'
864 * sim-main.h: Likewise.
865
402586aa
CD		 8662002-05-01 Chris Demetriou <cgd@broadcom.com>
867
868 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
869 which wouldn't compile anyway.
870 * sim-main.h (unpredictable_action): New function prototype.
871 (Unpredictable): Define to call igen function unpredictable().
872 (NotWordValue): New macro to call igen function not_word_value().
873 (UndefinedResult): Remove.
874 * interp.c (undefined_result): Remove.
875 (unpredictable_action): New function.
876 * mips.igen (not_word_value, unpredictable): New functions.
877 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
878 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
879 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
880 NotWordValue() to check for unpredictable inputs, then
881 Unpredictable() to handle them.
882
c9b9995a
CD		 8832002-02-24 Chris Demetriou <cgd@broadcom.com>
884
885 * mips.igen: Fix formatting of calls to Unpredictable().
886
e1015982
AC		 8872002-04-20 Andrew Cagney <ac131313@redhat.com>
888
889 * interp.c (sim_open): Revert previous change.
890
b882a66b
AO		 8912002-04-18 Alexandre Oliva <aoliva@redhat.com>
892
893 * interp.c (sim_open): Disable chunk of code that wrote code in
894 vector table entries.
895
c429b7dd
CD		 8962002-03-19 Chris Demetriou <cgd@broadcom.com>
897
898 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
899 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
900 unused definitions.
901
37d146fa
CD		 9022002-03-19 Chris Demetriou <cgd@broadcom.com>
903
904 * cp1.c: Fix many formatting issues.
905
07892c0b
CD		 9062002-03-19 Chris G. Demetriou <cgd@broadcom.com>
907
908 * cp1.c (fpu_format_name): New function to replace...
909 (DOFMT): This. Delete, and update all callers.
910 (fpu_rounding_mode_name): New function to replace...
911 (RMMODE): This. Delete, and update all callers.
912
487f79b7
CD		 9132002-03-19 Chris G. Demetriou <cgd@broadcom.com>
914
915 * interp.c: Move FPU support routines from here to...
916 * cp1.c: Here. New file.
917 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
918 (cp1.o): New target.
919
1e799e28
CD		 9202002-03-12 Chris Demetriou <cgd@broadcom.com>
921
922 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
923 * mips.igen (mips32, mips64): New models, add to all instructions
924 and functions as appropriate.
925 (loadstore_ea, check_u64): New variant for model mips64.
926 (check_fmt_p): New variant for models mipsV and mips64, remove
927 mipsV model marking fro other variant.
928 (SLL) Rename to...
929 (SLLa) this.
930 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
931 for mips32 and mips64.
932 (DCLO, DCLZ): New instructions for mips64.
933
82f728db
CD		 9342002-03-07 Chris Demetriou <cgd@broadcom.com>
935
936 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
937 immediate or code as a hex value with the "%#lx" format.
938 (ANDI): Likewise, and fix printed instruction name.
939
b96e7ef1
CD		 9402002-03-05 Chris Demetriou <cgd@broadcom.com>
941
942 * sim-main.h (UndefinedResult, Unpredictable): New macros
943 which currently do nothing.
944
d35d4f70
CD		 9452002-03-05 Chris Demetriou <cgd@broadcom.com>
946
947 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
948 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
949 (status_CU3): New definitions.
950
951 * sim-main.h (ExceptionCause): Add new values for MIPS32
952 and MIPS64: MDMX, MCheck, CacheErr. Update comments
953 for DebugBreakPoint and NMIReset to note their status in
954 MIPS32 and MIPS64.
955 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
956 (SignalExceptionCacheErr): New exception macros.
957
3ad6f714
CD		 9582002-03-05 Chris Demetriou <cgd@broadcom.com>
959
960 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
961 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
962 is always enabled.
963 (SignalExceptionCoProcessorUnusable): Take as argument the
964 unusable coprocessor number.
965
86b77b47
CD		 9662002-03-05 Chris Demetriou <cgd@broadcom.com>
967
968 * mips.igen: Fix formatting of all SignalException calls.
969
97a88e93 9702002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 971
972 * sim-main.h (SIGNEXTEND): Remove.
973
97a88e93 9742002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 975
976 * mips.igen: Remove gencode comment from top of file, fix
977 spelling in another comment.
978
97a88e93 9792002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 980
981 * mips.igen (check_fmt, check_fmt_p): New functions to check
982 whether specific floating point formats are usable.
983 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
984 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
985 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
986 Use the new functions.
987 (do_c_cond_fmt): Remove format checks...
988 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
989
97a88e93 9902002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 991
992 * mips.igen: Fix formatting of check_fpu calls.
993
41774c9d
CD		 9942002-03-03 Chris Demetriou <cgd@broadcom.com>
995
996 * mips.igen (FLOOR.L.fmt): Store correct destination register.
997
4a0bd876
CD		 9982002-03-03 Chris Demetriou <cgd@broadcom.com>
999
1000 * mips.igen: Remove whitespace at end of lines.
1001
09297648
CD		 10022002-03-02 Chris Demetriou <cgd@broadcom.com>
1003
1004 * mips.igen (loadstore_ea): New function to do effective
1005 address calculations.
1006 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1007 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1008 CACHE): Use loadstore_ea to do effective address computations.
1009
043b7057
CD		 10102002-03-02 Chris Demetriou <cgd@broadcom.com>
1011
1012 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1013 * mips.igen (LL, CxC1, MxC1): Likewise.
1014
c1e8ada4
CD		 10152002-03-02 Chris Demetriou <cgd@broadcom.com>
1016
1017 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1018 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1019 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1020 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1021 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1022 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1023 Don't split opcode fields by hand, use the opcode field values
1024 provided by igen.
1025
3e1dca16
CD		 10262002-03-01 Chris Demetriou <cgd@broadcom.com>
1027
1028 * mips.igen (do_divu): Fix spacing.
1029
1030 * mips.igen (do_dsllv): Move to be right before DSLLV,
1031 to match the rest of the do_<shift> functions.
1032
fff8d27d
CD		 10332002-03-01 Chris Demetriou <cgd@broadcom.com>
1034
1035 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1036 DSRL32, do_dsrlv): Trace inputs and results.
1037
0d3e762b
CD		 10382002-03-01 Chris Demetriou <cgd@broadcom.com>
1039
1040 * mips.igen (CACHE): Provide instruction-printing string.
1041
1042 * interp.c (signal_exception): Comment tokens after #endif.
1043
eb5fcf93
CD		 10442002-02-28 Chris Demetriou <cgd@broadcom.com>
1045
1046 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1047 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1048 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1049 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1050 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1051 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1052 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1053 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1054
bb22bd7d
CD		 10552002-02-28 Chris Demetriou <cgd@broadcom.com>
1056
1057 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1058 instruction-printing string.
1059 (LWU): Use '64' as the filter flag.
1060
91a177cf
CD		 10612002-02-28 Chris Demetriou <cgd@broadcom.com>
1062
1063 * mips.igen (SDXC1): Fix instruction-printing string.
1064
387f484a
CD		 10652002-02-28 Chris Demetriou <cgd@broadcom.com>
1066
1067 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1068 filter flags "32,f".
1069
3d81f391
CD		 10702002-02-27 Chris Demetriou <cgd@broadcom.com>
1071
1072 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1073 as the filter flag.
1074
af5107af
CD		 10752002-02-27 Chris Demetriou <cgd@broadcom.com>
1076
1077 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1078 add a comma) so that it more closely match the MIPS ISA
1079 documentation opcode partitioning.
1080 (PREF): Put useful names on opcode fields, and include
1081 instruction-printing string.
1082
ca971540
CD		 10832002-02-27 Chris Demetriou <cgd@broadcom.com>
1084
1085 * mips.igen (check_u64): New function which in the future will
1086 check whether 64-bit instructions are usable and signal an
1087 exception if not. Currently a no-op.
1088 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1089 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1090 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1091 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1092
1093 * mips.igen (check_fpu): New function which in the future will
1094 check whether FPU instructions are usable and signal an exception
1095 if not. Currently a no-op.
1096 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1097 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1098 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1099 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1100 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1101 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1102 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1103 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1104
1c47a468
CD		 11052002-02-27 Chris Demetriou <cgd@broadcom.com>
1106
1107 * mips.igen (do_load_left, do_load_right): Move to be immediately
1108 following do_load.
1109 (do_store_left, do_store_right): Move to be immediately following
1110 do_store.
1111
603a98e7
CD		 11122002-02-27 Chris Demetriou <cgd@broadcom.com>
1113
1114 * mips.igen (mipsV): New model name. Also, add it to
1115 all instructions and functions where it is appropriate.
1116
c5d00cc7
CD		 11172002-02-18 Chris Demetriou <cgd@broadcom.com>
1118
1119 * mips.igen: For all functions and instructions, list model
1120 names that support that instruction one per line.
1121
074e9cb8
CD		 11222002-02-11 Chris Demetriou <cgd@broadcom.com>
1123
1124 * mips.igen: Add some additional comments about supported
1125 models, and about which instructions go where.
1126 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1127 order as is used in the rest of the file.
1128
9805e229
CD		 11292002-02-11 Chris Demetriou <cgd@broadcom.com>
1130
1131 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1132 indicating that ALU32_END or ALU64_END are there to check
1133 for overflow.
1134 (DADD): Likewise, but also remove previous comment about
1135 overflow checking.
1136
f701dad2
CD		 11372002-02-10 Chris Demetriou <cgd@broadcom.com>
1138
1139 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1140 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1141 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1142 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1143 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1144 fields (i.e., add and move commas) so that they more closely
1145 match the MIPS ISA documentation opcode partitioning.
1146
11472002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 1148
1149 * mips.igen (ADDI): Print immediate value.
1150 (BREAK): Print code.
1151 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1152 (SLL): Print "nop" specially, and don't run the code
1153 that does the shift for the "nop" case.
1154
9e52972e
FF		 11552001-11-17 Fred Fish <fnf@redhat.com>
1156
1157 * sim-main.h (float_operation): Move enum declaration outside
1158 of _sim_cpu struct declaration.
1159
c0efbca4
JB		 11602001-04-12 Jim Blandy <jimb@redhat.com>
1161
1162 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1163 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1164 set of the FCSR.
1165 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1166 PENDING_FILL, and you can get the intended effect gracefully by
1167 calling PENDING_SCHED directly.
1168
fb891446
BE		 11692001-02-23 Ben Elliston <bje@redhat.com>
1170
1171 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1172 already defined elsewhere.
1173
8030f857
BE		 11742001-02-19 Ben Elliston <bje@redhat.com>
1175
1176 * sim-main.h (sim_monitor): Return an int.
1177 * interp.c (sim_monitor): Add return values.
1178 (signal_exception): Handle error conditions from sim_monitor.
1179
56b48a7a
CD		 11802001-02-08 Ben Elliston <bje@redhat.com>
1181
1182 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1183 (store_memory): Likewise, pass cia to sim_core_write*.
1184
d3ee60d9
FCE		 11852000-10-19 Frank Ch. Eigler <fche@redhat.com>
1186
1187 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1188 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1189
071da002
AC		 1190Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1191
1192 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1193 * Makefile.in: Don't delete *.igen when cleaning directory.
1194
a28c02cd
AC		 1195Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1196
1197 * m16.igen (break): Call SignalException not sim_engine_halt.
1198
80ee11fa
AC		 1199Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1200
1201 From Jason Eckhardt:
1202 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1203
673388c0
AC		 1204Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1205
1206 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1207
4c0deff4
NC		 12082000-05-24 Michael Hayes <mhayes@cygnus.com>
1209
1210 * mips.igen (do_dmultx): Fix typo.
1211
eb2d80b4
AC		 1212Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1213
1214 * configure: Regenerated to track ../common/aclocal.m4 changes.
1215
dd37a34b
AC		 1216Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1217
1218 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1219
4c0deff4
NC		 12202000-04-12 Frank Ch. Eigler <fche@redhat.com>
1221
1222 * sim-main.h (GPR_CLEAR): Define macro.
1223
e30db738
AC		 1224Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1225
1226 * interp.c (decode_coproc): Output long using %lx and not %s.
1227
cb7450ea
FCE		 12282000-03-21 Frank Ch. Eigler <fche@redhat.com>
1229
1230 * interp.c (sim_open): Sort & extend dummy memory regions for
1231 --board=jmr3904 for eCos.
1232
a3027dd7
FCE		 12332000-03-02 Frank Ch. Eigler <fche@redhat.com>
1234
1235 * configure: Regenerated.
1236
1237Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1238
1239 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1240 calls, conditional on the simulator being in verbose mode.
1241
dfcd3bfb
JM		 1242Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1243
1244 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1245 cache don't get ReservedInstruction traps.
1246
c2d11a7d
JM		 12471999-11-29 Mark Salter <msalter@cygnus.com>
1248
1249 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1250 to clear status bits in sdisr register. This is how the hardware works.
1251
1252 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1253 being used by cygmon.
1254
4ce44c66
JM		 12551999-11-11 Andrew Haley <aph@cygnus.com>
1256
1257 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1258 instructions.
1259
cff3e48b
JM		 1260Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1261
1262 * mips.igen (MULT): Correct previous mis-applied patch.
1263
d4f3574e
SS		 1264Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1265
1266 * mips.igen (delayslot32): Handle sequence like
1267 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1268 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1269 (MULT): Actually pass the third register...
1270
12711999-09-03 Mark Salter <msalter@cygnus.com>
1272
1273 * interp.c (sim_open): Added more memory aliases for additional
1274 hardware being touched by cygmon on jmr3904 board.
1275
1276Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1277
1278 * configure: Regenerated to track ../common/aclocal.m4 changes.
1279
a0b3c4fd
JM		 1280Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1281
1282 * interp.c (sim_store_register): Handle case where client - GDB -
1283 specifies that a 4 byte register is 8 bytes in size.
1284 (sim_fetch_register): Ditto.
1285
adf40b2e
JM		 12861999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1287
1288 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1289 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1290 (idt_monitor_base): Base address for IDT monitor traps.
1291 (pmon_monitor_base): Ditto for PMON.
1292 (lsipmon_monitor_base): Ditto for LSI PMON.
1293 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1294 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1295 (sim_firmware_command): New function.
1296 (mips_option_handler): Call it for OPTION_FIRMWARE.
1297 (sim_open): Allocate memory for idt_monitor region. If "--board"
1298 option was given, add no monitor by default. Add BREAK hooks only if
1299 monitors are also there.
1300
43e526b9
JM		 1301Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1302
1303 * interp.c (sim_monitor): Flush output before reading input.
1304
1305Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1306
1307 * tconfig.in (SIM_HANDLES_LMA): Always define.
1308
1309Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1310
1311 From Mark Salter <msalter@cygnus.com>:
1312 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1313 (sim_open): Add setup for BSP board.
1314
9846de1b
JM		 1315Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1316
1317 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1318 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1319 them as unimplemented.
1320
cd0fc7c3
SS		 13211999-05-08 Felix Lee <flee@cygnus.com>
1322
1323 * configure: Regenerated to track ../common/aclocal.m4 changes.
1324
7a292a7a
SS		 13251999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1326
1327 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1328
1329Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1330
1331 * configure.in: Any mips64vr5*-*-* target should have
1332 -DTARGET_ENABLE_FR=1.
1333 (default_endian): Any mips64vr*el-*-* target should default to
1334 LITTLE_ENDIAN.
1335 * configure: Re-generate.
1336
13371999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1338
1339 * mips.igen (ldl): Extend from _16_, not 32.
1340
1341Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1342
1343 * interp.c (sim_store_register): Force registers written to by GDB
1344 into an un-interpreted state.
1345
c906108c
SS		 13461999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1347
1348 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1349 CPU, start periodic background I/O polls.
1350 (tx3904sio_poll): New function: periodic I/O poller.
1351
13521998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1353
1354 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1355
1356Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1357
1358 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1359 case statement.
1360
13611998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1362
1363 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1364 (load_word): Call SIM_CORE_SIGNAL hook on error.
1365 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1366 starting. For exception dispatching, pass PC instead of NULL_CIA.
1367 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1368 * sim-main.h (COP0_BADVADDR): Define.
1369 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1370 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1371 (_sim_cpu): Add exc_* fields to store register value snapshots.
1372 * mips.igen (*): Replace memory-related SignalException* calls
1373 with references to SIM_CORE_SIGNAL hook.
1374
1375 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1376 fix.
1377 * sim-main.c (*): Minor warning cleanups.
1378
13791998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1380
1381 * m16.igen (DADDIU5): Correct type-o.
1382
1383Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1384
1385 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1386 variables.
1387
1388Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1389
1390 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1391 to include path.
1392 (interp.o): Add dependency on itable.h
1393 (oengine.c, gencode): Delete remaining references.
1394 (BUILT_SRC_FROM_GEN): Clean up.
1395
13961998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1397
1398 * vr4run.c: New.
1399 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1400 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1401 tmp-run-hack) : New.
1402 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1403 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1404 Drop the "64" qualifier to get the HACK generator working.
1405 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1406 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1407 qualifier to get the hack generator working.
1408 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1409 (DSLL): Use do_dsll.
1410 (DSLLV): Use do_dsllv.
1411 (DSRA): Use do_dsra.
1412 (DSRL): Use do_dsrl.
1413 (DSRLV): Use do_dsrlv.
1414 (BC1): Move *vr4100 to get the HACK generator working.
1415 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1416 get the HACK generator working.
1417 (MACC) Rename to get the HACK generator working.
1418 (DMACC,MACCS,DMACCS): Add the 64.
1419
14201998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1421
1422 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1423 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1424
14251998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1426
1427 * mips/interp.c (DEBUG): Cleanups.
1428
14291998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1430
1431 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1432 (tx3904sio_tickle): fflush after a stdout character output.
1433
14341998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1435
1436 * interp.c (sim_close): Uninstall modules.
1437
1438Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1439
1440 * sim-main.h, interp.c (sim_monitor): Change to global
1441 function.
1442
1443Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1444
1445 * configure.in (vr4100): Only include vr4100 instructions in
1446 simulator.
1447 * configure: Re-generate.
1448 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1449
1450Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1451
1452 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1453 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1454 true alternative.
1455
1456 * configure.in (sim_default_gen, sim_use_gen): Replace with
1457 sim_gen.
1458 (--enable-sim-igen): Delete config option. Always using IGEN.
1459 * configure: Re-generate.
1460
1461 * Makefile.in (gencode): Kill, kill, kill.
1462 * gencode.c: Ditto.
1463
1464Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1465
1466 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1467 bit mips16 igen simulator.
1468 * configure: Re-generate.
1469
1470 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1471 as part of vr4100 ISA.
1472 * vr.igen: Mark all instructions as 64 bit only.
1473
1474Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1475
1476 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1477 Pacify GCC.
1478
1479Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1480
1481 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1482 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1483 * configure: Re-generate.
1484
1485 * m16.igen (BREAK): Define breakpoint instruction.
1486 (JALX32): Mark instruction as mips16 and not r3900.
1487 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1488
1489 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1490
1491Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1492
1493 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1494 insn as a debug breakpoint.
1495
1496 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1497 pending.slot_size.
1498 (PENDING_SCHED): Clean up trace statement.
1499 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1500 (PENDING_FILL): Delay write by only one cycle.
1501 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1502
1503 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1504 of pending writes.
1505 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1506 32 & 64.
1507 (pending_tick): Move incrementing of index to FOR statement.
1508 (pending_tick): Only update PENDING_OUT after a write has occured.
1509
1510 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1511 build simulator.
1512 * configure: Re-generate.
1513
1514 * interp.c (sim_engine_run OLD): Delete explicit call to
1515 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1516
1517Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1518
1519 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1520 interrupt level number to match changed SignalExceptionInterrupt
1521 macro.
1522
1523Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1524
1525 * interp.c: #include "itable.h" if WITH_IGEN.
1526 (get_insn_name): New function.
1527 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1528 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1529
1530Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1531
1532 * configure: Rebuilt to inhale new common/aclocal.m4.
1533
1534Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1535
1536 * dv-tx3904sio.c: Include sim-assert.h.
1537
1538Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1539
1540 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1541 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1542 Reorganize target-specific sim-hardware checks.
1543 * configure: rebuilt.
1544 * interp.c (sim_open): For tx39 target boards, set
1545 OPERATING_ENVIRONMENT, add tx3904sio devices.
1546 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1547 ROM executables. Install dv-sockser into sim-modules list.
1548
1549 * dv-tx3904irc.c: Compiler warning clean-up.
1550 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1551 frequent hw-trace messages.
1552
1553Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1554
1555 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1556
1557Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1558
1559 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1560
1561 * vr.igen: New file.
1562 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1563 * mips.igen: Define vr4100 model. Include vr.igen.
1564Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1565
1566 * mips.igen (check_mf_hilo): Correct check.
1567
1568Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1569
1570 * sim-main.h (interrupt_event): Add prototype.
1571
1572 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1573 register_ptr, register_value.
1574 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1575
1576 * sim-main.h (tracefh): Make extern.
1577
1578Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1579
1580 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1581 Reduce unnecessarily high timer event frequency.
1582 * dv-tx3904cpu.c: Ditto for interrupt event.
1583
1584Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1585
1586 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1587 to allay warnings.
1588 (interrupt_event): Made non-static.
1589
1590 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1591 interchange of configuration values for external vs. internal
1592 clock dividers.
1593
1594Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1595
1596 * mips.igen (BREAK): Moved code to here for
1597 simulator-reserved break instructions.
1598 * gencode.c (build_instruction): Ditto.
1599 * interp.c (signal_exception): Code moved from here. Non-
1600 reserved instructions now use exception vector, rather
1601 than halting sim.
1602 * sim-main.h: Moved magic constants to here.
1603
1604Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1605
1606 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1607 register upon non-zero interrupt event level, clear upon zero
1608 event value.
1609 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1610 by passing zero event value.
1611 (*_io_{read,write}_buffer): Endianness fixes.
1612 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1613 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1614
1615 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1616 serial I/O and timer module at base address 0xFFFF0000.
1617
1618Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1619
1620 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1621 and BigEndianCPU.
1622
1623Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1624
1625 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1626 parts.
1627 * configure: Update.
1628
1629Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1630
1631 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1632 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1633 * configure.in: Include tx3904tmr in hw_device list.
1634 * configure: Rebuilt.
1635 * interp.c (sim_open): Instantiate three timer instances.
1636 Fix address typo of tx3904irc instance.
1637
1638Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1639
1640 * interp.c (signal_exception): SystemCall exception now uses
1641 the exception vector.
1642
1643Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1644
1645 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1646 to allay warnings.
1647
1648Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1649
1650 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1651
1652Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1653
1654 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1655
1656 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1657 sim-main.h. Declare a struct hw_descriptor instead of struct
1658 hw_device_descriptor.
1659
1660Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1661
1662 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1663 right bits and then re-align left hand bytes to correct byte
1664 lanes. Fix incorrect computation in do_store_left when loading
1665 bytes from second word.
1666
1667Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1668
1669 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1670 * interp.c (sim_open): Only create a device tree when HW is
1671 enabled.
1672
1673 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1674 * interp.c (signal_exception): Ditto.
1675
1676Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1677
1678 * gencode.c: Mark BEGEZALL as LIKELY.
1679
1680Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1681
1682 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1683 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1684
1685Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1686
1687 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1688 modules. Recognize TX39 target with "mips*tx39" pattern.
1689 * configure: Rebuilt.
1690 * sim-main.h (*): Added many macros defining bits in
1691 TX39 control registers.
1692 (SignalInterrupt): Send actual PC instead of NULL.
1693 (SignalNMIReset): New exception type.
1694 * interp.c (board): New variable for future use to identify
1695 a particular board being simulated.
1696 (mips_option_handler,mips_options): Added "--board" option.
1697 (interrupt_event): Send actual PC.
1698 (sim_open): Make memory layout conditional on board setting.
1699 (signal_exception): Initial implementation of hardware interrupt
1700 handling. Accept another break instruction variant for simulator
1701 exit.
1702 (decode_coproc): Implement RFE instruction for TX39.
1703 (mips.igen): Decode RFE instruction as such.
1704 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1705 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1706 bbegin to implement memory map.
1707 * dv-tx3904cpu.c: New file.
1708 * dv-tx3904irc.c: New file.
1709
1710Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1711
1712 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1713
1714Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1715
1716 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1717 with calls to check_div_hilo.
1718
1719Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1720
1721 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1722 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1723 Add special r3900 version of do_mult_hilo.
1724 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1725 with calls to check_mult_hilo.
1726 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1727 with calls to check_div_hilo.
1728
1729Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1730
1731 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1732 Document a replacement.
1733
1734Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1735
1736 * interp.c (sim_monitor): Make mon_printf work.
1737
1738Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1739
1740 * sim-main.h (INSN_NAME): New arg `cpu'.
1741
1742Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1743
1744 * configure: Regenerated to track ../common/aclocal.m4 changes.
1745
1746Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1747
1748 * configure: Regenerated to track ../common/aclocal.m4 changes.
1749 * config.in: Ditto.
1750
1751Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1752
1753 * acconfig.h: New file.
1754 * configure.in: Reverted change of Apr 24; use sinclude again.
1755
1756Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1757
1758 * configure: Regenerated to track ../common/aclocal.m4 changes.
1759 * config.in: Ditto.
1760
1761Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1762
1763 * configure.in: Don't call sinclude.
1764
1765Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1766
1767 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1768
1769Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1770
1771 * mips.igen (ERET): Implement.
1772
1773 * interp.c (decode_coproc): Return sign-extended EPC.
1774
1775 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1776
1777 * interp.c (signal_exception): Do not ignore Trap.
1778 (signal_exception): On TRAP, restart at exception address.
1779 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1780 (signal_exception): Update.
1781 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1782 so that TRAP instructions are caught.
1783
1784Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1785
1786 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1787 contains HI/LO access history.
1788 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1789 (HIACCESS, LOACCESS): Delete, replace with
1790 (HIHISTORY, LOHISTORY): New macros.
1791 (CHECKHILO): Delete all, moved to mips.igen
1792
1793 * gencode.c (build_instruction): Do not generate checks for
1794 correct HI/LO register usage.
1795
1796 * interp.c (old_engine_run): Delete checks for correct HI/LO
1797 register usage.
1798
1799 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1800 check_mf_cycles): New functions.
1801 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1802 do_divu, domultx, do_mult, do_multu): Use.
1803
1804 * tx.igen ("madd", "maddu"): Use.
1805
1806Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1807
1808 * mips.igen (DSRAV): Use function do_dsrav.
1809 (SRAV): Use new function do_srav.
1810
1811 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1812 (B): Sign extend 11 bit immediate.
1813 (EXT-B*): Shift 16 bit immediate left by 1.
1814 (ADDIU*): Don't sign extend immediate value.
1815
1816Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1817
1818 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1819
1820 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1821 functions.
1822
1823 * mips.igen (delayslot32, nullify_next_insn): New functions.
1824 (m16.igen): Always include.
1825 (do_*): Add more tracing.
1826
1827 * m16.igen (delayslot16): Add NIA argument, could be called by a
1828 32 bit MIPS16 instruction.
1829
1830 * interp.c (ifetch16): Move function from here.
1831 * sim-main.c (ifetch16): To here.
1832
1833 * sim-main.c (ifetch16, ifetch32): Update to match current
1834 implementations of LH, LW.
1835 (signal_exception): Don't print out incorrect hex value of illegal
1836 instruction.
1837
1838Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1839
1840 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1841 instruction.
1842
1843 * m16.igen: Implement MIPS16 instructions.
1844
1845 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1846 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1847 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1848 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1849 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1850 bodies of corresponding code from 32 bit insn to these. Also used
1851 by MIPS16 versions of functions.
1852
1853 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1854 (IMEM16): Drop NR argument from macro.
1855
1856Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1857
1858 * Makefile.in (SIM_OBJS): Add sim-main.o.
1859
1860 * sim-main.h (address_translation, load_memory, store_memory,
1861 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1862 as INLINE_SIM_MAIN.
1863 (pr_addr, pr_uword64): Declare.
1864 (sim-main.c): Include when H_REVEALS_MODULE_P.
1865
1866 * interp.c (address_translation, load_memory, store_memory,
1867 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1868 from here.
1869 * sim-main.c: To here. Fix compilation problems.
1870
1871 * configure.in: Enable inlining.
1872 * configure: Re-config.
1873
1874Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1875
1876 * configure: Regenerated to track ../common/aclocal.m4 changes.
1877
1878Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1879
1880 * mips.igen: Include tx.igen.
1881 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1882 * tx.igen: New file, contains MADD and MADDU.
1883
1884 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1885 the hardwired constant `7'.
1886 (store_memory): Ditto.
1887 (LOADDRMASK): Move definition to sim-main.h.
1888
1889 mips.igen (MTC0): Enable for r3900.
1890 (ADDU): Add trace.
1891
1892 mips.igen (do_load_byte): Delete.
1893 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1894 do_store_right): New functions.
1895 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1896
1897 configure.in: Let the tx39 use igen again.
1898 configure: Update.
1899
1900Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1901
1902 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1903 not an address sized quantity. Return zero for cache sizes.
1904
1905Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1906
1907 * mips.igen (r3900): r3900 does not support 64 bit integer
1908 operations.
1909
1910Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1911
1912 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1913 than igen one.
1914 * configure : Rebuild.
1915
1916Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1917
1918 * configure: Regenerated to track ../common/aclocal.m4 changes.
1919
1920Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1921
1922 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1923
1924Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1925
1926 * configure: Regenerated to track ../common/aclocal.m4 changes.
1927 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1928
1929Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1930
1931 * configure: Regenerated to track ../common/aclocal.m4 changes.
1932
1933Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1934
1935 * interp.c (Max, Min): Comment out functions. Not yet used.
1936
1937Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1938
1939 * configure: Regenerated to track ../common/aclocal.m4 changes.
1940
1941Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1942
1943 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1944 configurable settings for stand-alone simulator.
1945
1946 * configure.in: Added X11 search, just in case.
1947
1948 * configure: Regenerated.
1949
1950Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1951
1952 * interp.c (sim_write, sim_read, load_memory, store_memory):
1953 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1954
1955Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1956
1957 * sim-main.h (GETFCC): Return an unsigned value.
1958
1959Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1960
1961 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1962 (DADD): Result destination is RD not RT.
1963
1964Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1965
1966 * sim-main.h (HIACCESS, LOACCESS): Always define.
1967
1968 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1969
1970 * interp.c (sim_info): Delete.
1971
1972Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1973
1974 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1975 (mips_option_handler): New argument `cpu'.
1976 (sim_open): Update call to sim_add_option_table.
1977
1978Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1979
1980 * mips.igen (CxC1): Add tracing.
1981
1982Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1983
1984 * sim-main.h (Max, Min): Declare.
1985
1986 * interp.c (Max, Min): New functions.
1987
1988 * mips.igen (BC1): Add tracing.
1989
1990Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1991
1992 * interp.c Added memory map for stack in vr4100
1993
1994Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1995
1996 * interp.c (load_memory): Add missing "break"'s.
1997
1998Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1999
2000 * interp.c (sim_store_register, sim_fetch_register): Pass in
2001 length parameter. Return -1.
2002
2003Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2004
2005 * interp.c: Added hardware init hook, fixed warnings.
2006
2007Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2008
2009 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2010
2011Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2012
2013 * interp.c (ifetch16): New function.
2014
2015 * sim-main.h (IMEM32): Rename IMEM.
2016 (IMEM16_IMMED): Define.
2017 (IMEM16): Define.
2018 (DELAY_SLOT): Update.
2019
2020 * m16run.c (sim_engine_run): New file.
2021
2022 * m16.igen: All instructions except LB.
2023 (LB): Call do_load_byte.
2024 * mips.igen (do_load_byte): New function.
2025 (LB): Call do_load_byte.
2026
2027 * mips.igen: Move spec for insn bit size and high bit from here.
2028 * Makefile.in (tmp-igen, tmp-m16): To here.
2029
2030 * m16.dc: New file, decode mips16 instructions.
2031
2032 * Makefile.in (SIM_NO_ALL): Define.
2033 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2034
2035Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2036
2037 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2038 point unit to 32 bit registers.
2039 * configure: Re-generate.
2040
2041Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2042
2043 * configure.in (sim_use_gen): Make IGEN the default simulator
2044 generator for generic 32 and 64 bit mips targets.
2045 * configure: Re-generate.
2046
2047Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2048
2049 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2050 bitsize.
2051
2052 * interp.c (sim_fetch_register, sim_store_register): Read/write
2053 FGR from correct location.
2054 (sim_open): Set size of FGR's according to
2055 WITH_TARGET_FLOATING_POINT_BITSIZE.
2056
2057 * sim-main.h (FGR): Store floating point registers in a separate
2058 array.
2059
2060Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2061
2062 * configure: Regenerated to track ../common/aclocal.m4 changes.
2063
2064Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2065
2066 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2067
2068 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2069
2070 * interp.c (pending_tick): New function. Deliver pending writes.
2071
2072 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2073 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2074 it can handle mixed sized quantites and single bits.
2075
2076Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2077
2078 * interp.c (oengine.h): Do not include when building with IGEN.
2079 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2080 (sim_info): Ditto for PROCESSOR_64BIT.
2081 (sim_monitor): Replace ut_reg with unsigned_word.
2082 (*): Ditto for t_reg.
2083 (LOADDRMASK): Define.
2084 (sim_open): Remove defunct check that host FP is IEEE compliant,
2085 using software to emulate floating point.
2086 (value_fpr, ...): Always compile, was conditional on HASFPU.
2087
2088Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2089
2090 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2091 size.
2092
2093 * interp.c (SD, CPU): Define.
2094 (mips_option_handler): Set flags in each CPU.
2095 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2096 (sim_close): Do not clear STATE, deleted anyway.
2097 (sim_write, sim_read): Assume CPU zero's vm should be used for
2098 data transfers.
2099 (sim_create_inferior): Set the PC for all processors.
2100 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2101 argument.
2102 (mips16_entry): Pass correct nr of args to store_word, load_word.
2103 (ColdReset): Cold reset all cpu's.
2104 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2105 (sim_monitor, load_memory, store_memory, signal_exception): Use
2106 `CPU' instead of STATE_CPU.
2107
2108
2109 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2110 SD or CPU_.
2111
2112 * sim-main.h (signal_exception): Add sim_cpu arg.
2113 (SignalException*): Pass both SD and CPU to signal_exception.
2114 * interp.c (signal_exception): Update.
2115
2116 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2117 Ditto
2118 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2119 address_translation): Ditto
2120 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2121
2122Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2123
2124 * configure: Regenerated to track ../common/aclocal.m4 changes.
2125
2126Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2127
2128 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2129
2130 * mips.igen (model): Map processor names onto BFD name.
2131
2132 * sim-main.h (CPU_CIA): Delete.
2133 (SET_CIA, GET_CIA): Define
2134
2135Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2136
2137 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2138 regiser.
2139
2140 * configure.in (default_endian): Configure a big-endian simulator
2141 by default.
2142 * configure: Re-generate.
2143
2144Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2145
2146 * configure: Regenerated to track ../common/aclocal.m4 changes.
2147
2148Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2149
2150 * interp.c (sim_monitor): Handle Densan monitor outbyte
2151 and inbyte functions.
2152
21531997-12-29 Felix Lee <flee@cygnus.com>
2154
2155 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2156
2157Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2158
2159 * Makefile.in (tmp-igen): Arrange for $zero to always be
2160 reset to zero after every instruction.
2161
2162Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2163
2164 * configure: Regenerated to track ../common/aclocal.m4 changes.
2165 * config.in: Ditto.
2166
2167Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2168
2169 * mips.igen (MSUB): Fix to work like MADD.
2170 * gencode.c (MSUB): Similarly.
2171
2172Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2173
2174 * configure: Regenerated to track ../common/aclocal.m4 changes.
2175
2176Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2177
2178 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2179
2180Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2181
2182 * sim-main.h (sim-fpu.h): Include.
2183
2184 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2185 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2186 using host independant sim_fpu module.
2187
2188Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2189
2190 * interp.c (signal_exception): Report internal errors with SIGABRT
2191 not SIGQUIT.
2192
2193 * sim-main.h (C0_CONFIG): New register.
2194 (signal.h): No longer include.
2195
2196 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2197
2198Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2199
2200 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2201
2202Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2203
2204 * mips.igen: Tag vr5000 instructions.
2205 (ANDI): Was missing mipsIV model, fix assembler syntax.
2206 (do_c_cond_fmt): New function.
2207 (C.cond.fmt): Handle mips I-III which do not support CC field
2208 separatly.
2209 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2210 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2211 in IV3.2 spec.
2212 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2213 vr5000 which saves LO in a GPR separatly.
2214
2215 * configure.in (enable-sim-igen): For vr5000, select vr5000
2216 specific instructions.
2217 * configure: Re-generate.
2218
2219Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2220
2221 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2222
2223 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2224 fmt_uninterpreted_64 bit cases to switch. Convert to
2225 fmt_formatted,
2226
2227 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2228
2229 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2230 as specified in IV3.2 spec.
2231 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2232
2233Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2234
2235 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2236 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2237 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2238 PENDING_FILL versions of instructions. Simplify.
2239 (X): New function.
2240 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2241 instructions.
2242 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2243 a signed value.
2244 (MTHI, MFHI): Disable code checking HI-LO.
2245
2246 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2247 global.
2248 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2249
2250Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2251
2252 * gencode.c (build_mips16_operands): Replace IPC with cia.
2253
2254 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2255 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2256 IPC to `cia'.
2257 (UndefinedResult): Replace function with macro/function
2258 combination.
2259 (sim_engine_run): Don't save PC in IPC.
2260
2261 * sim-main.h (IPC): Delete.
2262
2263
2264 * interp.c (signal_exception, store_word, load_word,
2265 address_translation, load_memory, store_memory, cache_op,
2266 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2267 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2268 current instruction address - cia - argument.
2269 (sim_read, sim_write): Call address_translation directly.
2270 (sim_engine_run): Rename variable vaddr to cia.
2271 (signal_exception): Pass cia to sim_monitor
2272
2273 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2274 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2275 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2276
2277 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2278 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2279 SIM_ASSERT.
2280
2281 * interp.c (signal_exception): Pass restart address to
2282 sim_engine_restart.
2283
2284 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2285 idecode.o): Add dependency.
2286
2287 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2288 Delete definitions
2289 (DELAY_SLOT): Update NIA not PC with branch address.
2290 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2291
2292 * mips.igen: Use CIA not PC in branch calculations.
2293 (illegal): Call SignalException.
2294 (BEQ, ADDIU): Fix assembler.
2295
2296Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2297
2298 * m16.igen (JALX): Was missing.
2299
2300 * configure.in (enable-sim-igen): New configuration option.
2301 * configure: Re-generate.
2302
2303 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2304
2305 * interp.c (load_memory, store_memory): Delete parameter RAW.
2306 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2307 bypassing {load,store}_memory.
2308
2309 * sim-main.h (ByteSwapMem): Delete definition.
2310
2311 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2312
2313 * interp.c (sim_do_command, sim_commands): Delete mips specific
2314 commands. Handled by module sim-options.
2315
2316 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2317 (WITH_MODULO_MEMORY): Define.
2318
2319 * interp.c (sim_info): Delete code printing memory size.
2320
2321 * interp.c (mips_size): Nee sim_size, delete function.
2322 (power2): Delete.
2323 (monitor, monitor_base, monitor_size): Delete global variables.
2324 (sim_open, sim_close): Delete code creating monitor and other
2325 memory regions. Use sim-memopts module, via sim_do_commandf, to
2326 manage memory regions.
2327 (load_memory, store_memory): Use sim-core for memory model.
2328
2329 * interp.c (address_translation): Delete all memory map code
2330 except line forcing 32 bit addresses.
2331
2332Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2333
2334 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2335 trace options.
2336
2337 * interp.c (logfh, logfile): Delete globals.
2338 (sim_open, sim_close): Delete code opening & closing log file.
2339 (mips_option_handler): Delete -l and -n options.
2340 (OPTION mips_options): Ditto.
2341
2342 * interp.c (OPTION mips_options): Rename option trace to dinero.
2343 (mips_option_handler): Update.
2344
2345Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2346
2347 * interp.c (fetch_str): New function.
2348 (sim_monitor): Rewrite using sim_read & sim_write.
2349 (sim_open): Check magic number.
2350 (sim_open): Write monitor vectors into memory using sim_write.
2351 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2352 (sim_read, sim_write): Simplify - transfer data one byte at a
2353 time.
2354 (load_memory, store_memory): Clarify meaning of parameter RAW.
2355
2356 * sim-main.h (isHOST): Defete definition.
2357 (isTARGET): Mark as depreciated.
2358 (address_translation): Delete parameter HOST.
2359
2360 * interp.c (address_translation): Delete parameter HOST.
2361
2362Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2363
2364 * mips.igen:
2365
2366 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2367 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2368
2369Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2370
2371 * mips.igen: Add model filter field to records.
2372
2373Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2374
2375 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2376
2377 interp.c (sim_engine_run): Do not compile function sim_engine_run
2378 when WITH_IGEN == 1.
2379
2380 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2381 target architecture.
2382
2383 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2384 igen. Replace with configuration variables sim_igen_flags /
2385 sim_m16_flags.
2386
2387 * m16.igen: New file. Copy mips16 insns here.
2388 * mips.igen: From here.
2389
2390Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2391
2392 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2393 to top.
2394 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2395
2396Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2397
2398 * gencode.c (build_instruction): Follow sim_write's lead in using
2399 BigEndianMem instead of !ByteSwapMem.
2400
2401Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2402
2403 * configure.in (sim_gen): Dependent on target, select type of
2404 generator. Always select old style generator.
2405
2406 configure: Re-generate.
2407
2408 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2409 targets.
2410 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2411 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2412 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2413 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2414 SIM_@sim_gen@_*, set by autoconf.
2415
2416Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2417
2418 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2419
2420 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2421 CURRENT_FLOATING_POINT instead.
2422
2423 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2424 (address_translation): Raise exception InstructionFetch when
2425 translation fails and isINSTRUCTION.
2426
2427 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2428 sim_engine_run): Change type of of vaddr and paddr to
2429 address_word.
2430 (address_translation, prefetch, load_memory, store_memory,
2431 cache_op): Change type of vAddr and pAddr to address_word.
2432
2433 * gencode.c (build_instruction): Change type of vaddr and paddr to
2434 address_word.
2435
2436Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2437
2438 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2439 macro to obtain result of ALU op.
2440
2441Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2442
2443 * interp.c (sim_info): Call profile_print.
2444
2445Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2446
2447 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2448
2449 * sim-main.h (WITH_PROFILE): Do not define, defined in
2450 common/sim-config.h. Use sim-profile module.
2451 (simPROFILE): Delete defintion.
2452
2453 * interp.c (PROFILE): Delete definition.
2454 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2455 (sim_close): Delete code writing profile histogram.
2456 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2457 Delete.
2458 (sim_engine_run): Delete code profiling the PC.
2459
2460Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2461
2462 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2463
2464 * interp.c (sim_monitor): Make register pointers of type
2465 unsigned_word*.
2466
2467 * sim-main.h: Make registers of type unsigned_word not
2468 signed_word.
2469
2470Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2471
2472 * interp.c (sync_operation): Rename from SyncOperation, make
2473 global, add SD argument.
2474 (prefetch): Rename from Prefetch, make global, add SD argument.
2475 (decode_coproc): Make global.
2476
2477 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2478
2479 * gencode.c (build_instruction): Generate DecodeCoproc not
2480 decode_coproc calls.
2481
2482 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2483 (SizeFGR): Move to sim-main.h
2484 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2485 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2486 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2487 sim-main.h.
2488 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2489 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2490 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2491 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2492 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2493 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2494
2495 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2496 exception.
2497 (sim-alu.h): Include.
2498 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2499 (sim_cia): Typedef to instruction_address.
2500
2501Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2502
2503 * Makefile.in (interp.o): Rename generated file engine.c to
2504 oengine.c.
2505
2506 * interp.c: Update.
2507
2508Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2509
2510 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2511
2512Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2513
2514 * gencode.c (build_instruction): For "FPSQRT", output correct
2515 number of arguments to Recip.
2516
2517Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2518
2519 * Makefile.in (interp.o): Depends on sim-main.h
2520
2521 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2522
2523 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2524 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2525 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2526 STATE, DSSTATE): Define
2527 (GPR, FGRIDX, ..): Define.
2528
2529 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2530 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2531 (GPR, FGRIDX, ...): Delete macros.
2532
2533 * interp.c: Update names to match defines from sim-main.h
2534
2535Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2536
2537 * interp.c (sim_monitor): Add SD argument.
2538 (sim_warning): Delete. Replace calls with calls to
2539 sim_io_eprintf.
2540 (sim_error): Delete. Replace calls with sim_io_error.
2541 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2542 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2543 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2544 argument.
2545 (mips_size): Rename from sim_size. Add SD argument.
2546
2547 * interp.c (simulator): Delete global variable.
2548 (callback): Delete global variable.
2549 (mips_option_handler, sim_open, sim_write, sim_read,
2550 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2551 sim_size,sim_monitor): Use sim_io_* not callback->*.
2552 (sim_open): ZALLOC simulator struct.
2553 (PROFILE): Do not define.
2554
2555Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2556
2557 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2558 support.h with corresponding code.
2559
2560 * sim-main.h (word64, uword64), support.h: Move definition to
2561 sim-main.h.
2562 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2563
2564 * support.h: Delete
2565 * Makefile.in: Update dependencies
2566 * interp.c: Do not include.
2567
2568Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2569
2570 * interp.c (address_translation, load_memory, store_memory,
2571 cache_op): Rename to from AddressTranslation et.al., make global,
2572 add SD argument
2573
2574 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2575 CacheOp): Define.
2576
2577 * interp.c (SignalException): Rename to signal_exception, make
2578 global.
2579
2580 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2581
2582 * sim-main.h (SignalException, SignalExceptionInterrupt,
2583 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2584 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2585 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2586 Define.
2587
2588 * interp.c, support.h: Use.
2589
2590Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2591
2592 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2593 to value_fpr / store_fpr. Add SD argument.
2594 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2595 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2596
2597 * sim-main.h (ValueFPR, StoreFPR): Define.
2598
2599Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2600
2601 * interp.c (sim_engine_run): Check consistency between configure
2602 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2603 and HASFPU.
2604
2605 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2606 (mips_fpu): Configure WITH_FLOATING_POINT.
2607 (mips_endian): Configure WITH_TARGET_ENDIAN.
2608 * configure: Update.
2609
2610Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2611
2612 * configure: Regenerated to track ../common/aclocal.m4 changes.
2613
2614Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2615
2616 * configure: Regenerated.
2617
2618Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2619
2620 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2621
2622Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2623
2624 * gencode.c (print_igen_insn_models): Assume certain architectures
2625 include all mips* instructions.
2626 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2627 instruction.
2628
2629 * Makefile.in (tmp.igen): Add target. Generate igen input from
2630 gencode file.
2631
2632 * gencode.c (FEATURE_IGEN): Define.
2633 (main): Add --igen option. Generate output in igen format.
2634 (process_instructions): Format output according to igen option.
2635 (print_igen_insn_format): New function.
2636 (print_igen_insn_models): New function.
2637 (process_instructions): Only issue warnings and ignore
2638 instructions when no FEATURE_IGEN.
2639
2640Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2641
2642 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2643 MIPS targets.
2644
2645Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2646
2647 * configure: Regenerated to track ../common/aclocal.m4 changes.
2648
2649Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2650
2651 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2652 SIM_RESERVED_BITS): Delete, moved to common.
2653 (SIM_EXTRA_CFLAGS): Update.
2654
2655Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2656
2657 * configure.in: Configure non-strict memory alignment.
2658 * configure: Regenerated to track ../common/aclocal.m4 changes.
2659
2660Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2661
2662 * configure: Regenerated to track ../common/aclocal.m4 changes.
2663
2664Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2665
2666 * gencode.c (SDBBP,DERET): Added (3900) insns.
2667 (RFE): Turn on for 3900.
2668 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2669 (dsstate): Made global.
2670 (SUBTARGET_R3900): Added.
2671 (CANCELDELAYSLOT): New.
2672 (SignalException): Ignore SystemCall rather than ignore and
2673 terminate. Add DebugBreakPoint handling.
2674 (decode_coproc): New insns RFE, DERET; and new registers Debug
2675 and DEPC protected by SUBTARGET_R3900.
2676 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2677 bits explicitly.
2678 * Makefile.in,configure.in: Add mips subtarget option.
2679 * configure: Update.
2680
2681Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2682
2683 * gencode.c: Add r3900 (tx39).
2684
2685
2686Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2687
2688 * gencode.c (build_instruction): Don't need to subtract 4 for
2689 JALR, just 2.
2690
2691Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2692
2693 * interp.c: Correct some HASFPU problems.
2694
2695Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2696
2697 * configure: Regenerated to track ../common/aclocal.m4 changes.
2698
2699Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2700
2701 * interp.c (mips_options): Fix samples option short form, should
2702 be `x'.
2703
2704Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2705
2706 * interp.c (sim_info): Enable info code. Was just returning.
2707
2708Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2709
2710 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2711 MFC0.
2712
2713Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2714
2715 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2716 constants.
2717 (build_instruction): Ditto for LL.
2718
2719Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2720
2721 * configure: Regenerated to track ../common/aclocal.m4 changes.
2722
2723Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2724
2725 * configure: Regenerated to track ../common/aclocal.m4 changes.
2726 * config.in: Ditto.
2727
2728Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2729
2730 * interp.c (sim_open): Add call to sim_analyze_program, update
2731 call to sim_config.
2732
2733Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2734
2735 * interp.c (sim_kill): Delete.
2736 (sim_create_inferior): Add ABFD argument. Set PC from same.
2737 (sim_load): Move code initializing trap handlers from here.
2738 (sim_open): To here.
2739 (sim_load): Delete, use sim-hload.c.
2740
2741 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2742
2743Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2744
2745 * configure: Regenerated to track ../common/aclocal.m4 changes.
2746 * config.in: Ditto.
2747
2748Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2749
2750 * interp.c (sim_open): Add ABFD argument.
2751 (sim_load): Move call to sim_config from here.
2752 (sim_open): To here. Check return status.
2753
2754Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2755
2756 * gencode.c (build_instruction): Two arg MADD should
2757 not assign result to $0.
2758
2759Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2760
2761 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2762 * sim/mips/configure.in: Regenerate.
2763
2764Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2765
2766 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2767 signed8, unsigned8 et.al. types.
2768
2769 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2770 hosts when selecting subreg.
2771
2772Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2773
2774 * interp.c (sim_engine_run): Reset the ZERO register to zero
2775 regardless of FEATURE_WARN_ZERO.
2776 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2777
2778Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2779
2780 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2781 (SignalException): For BreakPoints ignore any mode bits and just
2782 save the PC.
2783 (SignalException): Always set the CAUSE register.
2784
2785Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2786
2787 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2788 exception has been taken.
2789
2790 * interp.c: Implement the ERET and mt/f sr instructions.
2791
2792Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2793
2794 * interp.c (SignalException): Don't bother restarting an
2795 interrupt.
2796
2797Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2798
2799 * interp.c (SignalException): Really take an interrupt.
2800 (interrupt_event): Only deliver interrupts when enabled.
2801
2802Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2803
2804 * interp.c (sim_info): Only print info when verbose.
2805 (sim_info) Use sim_io_printf for output.
2806
2807Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2808
2809 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2810 mips architectures.
2811
2812Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2813
2814 * interp.c (sim_do_command): Check for common commands if a
2815 simulator specific command fails.
2816
2817Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2818
2819 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2820 and simBE when DEBUG is defined.
2821
2822Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2823
2824 * interp.c (interrupt_event): New function. Pass exception event
2825 onto exception handler.
2826
2827 * configure.in: Check for stdlib.h.
2828 * configure: Regenerate.
2829
2830 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2831 variable declaration.
2832 (build_instruction): Initialize memval1.
2833 (build_instruction): Add UNUSED attribute to byte, bigend,
2834 reverse.
2835 (build_operands): Ditto.
2836
2837 * interp.c: Fix GCC warnings.
2838 (sim_get_quit_code): Delete.
2839
2840 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2841 * Makefile.in: Ditto.
2842 * configure: Re-generate.
2843
2844 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2845
2846Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2847
2848 * interp.c (mips_option_handler): New function parse argumes using
2849 sim-options.
2850 (myname): Replace with STATE_MY_NAME.
2851 (sim_open): Delete check for host endianness - performed by
2852 sim_config.
2853 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2854 (sim_open): Move much of the initialization from here.
2855 (sim_load): To here. After the image has been loaded and
2856 endianness set.
2857 (sim_open): Move ColdReset from here.
2858 (sim_create_inferior): To here.
2859 (sim_open): Make FP check less dependant on host endianness.
2860
2861 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2862 run.
2863 * interp.c (sim_set_callbacks): Delete.
2864
2865 * interp.c (membank, membank_base, membank_size): Replace with
2866 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2867 (sim_open): Remove call to callback->init. gdb/run do this.
2868
2869 * interp.c: Update
2870
2871 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2872
2873 * interp.c (big_endian_p): Delete, replaced by
2874 current_target_byte_order.
2875
2876Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2877
2878 * interp.c (host_read_long, host_read_word, host_swap_word,
2879 host_swap_long): Delete. Using common sim-endian.
2880 (sim_fetch_register, sim_store_register): Use H2T.
2881 (pipeline_ticks): Delete. Handled by sim-events.
2882 (sim_info): Update.
2883 (sim_engine_run): Update.
2884
2885Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2886
2887 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2888 reason from here.
2889 (SignalException): To here. Signal using sim_engine_halt.
2890 (sim_stop_reason): Delete, moved to common.
2891
2892Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2893
2894 * interp.c (sim_open): Add callback argument.
2895 (sim_set_callbacks): Delete SIM_DESC argument.
2896 (sim_size): Ditto.
2897
2898Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2899
2900 * Makefile.in (SIM_OBJS): Add common modules.
2901
2902 * interp.c (sim_set_callbacks): Also set SD callback.
2903 (set_endianness, xfer_*, swap_*): Delete.
2904 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2905 Change to functions using sim-endian macros.
2906 (control_c, sim_stop): Delete, use common version.
2907 (simulate): Convert into.
2908 (sim_engine_run): This function.
2909 (sim_resume): Delete.
2910
2911 * interp.c (simulation): New variable - the simulator object.
2912 (sim_kind): Delete global - merged into simulation.
2913 (sim_load): Cleanup. Move PC assignment from here.
2914 (sim_create_inferior): To here.
2915
2916 * sim-main.h: New file.
2917 * interp.c (sim-main.h): Include.
2918
2919Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2920
2921 * configure: Regenerated to track ../common/aclocal.m4 changes.
2922
2923Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2924
2925 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2926
2927Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2928
2929 * gencode.c (build_instruction): DIV instructions: check
2930 for division by zero and integer overflow before using
2931 host's division operation.
2932
2933Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2934
2935 * Makefile.in (SIM_OBJS): Add sim-load.o.
2936 * interp.c: #include bfd.h.
2937 (target_byte_order): Delete.
2938 (sim_kind, myname, big_endian_p): New static locals.
2939 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2940 after argument parsing. Recognize -E arg, set endianness accordingly.
2941 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2942 load file into simulator. Set PC from bfd.
2943 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2944 (set_endianness): Use big_endian_p instead of target_byte_order.
2945
2946Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2947
2948 * interp.c (sim_size): Delete prototype - conflicts with
2949 definition in remote-sim.h. Correct definition.
2950
2951Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2952
2953 * configure: Regenerated to track ../common/aclocal.m4 changes.
2954 * config.in: Ditto.
2955
2956Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2957
2958 * interp.c (sim_open): New arg `kind'.
2959
2960 * configure: Regenerated to track ../common/aclocal.m4 changes.
2961
2962Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2963
2964 * configure: Regenerated to track ../common/aclocal.m4 changes.
2965
2966Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2967
2968 * interp.c (sim_open): Set optind to 0 before calling getopt.
2969
2970Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2971
2972 * configure: Regenerated to track ../common/aclocal.m4 changes.
2973
2974Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2975
2976 * interp.c : Replace uses of pr_addr with pr_uword64
2977 where the bit length is always 64 independent of SIM_ADDR.
2978 (pr_uword64) : added.
2979
2980Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2981
2982 * configure: Re-generate.
2983
2984Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2985
2986 * configure: Regenerate to track ../common/aclocal.m4 changes.
2987
2988Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2989
2990 * interp.c (sim_open): New SIM_DESC result. Argument is now
2991 in argv form.
2992 (other sim_*): New SIM_DESC argument.
2993
2994Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2995
2996 * interp.c: Fix printing of addresses for non-64-bit targets.
2997 (pr_addr): Add function to print address based on size.
2998
2999Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3000
3001 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3002
3003Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3004
3005 * gencode.c (build_mips16_operands): Correct computation of base
3006 address for extended PC relative instruction.
3007
3008Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3009
3010 * interp.c (mips16_entry): Add support for floating point cases.
3011 (SignalException): Pass floating point cases to mips16_entry.
3012 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3013 registers.
3014 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3015 or fmt_word.
3016 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3017 and then set the state to fmt_uninterpreted.
3018 (COP_SW): Temporarily set the state to fmt_word while calling
3019 ValueFPR.
3020
3021Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3022
3023 * gencode.c (build_instruction): The high order may be set in the
3024 comparison flags at any ISA level, not just ISA 4.
3025
3026Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3027
3028 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3029 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3030 * configure.in: sinclude ../common/aclocal.m4.
3031 * configure: Regenerated.
3032
3033Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3034
3035 * configure: Rebuild after change to aclocal.m4.
3036
3037Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3038
3039 * configure configure.in Makefile.in: Update to new configure
3040 scheme which is more compatible with WinGDB builds.
3041 * configure.in: Improve comment on how to run autoconf.
3042 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3043 * Makefile.in: Use autoconf substitution to install common
3044 makefile fragment.
3045
3046Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3047
3048 * gencode.c (build_instruction): Use BigEndianCPU instead of
3049 ByteSwapMem.
3050
3051Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3052
3053 * interp.c (sim_monitor): Make output to stdout visible in
3054 wingdb's I/O log window.
3055
3056Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3057
3058 * support.h: Undo previous change to SIGTRAP
3059 and SIGQUIT values.
3060
3061Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3062
3063 * interp.c (store_word, load_word): New static functions.
3064 (mips16_entry): New static function.
3065 (SignalException): Look for mips16 entry and exit instructions.
3066 (simulate): Use the correct index when setting fpr_state after
3067 doing a pending move.
3068
3069Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3070
3071 * interp.c: Fix byte-swapping code throughout to work on
3072 both little- and big-endian hosts.
3073
3074Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3075
3076 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3077 with gdb/config/i386/xm-windows.h.
3078
3079Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3080
3081 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3082 that messes up arithmetic shifts.
3083
3084Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3085
3086 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3087 SIGTRAP and SIGQUIT for _WIN32.
3088
3089Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3090
3091 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3092 force a 64 bit multiplication.
3093 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3094 destination register is 0, since that is the default mips16 nop
3095 instruction.
3096
3097Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3098
3099 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3100 (build_endian_shift): Don't check proc64.
3101 (build_instruction): Always set memval to uword64. Cast op2 to
3102 uword64 when shifting it left in memory instructions. Always use
3103 the same code for stores--don't special case proc64.
3104
3105 * gencode.c (build_mips16_operands): Fix base PC value for PC
3106 relative operands.
3107 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3108 jal instruction.
3109 * interp.c (simJALDELAYSLOT): Define.
3110 (JALDELAYSLOT): Define.
3111 (INDELAYSLOT, INJALDELAYSLOT): Define.
3112 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3113
3114Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3115
3116 * interp.c (sim_open): add flush_cache as a PMON routine
3117 (sim_monitor): handle flush_cache by ignoring it
3118
3119Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3120
3121 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3122 BigEndianMem.
3123 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3124 (BigEndianMem): Rename to ByteSwapMem and change sense.
3125 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3126 BigEndianMem references to !ByteSwapMem.
3127 (set_endianness): New function, with prototype.
3128 (sim_open): Call set_endianness.
3129 (sim_info): Use simBE instead of BigEndianMem.
3130 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3131 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3132 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3133 ifdefs, keeping the prototype declaration.
3134 (swap_word): Rewrite correctly.
3135 (ColdReset): Delete references to CONFIG. Delete endianness related
3136 code; moved to set_endianness.
3137
3138Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3139
3140 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3141 * interp.c (CHECKHILO): Define away.
3142 (simSIGINT): New macro.
3143 (membank_size): Increase from 1MB to 2MB.
3144 (control_c): New function.
3145 (sim_resume): Rename parameter signal to signal_number. Add local
3146 variable prev. Call signal before and after simulate.
3147 (sim_stop_reason): Add simSIGINT support.
3148 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3149 functions always.
3150 (sim_warning): Delete call to SignalException. Do call printf_filtered
3151 if logfh is NULL.
3152 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3153 a call to sim_warning.
3154
3155Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3156
3157 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3158 16 bit instructions.
3159
3160Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3161
3162 Add support for mips16 (16 bit MIPS implementation):
3163 * gencode.c (inst_type): Add mips16 instruction encoding types.
3164 (GETDATASIZEINSN): Define.
3165 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3166 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3167 mtlo.
3168 (MIPS16_DECODE): New table, for mips16 instructions.
3169 (bitmap_val): New static function.
3170 (struct mips16_op): Define.
3171 (mips16_op_table): New table, for mips16 operands.
3172 (build_mips16_operands): New static function.
3173 (process_instructions): If PC is odd, decode a mips16
3174 instruction. Break out instruction handling into new
3175 build_instruction function.
3176 (build_instruction): New static function, broken out of
3177 process_instructions. Check modifiers rather than flags for SHIFT
3178 bit count and m[ft]{hi,lo} direction.
3179 (usage): Pass program name to fprintf.
3180 (main): Remove unused variable this_option_optind. Change
3181 ``*loptarg++'' to ``loptarg++''.
3182 (my_strtoul): Parenthesize && within ||.
3183 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3184 (simulate): If PC is odd, fetch a 16 bit instruction, and
3185 increment PC by 2 rather than 4.
3186 * configure.in: Add case for mips16*-*-*.
3187 * configure: Rebuild.
3188
3189Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3190
3191 * interp.c: Allow -t to enable tracing in standalone simulator.
3192 Fix garbage output in trace file and error messages.
3193
3194Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3195
3196 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3197 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3198 * configure.in: Simplify using macros in ../common/aclocal.m4.
3199 * configure: Regenerated.
3200 * tconfig.in: New file.
3201
3202Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3203
3204 * interp.c: Fix bugs in 64-bit port.
3205 Use ansi function declarations for msvc compiler.
3206 Initialize and test file pointer in trace code.
3207 Prevent duplicate definition of LAST_EMED_REGNUM.
3208
3209Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3210
3211 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3212
3213Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3214
3215 * interp.c (SignalException): Check for explicit terminating
3216 breakpoint value.
3217 * gencode.c: Pass instruction value through SignalException()
3218 calls for Trap, Breakpoint and Syscall.
3219
3220Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3221
3222 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3223 only used on those hosts that provide it.
3224 * configure.in: Add sqrt() to list of functions to be checked for.
3225 * config.in: Re-generated.
3226 * configure: Re-generated.
3227
3228Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3229
3230 * gencode.c (process_instructions): Call build_endian_shift when
3231 expanding STORE RIGHT, to fix swr.
3232 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3233 clear the high bits.
3234 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3235 Fix float to int conversions to produce signed values.
3236
3237Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3238
3239 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3240 (process_instructions): Correct handling of nor instruction.
3241 Correct shift count for 32 bit shift instructions. Correct sign
3242 extension for arithmetic shifts to not shift the number of bits in
3243 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3244 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3245 Fix madd.
3246 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3247 It's OK to have a mult follow a mult. What's not OK is to have a
3248 mult follow an mfhi.
3249 (Convert): Comment out incorrect rounding code.
3250
3251Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3252
3253 * interp.c (sim_monitor): Improved monitor printf
3254 simulation. Tidied up simulator warnings, and added "--log" option
3255 for directing warning message output.
3256 * gencode.c: Use sim_warning() rather than WARNING macro.
3257
3258Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3259
3260 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3261 getopt1.o, rather than on gencode.c. Link objects together.
3262 Don't link against -liberty.
3263 (gencode.o, getopt.o, getopt1.o): New targets.
3264 * gencode.c: Include <ctype.h> and "ansidecl.h".
3265 (AND): Undefine after including "ansidecl.h".
3266 (ULONG_MAX): Define if not defined.
3267 (OP_*): Don't define macros; now defined in opcode/mips.h.
3268 (main): Call my_strtoul rather than strtoul.
3269 (my_strtoul): New static function.
3270
3271Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3272
3273 * gencode.c (process_instructions): Generate word64 and uword64
3274 instead of `long long' and `unsigned long long' data types.
3275 * interp.c: #include sysdep.h to get signals, and define default
3276 for SIGBUS.
3277 * (Convert): Work around for Visual-C++ compiler bug with type
3278 conversion.
3279 * support.h: Make things compile under Visual-C++ by using
3280 __int64 instead of `long long'. Change many refs to long long
3281 into word64/uword64 typedefs.
3282
3283Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3284
3285 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3286 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3287 (docdir): Removed.
3288 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3289 (AC_PROG_INSTALL): Added.
3290 (AC_PROG_CC): Moved to before configure.host call.
3291 * configure: Rebuilt.
3292
3293Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3294
3295 * configure.in: Define @SIMCONF@ depending on mips target.
3296 * configure: Rebuild.
3297 * Makefile.in (run): Add @SIMCONF@ to control simulator
3298 construction.
3299 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3300 * interp.c: Remove some debugging, provide more detailed error
3301 messages, update memory accesses to use LOADDRMASK.
3302
3303Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3304
3305 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3306 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3307 stamp-h.
3308 * configure: Rebuild.
3309 * config.in: New file, generated by autoheader.
3310 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3311 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3312 HAVE_ANINT and HAVE_AINT, as appropriate.
3313 * Makefile.in (run): Use @LIBS@ rather than -lm.
3314 (interp.o): Depend upon config.h.
3315 (Makefile): Just rebuild Makefile.
3316 (clean): Remove stamp-h.
3317 (mostlyclean): Make the same as clean, not as distclean.
3318 (config.h, stamp-h): New targets.
3319
3320Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3321
3322 * interp.c (ColdReset): Fix boolean test. Make all simulator
3323 globals static.
3324
3325Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3326
3327 * interp.c (xfer_direct_word, xfer_direct_long,
3328 swap_direct_word, swap_direct_long, xfer_big_word,
3329 xfer_big_long, xfer_little_word, xfer_little_long,
3330 swap_word,swap_long): Added.
3331 * interp.c (ColdReset): Provide function indirection to
3332 host<->simulated_target transfer routines.
3333 * interp.c (sim_store_register, sim_fetch_register): Updated to
3334 make use of indirected transfer routines.
3335
3336Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3337
3338 * gencode.c (process_instructions): Ensure FP ABS instruction
3339 recognised.
3340 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3341 system call support.
3342
3343Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3344
3345 * interp.c (sim_do_command): Complain if callback structure not
3346 initialised.
3347
3348Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3349
3350 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3351 support for Sun hosts.
3352 * Makefile.in (gencode): Ensure the host compiler and libraries
3353 used for cross-hosted build.
3354
3355Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3356
3357 * interp.c, gencode.c: Some more (TODO) tidying.
3358
3359Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3360
3361 * gencode.c, interp.c: Replaced explicit long long references with
3362 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3363 * support.h (SET64LO, SET64HI): Macros added.
3364
3365Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3366
3367 * configure: Regenerate with autoconf 2.7.
3368
3369Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3370
3371 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3372 * support.h: Remove superfluous "1" from #if.
3373 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3374
3375Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3376
3377 * interp.c (StoreFPR): Control UndefinedResult() call on
3378 WARN_RESULT manifest.
3379
3380Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3381
3382 * gencode.c: Tidied instruction decoding, and added FP instruction
3383 support.
3384
3385 * interp.c: Added dineroIII, and BSD profiling support. Also
3386 run-time FP handling.
3387
3388Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3389
3390 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3391 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
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