projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sim: move from common.m4 to SIM_AC_COMMON
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
6ffe910a
MF		 12011-10-17 Mike Frysinger <vapier@gentoo.org>
2
3 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
4 call. Replace common.m4 include with SIM_AC_COMMON.
5 * configure: Regenerate.
6
31b28250
HPN		 72011-07-08 Hans-Peter Nilsson <hp@axis.com>
8
3faa01e3
HPN		 9 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
10 $(SIM_EXTRA_DEPS).
11 (tmp-mach-multi): Exit early when igen fails.
31b28250 12
2419798b
MF		 132011-07-05 Mike Frysinger <vapier@gentoo.org>
14
15 * interp.c (sim_do_command): Delete.
16
d79fe0d6
MF		 172011-02-14 Mike Frysinger <vapier@gentoo.org>
18
19 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
20 (tx3904sio_fifo_reset): Likewise.
21 * interp.c (sim_monitor): Likewise.
22
5558e7e6
MF		 232010-04-14 Mike Frysinger <vapier@gentoo.org>
24
25 * interp.c (sim_write): Add const to buffer arg.
26
35aafff4
JB		 272010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
28
29 * interp.c: Don't include sysdep.h
30
3725885a
RW		 312010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
32
33 * configure: Regenerate.
34
d6416cdc
RW		 352009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
36
81ecdfbb
RW		 37 * config.in: Regenerate.
38 * configure: Likewise.
39
d6416cdc
RW		 40 * configure: Regenerate.
41
b5bd9624
HPN		 422008-07-11 Hans-Peter Nilsson <hp@axis.com>
43
44 * configure: Regenerate to track ../common/common.m4 changes.
45 * config.in: Ditto.
46
6efef468
JM		 472008-06-06 Vladimir Prus <vladimir@codesourcery.com>
48 Daniel Jacobowitz <dan@codesourcery.com>
49 Joseph Myers <joseph@codesourcery.com>
50
51 * configure: Regenerate.
52
60dc88db
RS		 532007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
54
55 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
56 that unconditionally allows fmt_ps.
57 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
58 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
59 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
60 filter from 64,f to 32,f.
61 (PREFX): Change filter from 64 to 32.
62 (LDXC1, LUXC1): Provide separate mips32r2 implementations
63 that use do_load_double instead of do_load. Make both LUXC1
64 versions unpredictable if SizeFGR () != 64.
65 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
66 instead of do_store. Remove unused variable. Make both SUXC1
67 versions unpredictable if SizeFGR () != 64.
68
599ca73e
RS		 692007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
70
71 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
72 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
73 shifts for that case.
74
2525df03
NC		 752007-09-04 Nick Clifton <nickc@redhat.com>
76
77 * interp.c (options enum): Add OPTION_INFO_MEMORY.
78 (display_mem_info): New static variable.
79 (mips_option_handler): Handle OPTION_INFO_MEMORY.
80 (mips_options): Add info-memory and memory-info.
81 (sim_open): After processing the command line and board
82 specification, check display_mem_info. If it is set then
83 call the real handler for the --memory-info command line
84 switch.
85
35ee6e1e
JB		 862007-08-24 Joel Brobecker <brobecker@adacore.com>
87
88 * configure.ac: Change license of multi-run.c to GPL version 3.
89 * configure: Regenerate.
90
d5fb0879
RS		 912007-06-28 Richard Sandiford <richard@codesourcery.com>
92
93 * configure.ac, configure: Revert last patch.
94
2a2ce21b
RS		 952007-06-26 Richard Sandiford <richard@codesourcery.com>
96
97 * configure.ac (sim_mipsisa3264_configs): New variable.
98 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
99 every configuration support all four targets, using the triplet to
100 determine the default.
101 * configure: Regenerate.
102
efdcccc9
RS		 1032007-06-25 Richard Sandiford <richard@codesourcery.com>
104
0a7692b2 105 * Makefile.in (m16run.o): New rule.
efdcccc9 106
f532a356
TS		 1072007-05-15 Thiemo Seufer <ths@mips.com>
108
109 * mips3264r2.igen (DSHD): Fix compile warning.
110
bfe9c90b
TS		 1112007-05-14 Thiemo Seufer <ths@mips.com>
112
113 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
114 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
115 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
116 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
117 for mips32r2.
118
53f4826b
TS		 1192007-03-01 Thiemo Seufer <ths@mips.com>
120
121 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
122 and mips64.
123
8bf3ddc8
TS		 1242007-02-20 Thiemo Seufer <ths@mips.com>
125
126 * dsp.igen: Update copyright notice.
127 * dsp2.igen: Fix copyright notice.
128
8b082fb1
TS		 1292007-02-20 Thiemo Seufer <ths@mips.com>
130 Chao-Ying Fu <fu@mips.com>
131
132 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
133 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
134 Add dsp2 to sim_igen_machine.
135 * configure: Regenerate.
136 * dsp.igen (do_ph_op): Add MUL support when op = 2.
137 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
138 (mulq_rs.ph): Use do_ph_mulq.
139 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
140 * mips.igen: Add dsp2 model and include dsp2.igen.
141 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
142 for *mips32r2, *mips64r2, *dsp.
143 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
144 for *mips32r2, *mips64r2, *dsp2.
145 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
146
b1004875
TS		 1472007-02-19 Thiemo Seufer <ths@mips.com>
148 Nigel Stephens <nigel@mips.com>
149
150 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
151 jumps with hazard barrier.
152
f8df4c77
TS		 1532007-02-19 Thiemo Seufer <ths@mips.com>
154 Nigel Stephens <nigel@mips.com>
155
156 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
157 after each call to sim_io_write.
158
b1004875 1592007-02-19 Thiemo Seufer <ths@mips.com>
07802d98 160 Nigel Stephens <nigel@mips.com>
b1004875
TS		 161
162 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
163 supported by this simulator.
07802d98
TS		 164 (decode_coproc): Recognise additional CP0 Config registers
165 correctly.
166
14fb6c5a
TS		 1672007-02-19 Thiemo Seufer <ths@mips.com>
168 Nigel Stephens <nigel@mips.com>
169 David Ung <davidu@mips.com>
170
171 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
172 uninterpreted formats. If fmt is one of the uninterpreted types
173 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
174 fmt_word, and fmt_uninterpreted_64 like fmt_long.
175 (store_fpr): When writing an invalid odd register, set the
176 matching even register to fmt_unknown, not the following register.
177 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
178 the the memory window at offset 0 set by --memory-size command
179 line option.
180 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
181 point register.
182 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
183 register.
184 (sim_monitor): When returning the memory size to the MIPS
185 application, use the value in STATE_MEM_SIZE, not an arbitrary
186 hardcoded value.
187 (cop_lw): Don' mess around with FPR_STATE, just pass
188 fmt_uninterpreted_32 to StoreFPR.
189 (cop_sw): Similarly.
190 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
191 (cop_sd): Similarly.
192 * mips.igen (not_word_value): Single version for mips32, mips64
193 and mips16.
194
c8847145
TS		 1952007-02-19 Thiemo Seufer <ths@mips.com>
196 Nigel Stephens <nigel@mips.com>
197
198 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
199 MBytes.
200
4b5d35ee
TS		 2012007-02-17 Thiemo Seufer <ths@mips.com>
202
203 * configure.ac (mips*-sde-elf*): Move in front of generic machine
204 configuration.
205 * configure: Regenerate.
206
3669427c
TS		 2072007-02-17 Thiemo Seufer <ths@mips.com>
208
209 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
210 Add mdmx to sim_igen_machine.
211 (mipsisa64*-*-*): Likewise. Remove dsp.
212 (mipsisa32*-*-*): Remove dsp.
213 * configure: Regenerate.
214
109ad085
TS		 2152007-02-13 Thiemo Seufer <ths@mips.com>
216
217 * configure.ac: Add mips*-sde-elf* target.
218 * configure: Regenerate.
219
921d7ad3
HPN		 2202006-12-21 Hans-Peter Nilsson <hp@axis.com>
221
222 * acconfig.h: Remove.
223 * config.in, configure: Regenerate.
224
02f97da7
TS		 2252006-11-07 Thiemo Seufer <ths@mips.com>
226
227 * dsp.igen (do_w_op): Fix compiler warning.
228
2d2733fc
TS		 2292006-08-29 Thiemo Seufer <ths@mips.com>
230 David Ung <davidu@mips.com>
231
232 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
233 sim_igen_machine.
234 * configure: Regenerate.
235 * mips.igen (model): Add smartmips.
236 (MADDU): Increment ACX if carry.
237 (do_mult): Clear ACX.
238 (ROR,RORV): Add smartmips.
239 (include): Include smartmips.igen.
240 * sim-main.h (ACX): Set to REGISTERS[89].
241 * smartmips.igen: New file.
242
d85c3a10
TS		 2432006-08-29 Thiemo Seufer <ths@mips.com>
244 David Ung <davidu@mips.com>
245
246 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
247 mips3264r2.igen. Add missing dependency rules.
248 * m16e.igen: Support for mips16e save/restore instructions.
249
e85e3205
RE		 2502006-06-13 Richard Earnshaw <rearnsha@arm.com>
251
252 * configure: Regenerated.
253
2f0122dc
DJ		 2542006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
255
256 * configure: Regenerated.
257
20e95c23
DJ		 2582006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
259
260 * configure: Regenerated.
261
69088b17
CF		 2622006-05-15 Chao-ying Fu <fu@mips.com>
263
264 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
265
0275de4e
NC		 2662006-04-18 Nick Clifton <nickc@redhat.com>
267
268 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
269 statement.
270
b3a3ffef
HPN		 2712006-03-29 Hans-Peter Nilsson <hp@axis.com>
272
273 * configure: Regenerate.
274
40a5538e
CF		 2752005-12-14 Chao-ying Fu <fu@mips.com>
276
277 * Makefile.in (SIM_OBJS): Add dsp.o.
278 (dsp.o): New dependency.
279 (IGEN_INCLUDE): Add dsp.igen.
280 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
281 mipsisa64*-*-*): Add dsp to sim_igen_machine.
282 * configure: Regenerate.
283 * mips.igen: Add dsp model and include dsp.igen.
284 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
285 because these instructions are extended in DSP ASE.
286 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
287 adding 6 DSP accumulator registers and 1 DSP control register.
288 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
289 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
290 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
291 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
292 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
293 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
294 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
295 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
296 DSPCR_CCOND_SMASK): New define.
297 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
298 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
299
21d14896
ILT		 3002005-07-08 Ian Lance Taylor <ian@airs.com>
301
302 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
303
b16d63da
DU		 3042005-06-16 David Ung <davidu@mips.com>
305 Nigel Stephens <nigel@mips.com>
306
307 * mips.igen: New mips16e model and include m16e.igen.
308 (check_u64): Add mips16e tag.
309 * m16e.igen: New file for MIPS16e instructions.
310 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
311 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
312 models.
313 * configure: Regenerate.
314
e70cb6cd
CD		 3152005-05-26 David Ung <davidu@mips.com>
316
317 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
318 tags to all instructions which are applicable to the new ISAs.
319 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
320 vr.igen.
321 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
322 instructions.
323 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
324 to mips.igen.
325 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
326 * configure: Regenerate.
327
2b193c4a
MK		 3282005-03-23 Mark Kettenis <kettenis@gnu.org>
329
330 * configure: Regenerate.
331
35695fd6
AC		 3322005-01-14 Andrew Cagney <cagney@gnu.org>
333
334 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
335 explicit call to AC_CONFIG_HEADER.
336 * configure: Regenerate.
337
f0569246
AC		 3382005-01-12 Andrew Cagney <cagney@gnu.org>
339
340 * configure.ac: Update to use ../common/common.m4.
341 * configure: Re-generate.
342
38f48d72
AC		 3432005-01-11 Andrew Cagney <cagney@localhost.localdomain>
344
345 * configure: Regenerated to track ../common/aclocal.m4 changes.
346
b7026657
AC		 3472005-01-07 Andrew Cagney <cagney@gnu.org>
348
349 * configure.ac: Rename configure.in, require autoconf 2.59.
350 * configure: Re-generate.
351
379832de
HPN		 3522004-12-08 Hans-Peter Nilsson <hp@axis.com>
353
354 * configure: Regenerate for ../common/aclocal.m4 update.
355
cd62154c
AC		 3562004-09-24 Monika Chaddha <monika@acmet.com>
357
358 Committed by Andrew Cagney.
359 * m16.igen (CMP, CMPI): Fix assembler.
360
e5da76ec
CD		 3612004-08-18 Chris Demetriou <cgd@broadcom.com>
362
363 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
364 * configure: Regenerate.
365
139181c8
CD		 3662004-06-25 Chris Demetriou <cgd@broadcom.com>
367
368 * configure.in (sim_m16_machine): Include mipsIII.
369 * configure: Regenerate.
370
1a27f959
CD		 3712004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
372
373 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
374 from COP0_BADVADDR.
375 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
376
5dbb7b5a
CD		 3772004-04-10 Chris Demetriou <cgd@broadcom.com>
378
379 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
380
14234056
CD		 3812004-04-09 Chris Demetriou <cgd@broadcom.com>
382
383 * mips.igen (check_fmt): Remove.
384 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
385 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
386 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
387 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
388 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
389 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
390 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
391 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
392 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
393 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
394
c6f9085c
CD		 3952004-04-09 Chris Demetriou <cgd@broadcom.com>
396
397 * sb1.igen (check_sbx): New function.
398 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
399
11d66e66 4002004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 401 Richard Sandiford <rsandifo@redhat.com>
402
403 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
404 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
405 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
406 separate implementations for mipsIV and mipsV. Use new macros to
407 determine whether the restrictions apply.
408
b3208fb8
CD		 4092004-01-19 Chris Demetriou <cgd@broadcom.com>
410
411 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
412 (check_mult_hilo): Improve comments.
413 (check_div_hilo): Likewise. Also, fork off a new version
414 to handle mips32/mips64 (since there are no hazards to check
415 in MIPS32/MIPS64).
416
9a1d84fb
CD		 4172003-06-17 Richard Sandiford <rsandifo@redhat.com>
418
419 * mips.igen (do_dmultx): Fix check for negative operands.
420
ae451ac6
ILT		 4212003-05-16 Ian Lance Taylor <ian@airs.com>
422
423 * Makefile.in (SHELL): Make sure this is defined.
424 (various): Use $(SHELL) whenever we invoke move-if-change.
425
dd69d292
CD		 4262003-05-03 Chris Demetriou <cgd@broadcom.com>
427
428 * cp1.c: Tweak attribution slightly.
429 * cp1.h: Likewise.
430 * mdmx.c: Likewise.
431 * mdmx.igen: Likewise.
432 * mips3d.igen: Likewise.
433 * sb1.igen: Likewise.
434
bcd0068e
CD		 4352003-04-15 Richard Sandiford <rsandifo@redhat.com>
436
437 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
438 unsigned operands.
439
6b4a8935
AC		 4402003-02-27 Andrew Cagney <cagney@redhat.com>
441
601da316
AC		 442 * interp.c (sim_open): Rename _bfd to bfd.
443 (sim_create_inferior): Ditto.
6b4a8935 444
d29e330f
CD		 4452003-01-14 Chris Demetriou <cgd@broadcom.com>
446
447 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
448
a2353a08
CD		 4492003-01-14 Chris Demetriou <cgd@broadcom.com>
450
451 * mips.igen (EI, DI): Remove.
452
80551777
CD		 4532003-01-05 Richard Sandiford <rsandifo@redhat.com>
454
455 * Makefile.in (tmp-run-multi): Fix mips16 filter.
456
4c54fc26
CD		 4572003-01-04 Richard Sandiford <rsandifo@redhat.com>
458 Andrew Cagney <ac131313@redhat.com>
459 Gavin Romig-Koch <gavin@redhat.com>
460 Graydon Hoare <graydon@redhat.com>
461 Aldy Hernandez <aldyh@redhat.com>
462 Dave Brolley <brolley@redhat.com>
463 Chris Demetriou <cgd@broadcom.com>
464
465 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
466 (sim_mach_default): New variable.
467 (mips64vr-*-*, mips64vrel-*-*): New configurations.
468 Add a new simulator generator, MULTI.
469 * configure: Regenerate.
470 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
471 (multi-run.o): New dependency.
472 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
473 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
474 (tmp-multi): Combine them.
475 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
476 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
477 (distclean-extra): New rule.
478 * sim-main.h: Include bfd.h.
479 (MIPS_MACH): New macro.
480 * mips.igen (vr4120, vr5400, vr5500): New models.
481 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
482 * vr.igen: Replace with new version.
483
e6c674b8
CD		 4842003-01-04 Chris Demetriou <cgd@broadcom.com>
485
486 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
487 * configure: Regenerate.
488
28f50ac8
CD		 4892002-12-31 Chris Demetriou <cgd@broadcom.com>
490
491 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
492 * mips.igen: Remove all invocations of check_branch_bug and
493 mark_branch_bug.
494
5071ffe6
CD		 4952002-12-16 Chris Demetriou <cgd@broadcom.com>
496
497 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
498
06e7837e
CD		 4992002-07-30 Chris Demetriou <cgd@broadcom.com>
500
501 * mips.igen (do_load_double, do_store_double): New functions.
502 (LDC1, SDC1): Rename to...
503 (LDC1b, SDC1b): respectively.
504 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
505
2265c243
MS		 5062002-07-29 Michael Snyder <msnyder@redhat.com>
507
508 * cp1.c (fp_recip2): Modify initialization expression so that
509 GCC will recognize it as constant.
510
a2f8b4f3
CD		 5112002-06-18 Chris Demetriou <cgd@broadcom.com>
512
513 * mdmx.c (SD_): Delete.
514 (Unpredictable): Re-define, for now, to directly invoke
515 unpredictable_action().
516 (mdmx_acc_op): Fix error in .ob immediate handling.
517
b4b6c939
AC		 5182002-06-18 Andrew Cagney <cagney@redhat.com>
519
520 * interp.c (sim_firmware_command): Initialize `address'.
521
c8cca39f
AC		 5222002-06-16 Andrew Cagney <ac131313@redhat.com>
523
524 * configure: Regenerated to track ../common/aclocal.m4 changes.
525
e7e81181
CD		 5262002-06-14 Chris Demetriou <cgd@broadcom.com>
527 Ed Satterthwaite <ehs@broadcom.com>
528
529 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
530 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
531 * mips.igen: Include mips3d.igen.
532 (mips3d): New model name for MIPS-3D ASE instructions.
533 (CVT.W.fmt): Don't use this instruction for word (source) format
534 instructions.
535 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
536 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
537 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
538 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
539 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
540 (RSquareRoot1, RSquareRoot2): New macros.
541 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
542 (fp_rsqrt2): New functions.
543 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
544 * configure: Regenerate.
545
3a2b820e 5462002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 547 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 548
549 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
550 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
551 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
552 (convert): Note that this function is not used for paired-single
553 format conversions.
554 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
555 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
556 (check_fmt_p): Enable paired-single support.
557 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
558 (PUU.PS): New instructions.
559 (CVT.S.fmt): Don't use this instruction for paired-single format
560 destinations.
561 * sim-main.h (FP_formats): New value 'fmt_ps.'
562 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
563 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
564
d18ea9c2
CD		 5652002-06-12 Chris Demetriou <cgd@broadcom.com>
566
567 * mips.igen: Fix formatting of function calls in
568 many FP operations.
569
95fd5cee
CD		 5702002-06-12 Chris Demetriou <cgd@broadcom.com>
571
572 * mips.igen (MOVN, MOVZ): Trace result.
573 (TNEI): Print "tnei" as the opcode name in traces.
574 (CEIL.W): Add disassembly string for traces.
575 (RSQRT.fmt): Make location of disassembly string consistent
576 with other instructions.
577
4f0d55ae
CD		 5782002-06-12 Chris Demetriou <cgd@broadcom.com>
579
580 * mips.igen (X): Delete unused function.
581
3c25f8c7
AC		 5822002-06-08 Andrew Cagney <cagney@redhat.com>
583
584 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
585
f3c08b7e
CD		 5862002-06-07 Chris Demetriou <cgd@broadcom.com>
587 Ed Satterthwaite <ehs@broadcom.com>
588
589 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
590 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
591 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
592 (fp_nmsub): New prototypes.
593 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
594 (NegMultiplySub): New defines.
595 * mips.igen (RSQRT.fmt): Use RSquareRoot().
596 (MADD.D, MADD.S): Replace with...
597 (MADD.fmt): New instruction.
598 (MSUB.D, MSUB.S): Replace with...
599 (MSUB.fmt): New instruction.
600 (NMADD.D, NMADD.S): Replace with...
601 (NMADD.fmt): New instruction.
602 (NMSUB.D, MSUB.S): Replace with...
603 (NMSUB.fmt): New instruction.
604
52714ff9
CD		 6052002-06-07 Chris Demetriou <cgd@broadcom.com>
606 Ed Satterthwaite <ehs@broadcom.com>
607
608 * cp1.c: Fix more comment spelling and formatting.
609 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
610 (denorm_mode): New function.
611 (fpu_unary, fpu_binary): Round results after operation, collect
612 status from rounding operations, and update the FCSR.
613 (convert): Collect status from integer conversions and rounding
614 operations, and update the FCSR. Adjust NaN values that result
615 from conversions. Convert to use sim_io_eprintf rather than
616 fprintf, and remove some debugging code.
617 * cp1.h (fenr_FS): New define.
618
577d8c4b
CD		 6192002-06-07 Chris Demetriou <cgd@broadcom.com>
620
621 * cp1.c (convert): Remove unusable debugging code, and move MIPS
622 rounding mode to sim FP rounding mode flag conversion code into...
623 (rounding_mode): New function.
624
196496ed
CD		 6252002-06-07 Chris Demetriou <cgd@broadcom.com>
626
627 * cp1.c: Clean up formatting of a few comments.
628 (value_fpr): Reformat switch statement.
629
cfe9ea23
CD		 6302002-06-06 Chris Demetriou <cgd@broadcom.com>
631 Ed Satterthwaite <ehs@broadcom.com>
632
633 * cp1.h: New file.
634 * sim-main.h: Include cp1.h.
635 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
636 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
637 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
638 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
639 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
640 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
641 * cp1.c: Don't include sim-fpu.h; already included by
642 sim-main.h. Clean up formatting of some comments.
643 (NaN, Equal, Less): Remove.
644 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
645 (fp_cmp): New functions.
646 * mips.igen (do_c_cond_fmt): Remove.
647 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
648 Compare. Add result tracing.
649 (CxC1): Remove, replace with...
650 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
651 (DMxC1): Remove, replace with...
652 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
653 (MxC1): Remove, replace with...
654 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
655
ee7254b0
CD		 6562002-06-04 Chris Demetriou <cgd@broadcom.com>
657
658 * sim-main.h (FGRIDX): Remove, replace all uses with...
659 (FGR_BASE): New macro.
660 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
661 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
662 (NR_FGR, FGR): Likewise.
663 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
664 * mips.igen: Likewise.
665
d3eb724f
CD		 6662002-06-04 Chris Demetriou <cgd@broadcom.com>
667
668 * cp1.c: Add an FSF Copyright notice to this file.
669
ba46ddd0
CD		 6702002-06-04 Chris Demetriou <cgd@broadcom.com>
671 Ed Satterthwaite <ehs@broadcom.com>
672
673 * cp1.c (Infinity): Remove.
674 * sim-main.h (Infinity): Likewise.
675
676 * cp1.c (fp_unary, fp_binary): New functions.
677 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
678 (fp_sqrt): New functions, implemented in terms of the above.
679 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
680 (Recip, SquareRoot): Remove (replaced by functions above).
681 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
682 (fp_recip, fp_sqrt): New prototypes.
683 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
684 (Recip, SquareRoot): Replace prototypes with #defines which
685 invoke the functions above.
686
18d8a52d
CD		 6872002-06-03 Chris Demetriou <cgd@broadcom.com>
688
689 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
690 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
691 file, remove PARAMS from prototypes.
692 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
693 simulator state arguments.
694 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
695 pass simulator state arguments.
696 * cp1.c (SD): Redefine as CPU_STATE(cpu).
697 (store_fpr, convert): Remove 'sd' argument.
698 (value_fpr): Likewise. Convert to use 'SD' instead.
699
0f154cbd
CD		 7002002-06-03 Chris Demetriou <cgd@broadcom.com>
701
702 * cp1.c (Min, Max): Remove #if 0'd functions.
703 * sim-main.h (Min, Max): Remove.
704
e80fc152
CD		 7052002-06-03 Chris Demetriou <cgd@broadcom.com>
706
707 * cp1.c: fix formatting of switch case and default labels.
708 * interp.c: Likewise.
709 * sim-main.c: Likewise.
710
bad673a9
CD		 7112002-06-03 Chris Demetriou <cgd@broadcom.com>
712
713 * cp1.c: Clean up comments which describe FP formats.
714 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
715
7cbea089
CD		 7162002-06-03 Chris Demetriou <cgd@broadcom.com>
717 Ed Satterthwaite <ehs@broadcom.com>
718
719 * configure.in (mipsisa64sb1*-*-*): New target for supporting
720 Broadcom SiByte SB-1 processor configurations.
721 * configure: Regenerate.
722 * sb1.igen: New file.
723 * mips.igen: Include sb1.igen.
724 (sb1): New model.
725 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
726 * mdmx.igen: Add "sb1" model to all appropriate functions and
727 instructions.
728 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
729 (ob_func, ob_acc): Reference the above.
730 (qh_acc): Adjust to keep the same size as ob_acc.
731 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
732 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
733
909daa82
CD		 7342002-06-03 Chris Demetriou <cgd@broadcom.com>
735
736 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
737
f4f1b9f1
CD		 7382002-06-02 Chris Demetriou <cgd@broadcom.com>
739 Ed Satterthwaite <ehs@broadcom.com>
740
741 * mips.igen (mdmx): New (pseudo-)model.
742 * mdmx.c, mdmx.igen: New files.
743 * Makefile.in (SIM_OBJS): Add mdmx.o.
744 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
745 New typedefs.
746 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
747 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
748 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
749 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
750 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
751 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
752 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
753 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
754 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
755 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
756 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
757 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
758 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
759 (qh_fmtsel): New macros.
760 (_sim_cpu): New member "acc".
761 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
762 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
763
5accf1ff
CD		 7642002-05-01 Chris Demetriou <cgd@broadcom.com>
765
766 * interp.c: Use 'deprecated' rather than 'depreciated.'
767 * sim-main.h: Likewise.
768
402586aa
CD		 7692002-05-01 Chris Demetriou <cgd@broadcom.com>
770
771 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
772 which wouldn't compile anyway.
773 * sim-main.h (unpredictable_action): New function prototype.
774 (Unpredictable): Define to call igen function unpredictable().
775 (NotWordValue): New macro to call igen function not_word_value().
776 (UndefinedResult): Remove.
777 * interp.c (undefined_result): Remove.
778 (unpredictable_action): New function.
779 * mips.igen (not_word_value, unpredictable): New functions.
780 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
781 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
782 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
783 NotWordValue() to check for unpredictable inputs, then
784 Unpredictable() to handle them.
785
c9b9995a
CD		 7862002-02-24 Chris Demetriou <cgd@broadcom.com>
787
788 * mips.igen: Fix formatting of calls to Unpredictable().
789
e1015982
AC		 7902002-04-20 Andrew Cagney <ac131313@redhat.com>
791
792 * interp.c (sim_open): Revert previous change.
793
b882a66b
AO		 7942002-04-18 Alexandre Oliva <aoliva@redhat.com>
795
796 * interp.c (sim_open): Disable chunk of code that wrote code in
797 vector table entries.
798
c429b7dd
CD		 7992002-03-19 Chris Demetriou <cgd@broadcom.com>
800
801 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
802 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
803 unused definitions.
804
37d146fa
CD		 8052002-03-19 Chris Demetriou <cgd@broadcom.com>
806
807 * cp1.c: Fix many formatting issues.
808
07892c0b
CD		 8092002-03-19 Chris G. Demetriou <cgd@broadcom.com>
810
811 * cp1.c (fpu_format_name): New function to replace...
812 (DOFMT): This. Delete, and update all callers.
813 (fpu_rounding_mode_name): New function to replace...
814 (RMMODE): This. Delete, and update all callers.
815
487f79b7
CD		 8162002-03-19 Chris G. Demetriou <cgd@broadcom.com>
817
818 * interp.c: Move FPU support routines from here to...
819 * cp1.c: Here. New file.
820 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
821 (cp1.o): New target.
822
1e799e28
CD		 8232002-03-12 Chris Demetriou <cgd@broadcom.com>
824
825 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
826 * mips.igen (mips32, mips64): New models, add to all instructions
827 and functions as appropriate.
828 (loadstore_ea, check_u64): New variant for model mips64.
829 (check_fmt_p): New variant for models mipsV and mips64, remove
830 mipsV model marking fro other variant.
831 (SLL) Rename to...
832 (SLLa) this.
833 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
834 for mips32 and mips64.
835 (DCLO, DCLZ): New instructions for mips64.
836
82f728db
CD		 8372002-03-07 Chris Demetriou <cgd@broadcom.com>
838
839 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
840 immediate or code as a hex value with the "%#lx" format.
841 (ANDI): Likewise, and fix printed instruction name.
842
b96e7ef1
CD		 8432002-03-05 Chris Demetriou <cgd@broadcom.com>
844
845 * sim-main.h (UndefinedResult, Unpredictable): New macros
846 which currently do nothing.
847
d35d4f70
CD		 8482002-03-05 Chris Demetriou <cgd@broadcom.com>
849
850 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
851 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
852 (status_CU3): New definitions.
853
854 * sim-main.h (ExceptionCause): Add new values for MIPS32
855 and MIPS64: MDMX, MCheck, CacheErr. Update comments
856 for DebugBreakPoint and NMIReset to note their status in
857 MIPS32 and MIPS64.
858 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
859 (SignalExceptionCacheErr): New exception macros.
860
3ad6f714
CD		 8612002-03-05 Chris Demetriou <cgd@broadcom.com>
862
863 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
864 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
865 is always enabled.
866 (SignalExceptionCoProcessorUnusable): Take as argument the
867 unusable coprocessor number.
868
86b77b47
CD		 8692002-03-05 Chris Demetriou <cgd@broadcom.com>
870
871 * mips.igen: Fix formatting of all SignalException calls.
872
97a88e93 8732002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 874
875 * sim-main.h (SIGNEXTEND): Remove.
876
97a88e93 8772002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 878
879 * mips.igen: Remove gencode comment from top of file, fix
880 spelling in another comment.
881
97a88e93 8822002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 883
884 * mips.igen (check_fmt, check_fmt_p): New functions to check
885 whether specific floating point formats are usable.
886 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
887 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
888 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
889 Use the new functions.
890 (do_c_cond_fmt): Remove format checks...
891 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
892
97a88e93 8932002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 894
895 * mips.igen: Fix formatting of check_fpu calls.
896
41774c9d
CD		 8972002-03-03 Chris Demetriou <cgd@broadcom.com>
898
899 * mips.igen (FLOOR.L.fmt): Store correct destination register.
900
4a0bd876
CD		 9012002-03-03 Chris Demetriou <cgd@broadcom.com>
902
903 * mips.igen: Remove whitespace at end of lines.
904
09297648
CD		 9052002-03-02 Chris Demetriou <cgd@broadcom.com>
906
907 * mips.igen (loadstore_ea): New function to do effective
908 address calculations.
909 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
910 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
911 CACHE): Use loadstore_ea to do effective address computations.
912
043b7057
CD		 9132002-03-02 Chris Demetriou <cgd@broadcom.com>
914
915 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
916 * mips.igen (LL, CxC1, MxC1): Likewise.
917
c1e8ada4
CD		 9182002-03-02 Chris Demetriou <cgd@broadcom.com>
919
920 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
921 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
922 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
923 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
924 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
925 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
926 Don't split opcode fields by hand, use the opcode field values
927 provided by igen.
928
3e1dca16
CD		 9292002-03-01 Chris Demetriou <cgd@broadcom.com>
930
931 * mips.igen (do_divu): Fix spacing.
932
933 * mips.igen (do_dsllv): Move to be right before DSLLV,
934 to match the rest of the do_<shift> functions.
935
fff8d27d
CD		 9362002-03-01 Chris Demetriou <cgd@broadcom.com>
937
938 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
939 DSRL32, do_dsrlv): Trace inputs and results.
940
0d3e762b
CD		 9412002-03-01 Chris Demetriou <cgd@broadcom.com>
942
943 * mips.igen (CACHE): Provide instruction-printing string.
944
945 * interp.c (signal_exception): Comment tokens after #endif.
946
eb5fcf93
CD		 9472002-02-28 Chris Demetriou <cgd@broadcom.com>
948
949 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
950 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
951 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
952 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
953 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
954 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
955 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
956 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
957
bb22bd7d
CD		 9582002-02-28 Chris Demetriou <cgd@broadcom.com>
959
960 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
961 instruction-printing string.
962 (LWU): Use '64' as the filter flag.
963
91a177cf
CD		 9642002-02-28 Chris Demetriou <cgd@broadcom.com>
965
966 * mips.igen (SDXC1): Fix instruction-printing string.
967
387f484a
CD		 9682002-02-28 Chris Demetriou <cgd@broadcom.com>
969
970 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
971 filter flags "32,f".
972
3d81f391
CD		 9732002-02-27 Chris Demetriou <cgd@broadcom.com>
974
975 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
976 as the filter flag.
977
af5107af
CD		 9782002-02-27 Chris Demetriou <cgd@broadcom.com>
979
980 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
981 add a comma) so that it more closely match the MIPS ISA
982 documentation opcode partitioning.
983 (PREF): Put useful names on opcode fields, and include
984 instruction-printing string.
985
ca971540
CD		 9862002-02-27 Chris Demetriou <cgd@broadcom.com>
987
988 * mips.igen (check_u64): New function which in the future will
989 check whether 64-bit instructions are usable and signal an
990 exception if not. Currently a no-op.
991 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
992 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
993 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
994 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
995
996 * mips.igen (check_fpu): New function which in the future will
997 check whether FPU instructions are usable and signal an exception
998 if not. Currently a no-op.
999 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1000 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1001 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1002 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1003 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1004 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1005 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1006 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1007
1c47a468
CD		 10082002-02-27 Chris Demetriou <cgd@broadcom.com>
1009
1010 * mips.igen (do_load_left, do_load_right): Move to be immediately
1011 following do_load.
1012 (do_store_left, do_store_right): Move to be immediately following
1013 do_store.
1014
603a98e7
CD		 10152002-02-27 Chris Demetriou <cgd@broadcom.com>
1016
1017 * mips.igen (mipsV): New model name. Also, add it to
1018 all instructions and functions where it is appropriate.
1019
c5d00cc7
CD		 10202002-02-18 Chris Demetriou <cgd@broadcom.com>
1021
1022 * mips.igen: For all functions and instructions, list model
1023 names that support that instruction one per line.
1024
074e9cb8
CD		 10252002-02-11 Chris Demetriou <cgd@broadcom.com>
1026
1027 * mips.igen: Add some additional comments about supported
1028 models, and about which instructions go where.
1029 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1030 order as is used in the rest of the file.
1031
9805e229
CD		 10322002-02-11 Chris Demetriou <cgd@broadcom.com>
1033
1034 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1035 indicating that ALU32_END or ALU64_END are there to check
1036 for overflow.
1037 (DADD): Likewise, but also remove previous comment about
1038 overflow checking.
1039
f701dad2
CD		 10402002-02-10 Chris Demetriou <cgd@broadcom.com>
1041
1042 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1043 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1044 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1045 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1046 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1047 fields (i.e., add and move commas) so that they more closely
1048 match the MIPS ISA documentation opcode partitioning.
1049
10502002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 1051
1052 * mips.igen (ADDI): Print immediate value.
1053 (BREAK): Print code.
1054 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1055 (SLL): Print "nop" specially, and don't run the code
1056 that does the shift for the "nop" case.
1057
9e52972e
FF		 10582001-11-17 Fred Fish <fnf@redhat.com>
1059
1060 * sim-main.h (float_operation): Move enum declaration outside
1061 of _sim_cpu struct declaration.
1062
c0efbca4
JB		 10632001-04-12 Jim Blandy <jimb@redhat.com>
1064
1065 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1066 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1067 set of the FCSR.
1068 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1069 PENDING_FILL, and you can get the intended effect gracefully by
1070 calling PENDING_SCHED directly.
1071
fb891446
BE		 10722001-02-23 Ben Elliston <bje@redhat.com>
1073
1074 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1075 already defined elsewhere.
1076
8030f857
BE		 10772001-02-19 Ben Elliston <bje@redhat.com>
1078
1079 * sim-main.h (sim_monitor): Return an int.
1080 * interp.c (sim_monitor): Add return values.
1081 (signal_exception): Handle error conditions from sim_monitor.
1082
56b48a7a
CD		 10832001-02-08 Ben Elliston <bje@redhat.com>
1084
1085 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1086 (store_memory): Likewise, pass cia to sim_core_write*.
1087
d3ee60d9
FCE		 10882000-10-19 Frank Ch. Eigler <fche@redhat.com>
1089
1090 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1091 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1092
071da002
AC		 1093Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1094
1095 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1096 * Makefile.in: Don't delete *.igen when cleaning directory.
1097
a28c02cd
AC		 1098Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1099
1100 * m16.igen (break): Call SignalException not sim_engine_halt.
1101
80ee11fa
AC		 1102Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1103
1104 From Jason Eckhardt:
1105 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1106
673388c0
AC		 1107Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1108
1109 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1110
4c0deff4
NC		 11112000-05-24 Michael Hayes <mhayes@cygnus.com>
1112
1113 * mips.igen (do_dmultx): Fix typo.
1114
eb2d80b4
AC		 1115Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1116
1117 * configure: Regenerated to track ../common/aclocal.m4 changes.
1118
dd37a34b
AC		 1119Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1120
1121 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1122
4c0deff4
NC		 11232000-04-12 Frank Ch. Eigler <fche@redhat.com>
1124
1125 * sim-main.h (GPR_CLEAR): Define macro.
1126
e30db738
AC		 1127Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1128
1129 * interp.c (decode_coproc): Output long using %lx and not %s.
1130
cb7450ea
FCE		 11312000-03-21 Frank Ch. Eigler <fche@redhat.com>
1132
1133 * interp.c (sim_open): Sort & extend dummy memory regions for
1134 --board=jmr3904 for eCos.
1135
a3027dd7
FCE		 11362000-03-02 Frank Ch. Eigler <fche@redhat.com>
1137
1138 * configure: Regenerated.
1139
1140Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1141
1142 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1143 calls, conditional on the simulator being in verbose mode.
1144
dfcd3bfb
JM		 1145Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1146
1147 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1148 cache don't get ReservedInstruction traps.
1149
c2d11a7d
JM		 11501999-11-29 Mark Salter <msalter@cygnus.com>
1151
1152 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1153 to clear status bits in sdisr register. This is how the hardware works.
1154
1155 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1156 being used by cygmon.
1157
4ce44c66
JM		 11581999-11-11 Andrew Haley <aph@cygnus.com>
1159
1160 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1161 instructions.
1162
cff3e48b
JM		 1163Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1164
1165 * mips.igen (MULT): Correct previous mis-applied patch.
1166
d4f3574e
SS		 1167Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1168
1169 * mips.igen (delayslot32): Handle sequence like
1170 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1171 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1172 (MULT): Actually pass the third register...
1173
11741999-09-03 Mark Salter <msalter@cygnus.com>
1175
1176 * interp.c (sim_open): Added more memory aliases for additional
1177 hardware being touched by cygmon on jmr3904 board.
1178
1179Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1180
1181 * configure: Regenerated to track ../common/aclocal.m4 changes.
1182
a0b3c4fd
JM		 1183Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1184
1185 * interp.c (sim_store_register): Handle case where client - GDB -
1186 specifies that a 4 byte register is 8 bytes in size.
1187 (sim_fetch_register): Ditto.
1188
adf40b2e
JM		 11891999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1190
1191 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1192 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1193 (idt_monitor_base): Base address for IDT monitor traps.
1194 (pmon_monitor_base): Ditto for PMON.
1195 (lsipmon_monitor_base): Ditto for LSI PMON.
1196 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1197 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1198 (sim_firmware_command): New function.
1199 (mips_option_handler): Call it for OPTION_FIRMWARE.
1200 (sim_open): Allocate memory for idt_monitor region. If "--board"
1201 option was given, add no monitor by default. Add BREAK hooks only if
1202 monitors are also there.
1203
43e526b9
JM		 1204Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1205
1206 * interp.c (sim_monitor): Flush output before reading input.
1207
1208Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1209
1210 * tconfig.in (SIM_HANDLES_LMA): Always define.
1211
1212Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1213
1214 From Mark Salter <msalter@cygnus.com>:
1215 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1216 (sim_open): Add setup for BSP board.
1217
9846de1b
JM		 1218Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1219
1220 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1221 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1222 them as unimplemented.
1223
cd0fc7c3
SS		 12241999-05-08 Felix Lee <flee@cygnus.com>
1225
1226 * configure: Regenerated to track ../common/aclocal.m4 changes.
1227
7a292a7a
SS		 12281999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1229
1230 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1231
1232Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1233
1234 * configure.in: Any mips64vr5*-*-* target should have
1235 -DTARGET_ENABLE_FR=1.
1236 (default_endian): Any mips64vr*el-*-* target should default to
1237 LITTLE_ENDIAN.
1238 * configure: Re-generate.
1239
12401999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1241
1242 * mips.igen (ldl): Extend from _16_, not 32.
1243
1244Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1245
1246 * interp.c (sim_store_register): Force registers written to by GDB
1247 into an un-interpreted state.
1248
c906108c
SS		 12491999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1250
1251 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1252 CPU, start periodic background I/O polls.
1253 (tx3904sio_poll): New function: periodic I/O poller.
1254
12551998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1256
1257 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1258
1259Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1260
1261 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1262 case statement.
1263
12641998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1265
1266 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1267 (load_word): Call SIM_CORE_SIGNAL hook on error.
1268 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1269 starting. For exception dispatching, pass PC instead of NULL_CIA.
1270 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1271 * sim-main.h (COP0_BADVADDR): Define.
1272 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1273 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1274 (_sim_cpu): Add exc_* fields to store register value snapshots.
1275 * mips.igen (*): Replace memory-related SignalException* calls
1276 with references to SIM_CORE_SIGNAL hook.
1277
1278 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1279 fix.
1280 * sim-main.c (*): Minor warning cleanups.
1281
12821998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1283
1284 * m16.igen (DADDIU5): Correct type-o.
1285
1286Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1287
1288 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1289 variables.
1290
1291Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1292
1293 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1294 to include path.
1295 (interp.o): Add dependency on itable.h
1296 (oengine.c, gencode): Delete remaining references.
1297 (BUILT_SRC_FROM_GEN): Clean up.
1298
12991998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1300
1301 * vr4run.c: New.
1302 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1303 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1304 tmp-run-hack) : New.
1305 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1306 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1307 Drop the "64" qualifier to get the HACK generator working.
1308 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1309 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1310 qualifier to get the hack generator working.
1311 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1312 (DSLL): Use do_dsll.
1313 (DSLLV): Use do_dsllv.
1314 (DSRA): Use do_dsra.
1315 (DSRL): Use do_dsrl.
1316 (DSRLV): Use do_dsrlv.
1317 (BC1): Move *vr4100 to get the HACK generator working.
1318 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1319 get the HACK generator working.
1320 (MACC) Rename to get the HACK generator working.
1321 (DMACC,MACCS,DMACCS): Add the 64.
1322
13231998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1324
1325 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1326 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1327
13281998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1329
1330 * mips/interp.c (DEBUG): Cleanups.
1331
13321998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1333
1334 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1335 (tx3904sio_tickle): fflush after a stdout character output.
1336
13371998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1338
1339 * interp.c (sim_close): Uninstall modules.
1340
1341Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1342
1343 * sim-main.h, interp.c (sim_monitor): Change to global
1344 function.
1345
1346Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1347
1348 * configure.in (vr4100): Only include vr4100 instructions in
1349 simulator.
1350 * configure: Re-generate.
1351 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1352
1353Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1354
1355 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1356 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1357 true alternative.
1358
1359 * configure.in (sim_default_gen, sim_use_gen): Replace with
1360 sim_gen.
1361 (--enable-sim-igen): Delete config option. Always using IGEN.
1362 * configure: Re-generate.
1363
1364 * Makefile.in (gencode): Kill, kill, kill.
1365 * gencode.c: Ditto.
1366
1367Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1368
1369 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1370 bit mips16 igen simulator.
1371 * configure: Re-generate.
1372
1373 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1374 as part of vr4100 ISA.
1375 * vr.igen: Mark all instructions as 64 bit only.
1376
1377Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1378
1379 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1380 Pacify GCC.
1381
1382Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1383
1384 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1385 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1386 * configure: Re-generate.
1387
1388 * m16.igen (BREAK): Define breakpoint instruction.
1389 (JALX32): Mark instruction as mips16 and not r3900.
1390 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1391
1392 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1393
1394Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1395
1396 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1397 insn as a debug breakpoint.
1398
1399 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1400 pending.slot_size.
1401 (PENDING_SCHED): Clean up trace statement.
1402 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1403 (PENDING_FILL): Delay write by only one cycle.
1404 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1405
1406 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1407 of pending writes.
1408 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1409 32 & 64.
1410 (pending_tick): Move incrementing of index to FOR statement.
1411 (pending_tick): Only update PENDING_OUT after a write has occured.
1412
1413 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1414 build simulator.
1415 * configure: Re-generate.
1416
1417 * interp.c (sim_engine_run OLD): Delete explicit call to
1418 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1419
1420Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1421
1422 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1423 interrupt level number to match changed SignalExceptionInterrupt
1424 macro.
1425
1426Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1427
1428 * interp.c: #include "itable.h" if WITH_IGEN.
1429 (get_insn_name): New function.
1430 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1431 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1432
1433Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1434
1435 * configure: Rebuilt to inhale new common/aclocal.m4.
1436
1437Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1438
1439 * dv-tx3904sio.c: Include sim-assert.h.
1440
1441Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1442
1443 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1444 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1445 Reorganize target-specific sim-hardware checks.
1446 * configure: rebuilt.
1447 * interp.c (sim_open): For tx39 target boards, set
1448 OPERATING_ENVIRONMENT, add tx3904sio devices.
1449 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1450 ROM executables. Install dv-sockser into sim-modules list.
1451
1452 * dv-tx3904irc.c: Compiler warning clean-up.
1453 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1454 frequent hw-trace messages.
1455
1456Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1457
1458 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1459
1460Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1461
1462 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1463
1464 * vr.igen: New file.
1465 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1466 * mips.igen: Define vr4100 model. Include vr.igen.
1467Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1468
1469 * mips.igen (check_mf_hilo): Correct check.
1470
1471Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1472
1473 * sim-main.h (interrupt_event): Add prototype.
1474
1475 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1476 register_ptr, register_value.
1477 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1478
1479 * sim-main.h (tracefh): Make extern.
1480
1481Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1482
1483 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1484 Reduce unnecessarily high timer event frequency.
1485 * dv-tx3904cpu.c: Ditto for interrupt event.
1486
1487Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1488
1489 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1490 to allay warnings.
1491 (interrupt_event): Made non-static.
1492
1493 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1494 interchange of configuration values for external vs. internal
1495 clock dividers.
1496
1497Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1498
1499 * mips.igen (BREAK): Moved code to here for
1500 simulator-reserved break instructions.
1501 * gencode.c (build_instruction): Ditto.
1502 * interp.c (signal_exception): Code moved from here. Non-
1503 reserved instructions now use exception vector, rather
1504 than halting sim.
1505 * sim-main.h: Moved magic constants to here.
1506
1507Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1508
1509 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1510 register upon non-zero interrupt event level, clear upon zero
1511 event value.
1512 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1513 by passing zero event value.
1514 (*_io_{read,write}_buffer): Endianness fixes.
1515 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1516 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1517
1518 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1519 serial I/O and timer module at base address 0xFFFF0000.
1520
1521Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1522
1523 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1524 and BigEndianCPU.
1525
1526Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1527
1528 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1529 parts.
1530 * configure: Update.
1531
1532Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1533
1534 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1535 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1536 * configure.in: Include tx3904tmr in hw_device list.
1537 * configure: Rebuilt.
1538 * interp.c (sim_open): Instantiate three timer instances.
1539 Fix address typo of tx3904irc instance.
1540
1541Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1542
1543 * interp.c (signal_exception): SystemCall exception now uses
1544 the exception vector.
1545
1546Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1547
1548 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1549 to allay warnings.
1550
1551Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1552
1553 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1554
1555Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1556
1557 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1558
1559 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1560 sim-main.h. Declare a struct hw_descriptor instead of struct
1561 hw_device_descriptor.
1562
1563Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1564
1565 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1566 right bits and then re-align left hand bytes to correct byte
1567 lanes. Fix incorrect computation in do_store_left when loading
1568 bytes from second word.
1569
1570Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1571
1572 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1573 * interp.c (sim_open): Only create a device tree when HW is
1574 enabled.
1575
1576 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1577 * interp.c (signal_exception): Ditto.
1578
1579Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1580
1581 * gencode.c: Mark BEGEZALL as LIKELY.
1582
1583Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1584
1585 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1586 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1587
1588Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1589
1590 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1591 modules. Recognize TX39 target with "mips*tx39" pattern.
1592 * configure: Rebuilt.
1593 * sim-main.h (*): Added many macros defining bits in
1594 TX39 control registers.
1595 (SignalInterrupt): Send actual PC instead of NULL.
1596 (SignalNMIReset): New exception type.
1597 * interp.c (board): New variable for future use to identify
1598 a particular board being simulated.
1599 (mips_option_handler,mips_options): Added "--board" option.
1600 (interrupt_event): Send actual PC.
1601 (sim_open): Make memory layout conditional on board setting.
1602 (signal_exception): Initial implementation of hardware interrupt
1603 handling. Accept another break instruction variant for simulator
1604 exit.
1605 (decode_coproc): Implement RFE instruction for TX39.
1606 (mips.igen): Decode RFE instruction as such.
1607 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1608 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1609 bbegin to implement memory map.
1610 * dv-tx3904cpu.c: New file.
1611 * dv-tx3904irc.c: New file.
1612
1613Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1614
1615 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1616
1617Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1618
1619 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1620 with calls to check_div_hilo.
1621
1622Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1623
1624 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1625 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1626 Add special r3900 version of do_mult_hilo.
1627 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1628 with calls to check_mult_hilo.
1629 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1630 with calls to check_div_hilo.
1631
1632Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1633
1634 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1635 Document a replacement.
1636
1637Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1638
1639 * interp.c (sim_monitor): Make mon_printf work.
1640
1641Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1642
1643 * sim-main.h (INSN_NAME): New arg `cpu'.
1644
1645Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1646
1647 * configure: Regenerated to track ../common/aclocal.m4 changes.
1648
1649Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1650
1651 * configure: Regenerated to track ../common/aclocal.m4 changes.
1652 * config.in: Ditto.
1653
1654Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1655
1656 * acconfig.h: New file.
1657 * configure.in: Reverted change of Apr 24; use sinclude again.
1658
1659Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1660
1661 * configure: Regenerated to track ../common/aclocal.m4 changes.
1662 * config.in: Ditto.
1663
1664Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1665
1666 * configure.in: Don't call sinclude.
1667
1668Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1669
1670 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1671
1672Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1673
1674 * mips.igen (ERET): Implement.
1675
1676 * interp.c (decode_coproc): Return sign-extended EPC.
1677
1678 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1679
1680 * interp.c (signal_exception): Do not ignore Trap.
1681 (signal_exception): On TRAP, restart at exception address.
1682 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1683 (signal_exception): Update.
1684 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1685 so that TRAP instructions are caught.
1686
1687Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1688
1689 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1690 contains HI/LO access history.
1691 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1692 (HIACCESS, LOACCESS): Delete, replace with
1693 (HIHISTORY, LOHISTORY): New macros.
1694 (CHECKHILO): Delete all, moved to mips.igen
1695
1696 * gencode.c (build_instruction): Do not generate checks for
1697 correct HI/LO register usage.
1698
1699 * interp.c (old_engine_run): Delete checks for correct HI/LO
1700 register usage.
1701
1702 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1703 check_mf_cycles): New functions.
1704 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1705 do_divu, domultx, do_mult, do_multu): Use.
1706
1707 * tx.igen ("madd", "maddu"): Use.
1708
1709Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1710
1711 * mips.igen (DSRAV): Use function do_dsrav.
1712 (SRAV): Use new function do_srav.
1713
1714 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1715 (B): Sign extend 11 bit immediate.
1716 (EXT-B*): Shift 16 bit immediate left by 1.
1717 (ADDIU*): Don't sign extend immediate value.
1718
1719Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1720
1721 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1722
1723 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1724 functions.
1725
1726 * mips.igen (delayslot32, nullify_next_insn): New functions.
1727 (m16.igen): Always include.
1728 (do_*): Add more tracing.
1729
1730 * m16.igen (delayslot16): Add NIA argument, could be called by a
1731 32 bit MIPS16 instruction.
1732
1733 * interp.c (ifetch16): Move function from here.
1734 * sim-main.c (ifetch16): To here.
1735
1736 * sim-main.c (ifetch16, ifetch32): Update to match current
1737 implementations of LH, LW.
1738 (signal_exception): Don't print out incorrect hex value of illegal
1739 instruction.
1740
1741Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1742
1743 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1744 instruction.
1745
1746 * m16.igen: Implement MIPS16 instructions.
1747
1748 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1749 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1750 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1751 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1752 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1753 bodies of corresponding code from 32 bit insn to these. Also used
1754 by MIPS16 versions of functions.
1755
1756 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1757 (IMEM16): Drop NR argument from macro.
1758
1759Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1760
1761 * Makefile.in (SIM_OBJS): Add sim-main.o.
1762
1763 * sim-main.h (address_translation, load_memory, store_memory,
1764 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1765 as INLINE_SIM_MAIN.
1766 (pr_addr, pr_uword64): Declare.
1767 (sim-main.c): Include when H_REVEALS_MODULE_P.
1768
1769 * interp.c (address_translation, load_memory, store_memory,
1770 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1771 from here.
1772 * sim-main.c: To here. Fix compilation problems.
1773
1774 * configure.in: Enable inlining.
1775 * configure: Re-config.
1776
1777Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1778
1779 * configure: Regenerated to track ../common/aclocal.m4 changes.
1780
1781Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1782
1783 * mips.igen: Include tx.igen.
1784 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1785 * tx.igen: New file, contains MADD and MADDU.
1786
1787 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1788 the hardwired constant `7'.
1789 (store_memory): Ditto.
1790 (LOADDRMASK): Move definition to sim-main.h.
1791
1792 mips.igen (MTC0): Enable for r3900.
1793 (ADDU): Add trace.
1794
1795 mips.igen (do_load_byte): Delete.
1796 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1797 do_store_right): New functions.
1798 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1799
1800 configure.in: Let the tx39 use igen again.
1801 configure: Update.
1802
1803Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1804
1805 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1806 not an address sized quantity. Return zero for cache sizes.
1807
1808Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1809
1810 * mips.igen (r3900): r3900 does not support 64 bit integer
1811 operations.
1812
1813Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1814
1815 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1816 than igen one.
1817 * configure : Rebuild.
1818
1819Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1820
1821 * configure: Regenerated to track ../common/aclocal.m4 changes.
1822
1823Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1824
1825 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1826
1827Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1828
1829 * configure: Regenerated to track ../common/aclocal.m4 changes.
1830 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1831
1832Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1833
1834 * configure: Regenerated to track ../common/aclocal.m4 changes.
1835
1836Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1837
1838 * interp.c (Max, Min): Comment out functions. Not yet used.
1839
1840Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1841
1842 * configure: Regenerated to track ../common/aclocal.m4 changes.
1843
1844Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1845
1846 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1847 configurable settings for stand-alone simulator.
1848
1849 * configure.in: Added X11 search, just in case.
1850
1851 * configure: Regenerated.
1852
1853Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1854
1855 * interp.c (sim_write, sim_read, load_memory, store_memory):
1856 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1857
1858Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1859
1860 * sim-main.h (GETFCC): Return an unsigned value.
1861
1862Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1863
1864 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1865 (DADD): Result destination is RD not RT.
1866
1867Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1868
1869 * sim-main.h (HIACCESS, LOACCESS): Always define.
1870
1871 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1872
1873 * interp.c (sim_info): Delete.
1874
1875Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1876
1877 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1878 (mips_option_handler): New argument `cpu'.
1879 (sim_open): Update call to sim_add_option_table.
1880
1881Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1882
1883 * mips.igen (CxC1): Add tracing.
1884
1885Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1886
1887 * sim-main.h (Max, Min): Declare.
1888
1889 * interp.c (Max, Min): New functions.
1890
1891 * mips.igen (BC1): Add tracing.
1892
1893Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1894
1895 * interp.c Added memory map for stack in vr4100
1896
1897Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1898
1899 * interp.c (load_memory): Add missing "break"'s.
1900
1901Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1902
1903 * interp.c (sim_store_register, sim_fetch_register): Pass in
1904 length parameter. Return -1.
1905
1906Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1907
1908 * interp.c: Added hardware init hook, fixed warnings.
1909
1910Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1911
1912 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1913
1914Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1915
1916 * interp.c (ifetch16): New function.
1917
1918 * sim-main.h (IMEM32): Rename IMEM.
1919 (IMEM16_IMMED): Define.
1920 (IMEM16): Define.
1921 (DELAY_SLOT): Update.
1922
1923 * m16run.c (sim_engine_run): New file.
1924
1925 * m16.igen: All instructions except LB.
1926 (LB): Call do_load_byte.
1927 * mips.igen (do_load_byte): New function.
1928 (LB): Call do_load_byte.
1929
1930 * mips.igen: Move spec for insn bit size and high bit from here.
1931 * Makefile.in (tmp-igen, tmp-m16): To here.
1932
1933 * m16.dc: New file, decode mips16 instructions.
1934
1935 * Makefile.in (SIM_NO_ALL): Define.
1936 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1937
1938Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1939
1940 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1941 point unit to 32 bit registers.
1942 * configure: Re-generate.
1943
1944Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1945
1946 * configure.in (sim_use_gen): Make IGEN the default simulator
1947 generator for generic 32 and 64 bit mips targets.
1948 * configure: Re-generate.
1949
1950Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1951
1952 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1953 bitsize.
1954
1955 * interp.c (sim_fetch_register, sim_store_register): Read/write
1956 FGR from correct location.
1957 (sim_open): Set size of FGR's according to
1958 WITH_TARGET_FLOATING_POINT_BITSIZE.
1959
1960 * sim-main.h (FGR): Store floating point registers in a separate
1961 array.
1962
1963Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1964
1965 * configure: Regenerated to track ../common/aclocal.m4 changes.
1966
1967Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1968
1969 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1970
1971 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1972
1973 * interp.c (pending_tick): New function. Deliver pending writes.
1974
1975 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1976 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1977 it can handle mixed sized quantites and single bits.
1978
1979Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1980
1981 * interp.c (oengine.h): Do not include when building with IGEN.
1982 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1983 (sim_info): Ditto for PROCESSOR_64BIT.
1984 (sim_monitor): Replace ut_reg with unsigned_word.
1985 (*): Ditto for t_reg.
1986 (LOADDRMASK): Define.
1987 (sim_open): Remove defunct check that host FP is IEEE compliant,
1988 using software to emulate floating point.
1989 (value_fpr, ...): Always compile, was conditional on HASFPU.
1990
1991Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1992
1993 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1994 size.
1995
1996 * interp.c (SD, CPU): Define.
1997 (mips_option_handler): Set flags in each CPU.
1998 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1999 (sim_close): Do not clear STATE, deleted anyway.
2000 (sim_write, sim_read): Assume CPU zero's vm should be used for
2001 data transfers.
2002 (sim_create_inferior): Set the PC for all processors.
2003 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2004 argument.
2005 (mips16_entry): Pass correct nr of args to store_word, load_word.
2006 (ColdReset): Cold reset all cpu's.
2007 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2008 (sim_monitor, load_memory, store_memory, signal_exception): Use
2009 `CPU' instead of STATE_CPU.
2010
2011
2012 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2013 SD or CPU_.
2014
2015 * sim-main.h (signal_exception): Add sim_cpu arg.
2016 (SignalException*): Pass both SD and CPU to signal_exception.
2017 * interp.c (signal_exception): Update.
2018
2019 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2020 Ditto
2021 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2022 address_translation): Ditto
2023 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2024
2025Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2026
2027 * configure: Regenerated to track ../common/aclocal.m4 changes.
2028
2029Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2030
2031 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2032
2033 * mips.igen (model): Map processor names onto BFD name.
2034
2035 * sim-main.h (CPU_CIA): Delete.
2036 (SET_CIA, GET_CIA): Define
2037
2038Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2039
2040 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2041 regiser.
2042
2043 * configure.in (default_endian): Configure a big-endian simulator
2044 by default.
2045 * configure: Re-generate.
2046
2047Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2048
2049 * configure: Regenerated to track ../common/aclocal.m4 changes.
2050
2051Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2052
2053 * interp.c (sim_monitor): Handle Densan monitor outbyte
2054 and inbyte functions.
2055
20561997-12-29 Felix Lee <flee@cygnus.com>
2057
2058 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2059
2060Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2061
2062 * Makefile.in (tmp-igen): Arrange for $zero to always be
2063 reset to zero after every instruction.
2064
2065Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2066
2067 * configure: Regenerated to track ../common/aclocal.m4 changes.
2068 * config.in: Ditto.
2069
2070Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2071
2072 * mips.igen (MSUB): Fix to work like MADD.
2073 * gencode.c (MSUB): Similarly.
2074
2075Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2076
2077 * configure: Regenerated to track ../common/aclocal.m4 changes.
2078
2079Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2080
2081 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2082
2083Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2084
2085 * sim-main.h (sim-fpu.h): Include.
2086
2087 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2088 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2089 using host independant sim_fpu module.
2090
2091Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2092
2093 * interp.c (signal_exception): Report internal errors with SIGABRT
2094 not SIGQUIT.
2095
2096 * sim-main.h (C0_CONFIG): New register.
2097 (signal.h): No longer include.
2098
2099 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2100
2101Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2102
2103 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2104
2105Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2106
2107 * mips.igen: Tag vr5000 instructions.
2108 (ANDI): Was missing mipsIV model, fix assembler syntax.
2109 (do_c_cond_fmt): New function.
2110 (C.cond.fmt): Handle mips I-III which do not support CC field
2111 separatly.
2112 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2113 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2114 in IV3.2 spec.
2115 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2116 vr5000 which saves LO in a GPR separatly.
2117
2118 * configure.in (enable-sim-igen): For vr5000, select vr5000
2119 specific instructions.
2120 * configure: Re-generate.
2121
2122Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2123
2124 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2125
2126 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2127 fmt_uninterpreted_64 bit cases to switch. Convert to
2128 fmt_formatted,
2129
2130 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2131
2132 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2133 as specified in IV3.2 spec.
2134 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2135
2136Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2137
2138 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2139 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2140 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2141 PENDING_FILL versions of instructions. Simplify.
2142 (X): New function.
2143 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2144 instructions.
2145 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2146 a signed value.
2147 (MTHI, MFHI): Disable code checking HI-LO.
2148
2149 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2150 global.
2151 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2152
2153Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2154
2155 * gencode.c (build_mips16_operands): Replace IPC with cia.
2156
2157 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2158 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2159 IPC to `cia'.
2160 (UndefinedResult): Replace function with macro/function
2161 combination.
2162 (sim_engine_run): Don't save PC in IPC.
2163
2164 * sim-main.h (IPC): Delete.
2165
2166
2167 * interp.c (signal_exception, store_word, load_word,
2168 address_translation, load_memory, store_memory, cache_op,
2169 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2170 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2171 current instruction address - cia - argument.
2172 (sim_read, sim_write): Call address_translation directly.
2173 (sim_engine_run): Rename variable vaddr to cia.
2174 (signal_exception): Pass cia to sim_monitor
2175
2176 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2177 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2178 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2179
2180 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2181 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2182 SIM_ASSERT.
2183
2184 * interp.c (signal_exception): Pass restart address to
2185 sim_engine_restart.
2186
2187 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2188 idecode.o): Add dependency.
2189
2190 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2191 Delete definitions
2192 (DELAY_SLOT): Update NIA not PC with branch address.
2193 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2194
2195 * mips.igen: Use CIA not PC in branch calculations.
2196 (illegal): Call SignalException.
2197 (BEQ, ADDIU): Fix assembler.
2198
2199Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2200
2201 * m16.igen (JALX): Was missing.
2202
2203 * configure.in (enable-sim-igen): New configuration option.
2204 * configure: Re-generate.
2205
2206 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2207
2208 * interp.c (load_memory, store_memory): Delete parameter RAW.
2209 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2210 bypassing {load,store}_memory.
2211
2212 * sim-main.h (ByteSwapMem): Delete definition.
2213
2214 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2215
2216 * interp.c (sim_do_command, sim_commands): Delete mips specific
2217 commands. Handled by module sim-options.
2218
2219 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2220 (WITH_MODULO_MEMORY): Define.
2221
2222 * interp.c (sim_info): Delete code printing memory size.
2223
2224 * interp.c (mips_size): Nee sim_size, delete function.
2225 (power2): Delete.
2226 (monitor, monitor_base, monitor_size): Delete global variables.
2227 (sim_open, sim_close): Delete code creating monitor and other
2228 memory regions. Use sim-memopts module, via sim_do_commandf, to
2229 manage memory regions.
2230 (load_memory, store_memory): Use sim-core for memory model.
2231
2232 * interp.c (address_translation): Delete all memory map code
2233 except line forcing 32 bit addresses.
2234
2235Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2236
2237 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2238 trace options.
2239
2240 * interp.c (logfh, logfile): Delete globals.
2241 (sim_open, sim_close): Delete code opening & closing log file.
2242 (mips_option_handler): Delete -l and -n options.
2243 (OPTION mips_options): Ditto.
2244
2245 * interp.c (OPTION mips_options): Rename option trace to dinero.
2246 (mips_option_handler): Update.
2247
2248Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2249
2250 * interp.c (fetch_str): New function.
2251 (sim_monitor): Rewrite using sim_read & sim_write.
2252 (sim_open): Check magic number.
2253 (sim_open): Write monitor vectors into memory using sim_write.
2254 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2255 (sim_read, sim_write): Simplify - transfer data one byte at a
2256 time.
2257 (load_memory, store_memory): Clarify meaning of parameter RAW.
2258
2259 * sim-main.h (isHOST): Defete definition.
2260 (isTARGET): Mark as depreciated.
2261 (address_translation): Delete parameter HOST.
2262
2263 * interp.c (address_translation): Delete parameter HOST.
2264
2265Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2266
2267 * mips.igen:
2268
2269 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2270 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2271
2272Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2273
2274 * mips.igen: Add model filter field to records.
2275
2276Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2277
2278 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2279
2280 interp.c (sim_engine_run): Do not compile function sim_engine_run
2281 when WITH_IGEN == 1.
2282
2283 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2284 target architecture.
2285
2286 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2287 igen. Replace with configuration variables sim_igen_flags /
2288 sim_m16_flags.
2289
2290 * m16.igen: New file. Copy mips16 insns here.
2291 * mips.igen: From here.
2292
2293Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2294
2295 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2296 to top.
2297 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2298
2299Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2300
2301 * gencode.c (build_instruction): Follow sim_write's lead in using
2302 BigEndianMem instead of !ByteSwapMem.
2303
2304Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2305
2306 * configure.in (sim_gen): Dependent on target, select type of
2307 generator. Always select old style generator.
2308
2309 configure: Re-generate.
2310
2311 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2312 targets.
2313 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2314 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2315 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2316 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2317 SIM_@sim_gen@_*, set by autoconf.
2318
2319Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2320
2321 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2322
2323 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2324 CURRENT_FLOATING_POINT instead.
2325
2326 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2327 (address_translation): Raise exception InstructionFetch when
2328 translation fails and isINSTRUCTION.
2329
2330 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2331 sim_engine_run): Change type of of vaddr and paddr to
2332 address_word.
2333 (address_translation, prefetch, load_memory, store_memory,
2334 cache_op): Change type of vAddr and pAddr to address_word.
2335
2336 * gencode.c (build_instruction): Change type of vaddr and paddr to
2337 address_word.
2338
2339Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2340
2341 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2342 macro to obtain result of ALU op.
2343
2344Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2345
2346 * interp.c (sim_info): Call profile_print.
2347
2348Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2349
2350 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2351
2352 * sim-main.h (WITH_PROFILE): Do not define, defined in
2353 common/sim-config.h. Use sim-profile module.
2354 (simPROFILE): Delete defintion.
2355
2356 * interp.c (PROFILE): Delete definition.
2357 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2358 (sim_close): Delete code writing profile histogram.
2359 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2360 Delete.
2361 (sim_engine_run): Delete code profiling the PC.
2362
2363Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2364
2365 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2366
2367 * interp.c (sim_monitor): Make register pointers of type
2368 unsigned_word*.
2369
2370 * sim-main.h: Make registers of type unsigned_word not
2371 signed_word.
2372
2373Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2374
2375 * interp.c (sync_operation): Rename from SyncOperation, make
2376 global, add SD argument.
2377 (prefetch): Rename from Prefetch, make global, add SD argument.
2378 (decode_coproc): Make global.
2379
2380 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2381
2382 * gencode.c (build_instruction): Generate DecodeCoproc not
2383 decode_coproc calls.
2384
2385 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2386 (SizeFGR): Move to sim-main.h
2387 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2388 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2389 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2390 sim-main.h.
2391 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2392 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2393 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2394 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2395 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2396 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2397
2398 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2399 exception.
2400 (sim-alu.h): Include.
2401 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2402 (sim_cia): Typedef to instruction_address.
2403
2404Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2405
2406 * Makefile.in (interp.o): Rename generated file engine.c to
2407 oengine.c.
2408
2409 * interp.c: Update.
2410
2411Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2412
2413 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2414
2415Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2416
2417 * gencode.c (build_instruction): For "FPSQRT", output correct
2418 number of arguments to Recip.
2419
2420Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2421
2422 * Makefile.in (interp.o): Depends on sim-main.h
2423
2424 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2425
2426 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2427 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2428 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2429 STATE, DSSTATE): Define
2430 (GPR, FGRIDX, ..): Define.
2431
2432 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2433 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2434 (GPR, FGRIDX, ...): Delete macros.
2435
2436 * interp.c: Update names to match defines from sim-main.h
2437
2438Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2439
2440 * interp.c (sim_monitor): Add SD argument.
2441 (sim_warning): Delete. Replace calls with calls to
2442 sim_io_eprintf.
2443 (sim_error): Delete. Replace calls with sim_io_error.
2444 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2445 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2446 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2447 argument.
2448 (mips_size): Rename from sim_size. Add SD argument.
2449
2450 * interp.c (simulator): Delete global variable.
2451 (callback): Delete global variable.
2452 (mips_option_handler, sim_open, sim_write, sim_read,
2453 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2454 sim_size,sim_monitor): Use sim_io_* not callback->*.
2455 (sim_open): ZALLOC simulator struct.
2456 (PROFILE): Do not define.
2457
2458Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2459
2460 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2461 support.h with corresponding code.
2462
2463 * sim-main.h (word64, uword64), support.h: Move definition to
2464 sim-main.h.
2465 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2466
2467 * support.h: Delete
2468 * Makefile.in: Update dependencies
2469 * interp.c: Do not include.
2470
2471Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2472
2473 * interp.c (address_translation, load_memory, store_memory,
2474 cache_op): Rename to from AddressTranslation et.al., make global,
2475 add SD argument
2476
2477 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2478 CacheOp): Define.
2479
2480 * interp.c (SignalException): Rename to signal_exception, make
2481 global.
2482
2483 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2484
2485 * sim-main.h (SignalException, SignalExceptionInterrupt,
2486 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2487 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2488 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2489 Define.
2490
2491 * interp.c, support.h: Use.
2492
2493Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2494
2495 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2496 to value_fpr / store_fpr. Add SD argument.
2497 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2498 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2499
2500 * sim-main.h (ValueFPR, StoreFPR): Define.
2501
2502Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2503
2504 * interp.c (sim_engine_run): Check consistency between configure
2505 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2506 and HASFPU.
2507
2508 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2509 (mips_fpu): Configure WITH_FLOATING_POINT.
2510 (mips_endian): Configure WITH_TARGET_ENDIAN.
2511 * configure: Update.
2512
2513Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2514
2515 * configure: Regenerated to track ../common/aclocal.m4 changes.
2516
2517Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2518
2519 * configure: Regenerated.
2520
2521Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2522
2523 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2524
2525Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2526
2527 * gencode.c (print_igen_insn_models): Assume certain architectures
2528 include all mips* instructions.
2529 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2530 instruction.
2531
2532 * Makefile.in (tmp.igen): Add target. Generate igen input from
2533 gencode file.
2534
2535 * gencode.c (FEATURE_IGEN): Define.
2536 (main): Add --igen option. Generate output in igen format.
2537 (process_instructions): Format output according to igen option.
2538 (print_igen_insn_format): New function.
2539 (print_igen_insn_models): New function.
2540 (process_instructions): Only issue warnings and ignore
2541 instructions when no FEATURE_IGEN.
2542
2543Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2544
2545 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2546 MIPS targets.
2547
2548Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2549
2550 * configure: Regenerated to track ../common/aclocal.m4 changes.
2551
2552Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2553
2554 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2555 SIM_RESERVED_BITS): Delete, moved to common.
2556 (SIM_EXTRA_CFLAGS): Update.
2557
2558Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2559
2560 * configure.in: Configure non-strict memory alignment.
2561 * configure: Regenerated to track ../common/aclocal.m4 changes.
2562
2563Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2564
2565 * configure: Regenerated to track ../common/aclocal.m4 changes.
2566
2567Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2568
2569 * gencode.c (SDBBP,DERET): Added (3900) insns.
2570 (RFE): Turn on for 3900.
2571 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2572 (dsstate): Made global.
2573 (SUBTARGET_R3900): Added.
2574 (CANCELDELAYSLOT): New.
2575 (SignalException): Ignore SystemCall rather than ignore and
2576 terminate. Add DebugBreakPoint handling.
2577 (decode_coproc): New insns RFE, DERET; and new registers Debug
2578 and DEPC protected by SUBTARGET_R3900.
2579 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2580 bits explicitly.
2581 * Makefile.in,configure.in: Add mips subtarget option.
2582 * configure: Update.
2583
2584Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2585
2586 * gencode.c: Add r3900 (tx39).
2587
2588
2589Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2590
2591 * gencode.c (build_instruction): Don't need to subtract 4 for
2592 JALR, just 2.
2593
2594Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2595
2596 * interp.c: Correct some HASFPU problems.
2597
2598Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2599
2600 * configure: Regenerated to track ../common/aclocal.m4 changes.
2601
2602Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2603
2604 * interp.c (mips_options): Fix samples option short form, should
2605 be `x'.
2606
2607Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2608
2609 * interp.c (sim_info): Enable info code. Was just returning.
2610
2611Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2612
2613 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2614 MFC0.
2615
2616Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2617
2618 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2619 constants.
2620 (build_instruction): Ditto for LL.
2621
2622Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2623
2624 * configure: Regenerated to track ../common/aclocal.m4 changes.
2625
2626Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2627
2628 * configure: Regenerated to track ../common/aclocal.m4 changes.
2629 * config.in: Ditto.
2630
2631Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2632
2633 * interp.c (sim_open): Add call to sim_analyze_program, update
2634 call to sim_config.
2635
2636Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2637
2638 * interp.c (sim_kill): Delete.
2639 (sim_create_inferior): Add ABFD argument. Set PC from same.
2640 (sim_load): Move code initializing trap handlers from here.
2641 (sim_open): To here.
2642 (sim_load): Delete, use sim-hload.c.
2643
2644 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2645
2646Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2647
2648 * configure: Regenerated to track ../common/aclocal.m4 changes.
2649 * config.in: Ditto.
2650
2651Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2652
2653 * interp.c (sim_open): Add ABFD argument.
2654 (sim_load): Move call to sim_config from here.
2655 (sim_open): To here. Check return status.
2656
2657Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2658
2659 * gencode.c (build_instruction): Two arg MADD should
2660 not assign result to $0.
2661
2662Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2663
2664 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2665 * sim/mips/configure.in: Regenerate.
2666
2667Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2668
2669 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2670 signed8, unsigned8 et.al. types.
2671
2672 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2673 hosts when selecting subreg.
2674
2675Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2676
2677 * interp.c (sim_engine_run): Reset the ZERO register to zero
2678 regardless of FEATURE_WARN_ZERO.
2679 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2680
2681Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2682
2683 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2684 (SignalException): For BreakPoints ignore any mode bits and just
2685 save the PC.
2686 (SignalException): Always set the CAUSE register.
2687
2688Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2689
2690 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2691 exception has been taken.
2692
2693 * interp.c: Implement the ERET and mt/f sr instructions.
2694
2695Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2696
2697 * interp.c (SignalException): Don't bother restarting an
2698 interrupt.
2699
2700Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2701
2702 * interp.c (SignalException): Really take an interrupt.
2703 (interrupt_event): Only deliver interrupts when enabled.
2704
2705Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2706
2707 * interp.c (sim_info): Only print info when verbose.
2708 (sim_info) Use sim_io_printf for output.
2709
2710Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2711
2712 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2713 mips architectures.
2714
2715Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2716
2717 * interp.c (sim_do_command): Check for common commands if a
2718 simulator specific command fails.
2719
2720Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2721
2722 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2723 and simBE when DEBUG is defined.
2724
2725Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2726
2727 * interp.c (interrupt_event): New function. Pass exception event
2728 onto exception handler.
2729
2730 * configure.in: Check for stdlib.h.
2731 * configure: Regenerate.
2732
2733 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2734 variable declaration.
2735 (build_instruction): Initialize memval1.
2736 (build_instruction): Add UNUSED attribute to byte, bigend,
2737 reverse.
2738 (build_operands): Ditto.
2739
2740 * interp.c: Fix GCC warnings.
2741 (sim_get_quit_code): Delete.
2742
2743 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2744 * Makefile.in: Ditto.
2745 * configure: Re-generate.
2746
2747 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2748
2749Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2750
2751 * interp.c (mips_option_handler): New function parse argumes using
2752 sim-options.
2753 (myname): Replace with STATE_MY_NAME.
2754 (sim_open): Delete check for host endianness - performed by
2755 sim_config.
2756 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2757 (sim_open): Move much of the initialization from here.
2758 (sim_load): To here. After the image has been loaded and
2759 endianness set.
2760 (sim_open): Move ColdReset from here.
2761 (sim_create_inferior): To here.
2762 (sim_open): Make FP check less dependant on host endianness.
2763
2764 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2765 run.
2766 * interp.c (sim_set_callbacks): Delete.
2767
2768 * interp.c (membank, membank_base, membank_size): Replace with
2769 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2770 (sim_open): Remove call to callback->init. gdb/run do this.
2771
2772 * interp.c: Update
2773
2774 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2775
2776 * interp.c (big_endian_p): Delete, replaced by
2777 current_target_byte_order.
2778
2779Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2780
2781 * interp.c (host_read_long, host_read_word, host_swap_word,
2782 host_swap_long): Delete. Using common sim-endian.
2783 (sim_fetch_register, sim_store_register): Use H2T.
2784 (pipeline_ticks): Delete. Handled by sim-events.
2785 (sim_info): Update.
2786 (sim_engine_run): Update.
2787
2788Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2789
2790 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2791 reason from here.
2792 (SignalException): To here. Signal using sim_engine_halt.
2793 (sim_stop_reason): Delete, moved to common.
2794
2795Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2796
2797 * interp.c (sim_open): Add callback argument.
2798 (sim_set_callbacks): Delete SIM_DESC argument.
2799 (sim_size): Ditto.
2800
2801Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2802
2803 * Makefile.in (SIM_OBJS): Add common modules.
2804
2805 * interp.c (sim_set_callbacks): Also set SD callback.
2806 (set_endianness, xfer_*, swap_*): Delete.
2807 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2808 Change to functions using sim-endian macros.
2809 (control_c, sim_stop): Delete, use common version.
2810 (simulate): Convert into.
2811 (sim_engine_run): This function.
2812 (sim_resume): Delete.
2813
2814 * interp.c (simulation): New variable - the simulator object.
2815 (sim_kind): Delete global - merged into simulation.
2816 (sim_load): Cleanup. Move PC assignment from here.
2817 (sim_create_inferior): To here.
2818
2819 * sim-main.h: New file.
2820 * interp.c (sim-main.h): Include.
2821
2822Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2823
2824 * configure: Regenerated to track ../common/aclocal.m4 changes.
2825
2826Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2827
2828 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2829
2830Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2831
2832 * gencode.c (build_instruction): DIV instructions: check
2833 for division by zero and integer overflow before using
2834 host's division operation.
2835
2836Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2837
2838 * Makefile.in (SIM_OBJS): Add sim-load.o.
2839 * interp.c: #include bfd.h.
2840 (target_byte_order): Delete.
2841 (sim_kind, myname, big_endian_p): New static locals.
2842 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2843 after argument parsing. Recognize -E arg, set endianness accordingly.
2844 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2845 load file into simulator. Set PC from bfd.
2846 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2847 (set_endianness): Use big_endian_p instead of target_byte_order.
2848
2849Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2850
2851 * interp.c (sim_size): Delete prototype - conflicts with
2852 definition in remote-sim.h. Correct definition.
2853
2854Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2855
2856 * configure: Regenerated to track ../common/aclocal.m4 changes.
2857 * config.in: Ditto.
2858
2859Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2860
2861 * interp.c (sim_open): New arg `kind'.
2862
2863 * configure: Regenerated to track ../common/aclocal.m4 changes.
2864
2865Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2866
2867 * configure: Regenerated to track ../common/aclocal.m4 changes.
2868
2869Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2870
2871 * interp.c (sim_open): Set optind to 0 before calling getopt.
2872
2873Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2874
2875 * configure: Regenerated to track ../common/aclocal.m4 changes.
2876
2877Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2878
2879 * interp.c : Replace uses of pr_addr with pr_uword64
2880 where the bit length is always 64 independent of SIM_ADDR.
2881 (pr_uword64) : added.
2882
2883Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2884
2885 * configure: Re-generate.
2886
2887Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2888
2889 * configure: Regenerate to track ../common/aclocal.m4 changes.
2890
2891Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2892
2893 * interp.c (sim_open): New SIM_DESC result. Argument is now
2894 in argv form.
2895 (other sim_*): New SIM_DESC argument.
2896
2897Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2898
2899 * interp.c: Fix printing of addresses for non-64-bit targets.
2900 (pr_addr): Add function to print address based on size.
2901
2902Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2903
2904 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2905
2906Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2907
2908 * gencode.c (build_mips16_operands): Correct computation of base
2909 address for extended PC relative instruction.
2910
2911Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2912
2913 * interp.c (mips16_entry): Add support for floating point cases.
2914 (SignalException): Pass floating point cases to mips16_entry.
2915 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2916 registers.
2917 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2918 or fmt_word.
2919 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2920 and then set the state to fmt_uninterpreted.
2921 (COP_SW): Temporarily set the state to fmt_word while calling
2922 ValueFPR.
2923
2924Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2925
2926 * gencode.c (build_instruction): The high order may be set in the
2927 comparison flags at any ISA level, not just ISA 4.
2928
2929Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2930
2931 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2932 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2933 * configure.in: sinclude ../common/aclocal.m4.
2934 * configure: Regenerated.
2935
2936Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2937
2938 * configure: Rebuild after change to aclocal.m4.
2939
2940Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2941
2942 * configure configure.in Makefile.in: Update to new configure
2943 scheme which is more compatible with WinGDB builds.
2944 * configure.in: Improve comment on how to run autoconf.
2945 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2946 * Makefile.in: Use autoconf substitution to install common
2947 makefile fragment.
2948
2949Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2950
2951 * gencode.c (build_instruction): Use BigEndianCPU instead of
2952 ByteSwapMem.
2953
2954Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2955
2956 * interp.c (sim_monitor): Make output to stdout visible in
2957 wingdb's I/O log window.
2958
2959Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2960
2961 * support.h: Undo previous change to SIGTRAP
2962 and SIGQUIT values.
2963
2964Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2965
2966 * interp.c (store_word, load_word): New static functions.
2967 (mips16_entry): New static function.
2968 (SignalException): Look for mips16 entry and exit instructions.
2969 (simulate): Use the correct index when setting fpr_state after
2970 doing a pending move.
2971
2972Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2973
2974 * interp.c: Fix byte-swapping code throughout to work on
2975 both little- and big-endian hosts.
2976
2977Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2978
2979 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2980 with gdb/config/i386/xm-windows.h.
2981
2982Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2983
2984 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2985 that messes up arithmetic shifts.
2986
2987Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2988
2989 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2990 SIGTRAP and SIGQUIT for _WIN32.
2991
2992Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2993
2994 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2995 force a 64 bit multiplication.
2996 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2997 destination register is 0, since that is the default mips16 nop
2998 instruction.
2999
3000Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3001
3002 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3003 (build_endian_shift): Don't check proc64.
3004 (build_instruction): Always set memval to uword64. Cast op2 to
3005 uword64 when shifting it left in memory instructions. Always use
3006 the same code for stores--don't special case proc64.
3007
3008 * gencode.c (build_mips16_operands): Fix base PC value for PC
3009 relative operands.
3010 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3011 jal instruction.
3012 * interp.c (simJALDELAYSLOT): Define.
3013 (JALDELAYSLOT): Define.
3014 (INDELAYSLOT, INJALDELAYSLOT): Define.
3015 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3016
3017Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3018
3019 * interp.c (sim_open): add flush_cache as a PMON routine
3020 (sim_monitor): handle flush_cache by ignoring it
3021
3022Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3023
3024 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3025 BigEndianMem.
3026 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3027 (BigEndianMem): Rename to ByteSwapMem and change sense.
3028 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3029 BigEndianMem references to !ByteSwapMem.
3030 (set_endianness): New function, with prototype.
3031 (sim_open): Call set_endianness.
3032 (sim_info): Use simBE instead of BigEndianMem.
3033 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3034 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3035 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3036 ifdefs, keeping the prototype declaration.
3037 (swap_word): Rewrite correctly.
3038 (ColdReset): Delete references to CONFIG. Delete endianness related
3039 code; moved to set_endianness.
3040
3041Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3042
3043 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3044 * interp.c (CHECKHILO): Define away.
3045 (simSIGINT): New macro.
3046 (membank_size): Increase from 1MB to 2MB.
3047 (control_c): New function.
3048 (sim_resume): Rename parameter signal to signal_number. Add local
3049 variable prev. Call signal before and after simulate.
3050 (sim_stop_reason): Add simSIGINT support.
3051 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3052 functions always.
3053 (sim_warning): Delete call to SignalException. Do call printf_filtered
3054 if logfh is NULL.
3055 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3056 a call to sim_warning.
3057
3058Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3059
3060 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3061 16 bit instructions.
3062
3063Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3064
3065 Add support for mips16 (16 bit MIPS implementation):
3066 * gencode.c (inst_type): Add mips16 instruction encoding types.
3067 (GETDATASIZEINSN): Define.
3068 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3069 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3070 mtlo.
3071 (MIPS16_DECODE): New table, for mips16 instructions.
3072 (bitmap_val): New static function.
3073 (struct mips16_op): Define.
3074 (mips16_op_table): New table, for mips16 operands.
3075 (build_mips16_operands): New static function.
3076 (process_instructions): If PC is odd, decode a mips16
3077 instruction. Break out instruction handling into new
3078 build_instruction function.
3079 (build_instruction): New static function, broken out of
3080 process_instructions. Check modifiers rather than flags for SHIFT
3081 bit count and m[ft]{hi,lo} direction.
3082 (usage): Pass program name to fprintf.
3083 (main): Remove unused variable this_option_optind. Change
3084 ``*loptarg++'' to ``loptarg++''.
3085 (my_strtoul): Parenthesize && within ||.
3086 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3087 (simulate): If PC is odd, fetch a 16 bit instruction, and
3088 increment PC by 2 rather than 4.
3089 * configure.in: Add case for mips16*-*-*.
3090 * configure: Rebuild.
3091
3092Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3093
3094 * interp.c: Allow -t to enable tracing in standalone simulator.
3095 Fix garbage output in trace file and error messages.
3096
3097Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3098
3099 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3100 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3101 * configure.in: Simplify using macros in ../common/aclocal.m4.
3102 * configure: Regenerated.
3103 * tconfig.in: New file.
3104
3105Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3106
3107 * interp.c: Fix bugs in 64-bit port.
3108 Use ansi function declarations for msvc compiler.
3109 Initialize and test file pointer in trace code.
3110 Prevent duplicate definition of LAST_EMED_REGNUM.
3111
3112Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3113
3114 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3115
3116Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3117
3118 * interp.c (SignalException): Check for explicit terminating
3119 breakpoint value.
3120 * gencode.c: Pass instruction value through SignalException()
3121 calls for Trap, Breakpoint and Syscall.
3122
3123Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3124
3125 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3126 only used on those hosts that provide it.
3127 * configure.in: Add sqrt() to list of functions to be checked for.
3128 * config.in: Re-generated.
3129 * configure: Re-generated.
3130
3131Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3132
3133 * gencode.c (process_instructions): Call build_endian_shift when
3134 expanding STORE RIGHT, to fix swr.
3135 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3136 clear the high bits.
3137 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3138 Fix float to int conversions to produce signed values.
3139
3140Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3141
3142 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3143 (process_instructions): Correct handling of nor instruction.
3144 Correct shift count for 32 bit shift instructions. Correct sign
3145 extension for arithmetic shifts to not shift the number of bits in
3146 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3147 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3148 Fix madd.
3149 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3150 It's OK to have a mult follow a mult. What's not OK is to have a
3151 mult follow an mfhi.
3152 (Convert): Comment out incorrect rounding code.
3153
3154Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3155
3156 * interp.c (sim_monitor): Improved monitor printf
3157 simulation. Tidied up simulator warnings, and added "--log" option
3158 for directing warning message output.
3159 * gencode.c: Use sim_warning() rather than WARNING macro.
3160
3161Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3162
3163 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3164 getopt1.o, rather than on gencode.c. Link objects together.
3165 Don't link against -liberty.
3166 (gencode.o, getopt.o, getopt1.o): New targets.
3167 * gencode.c: Include <ctype.h> and "ansidecl.h".
3168 (AND): Undefine after including "ansidecl.h".
3169 (ULONG_MAX): Define if not defined.
3170 (OP_*): Don't define macros; now defined in opcode/mips.h.
3171 (main): Call my_strtoul rather than strtoul.
3172 (my_strtoul): New static function.
3173
3174Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3175
3176 * gencode.c (process_instructions): Generate word64 and uword64
3177 instead of `long long' and `unsigned long long' data types.
3178 * interp.c: #include sysdep.h to get signals, and define default
3179 for SIGBUS.
3180 * (Convert): Work around for Visual-C++ compiler bug with type
3181 conversion.
3182 * support.h: Make things compile under Visual-C++ by using
3183 __int64 instead of `long long'. Change many refs to long long
3184 into word64/uword64 typedefs.
3185
3186Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3187
3188 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3189 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3190 (docdir): Removed.
3191 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3192 (AC_PROG_INSTALL): Added.
3193 (AC_PROG_CC): Moved to before configure.host call.
3194 * configure: Rebuilt.
3195
3196Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3197
3198 * configure.in: Define @SIMCONF@ depending on mips target.
3199 * configure: Rebuild.
3200 * Makefile.in (run): Add @SIMCONF@ to control simulator
3201 construction.
3202 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3203 * interp.c: Remove some debugging, provide more detailed error
3204 messages, update memory accesses to use LOADDRMASK.
3205
3206Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3207
3208 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3209 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3210 stamp-h.
3211 * configure: Rebuild.
3212 * config.in: New file, generated by autoheader.
3213 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3214 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3215 HAVE_ANINT and HAVE_AINT, as appropriate.
3216 * Makefile.in (run): Use @LIBS@ rather than -lm.
3217 (interp.o): Depend upon config.h.
3218 (Makefile): Just rebuild Makefile.
3219 (clean): Remove stamp-h.
3220 (mostlyclean): Make the same as clean, not as distclean.
3221 (config.h, stamp-h): New targets.
3222
3223Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3224
3225 * interp.c (ColdReset): Fix boolean test. Make all simulator
3226 globals static.
3227
3228Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3229
3230 * interp.c (xfer_direct_word, xfer_direct_long,
3231 swap_direct_word, swap_direct_long, xfer_big_word,
3232 xfer_big_long, xfer_little_word, xfer_little_long,
3233 swap_word,swap_long): Added.
3234 * interp.c (ColdReset): Provide function indirection to
3235 host<->simulated_target transfer routines.
3236 * interp.c (sim_store_register, sim_fetch_register): Updated to
3237 make use of indirected transfer routines.
3238
3239Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3240
3241 * gencode.c (process_instructions): Ensure FP ABS instruction
3242 recognised.
3243 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3244 system call support.
3245
3246Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3247
3248 * interp.c (sim_do_command): Complain if callback structure not
3249 initialised.
3250
3251Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3252
3253 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3254 support for Sun hosts.
3255 * Makefile.in (gencode): Ensure the host compiler and libraries
3256 used for cross-hosted build.
3257
3258Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3259
3260 * interp.c, gencode.c: Some more (TODO) tidying.
3261
3262Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3263
3264 * gencode.c, interp.c: Replaced explicit long long references with
3265 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3266 * support.h (SET64LO, SET64HI): Macros added.
3267
3268Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3269
3270 * configure: Regenerate with autoconf 2.7.
3271
3272Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3273
3274 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3275 * support.h: Remove superfluous "1" from #if.
3276 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3277
3278Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3279
3280 * interp.c (StoreFPR): Control UndefinedResult() call on
3281 WARN_RESULT manifest.
3282
3283Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3284
3285 * gencode.c: Tidied instruction decoding, and added FP instruction
3286 support.
3287
3288 * interp.c: Added dineroIII, and BSD profiling support. Also
3289 run-time FP handling.
3290
3291Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3292
3293 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3294 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
This page took 0.62823 seconds and 4 git commands to generate.