projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sim: mcore: fix build time warnings
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
4df817de
MF		 12021-05-04 Mike Frysinger <vapier@gentoo.org>
2
3 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
4
aa0fca16
MF		 52021-05-04 Mike Frysinger <vapier@gentoo.org>
6
7 * configure: Regenerate.
8
adbaa7b8
MF		 92021-05-01 Mike Frysinger <vapier@gentoo.org>
10
11 * cp1.c (store_fcr): Mark static.
12
fe348617
MF		 132021-05-01 Mike Frysinger <vapier@gentoo.org>
14
15 * config.in, configure: Regenerate.
16
9d903352
MF		 172021-04-23 Mike Frysinger <vapier@gentoo.org>
18
19 * configure.ac (hw_enabled): Delete.
20 (SIM_AC_OPTION_HARDWARE): Delete first two args.
21 * configure: Regenerate.
22
19f6a43c
TT		 232021-04-22 Tom Tromey <tom@tromey.com>
24
25 * configure, config.in: Rebuild.
26
e7d8f1da
TT		 272021-04-22 Tom Tromey <tom@tromey.com>
28
29 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
30 Remove.
31 (SIM_EXTRA_DEPS): New variable.
32
efd82ac7
TT		 332021-04-22 Tom Tromey <tom@tromey.com>
34
35 * configure: Rebuild.
36
2662c237
MF		 372021-04-21 Mike Frysinger <vapier@gentoo.org>
38
39 * aclocal.m4: Regenerate.
40
1f195bc3
SM		 412021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
42
43 * configure: Regenerate.
44
37e9f182
MF		 452021-04-18 Mike Frysinger <vapier@gentoo.org>
46
47 * configure: Regenerate.
48
d5a71b11
MF		 492021-04-12 Mike Frysinger <vapier@gentoo.org>
50
51 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
52
2b8d134b
SM		 532021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
54
55 * Makefile.in: Set ASAN_OPTIONS when running igen.
56
5c6f091a
FS		 572021-04-04 Steve Ellcey <sellcey@mips.com>
58 Faraz Shahbazker <fshahbazker@wavecomp.com>
59
60 * interp.c (sim_monitor): Add switch entries for unlink (13),
61 lseek (14), and stat (15).
62
b6b1c790
MF		 632021-04-02 Mike Frysinger <vapier@gentoo.org>
64
65 * Makefile.in (../igen/igen): Delete rule.
66 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
67
c2783492
MF		 682021-04-02 Mike Frysinger <vapier@gentoo.org>
69
70 * aclocal.m4, configure: Regenerate.
71
ebe9564b
MF		 722021-02-28 Mike Frysinger <vapier@gentoo.org>
73
74 * configure: Regenerate.
75
f8069d55
MF		 762021-02-27 Mike Frysinger <vapier@gentoo.org>
77
78 * Makefile.in (SIM_EXTRA_ALL): Delete.
79 (all): New target.
80
760b3e8b
MF		 812021-02-21 Mike Frysinger <vapier@gentoo.org>
82
83 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
84 * aclocal.m4, configure: Regenerate.
85
136da8cd
MF		 862021-02-13 Mike Frysinger <vapier@gentoo.org>
87
88 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
89 * aclocal.m4, configure: Regenerate.
90
4c0d76b9
MF		 912021-02-06 Mike Frysinger <vapier@gentoo.org>
92
93 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
94
aa09469f
MF		 952021-02-06 Mike Frysinger <vapier@gentoo.org>
96
97 * configure: Regenerate.
98
d4e3adda
MF		 992021-01-30 Mike Frysinger <vapier@gentoo.org>
100
101 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
102
68ed2854
MF		 1032021-01-11 Mike Frysinger <vapier@gentoo.org>
104
105 * config.in, configure: Regenerate.
106 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
107 and strings.h include.
108
50df264d
MF		 1092021-01-09 Mike Frysinger <vapier@gentoo.org>
110
111 * configure: Regenerate.
112
bf470982
MF		 1132021-01-09 Mike Frysinger <vapier@gentoo.org>
114
115 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
116 * configure: Regenerate.
117
46f900c0
MF		 1182021-01-08 Mike Frysinger <vapier@gentoo.org>
119
120 * configure: Regenerate.
121
dfb856ba
MF		 1222021-01-04 Mike Frysinger <vapier@gentoo.org>
123
124 * configure: Regenerate.
125
382bc56b
PK		 1262020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
127
128 * sim-main.c: Include <stdlib.h>.
129
ad9675dd
PK		 1302020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
131
132 * cp1.c: Include <stdlib.h>.
133
f693213d
SM		 1342020-07-29 Simon Marchi <simon.marchi@efficios.com>
135
136 * configure: Re-generate.
137
5c887dd5
JB		 1382017-09-06 John Baldwin <jhb@FreeBSD.org>
139
140 * configure: Regenerate.
141
91588b3a
MF		 1422016-11-11 Mike Frysinger <vapier@gentoo.org>
143
6cb2202b 144 PR sim/20808
91588b3a
MF		 145 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
146 and SD to sd.
147
e04659e8
MF		 1482016-11-11 Mike Frysinger <vapier@gentoo.org>
149
6cb2202b 150 PR sim/20809
e04659e8
MF		 151 * mips.igen (check_u64): Enable for `r3900'.
152
1554f758
MF		 1532016-02-05 Mike Frysinger <vapier@gentoo.org>
154
155 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
156 STATE_PROG_BFD (sd).
157 * configure: Regenerate.
158
3d304f48
AB		 1592016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
160 Maciej W. Rozycki <macro@imgtec.com>
161
162 PR sim/19441
163 * micromips.igen (delayslot_micromips): Enable for `micromips32',
164 `micromips64' and `micromipsdsp' only.
165 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
166 (do_micromips_jalr, do_micromips_jal): Likewise.
167 (compute_movep_src_reg): Likewise.
168 (compute_andi16_imm): Likewise.
169 (convert_fmt_micromips): Likewise.
170 (convert_fmt_micromips_cvt_d): Likewise.
171 (convert_fmt_micromips_cvt_s): Likewise.
172 (FMT_MICROMIPS): Likewise.
173 (FMT_MICROMIPS_CVT_D): Likewise.
174 (FMT_MICROMIPS_CVT_S): Likewise.
175
b36d953b
MF		 1762016-01-12 Mike Frysinger <vapier@gentoo.org>
177
178 * interp.c: Include elf-bfd.h.
179 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
180 ELFCLASS32.
181
ce39bd38
MF		 1822016-01-10 Mike Frysinger <vapier@gentoo.org>
183
184 * config.in, configure: Regenerate.
185
99d8e879
MF		 1862016-01-10 Mike Frysinger <vapier@gentoo.org>
187
188 * configure: Regenerate.
189
35656e95
MF		 1902016-01-10 Mike Frysinger <vapier@gentoo.org>
191
192 * configure: Regenerate.
193
16f7876d
MF		 1942016-01-10 Mike Frysinger <vapier@gentoo.org>
195
196 * configure: Regenerate.
197
e19418e0
MF		 1982016-01-10 Mike Frysinger <vapier@gentoo.org>
199
200 * configure: Regenerate.
201
6d90347b
MF		 2022016-01-10 Mike Frysinger <vapier@gentoo.org>
203
204 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
205 * configure: Regenerate.
206
347fe5bb
MF		 2072016-01-10 Mike Frysinger <vapier@gentoo.org>
208
209 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
210 * configure: Regenerate.
211
22be3fbe
MF		 2122016-01-10 Mike Frysinger <vapier@gentoo.org>
213
214 * configure: Regenerate.
215
0dc73ef7
MF		 2162016-01-10 Mike Frysinger <vapier@gentoo.org>
217
218 * configure: Regenerate.
219
936df756
MF		 2202016-01-09 Mike Frysinger <vapier@gentoo.org>
221
222 * config.in, configure: Regenerate.
223
2e3d4f4d
MF		 2242016-01-06 Mike Frysinger <vapier@gentoo.org>
225
226 * interp.c (sim_open): Mark argv const.
227 (sim_create_inferior): Mark argv and env const.
228
9bbf6f91
MF		 2292016-01-04 Mike Frysinger <vapier@gentoo.org>
230
231 * configure: Regenerate.
232
77cf2ef5
MF		 2332016-01-03 Mike Frysinger <vapier@gentoo.org>
234
235 * interp.c (sim_open): Update sim_parse_args comment.
236
0cb8d851
MF		 2372016-01-03 Mike Frysinger <vapier@gentoo.org>
238
239 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
240 * configure: Regenerate.
241
1ac72f06
MF		 2422016-01-02 Mike Frysinger <vapier@gentoo.org>
243
244 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
245 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
246 * configure: Regenerate.
247 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
248
d47f5b30
MF		 2492016-01-02 Mike Frysinger <vapier@gentoo.org>
250
251 * dv-tx3904cpu.c (CPU, SD): Delete.
252
e1211e55
MF		 2532015-12-30 Mike Frysinger <vapier@gentoo.org>
254
255 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
256 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
257 (sim_store_register): Rename to ...
258 (mips_reg_store): ... this. Delete local cpu var.
259 Update sim_io_eprintf calls.
260 (sim_fetch_register): Rename to ...
261 (mips_reg_fetch): ... this. Delete local cpu var.
262 Update sim_io_eprintf calls.
263
5e744ef8
MF		 2642015-12-27 Mike Frysinger <vapier@gentoo.org>
265
266 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
267
1b393626
MF		 2682015-12-26 Mike Frysinger <vapier@gentoo.org>
269
270 * config.in, configure: Regenerate.
271
26f8bf63
MF		 2722015-12-26 Mike Frysinger <vapier@gentoo.org>
273
274 * interp.c (sim_write, sim_read): Delete.
275 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
276 (load_word): Likewise.
277 * micromips.igen (cache): Likewise.
278 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
279 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
280 do_store_left, do_store_right, do_load_double, do_store_double):
281 Likewise.
282 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
283 (do_prefx): Likewise.
284 * sim-main.c (address_translation, prefetch): Delete.
285 (ifetch32, ifetch16): Delete call to AddressTranslation and set
286 paddr=vaddr.
287 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
288 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
289 (LoadMemory, StoreMemory): Delete CCA arg.
290
ef04e371
MF		 2912015-12-24 Mike Frysinger <vapier@gentoo.org>
292
293 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
294 * configure: Regenerated.
295
cb379ede
MF		 2962015-12-24 Mike Frysinger <vapier@gentoo.org>
297
298 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
299 * tconfig.h: Delete.
300
26936211
MF		 3012015-12-24 Mike Frysinger <vapier@gentoo.org>
302
303 * tconfig.h (SIM_HANDLES_LMA): Delete.
304
84e8e361
MF		 3052015-12-24 Mike Frysinger <vapier@gentoo.org>
306
307 * sim-main.h (WITH_WATCHPOINTS): Delete.
308
3cabaf66
MF		 3092015-12-24 Mike Frysinger <vapier@gentoo.org>
310
311 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
312
8abe6c66
MF		 3132015-12-24 Mike Frysinger <vapier@gentoo.org>
314
315 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
316
1d19cae7
DV		 3172015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
318
319 * micromips.igen (process_isa_mode): Fix left shift of negative
320 value.
321
cdf850e9
MF		 3222015-11-17 Mike Frysinger <vapier@gentoo.org>
323
324 * sim-main.h (WITH_MODULO_MEMORY): Delete.
325
797eee42
MF		 3262015-11-15 Mike Frysinger <vapier@gentoo.org>
327
328 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
329
6e4f085c
MF		 3302015-11-14 Mike Frysinger <vapier@gentoo.org>
331
332 * interp.c (sim_close): Rename to ...
333 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
334 sim_io_shutdown.
335 * sim-main.h (mips_sim_close): Declare.
336 (SIM_CLOSE_HOOK): Define.
337
8e394ffc
AB		 3382015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
339 Ali Lown <ali.lown@imgtec.com>
340
341 * Makefile.in (tmp-micromips): New rule.
342 (tmp-mach-multi): Add support for micromips.
343 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
344 that works for both mips64 and micromips64.
345 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
346 micromips32.
347 Add build support for micromips.
348 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
349 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
350 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
351 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
352 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
353 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
354 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
355 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
356 Refactored instruction code to use these functions.
357 * dsp2.igen: Refactored instruction code to use the new functions.
358 * interp.c (decode_coproc): Refactored to work with any instruction
359 encoding.
360 (isa_mode): New variable
361 (RSVD_INSTRUCTION): Changed to 0x00000039.
362 * m16.igen (BREAK16): Refactored instruction to use do_break16.
363 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
364 * micromips.dc: New file.
365 * micromips.igen: New file.
366 * micromips16.dc: New file.
367 * micromipsdsp.igen: New file.
368 * micromipsrun.c: New file.
369 * mips.igen (do_swc1): Changed to work with any instruction encoding.
370 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
371 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
372 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
373 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
374 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
375 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
376 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
377 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
378 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
379 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
380 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
381 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
382 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
383 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
384 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
385 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
386 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
387 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
388 instructions.
389 Refactored instruction code to use these functions.
390 (RSVD): Changed to use new reserved instruction.
391 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
392 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
393 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
394 do_store_double): Added micromips32 and micromips64 models.
395 Added include for micromips.igen and micromipsdsp.igen
396 Add micromips32 and micromips64 models.
397 (DecodeCoproc): Updated to use new macro definition.
398 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
399 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
400 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
401 Refactored instruction code to use these functions.
402 * sim-main.h (CP0_operation): New enum.
403 (DecodeCoproc): Updated macro.
404 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
405 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
406 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
407 ISA_MODE_MICROMIPS): New defines.
408 (sim_state): Add isa_mode field.
409
8d0978fb
MF		 4102015-06-23 Mike Frysinger <vapier@gentoo.org>
411
412 * configure: Regenerate.
413
306f4178
MF		 4142015-06-12 Mike Frysinger <vapier@gentoo.org>
415
416 * configure.ac: Change configure.in to configure.ac.
417 * configure: Regenerate.
418
a3487082
MF		 4192015-06-12 Mike Frysinger <vapier@gentoo.org>
420
421 * configure: Regenerate.
422
29bc024d
MF		 4232015-06-12 Mike Frysinger <vapier@gentoo.org>
424
425 * interp.c [TRACE]: Delete.
426 (TRACE): Change to WITH_TRACE_ANY_P.
427 [!WITH_TRACE_ANY_P] (open_trace): Define.
428 (mips_option_handler, open_trace, sim_close, dotrace):
429 Change defined(TRACE) to WITH_TRACE_ANY_P.
430 (sim_open): Delete TRACE ifdef check.
431 * sim-main.c (load_memory): Delete TRACE ifdef check.
432 (store_memory): Likewise.
433 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
434 [!WITH_TRACE_ANY_P] (dotrace): Define.
435
3ebe2863
MF		 4362015-04-18 Mike Frysinger <vapier@gentoo.org>
437
438 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
439 comments.
440
20bca71d
MF		 4412015-04-18 Mike Frysinger <vapier@gentoo.org>
442
443 * sim-main.h (SIM_CPU): Delete.
444
7e83aa92
MF		 4452015-04-18 Mike Frysinger <vapier@gentoo.org>
446
447 * sim-main.h (sim_cia): Delete.
448
034685f9
MF		 4492015-04-17 Mike Frysinger <vapier@gentoo.org>
450
451 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
452 PU_PC_GET.
453 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
454 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
455 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
456 CIA_SET to CPU_PC_SET.
457 * sim-main.h (CIA_GET, CIA_SET): Delete.
458
78e9aa70
MF		 4592015-04-15 Mike Frysinger <vapier@gentoo.org>
460
461 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
462 * sim-main.h (STATE_CPU): Delete.
463
bf12d44e
MF		 4642015-04-13 Mike Frysinger <vapier@gentoo.org>
465
466 * configure: Regenerate.
467
7bebb329
MF		 4682015-04-13 Mike Frysinger <vapier@gentoo.org>
469
470 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
471 * interp.c (mips_pc_get, mips_pc_set): New functions.
472 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
473 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
474 (sim_pc_get): Delete.
475 * sim-main.h (SIM_CPU): Define.
476 (struct sim_state): Change cpu to an array of pointers.
477 (STATE_CPU): Drop &.
478
8ac57fbd
MF		 4792015-04-13 Mike Frysinger <vapier@gentoo.org>
480
481 * interp.c (mips_option_handler, open_trace, sim_close,
482 sim_write, sim_read, sim_store_register, sim_fetch_register,
483 sim_create_inferior, pr_addr, pr_uword64): Convert old style
484 prototypes.
485 (sim_open): Convert old style prototype. Change casts with
486 sim_write to unsigned char *.
487 (fetch_str): Change null to unsigned char, and change cast to
488 unsigned char *.
489 (sim_monitor): Change c & ch to unsigned char. Change cast to
490 unsigned char *.
491
e787f858
MF		 4922015-04-12 Mike Frysinger <vapier@gentoo.org>
493
494 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
495
122bbfb5
MF		 4962015-04-06 Mike Frysinger <vapier@gentoo.org>
497
498 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
499
0fe84f3f
MF		 5002015-04-01 Mike Frysinger <vapier@gentoo.org>
501
502 * tconfig.h (SIM_HAVE_PROFILE): Delete.
503
aadc9410
MF		 5042015-03-31 Mike Frysinger <vapier@gentoo.org>
505
506 * config.in, configure: Regenerate.
507
05f53ed6
MF		 5082015-03-24 Mike Frysinger <vapier@gentoo.org>
509
510 * interp.c (sim_pc_get): New function.
511
c0931f26
MF		 5122015-03-24 Mike Frysinger <vapier@gentoo.org>
513
514 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
515 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
516
30452bbe
MF		 5172015-03-24 Mike Frysinger <vapier@gentoo.org>
518
519 * configure: Regenerate.
520
64dd13df
MF		 5212015-03-23 Mike Frysinger <vapier@gentoo.org>
522
523 * configure: Regenerate.
524
49cd1634
MF		 5252015-03-23 Mike Frysinger <vapier@gentoo.org>
526
527 * configure: Regenerate.
528 * configure.ac (mips_extra_objs): Delete.
529 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
530 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
531
3649cb06
MF		 5322015-03-23 Mike Frysinger <vapier@gentoo.org>
533
534 * configure: Regenerate.
535 * configure.ac: Delete sim_hw checks for dv-sockser.
536
ae7d0cac
MF		 5372015-03-16 Mike Frysinger <vapier@gentoo.org>
538
539 * config.in, configure: Regenerate.
540 * tconfig.in: Rename file ...
541 * tconfig.h: ... here.
542
8406bb59
MF		 5432015-03-15 Mike Frysinger <vapier@gentoo.org>
544
545 * tconfig.in: Delete includes.
546 [HAVE_DV_SOCKSER]: Delete.
547
465fb143
MF		 5482015-03-14 Mike Frysinger <vapier@gentoo.org>
549
550 * Makefile.in (SIM_RUN_OBJS): Delete.
551
5cddc23a
MF		 5522015-03-14 Mike Frysinger <vapier@gentoo.org>
553
554 * configure.ac (AC_CHECK_HEADERS): Delete.
555 * aclocal.m4, configure: Regenerate.
556
2974be62
AM		 5572014-08-19 Alan Modra <amodra@gmail.com>
558
559 * configure: Regenerate.
560
faa743bb
RM		 5612014-08-15 Roland McGrath <mcgrathr@google.com>
562
563 * configure: Regenerate.
564 * config.in: Regenerate.
565
1a8a700e
MF		 5662014-03-04 Mike Frysinger <vapier@gentoo.org>
567
568 * configure: Regenerate.
569
bf3d9781
AM		 5702013-09-23 Alan Modra <amodra@gmail.com>
571
572 * configure: Regenerate.
573
31e6ad7d
MF		 5742013-06-03 Mike Frysinger <vapier@gentoo.org>
575
576 * aclocal.m4, configure: Regenerate.
577
d3685d60
TT		 5782013-05-10 Freddie Chopin <freddie_chopin@op.pl>
579
580 * configure: Rebuild.
581
1517bd27
MF		 5822013-03-26 Mike Frysinger <vapier@gentoo.org>
583
584 * configure: Regenerate.
585
3be31516
JS		 5862013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
587
588 * configure.ac: Address use of dv-sockser.o.
589 * tconfig.in: Conditionalize use of dv_sockser_install.
590 * configure: Regenerated.
591 * config.in: Regenerated.
592
37cb8f8e
SE		 5932012-10-04 Chao-ying Fu <fu@mips.com>
594 Steve Ellcey <sellcey@mips.com>
595
596 * mips/mips3264r2.igen (rdhwr): New.
597
87c8644f
JS		 5982012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
599
600 * configure.ac: Always link against dv-sockser.o.
601 * configure: Regenerate.
602
5f3ef9d0
JB		 6032012-06-15 Joel Brobecker <brobecker@adacore.com>
604
605 * config.in, configure: Regenerate.
606
a6ff997c
NC		 6072012-05-18 Nick Clifton <nickc@redhat.com>
608
609 PR 14072
610 * interp.c: Include config.h before system header files.
611
2232061b
MF		 6122012-03-24 Mike Frysinger <vapier@gentoo.org>
613
614 * aclocal.m4, config.in, configure: Regenerate.
615
db2e4d67
MF		 6162011-12-03 Mike Frysinger <vapier@gentoo.org>
617
618 * aclocal.m4: New file.
619 * configure: Regenerate.
620
4399a56b
MF		 6212011-10-19 Mike Frysinger <vapier@gentoo.org>
622
623 * configure: Regenerate after common/acinclude.m4 update.
624
9c082ca8
MF		 6252011-10-17 Mike Frysinger <vapier@gentoo.org>
626
627 * configure.ac: Change include to common/acinclude.m4.
628
6ffe910a
MF		 6292011-10-17 Mike Frysinger <vapier@gentoo.org>
630
631 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
632 call. Replace common.m4 include with SIM_AC_COMMON.
633 * configure: Regenerate.
634
31b28250
HPN		 6352011-07-08 Hans-Peter Nilsson <hp@axis.com>
636
3faa01e3
HPN		 637 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
638 $(SIM_EXTRA_DEPS).
639 (tmp-mach-multi): Exit early when igen fails.
31b28250 640
2419798b
MF		 6412011-07-05 Mike Frysinger <vapier@gentoo.org>
642
643 * interp.c (sim_do_command): Delete.
644
d79fe0d6
MF		 6452011-02-14 Mike Frysinger <vapier@gentoo.org>
646
647 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
648 (tx3904sio_fifo_reset): Likewise.
649 * interp.c (sim_monitor): Likewise.
650
5558e7e6
MF		 6512010-04-14 Mike Frysinger <vapier@gentoo.org>
652
653 * interp.c (sim_write): Add const to buffer arg.
654
35aafff4
JB		 6552010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
656
657 * interp.c: Don't include sysdep.h
658
3725885a
RW		 6592010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
660
661 * configure: Regenerate.
662
d6416cdc
RW		 6632009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
664
81ecdfbb
RW		 665 * config.in: Regenerate.
666 * configure: Likewise.
667
d6416cdc
RW		 668 * configure: Regenerate.
669
b5bd9624
HPN		 6702008-07-11 Hans-Peter Nilsson <hp@axis.com>
671
672 * configure: Regenerate to track ../common/common.m4 changes.
673 * config.in: Ditto.
674
6efef468 6752008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 676 Daniel Jacobowitz <dan@codesourcery.com>
677 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 678
679 * configure: Regenerate.
680
60dc88db
RS		 6812007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
682
683 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
684 that unconditionally allows fmt_ps.
685 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
686 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
687 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
688 filter from 64,f to 32,f.
689 (PREFX): Change filter from 64 to 32.
690 (LDXC1, LUXC1): Provide separate mips32r2 implementations
691 that use do_load_double instead of do_load. Make both LUXC1
692 versions unpredictable if SizeFGR () != 64.
693 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
694 instead of do_store. Remove unused variable. Make both SUXC1
695 versions unpredictable if SizeFGR () != 64.
696
599ca73e
RS		 6972007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
698
699 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
700 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
701 shifts for that case.
702
2525df03
NC		 7032007-09-04 Nick Clifton <nickc@redhat.com>
704
705 * interp.c (options enum): Add OPTION_INFO_MEMORY.
706 (display_mem_info): New static variable.
707 (mips_option_handler): Handle OPTION_INFO_MEMORY.
708 (mips_options): Add info-memory and memory-info.
709 (sim_open): After processing the command line and board
710 specification, check display_mem_info. If it is set then
711 call the real handler for the --memory-info command line
712 switch.
713
35ee6e1e
JB		 7142007-08-24 Joel Brobecker <brobecker@adacore.com>
715
716 * configure.ac: Change license of multi-run.c to GPL version 3.
717 * configure: Regenerate.
718
d5fb0879
RS		 7192007-06-28 Richard Sandiford <richard@codesourcery.com>
720
721 * configure.ac, configure: Revert last patch.
722
2a2ce21b
RS		 7232007-06-26 Richard Sandiford <richard@codesourcery.com>
724
725 * configure.ac (sim_mipsisa3264_configs): New variable.
726 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
727 every configuration support all four targets, using the triplet to
728 determine the default.
729 * configure: Regenerate.
730
efdcccc9
RS		 7312007-06-25 Richard Sandiford <richard@codesourcery.com>
732
0a7692b2 733 * Makefile.in (m16run.o): New rule.
efdcccc9 734
f532a356
TS		 7352007-05-15 Thiemo Seufer <ths@mips.com>
736
737 * mips3264r2.igen (DSHD): Fix compile warning.
738
bfe9c90b
TS		 7392007-05-14 Thiemo Seufer <ths@mips.com>
740
741 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
742 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
743 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
744 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
745 for mips32r2.
746
53f4826b
TS		 7472007-03-01 Thiemo Seufer <ths@mips.com>
748
749 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
750 and mips64.
751
8bf3ddc8
TS		 7522007-02-20 Thiemo Seufer <ths@mips.com>
753
754 * dsp.igen: Update copyright notice.
755 * dsp2.igen: Fix copyright notice.
756
8b082fb1 7572007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 758 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 759
760 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
761 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
762 Add dsp2 to sim_igen_machine.
763 * configure: Regenerate.
764 * dsp.igen (do_ph_op): Add MUL support when op = 2.
765 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
766 (mulq_rs.ph): Use do_ph_mulq.
767 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
768 * mips.igen: Add dsp2 model and include dsp2.igen.
769 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
770 for *mips32r2, *mips64r2, *dsp.
771 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
772 for *mips32r2, *mips64r2, *dsp2.
773 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
774
b1004875 7752007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 776 Nigel Stephens <nigel@mips.com>
b1004875
TS		 777
778 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
779 jumps with hazard barrier.
780
f8df4c77 7812007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 782 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 783
784 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
785 after each call to sim_io_write.
786
b1004875 7872007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 788 Nigel Stephens <nigel@mips.com>
b1004875
TS		 789
790 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
791 supported by this simulator.
07802d98
TS		 792 (decode_coproc): Recognise additional CP0 Config registers
793 correctly.
794
14fb6c5a 7952007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 796 Nigel Stephens <nigel@mips.com>
797 David Ung <davidu@mips.com>
14fb6c5a
TS		 798
799 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
800 uninterpreted formats. If fmt is one of the uninterpreted types
801 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
802 fmt_word, and fmt_uninterpreted_64 like fmt_long.
803 (store_fpr): When writing an invalid odd register, set the
804 matching even register to fmt_unknown, not the following register.
805 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
806 the the memory window at offset 0 set by --memory-size command
807 line option.
808 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
809 point register.
810 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
811 register.
812 (sim_monitor): When returning the memory size to the MIPS
813 application, use the value in STATE_MEM_SIZE, not an arbitrary
814 hardcoded value.
815 (cop_lw): Don' mess around with FPR_STATE, just pass
816 fmt_uninterpreted_32 to StoreFPR.
817 (cop_sw): Similarly.
818 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
819 (cop_sd): Similarly.
820 * mips.igen (not_word_value): Single version for mips32, mips64
821 and mips16.
822
c8847145 8232007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 824 Nigel Stephens <nigel@mips.com>
c8847145
TS		 825
826 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
827 MBytes.
828
4b5d35ee
TS		 8292007-02-17 Thiemo Seufer <ths@mips.com>
830
831 * configure.ac (mips*-sde-elf*): Move in front of generic machine
832 configuration.
833 * configure: Regenerate.
834
3669427c
TS		 8352007-02-17 Thiemo Seufer <ths@mips.com>
836
837 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
838 Add mdmx to sim_igen_machine.
839 (mipsisa64*-*-*): Likewise. Remove dsp.
840 (mipsisa32*-*-*): Remove dsp.
841 * configure: Regenerate.
842
109ad085
TS		 8432007-02-13 Thiemo Seufer <ths@mips.com>
844
845 * configure.ac: Add mips*-sde-elf* target.
846 * configure: Regenerate.
847
921d7ad3
HPN		 8482006-12-21 Hans-Peter Nilsson <hp@axis.com>
849
850 * acconfig.h: Remove.
851 * config.in, configure: Regenerate.
852
02f97da7
TS		 8532006-11-07 Thiemo Seufer <ths@mips.com>
854
855 * dsp.igen (do_w_op): Fix compiler warning.
856
2d2733fc 8572006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 858 David Ung <davidu@mips.com>
2d2733fc
TS		 859
860 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
861 sim_igen_machine.
862 * configure: Regenerate.
863 * mips.igen (model): Add smartmips.
864 (MADDU): Increment ACX if carry.
865 (do_mult): Clear ACX.
866 (ROR,RORV): Add smartmips.
72f4393d 867 (include): Include smartmips.igen.
2d2733fc
TS		 868 * sim-main.h (ACX): Set to REGISTERS[89].
869 * smartmips.igen: New file.
870
d85c3a10 8712006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 872 David Ung <davidu@mips.com>
d85c3a10
TS		 873
874 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
875 mips3264r2.igen. Add missing dependency rules.
876 * m16e.igen: Support for mips16e save/restore instructions.
877
e85e3205
RE		 8782006-06-13 Richard Earnshaw <rearnsha@arm.com>
879
880 * configure: Regenerated.
881
2f0122dc
DJ		 8822006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
883
884 * configure: Regenerated.
885
20e95c23
DJ		 8862006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
887
888 * configure: Regenerated.
889
69088b17
CF		 8902006-05-15 Chao-ying Fu <fu@mips.com>
891
892 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
893
0275de4e
NC		 8942006-04-18 Nick Clifton <nickc@redhat.com>
895
896 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
897 statement.
898
b3a3ffef
HPN		 8992006-03-29 Hans-Peter Nilsson <hp@axis.com>
900
901 * configure: Regenerate.
902
40a5538e
CF		 9032005-12-14 Chao-ying Fu <fu@mips.com>
904
905 * Makefile.in (SIM_OBJS): Add dsp.o.
906 (dsp.o): New dependency.
907 (IGEN_INCLUDE): Add dsp.igen.
908 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
909 mipsisa64*-*-*): Add dsp to sim_igen_machine.
910 * configure: Regenerate.
911 * mips.igen: Add dsp model and include dsp.igen.
912 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
913 because these instructions are extended in DSP ASE.
914 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
915 adding 6 DSP accumulator registers and 1 DSP control register.
916 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
917 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
918 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
919 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
920 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
921 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
922 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
923 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
924 DSPCR_CCOND_SMASK): New define.
925 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
926 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
927
21d14896
ILT		 9282005-07-08 Ian Lance Taylor <ian@airs.com>
929
930 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
931
b16d63da 9322005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 933 Nigel Stephens <nigel@mips.com>
934
935 * mips.igen: New mips16e model and include m16e.igen.
936 (check_u64): Add mips16e tag.
937 * m16e.igen: New file for MIPS16e instructions.
938 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
939 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
940 models.
941 * configure: Regenerate.
b16d63da 942
e70cb6cd 9432005-05-26 David Ung <davidu@mips.com>
72f4393d 944
e70cb6cd
CD		 945 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
946 tags to all instructions which are applicable to the new ISAs.
947 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
948 vr.igen.
949 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 950 instructions.
e70cb6cd
CD		 951 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
952 to mips.igen.
953 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
954 * configure: Regenerate.
72f4393d 955
2b193c4a
MK		 9562005-03-23 Mark Kettenis <kettenis@gnu.org>
957
958 * configure: Regenerate.
959
35695fd6
AC		 9602005-01-14 Andrew Cagney <cagney@gnu.org>
961
962 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
963 explicit call to AC_CONFIG_HEADER.
964 * configure: Regenerate.
965
f0569246
AC		 9662005-01-12 Andrew Cagney <cagney@gnu.org>
967
968 * configure.ac: Update to use ../common/common.m4.
969 * configure: Re-generate.
970
38f48d72
AC		 9712005-01-11 Andrew Cagney <cagney@localhost.localdomain>
972
973 * configure: Regenerated to track ../common/aclocal.m4 changes.
974
b7026657
AC		 9752005-01-07 Andrew Cagney <cagney@gnu.org>
976
977 * configure.ac: Rename configure.in, require autoconf 2.59.
978 * configure: Re-generate.
979
379832de
HPN		 9802004-12-08 Hans-Peter Nilsson <hp@axis.com>
981
982 * configure: Regenerate for ../common/aclocal.m4 update.
983
cd62154c 9842004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 985
cd62154c
AC		 986 Committed by Andrew Cagney.
987 * m16.igen (CMP, CMPI): Fix assembler.
988
e5da76ec
CD		 9892004-08-18 Chris Demetriou <cgd@broadcom.com>
990
991 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
992 * configure: Regenerate.
993
139181c8
CD		 9942004-06-25 Chris Demetriou <cgd@broadcom.com>
995
996 * configure.in (sim_m16_machine): Include mipsIII.
997 * configure: Regenerate.
998
1a27f959
CD		 9992004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1000
72f4393d 1001 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1002 from COP0_BADVADDR.
1003 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1004
5dbb7b5a
CD		 10052004-04-10 Chris Demetriou <cgd@broadcom.com>
1006
1007 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1008
14234056
CD		 10092004-04-09 Chris Demetriou <cgd@broadcom.com>
1010
1011 * mips.igen (check_fmt): Remove.
1012 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1013 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1014 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1015 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1016 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1017 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1018 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1019 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1020 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1021 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1022
c6f9085c
CD		 10232004-04-09 Chris Demetriou <cgd@broadcom.com>
1024
1025 * sb1.igen (check_sbx): New function.
1026 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1027
11d66e66 10282004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1029 Richard Sandiford <rsandifo@redhat.com>
1030
1031 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1032 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1033 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1034 separate implementations for mipsIV and mipsV. Use new macros to
1035 determine whether the restrictions apply.
1036
b3208fb8
CD		 10372004-01-19 Chris Demetriou <cgd@broadcom.com>
1038
1039 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1040 (check_mult_hilo): Improve comments.
1041 (check_div_hilo): Likewise. Also, fork off a new version
1042 to handle mips32/mips64 (since there are no hazards to check
1043 in MIPS32/MIPS64).
1044
9a1d84fb
CD		 10452003-06-17 Richard Sandiford <rsandifo@redhat.com>
1046
1047 * mips.igen (do_dmultx): Fix check for negative operands.
1048
ae451ac6
ILT		 10492003-05-16 Ian Lance Taylor <ian@airs.com>
1050
1051 * Makefile.in (SHELL): Make sure this is defined.
1052 (various): Use $(SHELL) whenever we invoke move-if-change.
1053
dd69d292
CD		 10542003-05-03 Chris Demetriou <cgd@broadcom.com>
1055
1056 * cp1.c: Tweak attribution slightly.
1057 * cp1.h: Likewise.
1058 * mdmx.c: Likewise.
1059 * mdmx.igen: Likewise.
1060 * mips3d.igen: Likewise.
1061 * sb1.igen: Likewise.
1062
bcd0068e
CD		 10632003-04-15 Richard Sandiford <rsandifo@redhat.com>
1064
1065 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1066 unsigned operands.
1067
6b4a8935
AC		 10682003-02-27 Andrew Cagney <cagney@redhat.com>
1069
601da316
AC		 1070 * interp.c (sim_open): Rename _bfd to bfd.
1071 (sim_create_inferior): Ditto.
6b4a8935 1072
d29e330f
CD		 10732003-01-14 Chris Demetriou <cgd@broadcom.com>
1074
1075 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1076
a2353a08
CD		 10772003-01-14 Chris Demetriou <cgd@broadcom.com>
1078
1079 * mips.igen (EI, DI): Remove.
1080
80551777
CD		 10812003-01-05 Richard Sandiford <rsandifo@redhat.com>
1082
1083 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1084
4c54fc26
CD		 10852003-01-04 Richard Sandiford <rsandifo@redhat.com>
1086 Andrew Cagney <ac131313@redhat.com>
1087 Gavin Romig-Koch <gavin@redhat.com>
1088 Graydon Hoare <graydon@redhat.com>
1089 Aldy Hernandez <aldyh@redhat.com>
1090 Dave Brolley <brolley@redhat.com>
1091 Chris Demetriou <cgd@broadcom.com>
1092
1093 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1094 (sim_mach_default): New variable.
1095 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1096 Add a new simulator generator, MULTI.
1097 * configure: Regenerate.
1098 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1099 (multi-run.o): New dependency.
1100 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1101 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1102 (tmp-multi): Combine them.
1103 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1104 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1105 (distclean-extra): New rule.
1106 * sim-main.h: Include bfd.h.
1107 (MIPS_MACH): New macro.
1108 * mips.igen (vr4120, vr5400, vr5500): New models.
1109 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1110 * vr.igen: Replace with new version.
1111
e6c674b8
CD		 11122003-01-04 Chris Demetriou <cgd@broadcom.com>
1113
1114 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1115 * configure: Regenerate.
1116
28f50ac8
CD		 11172002-12-31 Chris Demetriou <cgd@broadcom.com>
1118
1119 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1120 * mips.igen: Remove all invocations of check_branch_bug and
1121 mark_branch_bug.
1122
5071ffe6
CD		 11232002-12-16 Chris Demetriou <cgd@broadcom.com>
1124
72f4393d 1125 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1126
06e7837e
CD		 11272002-07-30 Chris Demetriou <cgd@broadcom.com>
1128
1129 * mips.igen (do_load_double, do_store_double): New functions.
1130 (LDC1, SDC1): Rename to...
1131 (LDC1b, SDC1b): respectively.
1132 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1133
2265c243
MS		 11342002-07-29 Michael Snyder <msnyder@redhat.com>
1135
1136 * cp1.c (fp_recip2): Modify initialization expression so that
1137 GCC will recognize it as constant.
1138
a2f8b4f3
CD		 11392002-06-18 Chris Demetriou <cgd@broadcom.com>
1140
1141 * mdmx.c (SD_): Delete.
1142 (Unpredictable): Re-define, for now, to directly invoke
1143 unpredictable_action().
1144 (mdmx_acc_op): Fix error in .ob immediate handling.
1145
b4b6c939
AC		 11462002-06-18 Andrew Cagney <cagney@redhat.com>
1147
1148 * interp.c (sim_firmware_command): Initialize `address'.
1149
c8cca39f
AC		 11502002-06-16 Andrew Cagney <ac131313@redhat.com>
1151
1152 * configure: Regenerated to track ../common/aclocal.m4 changes.
1153
e7e81181 11542002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1155 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1156
1157 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1158 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1159 * mips.igen: Include mips3d.igen.
1160 (mips3d): New model name for MIPS-3D ASE instructions.
1161 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1162 instructions.
e7e81181
CD		 1163 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1164 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1165 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1166 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1167 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1168 (RSquareRoot1, RSquareRoot2): New macros.
1169 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1170 (fp_rsqrt2): New functions.
1171 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1172 * configure: Regenerate.
1173
3a2b820e 11742002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1175 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1176
1177 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1178 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1179 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1180 (convert): Note that this function is not used for paired-single
1181 format conversions.
1182 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1183 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1184 (check_fmt_p): Enable paired-single support.
1185 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1186 (PUU.PS): New instructions.
1187 (CVT.S.fmt): Don't use this instruction for paired-single format
1188 destinations.
1189 * sim-main.h (FP_formats): New value 'fmt_ps.'
1190 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1191 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1192
d18ea9c2
CD		 11932002-06-12 Chris Demetriou <cgd@broadcom.com>
1194
1195 * mips.igen: Fix formatting of function calls in
1196 many FP operations.
1197
95fd5cee
CD		 11982002-06-12 Chris Demetriou <cgd@broadcom.com>
1199
1200 * mips.igen (MOVN, MOVZ): Trace result.
1201 (TNEI): Print "tnei" as the opcode name in traces.
1202 (CEIL.W): Add disassembly string for traces.
1203 (RSQRT.fmt): Make location of disassembly string consistent
1204 with other instructions.
1205
4f0d55ae
CD		 12062002-06-12 Chris Demetriou <cgd@broadcom.com>
1207
1208 * mips.igen (X): Delete unused function.
1209
3c25f8c7
AC		 12102002-06-08 Andrew Cagney <cagney@redhat.com>
1211
1212 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1213
f3c08b7e 12142002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1215 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1216
1217 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1218 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1219 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1220 (fp_nmsub): New prototypes.
1221 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1222 (NegMultiplySub): New defines.
1223 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1224 (MADD.D, MADD.S): Replace with...
1225 (MADD.fmt): New instruction.
1226 (MSUB.D, MSUB.S): Replace with...
1227 (MSUB.fmt): New instruction.
1228 (NMADD.D, NMADD.S): Replace with...
1229 (NMADD.fmt): New instruction.
1230 (NMSUB.D, MSUB.S): Replace with...
1231 (NMSUB.fmt): New instruction.
1232
52714ff9 12332002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1234 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1235
1236 * cp1.c: Fix more comment spelling and formatting.
1237 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1238 (denorm_mode): New function.
1239 (fpu_unary, fpu_binary): Round results after operation, collect
1240 status from rounding operations, and update the FCSR.
1241 (convert): Collect status from integer conversions and rounding
1242 operations, and update the FCSR. Adjust NaN values that result
1243 from conversions. Convert to use sim_io_eprintf rather than
1244 fprintf, and remove some debugging code.
1245 * cp1.h (fenr_FS): New define.
1246
577d8c4b
CD		 12472002-06-07 Chris Demetriou <cgd@broadcom.com>
1248
1249 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1250 rounding mode to sim FP rounding mode flag conversion code into...
1251 (rounding_mode): New function.
1252
196496ed
CD		 12532002-06-07 Chris Demetriou <cgd@broadcom.com>
1254
1255 * cp1.c: Clean up formatting of a few comments.
1256 (value_fpr): Reformat switch statement.
1257
cfe9ea23 12582002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1259 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1260
1261 * cp1.h: New file.
1262 * sim-main.h: Include cp1.h.
1263 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1264 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1265 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1266 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1267 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1268 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1269 * cp1.c: Don't include sim-fpu.h; already included by
1270 sim-main.h. Clean up formatting of some comments.
1271 (NaN, Equal, Less): Remove.
1272 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1273 (fp_cmp): New functions.
1274 * mips.igen (do_c_cond_fmt): Remove.
1275 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1276 Compare. Add result tracing.
1277 (CxC1): Remove, replace with...
1278 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1279 (DMxC1): Remove, replace with...
1280 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1281 (MxC1): Remove, replace with...
1282 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1283
ee7254b0
CD		 12842002-06-04 Chris Demetriou <cgd@broadcom.com>
1285
1286 * sim-main.h (FGRIDX): Remove, replace all uses with...
1287 (FGR_BASE): New macro.
1288 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1289 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1290 (NR_FGR, FGR): Likewise.
1291 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1292 * mips.igen: Likewise.
1293
d3eb724f
CD		 12942002-06-04 Chris Demetriou <cgd@broadcom.com>
1295
1296 * cp1.c: Add an FSF Copyright notice to this file.
1297
ba46ddd0 12982002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1299 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1300
1301 * cp1.c (Infinity): Remove.
1302 * sim-main.h (Infinity): Likewise.
1303
1304 * cp1.c (fp_unary, fp_binary): New functions.
1305 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1306 (fp_sqrt): New functions, implemented in terms of the above.
1307 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1308 (Recip, SquareRoot): Remove (replaced by functions above).
1309 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1310 (fp_recip, fp_sqrt): New prototypes.
1311 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1312 (Recip, SquareRoot): Replace prototypes with #defines which
1313 invoke the functions above.
72f4393d 1314
18d8a52d
CD		 13152002-06-03 Chris Demetriou <cgd@broadcom.com>
1316
1317 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1318 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1319 file, remove PARAMS from prototypes.
1320 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1321 simulator state arguments.
1322 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1323 pass simulator state arguments.
1324 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1325 (store_fpr, convert): Remove 'sd' argument.
1326 (value_fpr): Likewise. Convert to use 'SD' instead.
1327
0f154cbd
CD		 13282002-06-03 Chris Demetriou <cgd@broadcom.com>
1329
1330 * cp1.c (Min, Max): Remove #if 0'd functions.
1331 * sim-main.h (Min, Max): Remove.
1332
e80fc152
CD		 13332002-06-03 Chris Demetriou <cgd@broadcom.com>
1334
1335 * cp1.c: fix formatting of switch case and default labels.
1336 * interp.c: Likewise.
1337 * sim-main.c: Likewise.
1338
bad673a9
CD		 13392002-06-03 Chris Demetriou <cgd@broadcom.com>
1340
1341 * cp1.c: Clean up comments which describe FP formats.
1342 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1343
7cbea089 13442002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1345 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1346
1347 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1348 Broadcom SiByte SB-1 processor configurations.
1349 * configure: Regenerate.
1350 * sb1.igen: New file.
1351 * mips.igen: Include sb1.igen.
1352 (sb1): New model.
1353 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1354 * mdmx.igen: Add "sb1" model to all appropriate functions and
1355 instructions.
1356 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1357 (ob_func, ob_acc): Reference the above.
1358 (qh_acc): Adjust to keep the same size as ob_acc.
1359 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1360 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1361
909daa82
CD		 13622002-06-03 Chris Demetriou <cgd@broadcom.com>
1363
1364 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1365
f4f1b9f1 13662002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1367 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1368
1369 * mips.igen (mdmx): New (pseudo-)model.
1370 * mdmx.c, mdmx.igen: New files.
1371 * Makefile.in (SIM_OBJS): Add mdmx.o.
1372 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1373 New typedefs.
1374 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1375 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1376 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1377 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1378 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1379 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1380 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1381 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1382 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1383 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1384 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1385 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1386 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1387 (qh_fmtsel): New macros.
1388 (_sim_cpu): New member "acc".
1389 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1390 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1391
5accf1ff
CD		 13922002-05-01 Chris Demetriou <cgd@broadcom.com>
1393
1394 * interp.c: Use 'deprecated' rather than 'depreciated.'
1395 * sim-main.h: Likewise.
1396
402586aa
CD		 13972002-05-01 Chris Demetriou <cgd@broadcom.com>
1398
1399 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1400 which wouldn't compile anyway.
1401 * sim-main.h (unpredictable_action): New function prototype.
1402 (Unpredictable): Define to call igen function unpredictable().
1403 (NotWordValue): New macro to call igen function not_word_value().
1404 (UndefinedResult): Remove.
1405 * interp.c (undefined_result): Remove.
1406 (unpredictable_action): New function.
1407 * mips.igen (not_word_value, unpredictable): New functions.
1408 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1409 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1410 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1411 NotWordValue() to check for unpredictable inputs, then
1412 Unpredictable() to handle them.
1413
c9b9995a
CD		 14142002-02-24 Chris Demetriou <cgd@broadcom.com>
1415
1416 * mips.igen: Fix formatting of calls to Unpredictable().
1417
e1015982
AC		 14182002-04-20 Andrew Cagney <ac131313@redhat.com>
1419
1420 * interp.c (sim_open): Revert previous change.
1421
b882a66b
AO		 14222002-04-18 Alexandre Oliva <aoliva@redhat.com>
1423
1424 * interp.c (sim_open): Disable chunk of code that wrote code in
1425 vector table entries.
1426
c429b7dd
CD		 14272002-03-19 Chris Demetriou <cgd@broadcom.com>
1428
1429 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1430 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1431 unused definitions.
1432
37d146fa
CD		 14332002-03-19 Chris Demetriou <cgd@broadcom.com>
1434
1435 * cp1.c: Fix many formatting issues.
1436
07892c0b
CD		 14372002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1438
1439 * cp1.c (fpu_format_name): New function to replace...
1440 (DOFMT): This. Delete, and update all callers.
1441 (fpu_rounding_mode_name): New function to replace...
1442 (RMMODE): This. Delete, and update all callers.
1443
487f79b7
CD		 14442002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1445
1446 * interp.c: Move FPU support routines from here to...
1447 * cp1.c: Here. New file.
1448 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1449 (cp1.o): New target.
1450
1e799e28
CD		 14512002-03-12 Chris Demetriou <cgd@broadcom.com>
1452
1453 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1454 * mips.igen (mips32, mips64): New models, add to all instructions
1455 and functions as appropriate.
1456 (loadstore_ea, check_u64): New variant for model mips64.
1457 (check_fmt_p): New variant for models mipsV and mips64, remove
1458 mipsV model marking fro other variant.
1459 (SLL) Rename to...
1460 (SLLa) this.
1461 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1462 for mips32 and mips64.
1463 (DCLO, DCLZ): New instructions for mips64.
1464
82f728db
CD		 14652002-03-07 Chris Demetriou <cgd@broadcom.com>
1466
1467 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1468 immediate or code as a hex value with the "%#lx" format.
1469 (ANDI): Likewise, and fix printed instruction name.
1470
b96e7ef1
CD		 14712002-03-05 Chris Demetriou <cgd@broadcom.com>
1472
1473 * sim-main.h (UndefinedResult, Unpredictable): New macros
1474 which currently do nothing.
1475
d35d4f70
CD		 14762002-03-05 Chris Demetriou <cgd@broadcom.com>
1477
1478 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1479 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1480 (status_CU3): New definitions.
1481
1482 * sim-main.h (ExceptionCause): Add new values for MIPS32
1483 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1484 for DebugBreakPoint and NMIReset to note their status in
1485 MIPS32 and MIPS64.
1486 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1487 (SignalExceptionCacheErr): New exception macros.
1488
3ad6f714
CD		 14892002-03-05 Chris Demetriou <cgd@broadcom.com>
1490
1491 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1492 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1493 is always enabled.
1494 (SignalExceptionCoProcessorUnusable): Take as argument the
1495 unusable coprocessor number.
1496
86b77b47
CD		 14972002-03-05 Chris Demetriou <cgd@broadcom.com>
1498
1499 * mips.igen: Fix formatting of all SignalException calls.
1500
97a88e93 15012002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1502
1503 * sim-main.h (SIGNEXTEND): Remove.
1504
97a88e93 15052002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1506
1507 * mips.igen: Remove gencode comment from top of file, fix
1508 spelling in another comment.
1509
97a88e93 15102002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1511
1512 * mips.igen (check_fmt, check_fmt_p): New functions to check
1513 whether specific floating point formats are usable.
1514 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1515 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1516 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1517 Use the new functions.
1518 (do_c_cond_fmt): Remove format checks...
1519 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1520
97a88e93 15212002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1522
1523 * mips.igen: Fix formatting of check_fpu calls.
1524
41774c9d
CD		 15252002-03-03 Chris Demetriou <cgd@broadcom.com>
1526
1527 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1528
4a0bd876
CD		 15292002-03-03 Chris Demetriou <cgd@broadcom.com>
1530
1531 * mips.igen: Remove whitespace at end of lines.
1532
09297648
CD		 15332002-03-02 Chris Demetriou <cgd@broadcom.com>
1534
1535 * mips.igen (loadstore_ea): New function to do effective
1536 address calculations.
1537 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1538 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1539 CACHE): Use loadstore_ea to do effective address computations.
1540
043b7057
CD		 15412002-03-02 Chris Demetriou <cgd@broadcom.com>
1542
1543 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1544 * mips.igen (LL, CxC1, MxC1): Likewise.
1545
c1e8ada4
CD		 15462002-03-02 Chris Demetriou <cgd@broadcom.com>
1547
1548 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1549 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1550 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1551 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1552 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1553 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1554 Don't split opcode fields by hand, use the opcode field values
1555 provided by igen.
1556
3e1dca16
CD		 15572002-03-01 Chris Demetriou <cgd@broadcom.com>
1558
1559 * mips.igen (do_divu): Fix spacing.
1560
1561 * mips.igen (do_dsllv): Move to be right before DSLLV,
1562 to match the rest of the do_<shift> functions.
1563
fff8d27d
CD		 15642002-03-01 Chris Demetriou <cgd@broadcom.com>
1565
1566 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1567 DSRL32, do_dsrlv): Trace inputs and results.
1568
0d3e762b
CD		 15692002-03-01 Chris Demetriou <cgd@broadcom.com>
1570
1571 * mips.igen (CACHE): Provide instruction-printing string.
1572
1573 * interp.c (signal_exception): Comment tokens after #endif.
1574
eb5fcf93
CD		 15752002-02-28 Chris Demetriou <cgd@broadcom.com>
1576
1577 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1578 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1579 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1580 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1581 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1582 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1583 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1584 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1585
bb22bd7d
CD		 15862002-02-28 Chris Demetriou <cgd@broadcom.com>
1587
1588 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1589 instruction-printing string.
1590 (LWU): Use '64' as the filter flag.
1591
91a177cf
CD		 15922002-02-28 Chris Demetriou <cgd@broadcom.com>
1593
1594 * mips.igen (SDXC1): Fix instruction-printing string.
1595
387f484a
CD		 15962002-02-28 Chris Demetriou <cgd@broadcom.com>
1597
1598 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1599 filter flags "32,f".
1600
3d81f391
CD		 16012002-02-27 Chris Demetriou <cgd@broadcom.com>
1602
1603 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1604 as the filter flag.
1605
af5107af
CD		 16062002-02-27 Chris Demetriou <cgd@broadcom.com>
1607
1608 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1609 add a comma) so that it more closely match the MIPS ISA
1610 documentation opcode partitioning.
1611 (PREF): Put useful names on opcode fields, and include
1612 instruction-printing string.
1613
ca971540
CD		 16142002-02-27 Chris Demetriou <cgd@broadcom.com>
1615
1616 * mips.igen (check_u64): New function which in the future will
1617 check whether 64-bit instructions are usable and signal an
1618 exception if not. Currently a no-op.
1619 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1620 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1621 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1622 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1623
1624 * mips.igen (check_fpu): New function which in the future will
1625 check whether FPU instructions are usable and signal an exception
1626 if not. Currently a no-op.
1627 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1628 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1629 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1630 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1631 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1632 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1633 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1634 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1635
1c47a468
CD		 16362002-02-27 Chris Demetriou <cgd@broadcom.com>
1637
1638 * mips.igen (do_load_left, do_load_right): Move to be immediately
1639 following do_load.
1640 (do_store_left, do_store_right): Move to be immediately following
1641 do_store.
1642
603a98e7
CD		 16432002-02-27 Chris Demetriou <cgd@broadcom.com>
1644
1645 * mips.igen (mipsV): New model name. Also, add it to
1646 all instructions and functions where it is appropriate.
1647
c5d00cc7
CD		 16482002-02-18 Chris Demetriou <cgd@broadcom.com>
1649
1650 * mips.igen: For all functions and instructions, list model
1651 names that support that instruction one per line.
1652
074e9cb8
CD		 16532002-02-11 Chris Demetriou <cgd@broadcom.com>
1654
1655 * mips.igen: Add some additional comments about supported
1656 models, and about which instructions go where.
1657 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1658 order as is used in the rest of the file.
1659
9805e229
CD		 16602002-02-11 Chris Demetriou <cgd@broadcom.com>
1661
1662 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1663 indicating that ALU32_END or ALU64_END are there to check
1664 for overflow.
1665 (DADD): Likewise, but also remove previous comment about
1666 overflow checking.
1667
f701dad2
CD		 16682002-02-10 Chris Demetriou <cgd@broadcom.com>
1669
1670 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1671 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1672 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1673 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1674 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1675 fields (i.e., add and move commas) so that they more closely
1676 match the MIPS ISA documentation opcode partitioning.
1677
16782002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1679
72f4393d
L		 1680 * mips.igen (ADDI): Print immediate value.
1681 (BREAK): Print code.
1682 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1683 (SLL): Print "nop" specially, and don't run the code
1684 that does the shift for the "nop" case.
20ae0098 1685
9e52972e
FF		 16862001-11-17 Fred Fish <fnf@redhat.com>
1687
1688 * sim-main.h (float_operation): Move enum declaration outside
1689 of _sim_cpu struct declaration.
1690
c0efbca4
JB		 16912001-04-12 Jim Blandy <jimb@redhat.com>
1692
1693 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1694 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1695 set of the FCSR.
1696 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1697 PENDING_FILL, and you can get the intended effect gracefully by
1698 calling PENDING_SCHED directly.
1699
fb891446
BE		 17002001-02-23 Ben Elliston <bje@redhat.com>
1701
1702 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1703 already defined elsewhere.
1704
8030f857
BE		 17052001-02-19 Ben Elliston <bje@redhat.com>
1706
1707 * sim-main.h (sim_monitor): Return an int.
1708 * interp.c (sim_monitor): Add return values.
1709 (signal_exception): Handle error conditions from sim_monitor.
1710
56b48a7a
CD		 17112001-02-08 Ben Elliston <bje@redhat.com>
1712
1713 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1714 (store_memory): Likewise, pass cia to sim_core_write*.
1715
d3ee60d9
FCE		 17162000-10-19 Frank Ch. Eigler <fche@redhat.com>
1717
1718 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1719 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1720
071da002
AC		 1721Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1722
1723 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1724 * Makefile.in: Don't delete *.igen when cleaning directory.
1725
a28c02cd
AC		 1726Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1727
1728 * m16.igen (break): Call SignalException not sim_engine_halt.
1729
80ee11fa
AC		 1730Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1731
1732 From Jason Eckhardt:
1733 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1734
673388c0
AC		 1735Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1736
1737 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1738
4c0deff4
NC		 17392000-05-24 Michael Hayes <mhayes@cygnus.com>
1740
1741 * mips.igen (do_dmultx): Fix typo.
1742
eb2d80b4
AC		 1743Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1744
1745 * configure: Regenerated to track ../common/aclocal.m4 changes.
1746
dd37a34b
AC		 1747Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1748
1749 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1750
4c0deff4
NC		 17512000-04-12 Frank Ch. Eigler <fche@redhat.com>
1752
1753 * sim-main.h (GPR_CLEAR): Define macro.
1754
e30db738
AC		 1755Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1756
1757 * interp.c (decode_coproc): Output long using %lx and not %s.
1758
cb7450ea
FCE		 17592000-03-21 Frank Ch. Eigler <fche@redhat.com>
1760
1761 * interp.c (sim_open): Sort & extend dummy memory regions for
1762 --board=jmr3904 for eCos.
1763
a3027dd7
FCE		 17642000-03-02 Frank Ch. Eigler <fche@redhat.com>
1765
1766 * configure: Regenerated.
1767
1768Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1769
1770 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1771 calls, conditional on the simulator being in verbose mode.
1772
dfcd3bfb
JM		 1773Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1774
1775 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1776 cache don't get ReservedInstruction traps.
1777
c2d11a7d
JM		 17781999-11-29 Mark Salter <msalter@cygnus.com>
1779
1780 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1781 to clear status bits in sdisr register. This is how the hardware works.
1782
1783 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1784 being used by cygmon.
1785
4ce44c66
JM		 17861999-11-11 Andrew Haley <aph@cygnus.com>
1787
1788 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1789 instructions.
1790
cff3e48b
JM		 1791Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1792
1793 * mips.igen (MULT): Correct previous mis-applied patch.
1794
d4f3574e
SS		 1795Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1796
1797 * mips.igen (delayslot32): Handle sequence like
1798 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1799 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1800 (MULT): Actually pass the third register...
1801
18021999-09-03 Mark Salter <msalter@cygnus.com>
1803
1804 * interp.c (sim_open): Added more memory aliases for additional
1805 hardware being touched by cygmon on jmr3904 board.
1806
1807Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1808
1809 * configure: Regenerated to track ../common/aclocal.m4 changes.
1810
a0b3c4fd
JM		 1811Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1812
1813 * interp.c (sim_store_register): Handle case where client - GDB -
1814 specifies that a 4 byte register is 8 bytes in size.
1815 (sim_fetch_register): Ditto.
72f4393d 1816
adf40b2e
JM		 18171999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1818
1819 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1820 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1821 (idt_monitor_base): Base address for IDT monitor traps.
1822 (pmon_monitor_base): Ditto for PMON.
1823 (lsipmon_monitor_base): Ditto for LSI PMON.
1824 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1825 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1826 (sim_firmware_command): New function.
1827 (mips_option_handler): Call it for OPTION_FIRMWARE.
1828 (sim_open): Allocate memory for idt_monitor region. If "--board"
1829 option was given, add no monitor by default. Add BREAK hooks only if
1830 monitors are also there.
72f4393d 1831
43e526b9
JM		 1832Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1833
1834 * interp.c (sim_monitor): Flush output before reading input.
1835
1836Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1837
1838 * tconfig.in (SIM_HANDLES_LMA): Always define.
1839
1840Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1841
1842 From Mark Salter <msalter@cygnus.com>:
1843 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1844 (sim_open): Add setup for BSP board.
1845
9846de1b
JM		 1846Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1847
1848 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1849 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1850 them as unimplemented.
1851
cd0fc7c3
SS		 18521999-05-08 Felix Lee <flee@cygnus.com>
1853
1854 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1855
7a292a7a
SS		 18561999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1857
1858 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1859
1860Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1861
1862 * configure.in: Any mips64vr5*-*-* target should have
1863 -DTARGET_ENABLE_FR=1.
1864 (default_endian): Any mips64vr*el-*-* target should default to
1865 LITTLE_ENDIAN.
1866 * configure: Re-generate.
1867
18681999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1869
1870 * mips.igen (ldl): Extend from _16_, not 32.
1871
1872Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1873
1874 * interp.c (sim_store_register): Force registers written to by GDB
1875 into an un-interpreted state.
1876
c906108c
SS		 18771999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1878
1879 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1880 CPU, start periodic background I/O polls.
72f4393d 1881 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1882
18831998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1884
1885 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1886
c906108c
SS		 1887Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1888
1889 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1890 case statement.
1891
18921998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1893
1894 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1895 (load_word): Call SIM_CORE_SIGNAL hook on error.
1896 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1897 starting. For exception dispatching, pass PC instead of NULL_CIA.
1898 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1899 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1900 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1901 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1902 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1903 * mips.igen (*): Replace memory-related SignalException* calls
1904 with references to SIM_CORE_SIGNAL hook.
72f4393d 1905
c906108c
SS		 1906 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1907 fix.
1908 * sim-main.c (*): Minor warning cleanups.
72f4393d 1909
c906108c
SS		 19101998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1911
1912 * m16.igen (DADDIU5): Correct type-o.
1913
1914Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1915
1916 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1917 variables.
1918
1919Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1920
1921 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1922 to include path.
1923 (interp.o): Add dependency on itable.h
1924 (oengine.c, gencode): Delete remaining references.
1925 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1926
c906108c 19271998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1928
c906108c
SS		 1929 * vr4run.c: New.
1930 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1931 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1932 tmp-run-hack) : New.
1933 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1934 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1935 Drop the "64" qualifier to get the HACK generator working.
1936 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1937 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1938 qualifier to get the hack generator working.
1939 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1940 (DSLL): Use do_dsll.
1941 (DSLLV): Use do_dsllv.
1942 (DSRA): Use do_dsra.
1943 (DSRL): Use do_dsrl.
1944 (DSRLV): Use do_dsrlv.
1945 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1946 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1947 get the HACK generator working.
1948 (MACC) Rename to get the HACK generator working.
1949 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1950
c906108c
SS		 19511998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1952
1953 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1954 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1955
c906108c
SS		 19561998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1957
1958 * mips/interp.c (DEBUG): Cleanups.
1959
19601998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1961
1962 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1963 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1964
c906108c
SS		 19651998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1966
1967 * interp.c (sim_close): Uninstall modules.
1968
1969Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1970
1971 * sim-main.h, interp.c (sim_monitor): Change to global
1972 function.
1973
1974Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1975
1976 * configure.in (vr4100): Only include vr4100 instructions in
1977 simulator.
1978 * configure: Re-generate.
1979 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1980
1981Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1982
1983 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1984 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1985 true alternative.
1986
1987 * configure.in (sim_default_gen, sim_use_gen): Replace with
1988 sim_gen.
1989 (--enable-sim-igen): Delete config option. Always using IGEN.
1990 * configure: Re-generate.
72f4393d 1991
c906108c
SS		 1992 * Makefile.in (gencode): Kill, kill, kill.
1993 * gencode.c: Ditto.
72f4393d 1994
c906108c
SS		 1995Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1996
1997 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1998 bit mips16 igen simulator.
1999 * configure: Re-generate.
2000
2001 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2002 as part of vr4100 ISA.
2003 * vr.igen: Mark all instructions as 64 bit only.
2004
2005Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2006
2007 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2008 Pacify GCC.
2009
2010Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2011
2012 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2013 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2014 * configure: Re-generate.
2015
2016 * m16.igen (BREAK): Define breakpoint instruction.
2017 (JALX32): Mark instruction as mips16 and not r3900.
2018 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2019
2020 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2021
2022Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2023
2024 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2025 insn as a debug breakpoint.
2026
2027 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2028 pending.slot_size.
2029 (PENDING_SCHED): Clean up trace statement.
2030 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2031 (PENDING_FILL): Delay write by only one cycle.
2032 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2033
2034 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2035 of pending writes.
2036 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2037 32 & 64.
2038 (pending_tick): Move incrementing of index to FOR statement.
2039 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2040
c906108c
SS		 2041 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2042 build simulator.
2043 * configure: Re-generate.
72f4393d 2044
c906108c
SS		 2045 * interp.c (sim_engine_run OLD): Delete explicit call to
2046 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2047
c906108c
SS		 2048Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2049
2050 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2051 interrupt level number to match changed SignalExceptionInterrupt
2052 macro.
2053
2054Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2055
2056 * interp.c: #include "itable.h" if WITH_IGEN.
2057 (get_insn_name): New function.
2058 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2059 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2060
2061Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2062
2063 * configure: Rebuilt to inhale new common/aclocal.m4.
2064
2065Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2066
2067 * dv-tx3904sio.c: Include sim-assert.h.
2068
2069Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2070
2071 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2072 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2073 Reorganize target-specific sim-hardware checks.
2074 * configure: rebuilt.
2075 * interp.c (sim_open): For tx39 target boards, set
2076 OPERATING_ENVIRONMENT, add tx3904sio devices.
2077 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2078 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2079
c906108c
SS		 2080 * dv-tx3904irc.c: Compiler warning clean-up.
2081 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2082 frequent hw-trace messages.
2083
2084Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2085
2086 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2087
2088Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2089
2090 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2091
2092 * vr.igen: New file.
2093 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2094 * mips.igen: Define vr4100 model. Include vr.igen.
2095Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2096
2097 * mips.igen (check_mf_hilo): Correct check.
2098
2099Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2100
2101 * sim-main.h (interrupt_event): Add prototype.
2102
2103 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2104 register_ptr, register_value.
2105 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2106
2107 * sim-main.h (tracefh): Make extern.
2108
2109Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2110
2111 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2112 Reduce unnecessarily high timer event frequency.
c906108c 2113 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2114
c906108c
SS		 2115Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2116
2117 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2118 to allay warnings.
2119 (interrupt_event): Made non-static.
72f4393d 2120
c906108c
SS		 2121 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2122 interchange of configuration values for external vs. internal
2123 clock dividers.
72f4393d 2124
c906108c
SS		 2125Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2126
72f4393d 2127 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2128 simulator-reserved break instructions.
2129 * gencode.c (build_instruction): Ditto.
2130 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2131 reserved instructions now use exception vector, rather
c906108c
SS		 2132 than halting sim.
2133 * sim-main.h: Moved magic constants to here.
2134
2135Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2136
2137 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2138 register upon non-zero interrupt event level, clear upon zero
2139 event value.
2140 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2141 by passing zero event value.
2142 (*_io_{read,write}_buffer): Endianness fixes.
2143 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2144 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2145
2146 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2147 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2148
c906108c
SS		 2149Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2150
72f4393d 2151 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2152 and BigEndianCPU.
2153
2154Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2155
2156 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2157 parts.
2158 * configure: Update.
2159
2160Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2161
2162 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2163 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2164 * configure.in: Include tx3904tmr in hw_device list.
2165 * configure: Rebuilt.
2166 * interp.c (sim_open): Instantiate three timer instances.
2167 Fix address typo of tx3904irc instance.
2168
2169Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2170
2171 * interp.c (signal_exception): SystemCall exception now uses
2172 the exception vector.
2173
2174Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2175
2176 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2177 to allay warnings.
2178
2179Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2180
2181 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2182
2183Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2184
2185 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2186
2187 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2188 sim-main.h. Declare a struct hw_descriptor instead of struct
2189 hw_device_descriptor.
2190
2191Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2192
2193 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2194 right bits and then re-align left hand bytes to correct byte
2195 lanes. Fix incorrect computation in do_store_left when loading
2196 bytes from second word.
2197
2198Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2199
2200 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2201 * interp.c (sim_open): Only create a device tree when HW is
2202 enabled.
2203
2204 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2205 * interp.c (signal_exception): Ditto.
2206
2207Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2208
2209 * gencode.c: Mark BEGEZALL as LIKELY.
2210
2211Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2212
2213 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2214 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2215
c906108c
SS		 2216Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2217
2218 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2219 modules. Recognize TX39 target with "mips*tx39" pattern.
2220 * configure: Rebuilt.
2221 * sim-main.h (*): Added many macros defining bits in
2222 TX39 control registers.
2223 (SignalInterrupt): Send actual PC instead of NULL.
2224 (SignalNMIReset): New exception type.
2225 * interp.c (board): New variable for future use to identify
2226 a particular board being simulated.
2227 (mips_option_handler,mips_options): Added "--board" option.
2228 (interrupt_event): Send actual PC.
2229 (sim_open): Make memory layout conditional on board setting.
2230 (signal_exception): Initial implementation of hardware interrupt
2231 handling. Accept another break instruction variant for simulator
2232 exit.
2233 (decode_coproc): Implement RFE instruction for TX39.
2234 (mips.igen): Decode RFE instruction as such.
2235 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2236 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2237 bbegin to implement memory map.
2238 * dv-tx3904cpu.c: New file.
2239 * dv-tx3904irc.c: New file.
2240
2241Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2242
2243 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2244
2245Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2246
2247 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2248 with calls to check_div_hilo.
2249
2250Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2251
2252 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2253 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2254 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2255 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2256 with calls to check_mult_hilo.
2257 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2258 with calls to check_div_hilo.
2259
2260Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2261
2262 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2263 Document a replacement.
2264
2265Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2266
2267 * interp.c (sim_monitor): Make mon_printf work.
2268
2269Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2270
2271 * sim-main.h (INSN_NAME): New arg `cpu'.
2272
2273Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2274
72f4393d 2275 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2276
2277Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2278
2279 * configure: Regenerated to track ../common/aclocal.m4 changes.
2280 * config.in: Ditto.
2281
2282Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2283
2284 * acconfig.h: New file.
2285 * configure.in: Reverted change of Apr 24; use sinclude again.
2286
2287Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2288
2289 * configure: Regenerated to track ../common/aclocal.m4 changes.
2290 * config.in: Ditto.
2291
2292Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2293
2294 * configure.in: Don't call sinclude.
2295
2296Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2297
2298 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2299
2300Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2301
2302 * mips.igen (ERET): Implement.
2303
2304 * interp.c (decode_coproc): Return sign-extended EPC.
2305
2306 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2307
2308 * interp.c (signal_exception): Do not ignore Trap.
2309 (signal_exception): On TRAP, restart at exception address.
2310 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2311 (signal_exception): Update.
2312 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2313 so that TRAP instructions are caught.
2314
2315Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2316
2317 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2318 contains HI/LO access history.
2319 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2320 (HIACCESS, LOACCESS): Delete, replace with
2321 (HIHISTORY, LOHISTORY): New macros.
2322 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2323
c906108c
SS		 2324 * gencode.c (build_instruction): Do not generate checks for
2325 correct HI/LO register usage.
2326
2327 * interp.c (old_engine_run): Delete checks for correct HI/LO
2328 register usage.
2329
2330 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2331 check_mf_cycles): New functions.
2332 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2333 do_divu, domultx, do_mult, do_multu): Use.
2334
2335 * tx.igen ("madd", "maddu"): Use.
72f4393d 2336
c906108c
SS		 2337Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2338
2339 * mips.igen (DSRAV): Use function do_dsrav.
2340 (SRAV): Use new function do_srav.
2341
2342 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2343 (B): Sign extend 11 bit immediate.
2344 (EXT-B*): Shift 16 bit immediate left by 1.
2345 (ADDIU*): Don't sign extend immediate value.
2346
2347Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2348
2349 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2350
2351 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2352 functions.
2353
2354 * mips.igen (delayslot32, nullify_next_insn): New functions.
2355 (m16.igen): Always include.
2356 (do_*): Add more tracing.
2357
2358 * m16.igen (delayslot16): Add NIA argument, could be called by a
2359 32 bit MIPS16 instruction.
72f4393d 2360
c906108c
SS		 2361 * interp.c (ifetch16): Move function from here.
2362 * sim-main.c (ifetch16): To here.
72f4393d 2363
c906108c
SS		 2364 * sim-main.c (ifetch16, ifetch32): Update to match current
2365 implementations of LH, LW.
2366 (signal_exception): Don't print out incorrect hex value of illegal
2367 instruction.
2368
2369Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2370
2371 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2372 instruction.
2373
2374 * m16.igen: Implement MIPS16 instructions.
72f4393d 2375
c906108c
SS		 2376 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2377 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2378 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2379 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2380 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2381 bodies of corresponding code from 32 bit insn to these. Also used
2382 by MIPS16 versions of functions.
72f4393d 2383
c906108c
SS		 2384 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2385 (IMEM16): Drop NR argument from macro.
2386
2387Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2388
2389 * Makefile.in (SIM_OBJS): Add sim-main.o.
2390
2391 * sim-main.h (address_translation, load_memory, store_memory,
2392 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2393 as INLINE_SIM_MAIN.
2394 (pr_addr, pr_uword64): Declare.
2395 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2396
c906108c
SS		 2397 * interp.c (address_translation, load_memory, store_memory,
2398 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2399 from here.
2400 * sim-main.c: To here. Fix compilation problems.
72f4393d 2401
c906108c
SS		 2402 * configure.in: Enable inlining.
2403 * configure: Re-config.
2404
2405Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2406
2407 * configure: Regenerated to track ../common/aclocal.m4 changes.
2408
2409Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2410
2411 * mips.igen: Include tx.igen.
2412 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2413 * tx.igen: New file, contains MADD and MADDU.
2414
2415 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2416 the hardwired constant `7'.
2417 (store_memory): Ditto.
2418 (LOADDRMASK): Move definition to sim-main.h.
2419
2420 mips.igen (MTC0): Enable for r3900.
2421 (ADDU): Add trace.
2422
2423 mips.igen (do_load_byte): Delete.
2424 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2425 do_store_right): New functions.
2426 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2427
2428 configure.in: Let the tx39 use igen again.
2429 configure: Update.
72f4393d 2430
c906108c
SS		 2431Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2432
2433 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2434 not an address sized quantity. Return zero for cache sizes.
2435
2436Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2437
2438 * mips.igen (r3900): r3900 does not support 64 bit integer
2439 operations.
2440
2441Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2442
2443 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2444 than igen one.
2445 * configure : Rebuild.
72f4393d 2446
c906108c
SS		 2447Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2448
2449 * configure: Regenerated to track ../common/aclocal.m4 changes.
2450
2451Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2452
2453 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2454
2455Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2456
2457 * configure: Regenerated to track ../common/aclocal.m4 changes.
2458 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2459
2460Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2461
2462 * configure: Regenerated to track ../common/aclocal.m4 changes.
2463
2464Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2465
2466 * interp.c (Max, Min): Comment out functions. Not yet used.
2467
2468Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2469
2470 * configure: Regenerated to track ../common/aclocal.m4 changes.
2471
2472Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2473
2474 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2475 configurable settings for stand-alone simulator.
72f4393d 2476
c906108c 2477 * configure.in: Added X11 search, just in case.
72f4393d 2478
c906108c
SS		 2479 * configure: Regenerated.
2480
2481Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2482
2483 * interp.c (sim_write, sim_read, load_memory, store_memory):
2484 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2485
2486Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2487
2488 * sim-main.h (GETFCC): Return an unsigned value.
2489
2490Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2491
2492 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2493 (DADD): Result destination is RD not RT.
2494
2495Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2496
2497 * sim-main.h (HIACCESS, LOACCESS): Always define.
2498
2499 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2500
2501 * interp.c (sim_info): Delete.
2502
2503Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2504
2505 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2506 (mips_option_handler): New argument `cpu'.
2507 (sim_open): Update call to sim_add_option_table.
2508
2509Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2510
2511 * mips.igen (CxC1): Add tracing.
2512
2513Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2514
2515 * sim-main.h (Max, Min): Declare.
2516
2517 * interp.c (Max, Min): New functions.
2518
2519 * mips.igen (BC1): Add tracing.
72f4393d 2520
c906108c 2521Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2522
c906108c 2523 * interp.c Added memory map for stack in vr4100
72f4393d 2524
c906108c
SS		 2525Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2526
2527 * interp.c (load_memory): Add missing "break"'s.
2528
2529Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2530
2531 * interp.c (sim_store_register, sim_fetch_register): Pass in
2532 length parameter. Return -1.
2533
2534Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2535
2536 * interp.c: Added hardware init hook, fixed warnings.
2537
2538Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2539
2540 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2541
2542Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2543
2544 * interp.c (ifetch16): New function.
2545
2546 * sim-main.h (IMEM32): Rename IMEM.
2547 (IMEM16_IMMED): Define.
2548 (IMEM16): Define.
2549 (DELAY_SLOT): Update.
72f4393d 2550
c906108c 2551 * m16run.c (sim_engine_run): New file.
72f4393d 2552
c906108c
SS		 2553 * m16.igen: All instructions except LB.
2554 (LB): Call do_load_byte.
2555 * mips.igen (do_load_byte): New function.
2556 (LB): Call do_load_byte.
2557
2558 * mips.igen: Move spec for insn bit size and high bit from here.
2559 * Makefile.in (tmp-igen, tmp-m16): To here.
2560
2561 * m16.dc: New file, decode mips16 instructions.
2562
2563 * Makefile.in (SIM_NO_ALL): Define.
2564 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2565
2566Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2567
2568 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2569 point unit to 32 bit registers.
2570 * configure: Re-generate.
2571
2572Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2573
2574 * configure.in (sim_use_gen): Make IGEN the default simulator
2575 generator for generic 32 and 64 bit mips targets.
2576 * configure: Re-generate.
2577
2578Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2579
2580 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2581 bitsize.
2582
2583 * interp.c (sim_fetch_register, sim_store_register): Read/write
2584 FGR from correct location.
2585 (sim_open): Set size of FGR's according to
2586 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2587
c906108c
SS		 2588 * sim-main.h (FGR): Store floating point registers in a separate
2589 array.
2590
2591Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2592
2593 * configure: Regenerated to track ../common/aclocal.m4 changes.
2594
2595Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2596
2597 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2598
2599 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2600
2601 * interp.c (pending_tick): New function. Deliver pending writes.
2602
2603 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2604 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2605 it can handle mixed sized quantites and single bits.
72f4393d 2606
c906108c
SS		 2607Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2608
2609 * interp.c (oengine.h): Do not include when building with IGEN.
2610 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2611 (sim_info): Ditto for PROCESSOR_64BIT.
2612 (sim_monitor): Replace ut_reg with unsigned_word.
2613 (*): Ditto for t_reg.
2614 (LOADDRMASK): Define.
2615 (sim_open): Remove defunct check that host FP is IEEE compliant,
2616 using software to emulate floating point.
2617 (value_fpr, ...): Always compile, was conditional on HASFPU.
2618
2619Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2620
2621 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2622 size.
2623
2624 * interp.c (SD, CPU): Define.
2625 (mips_option_handler): Set flags in each CPU.
2626 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2627 (sim_close): Do not clear STATE, deleted anyway.
2628 (sim_write, sim_read): Assume CPU zero's vm should be used for
2629 data transfers.
2630 (sim_create_inferior): Set the PC for all processors.
2631 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2632 argument.
2633 (mips16_entry): Pass correct nr of args to store_word, load_word.
2634 (ColdReset): Cold reset all cpu's.
2635 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2636 (sim_monitor, load_memory, store_memory, signal_exception): Use
2637 `CPU' instead of STATE_CPU.
2638
2639
2640 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2641 SD or CPU_.
72f4393d 2642
c906108c
SS		 2643 * sim-main.h (signal_exception): Add sim_cpu arg.
2644 (SignalException*): Pass both SD and CPU to signal_exception.
2645 * interp.c (signal_exception): Update.
72f4393d 2646
c906108c
SS		 2647 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2648 Ditto
2649 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2650 address_translation): Ditto
2651 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2652
c906108c
SS		 2653Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2654
2655 * configure: Regenerated to track ../common/aclocal.m4 changes.
2656
2657Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2658
2659 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2660
72f4393d 2661 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2662
2663 * sim-main.h (CPU_CIA): Delete.
2664 (SET_CIA, GET_CIA): Define
2665
2666Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2667
2668 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2669 regiser.
2670
2671 * configure.in (default_endian): Configure a big-endian simulator
2672 by default.
2673 * configure: Re-generate.
72f4393d 2674
c906108c
SS		 2675Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2676
2677 * configure: Regenerated to track ../common/aclocal.m4 changes.
2678
2679Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2680
2681 * interp.c (sim_monitor): Handle Densan monitor outbyte
2682 and inbyte functions.
2683
26841997-12-29 Felix Lee <flee@cygnus.com>
2685
2686 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2687
2688Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2689
2690 * Makefile.in (tmp-igen): Arrange for $zero to always be
2691 reset to zero after every instruction.
2692
2693Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2694
2695 * configure: Regenerated to track ../common/aclocal.m4 changes.
2696 * config.in: Ditto.
2697
2698Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2699
2700 * mips.igen (MSUB): Fix to work like MADD.
2701 * gencode.c (MSUB): Similarly.
2702
2703Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2704
2705 * configure: Regenerated to track ../common/aclocal.m4 changes.
2706
2707Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2708
2709 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2710
2711Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2712
2713 * sim-main.h (sim-fpu.h): Include.
2714
2715 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2716 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2717 using host independant sim_fpu module.
2718
2719Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2720
2721 * interp.c (signal_exception): Report internal errors with SIGABRT
2722 not SIGQUIT.
2723
2724 * sim-main.h (C0_CONFIG): New register.
2725 (signal.h): No longer include.
2726
2727 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2728
2729Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2730
2731 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2732
2733Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2734
2735 * mips.igen: Tag vr5000 instructions.
2736 (ANDI): Was missing mipsIV model, fix assembler syntax.
2737 (do_c_cond_fmt): New function.
2738 (C.cond.fmt): Handle mips I-III which do not support CC field
2739 separatly.
2740 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2741 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2742 in IV3.2 spec.
2743 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2744 vr5000 which saves LO in a GPR separatly.
72f4393d 2745
c906108c
SS		 2746 * configure.in (enable-sim-igen): For vr5000, select vr5000
2747 specific instructions.
2748 * configure: Re-generate.
72f4393d 2749
c906108c
SS		 2750Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2751
2752 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2753
2754 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2755 fmt_uninterpreted_64 bit cases to switch. Convert to
2756 fmt_formatted,
2757
2758 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2759
2760 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2761 as specified in IV3.2 spec.
2762 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2763
2764Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2765
2766 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2767 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2768 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2769 PENDING_FILL versions of instructions. Simplify.
2770 (X): New function.
2771 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2772 instructions.
2773 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2774 a signed value.
2775 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2776
c906108c
SS		 2777 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2778 global.
2779 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2780
2781Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2782
2783 * gencode.c (build_mips16_operands): Replace IPC with cia.
2784
2785 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2786 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2787 IPC to `cia'.
2788 (UndefinedResult): Replace function with macro/function
2789 combination.
2790 (sim_engine_run): Don't save PC in IPC.
2791
2792 * sim-main.h (IPC): Delete.
2793
2794
2795 * interp.c (signal_exception, store_word, load_word,
2796 address_translation, load_memory, store_memory, cache_op,
2797 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2798 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2799 current instruction address - cia - argument.
2800 (sim_read, sim_write): Call address_translation directly.
2801 (sim_engine_run): Rename variable vaddr to cia.
2802 (signal_exception): Pass cia to sim_monitor
72f4393d 2803
c906108c
SS		 2804 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2805 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2806 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2807
2808 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2809 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2810 SIM_ASSERT.
72f4393d 2811
c906108c
SS		 2812 * interp.c (signal_exception): Pass restart address to
2813 sim_engine_restart.
2814
2815 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2816 idecode.o): Add dependency.
2817
2818 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2819 Delete definitions
2820 (DELAY_SLOT): Update NIA not PC with branch address.
2821 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2822
2823 * mips.igen: Use CIA not PC in branch calculations.
2824 (illegal): Call SignalException.
2825 (BEQ, ADDIU): Fix assembler.
2826
2827Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2828
2829 * m16.igen (JALX): Was missing.
2830
2831 * configure.in (enable-sim-igen): New configuration option.
2832 * configure: Re-generate.
72f4393d 2833
c906108c
SS		 2834 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2835
2836 * interp.c (load_memory, store_memory): Delete parameter RAW.
2837 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2838 bypassing {load,store}_memory.
2839
2840 * sim-main.h (ByteSwapMem): Delete definition.
2841
2842 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2843
2844 * interp.c (sim_do_command, sim_commands): Delete mips specific
2845 commands. Handled by module sim-options.
72f4393d 2846
c906108c
SS		 2847 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2848 (WITH_MODULO_MEMORY): Define.
2849
2850 * interp.c (sim_info): Delete code printing memory size.
2851
2852 * interp.c (mips_size): Nee sim_size, delete function.
2853 (power2): Delete.
2854 (monitor, monitor_base, monitor_size): Delete global variables.
2855 (sim_open, sim_close): Delete code creating monitor and other
2856 memory regions. Use sim-memopts module, via sim_do_commandf, to
2857 manage memory regions.
2858 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2859
c906108c
SS		 2860 * interp.c (address_translation): Delete all memory map code
2861 except line forcing 32 bit addresses.
2862
2863Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2864
2865 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2866 trace options.
2867
2868 * interp.c (logfh, logfile): Delete globals.
2869 (sim_open, sim_close): Delete code opening & closing log file.
2870 (mips_option_handler): Delete -l and -n options.
2871 (OPTION mips_options): Ditto.
2872
2873 * interp.c (OPTION mips_options): Rename option trace to dinero.
2874 (mips_option_handler): Update.
2875
2876Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2877
2878 * interp.c (fetch_str): New function.
2879 (sim_monitor): Rewrite using sim_read & sim_write.
2880 (sim_open): Check magic number.
2881 (sim_open): Write monitor vectors into memory using sim_write.
2882 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2883 (sim_read, sim_write): Simplify - transfer data one byte at a
2884 time.
2885 (load_memory, store_memory): Clarify meaning of parameter RAW.
2886
2887 * sim-main.h (isHOST): Defete definition.
2888 (isTARGET): Mark as depreciated.
2889 (address_translation): Delete parameter HOST.
2890
2891 * interp.c (address_translation): Delete parameter HOST.
2892
2893Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2894
72f4393d 2895 * mips.igen:
c906108c
SS		 2896
2897 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2898 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2899
2900Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2901
2902 * mips.igen: Add model filter field to records.
2903
2904Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2905
2906 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2907
c906108c
SS		 2908 interp.c (sim_engine_run): Do not compile function sim_engine_run
2909 when WITH_IGEN == 1.
2910
2911 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2912 target architecture.
2913
2914 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2915 igen. Replace with configuration variables sim_igen_flags /
2916 sim_m16_flags.
2917
2918 * m16.igen: New file. Copy mips16 insns here.
2919 * mips.igen: From here.
2920
2921Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2922
2923 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2924 to top.
2925 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2926
2927Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2928
2929 * gencode.c (build_instruction): Follow sim_write's lead in using
2930 BigEndianMem instead of !ByteSwapMem.
2931
2932Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2933
2934 * configure.in (sim_gen): Dependent on target, select type of
2935 generator. Always select old style generator.
2936
2937 configure: Re-generate.
2938
2939 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2940 targets.
2941 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2942 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2943 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2944 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2945 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2946
c906108c
SS		 2947Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2948
2949 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2950
2951 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2952 CURRENT_FLOATING_POINT instead.
2953
2954 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2955 (address_translation): Raise exception InstructionFetch when
2956 translation fails and isINSTRUCTION.
72f4393d 2957
c906108c
SS		 2958 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2959 sim_engine_run): Change type of of vaddr and paddr to
2960 address_word.
2961 (address_translation, prefetch, load_memory, store_memory,
2962 cache_op): Change type of vAddr and pAddr to address_word.
2963
2964 * gencode.c (build_instruction): Change type of vaddr and paddr to
2965 address_word.
2966
2967Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2968
2969 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2970 macro to obtain result of ALU op.
2971
2972Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2973
2974 * interp.c (sim_info): Call profile_print.
2975
2976Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2977
2978 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2979
2980 * sim-main.h (WITH_PROFILE): Do not define, defined in
2981 common/sim-config.h. Use sim-profile module.
2982 (simPROFILE): Delete defintion.
2983
2984 * interp.c (PROFILE): Delete definition.
2985 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2986 (sim_close): Delete code writing profile histogram.
2987 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2988 Delete.
2989 (sim_engine_run): Delete code profiling the PC.
2990
2991Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2992
2993 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2994
2995 * interp.c (sim_monitor): Make register pointers of type
2996 unsigned_word*.
2997
2998 * sim-main.h: Make registers of type unsigned_word not
2999 signed_word.
3000
3001Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3002
3003 * interp.c (sync_operation): Rename from SyncOperation, make
3004 global, add SD argument.
3005 (prefetch): Rename from Prefetch, make global, add SD argument.
3006 (decode_coproc): Make global.
3007
3008 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3009
3010 * gencode.c (build_instruction): Generate DecodeCoproc not
3011 decode_coproc calls.
3012
3013 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3014 (SizeFGR): Move to sim-main.h
3015 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3016 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3017 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3018 sim-main.h.
3019 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3020 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3021 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3022 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3023 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3024 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3025
c906108c
SS		 3026 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3027 exception.
3028 (sim-alu.h): Include.
3029 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3030 (sim_cia): Typedef to instruction_address.
72f4393d 3031
c906108c
SS		 3032Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3033
3034 * Makefile.in (interp.o): Rename generated file engine.c to
3035 oengine.c.
72f4393d 3036
c906108c 3037 * interp.c: Update.
72f4393d 3038
c906108c
SS		 3039Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3040
3041 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3042
c906108c
SS		 3043Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3044
3045 * gencode.c (build_instruction): For "FPSQRT", output correct
3046 number of arguments to Recip.
72f4393d 3047
c906108c
SS		 3048Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3049
3050 * Makefile.in (interp.o): Depends on sim-main.h
3051
3052 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3053
3054 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3055 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3056 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3057 STATE, DSSTATE): Define
3058 (GPR, FGRIDX, ..): Define.
3059
3060 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3061 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3062 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3063
c906108c 3064 * interp.c: Update names to match defines from sim-main.h
72f4393d 3065
c906108c
SS		 3066Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3067
3068 * interp.c (sim_monitor): Add SD argument.
3069 (sim_warning): Delete. Replace calls with calls to
3070 sim_io_eprintf.
3071 (sim_error): Delete. Replace calls with sim_io_error.
3072 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3073 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3074 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3075 argument.
3076 (mips_size): Rename from sim_size. Add SD argument.
3077
3078 * interp.c (simulator): Delete global variable.
3079 (callback): Delete global variable.
3080 (mips_option_handler, sim_open, sim_write, sim_read,
3081 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3082 sim_size,sim_monitor): Use sim_io_* not callback->*.
3083 (sim_open): ZALLOC simulator struct.
3084 (PROFILE): Do not define.
3085
3086Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3087
3088 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3089 support.h with corresponding code.
3090
3091 * sim-main.h (word64, uword64), support.h: Move definition to
3092 sim-main.h.
3093 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3094
3095 * support.h: Delete
3096 * Makefile.in: Update dependencies
3097 * interp.c: Do not include.
72f4393d 3098
c906108c
SS		 3099Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3100
3101 * interp.c (address_translation, load_memory, store_memory,
3102 cache_op): Rename to from AddressTranslation et.al., make global,
3103 add SD argument
72f4393d 3104
c906108c
SS		 3105 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3106 CacheOp): Define.
72f4393d 3107
c906108c
SS		 3108 * interp.c (SignalException): Rename to signal_exception, make
3109 global.
3110
3111 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3112
c906108c
SS		 3113 * sim-main.h (SignalException, SignalExceptionInterrupt,
3114 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3115 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3116 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3117 Define.
72f4393d 3118
c906108c 3119 * interp.c, support.h: Use.
72f4393d 3120
c906108c
SS		 3121Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3122
3123 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3124 to value_fpr / store_fpr. Add SD argument.
3125 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3126 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3127
3128 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3129
c906108c
SS		 3130Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3131
3132 * interp.c (sim_engine_run): Check consistency between configure
3133 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3134 and HASFPU.
3135
3136 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3137 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3138 (mips_endian): Configure WITH_TARGET_ENDIAN.
3139 * configure: Update.
3140
3141Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3142
3143 * configure: Regenerated to track ../common/aclocal.m4 changes.
3144
3145Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3146
3147 * configure: Regenerated.
3148
3149Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3150
3151 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3152
3153Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3154
3155 * gencode.c (print_igen_insn_models): Assume certain architectures
3156 include all mips* instructions.
3157 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3158 instruction.
3159
3160 * Makefile.in (tmp.igen): Add target. Generate igen input from
3161 gencode file.
3162
3163 * gencode.c (FEATURE_IGEN): Define.
3164 (main): Add --igen option. Generate output in igen format.
3165 (process_instructions): Format output according to igen option.
3166 (print_igen_insn_format): New function.
3167 (print_igen_insn_models): New function.
3168 (process_instructions): Only issue warnings and ignore
3169 instructions when no FEATURE_IGEN.
3170
3171Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3172
3173 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3174 MIPS targets.
3175
3176Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3177
3178 * configure: Regenerated to track ../common/aclocal.m4 changes.
3179
3180Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3181
3182 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3183 SIM_RESERVED_BITS): Delete, moved to common.
3184 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3185
c906108c
SS		 3186Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3187
3188 * configure.in: Configure non-strict memory alignment.
3189 * configure: Regenerated to track ../common/aclocal.m4 changes.
3190
3191Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3192
3193 * configure: Regenerated to track ../common/aclocal.m4 changes.
3194
3195Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3196
3197 * gencode.c (SDBBP,DERET): Added (3900) insns.
3198 (RFE): Turn on for 3900.
3199 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3200 (dsstate): Made global.
3201 (SUBTARGET_R3900): Added.
3202 (CANCELDELAYSLOT): New.
3203 (SignalException): Ignore SystemCall rather than ignore and
3204 terminate. Add DebugBreakPoint handling.
3205 (decode_coproc): New insns RFE, DERET; and new registers Debug
3206 and DEPC protected by SUBTARGET_R3900.
3207 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3208 bits explicitly.
3209 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3210 * configure: Update.
c906108c
SS		 3211
3212Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3213
3214 * gencode.c: Add r3900 (tx39).
72f4393d 3215
c906108c
SS		 3216
3217Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3218
3219 * gencode.c (build_instruction): Don't need to subtract 4 for
3220 JALR, just 2.
3221
3222Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3223
3224 * interp.c: Correct some HASFPU problems.
3225
3226Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3227
3228 * configure: Regenerated to track ../common/aclocal.m4 changes.
3229
3230Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3231
3232 * interp.c (mips_options): Fix samples option short form, should
3233 be `x'.
3234
3235Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3236
3237 * interp.c (sim_info): Enable info code. Was just returning.
3238
3239Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3240
3241 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3242 MFC0.
3243
3244Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3245
3246 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3247 constants.
3248 (build_instruction): Ditto for LL.
3249
3250Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3251
3252 * configure: Regenerated to track ../common/aclocal.m4 changes.
3253
3254Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3255
3256 * configure: Regenerated to track ../common/aclocal.m4 changes.
3257 * config.in: Ditto.
3258
3259Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3260
3261 * interp.c (sim_open): Add call to sim_analyze_program, update
3262 call to sim_config.
3263
3264Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3265
3266 * interp.c (sim_kill): Delete.
3267 (sim_create_inferior): Add ABFD argument. Set PC from same.
3268 (sim_load): Move code initializing trap handlers from here.
3269 (sim_open): To here.
3270 (sim_load): Delete, use sim-hload.c.
3271
3272 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3273
3274Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3275
3276 * configure: Regenerated to track ../common/aclocal.m4 changes.
3277 * config.in: Ditto.
3278
3279Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3280
3281 * interp.c (sim_open): Add ABFD argument.
3282 (sim_load): Move call to sim_config from here.
3283 (sim_open): To here. Check return status.
3284
3285Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3286
c906108c
SS		 3287 * gencode.c (build_instruction): Two arg MADD should
3288 not assign result to $0.
72f4393d 3289
c906108c
SS		 3290Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3291
3292 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3293 * sim/mips/configure.in: Regenerate.
3294
3295Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3296
3297 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3298 signed8, unsigned8 et.al. types.
3299
3300 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3301 hosts when selecting subreg.
3302
3303Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3304
3305 * interp.c (sim_engine_run): Reset the ZERO register to zero
3306 regardless of FEATURE_WARN_ZERO.
3307 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3308
3309Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3310
3311 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3312 (SignalException): For BreakPoints ignore any mode bits and just
3313 save the PC.
3314 (SignalException): Always set the CAUSE register.
3315
3316Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3317
3318 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3319 exception has been taken.
3320
3321 * interp.c: Implement the ERET and mt/f sr instructions.
3322
3323Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3324
3325 * interp.c (SignalException): Don't bother restarting an
3326 interrupt.
3327
3328Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3329
3330 * interp.c (SignalException): Really take an interrupt.
3331 (interrupt_event): Only deliver interrupts when enabled.
3332
3333Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3334
3335 * interp.c (sim_info): Only print info when verbose.
3336 (sim_info) Use sim_io_printf for output.
72f4393d 3337
c906108c
SS		 3338Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3339
3340 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3341 mips architectures.
3342
3343Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3344
3345 * interp.c (sim_do_command): Check for common commands if a
3346 simulator specific command fails.
3347
3348Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3349
3350 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3351 and simBE when DEBUG is defined.
3352
3353Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3354
3355 * interp.c (interrupt_event): New function. Pass exception event
3356 onto exception handler.
3357
3358 * configure.in: Check for stdlib.h.
3359 * configure: Regenerate.
3360
3361 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3362 variable declaration.
3363 (build_instruction): Initialize memval1.
3364 (build_instruction): Add UNUSED attribute to byte, bigend,
3365 reverse.
3366 (build_operands): Ditto.
3367
3368 * interp.c: Fix GCC warnings.
3369 (sim_get_quit_code): Delete.
3370
3371 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3372 * Makefile.in: Ditto.
3373 * configure: Re-generate.
72f4393d 3374
c906108c
SS		 3375 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3376
3377Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3378
3379 * interp.c (mips_option_handler): New function parse argumes using
3380 sim-options.
3381 (myname): Replace with STATE_MY_NAME.
3382 (sim_open): Delete check for host endianness - performed by
3383 sim_config.
3384 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3385 (sim_open): Move much of the initialization from here.
3386 (sim_load): To here. After the image has been loaded and
3387 endianness set.
3388 (sim_open): Move ColdReset from here.
3389 (sim_create_inferior): To here.
3390 (sim_open): Make FP check less dependant on host endianness.
3391
3392 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3393 run.
3394 * interp.c (sim_set_callbacks): Delete.
3395
3396 * interp.c (membank, membank_base, membank_size): Replace with
3397 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3398 (sim_open): Remove call to callback->init. gdb/run do this.
3399
3400 * interp.c: Update
3401
3402 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3403
3404 * interp.c (big_endian_p): Delete, replaced by
3405 current_target_byte_order.
3406
3407Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3408
3409 * interp.c (host_read_long, host_read_word, host_swap_word,
3410 host_swap_long): Delete. Using common sim-endian.
3411 (sim_fetch_register, sim_store_register): Use H2T.
3412 (pipeline_ticks): Delete. Handled by sim-events.
3413 (sim_info): Update.
3414 (sim_engine_run): Update.
3415
3416Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3417
3418 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3419 reason from here.
3420 (SignalException): To here. Signal using sim_engine_halt.
3421 (sim_stop_reason): Delete, moved to common.
72f4393d 3422
c906108c
SS		 3423Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3424
3425 * interp.c (sim_open): Add callback argument.
3426 (sim_set_callbacks): Delete SIM_DESC argument.
3427 (sim_size): Ditto.
3428
3429Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3430
3431 * Makefile.in (SIM_OBJS): Add common modules.
3432
3433 * interp.c (sim_set_callbacks): Also set SD callback.
3434 (set_endianness, xfer_*, swap_*): Delete.
3435 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3436 Change to functions using sim-endian macros.
3437 (control_c, sim_stop): Delete, use common version.
3438 (simulate): Convert into.
3439 (sim_engine_run): This function.
3440 (sim_resume): Delete.
72f4393d 3441
c906108c
SS		 3442 * interp.c (simulation): New variable - the simulator object.
3443 (sim_kind): Delete global - merged into simulation.
3444 (sim_load): Cleanup. Move PC assignment from here.
3445 (sim_create_inferior): To here.
3446
3447 * sim-main.h: New file.
3448 * interp.c (sim-main.h): Include.
72f4393d 3449
c906108c
SS		 3450Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3451
3452 * configure: Regenerated to track ../common/aclocal.m4 changes.
3453
3454Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3455
3456 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3457
3458Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3459
72f4393d
L		 3460 * gencode.c (build_instruction): DIV instructions: check
3461 for division by zero and integer overflow before using
c906108c
SS		 3462 host's division operation.
3463
3464Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3465
3466 * Makefile.in (SIM_OBJS): Add sim-load.o.
3467 * interp.c: #include bfd.h.
3468 (target_byte_order): Delete.
3469 (sim_kind, myname, big_endian_p): New static locals.
3470 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3471 after argument parsing. Recognize -E arg, set endianness accordingly.
3472 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3473 load file into simulator. Set PC from bfd.
3474 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3475 (set_endianness): Use big_endian_p instead of target_byte_order.
3476
3477Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3478
3479 * interp.c (sim_size): Delete prototype - conflicts with
3480 definition in remote-sim.h. Correct definition.
3481
3482Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3483
3484 * configure: Regenerated to track ../common/aclocal.m4 changes.
3485 * config.in: Ditto.
3486
3487Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3488
3489 * interp.c (sim_open): New arg `kind'.
3490
3491 * configure: Regenerated to track ../common/aclocal.m4 changes.
3492
3493Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3494
3495 * configure: Regenerated to track ../common/aclocal.m4 changes.
3496
3497Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3498
3499 * interp.c (sim_open): Set optind to 0 before calling getopt.
3500
3501Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3502
3503 * configure: Regenerated to track ../common/aclocal.m4 changes.
3504
3505Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3506
3507 * interp.c : Replace uses of pr_addr with pr_uword64
3508 where the bit length is always 64 independent of SIM_ADDR.
3509 (pr_uword64) : added.
3510
3511Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3512
3513 * configure: Re-generate.
3514
3515Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3516
3517 * configure: Regenerate to track ../common/aclocal.m4 changes.
3518
3519Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3520
3521 * interp.c (sim_open): New SIM_DESC result. Argument is now
3522 in argv form.
3523 (other sim_*): New SIM_DESC argument.
3524
3525Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3526
3527 * interp.c: Fix printing of addresses for non-64-bit targets.
3528 (pr_addr): Add function to print address based on size.
3529
3530Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3531
3532 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3533
3534Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3535
3536 * gencode.c (build_mips16_operands): Correct computation of base
3537 address for extended PC relative instruction.
3538
3539Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3540
3541 * interp.c (mips16_entry): Add support for floating point cases.
3542 (SignalException): Pass floating point cases to mips16_entry.
3543 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3544 registers.
3545 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3546 or fmt_word.
3547 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3548 and then set the state to fmt_uninterpreted.
3549 (COP_SW): Temporarily set the state to fmt_word while calling
3550 ValueFPR.
3551
3552Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3553
3554 * gencode.c (build_instruction): The high order may be set in the
3555 comparison flags at any ISA level, not just ISA 4.
3556
3557Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3558
3559 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3560 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3561 * configure.in: sinclude ../common/aclocal.m4.
3562 * configure: Regenerated.
3563
3564Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3565
3566 * configure: Rebuild after change to aclocal.m4.
3567
3568Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3569
3570 * configure configure.in Makefile.in: Update to new configure
3571 scheme which is more compatible with WinGDB builds.
3572 * configure.in: Improve comment on how to run autoconf.
3573 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3574 * Makefile.in: Use autoconf substitution to install common
3575 makefile fragment.
3576
3577Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3578
3579 * gencode.c (build_instruction): Use BigEndianCPU instead of
3580 ByteSwapMem.
3581
3582Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3583
3584 * interp.c (sim_monitor): Make output to stdout visible in
3585 wingdb's I/O log window.
3586
3587Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3588
3589 * support.h: Undo previous change to SIGTRAP
3590 and SIGQUIT values.
3591
3592Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3593
3594 * interp.c (store_word, load_word): New static functions.
3595 (mips16_entry): New static function.
3596 (SignalException): Look for mips16 entry and exit instructions.
3597 (simulate): Use the correct index when setting fpr_state after
3598 doing a pending move.
3599
3600Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3601
3602 * interp.c: Fix byte-swapping code throughout to work on
3603 both little- and big-endian hosts.
3604
3605Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3606
3607 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3608 with gdb/config/i386/xm-windows.h.
3609
3610Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3611
3612 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3613 that messes up arithmetic shifts.
3614
3615Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3616
3617 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3618 SIGTRAP and SIGQUIT for _WIN32.
3619
3620Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3621
3622 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3623 force a 64 bit multiplication.
3624 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3625 destination register is 0, since that is the default mips16 nop
3626 instruction.
3627
3628Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3629
3630 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3631 (build_endian_shift): Don't check proc64.
3632 (build_instruction): Always set memval to uword64. Cast op2 to
3633 uword64 when shifting it left in memory instructions. Always use
3634 the same code for stores--don't special case proc64.
3635
3636 * gencode.c (build_mips16_operands): Fix base PC value for PC
3637 relative operands.
3638 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3639 jal instruction.
3640 * interp.c (simJALDELAYSLOT): Define.
3641 (JALDELAYSLOT): Define.
3642 (INDELAYSLOT, INJALDELAYSLOT): Define.
3643 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3644
3645Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3646
3647 * interp.c (sim_open): add flush_cache as a PMON routine
3648 (sim_monitor): handle flush_cache by ignoring it
3649
3650Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3651
3652 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3653 BigEndianMem.
3654 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3655 (BigEndianMem): Rename to ByteSwapMem and change sense.
3656 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3657 BigEndianMem references to !ByteSwapMem.
3658 (set_endianness): New function, with prototype.
3659 (sim_open): Call set_endianness.
3660 (sim_info): Use simBE instead of BigEndianMem.
3661 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3662 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3663 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3664 ifdefs, keeping the prototype declaration.
3665 (swap_word): Rewrite correctly.
3666 (ColdReset): Delete references to CONFIG. Delete endianness related
3667 code; moved to set_endianness.
72f4393d 3668
c906108c
SS		 3669Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3670
3671 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3672 * interp.c (CHECKHILO): Define away.
3673 (simSIGINT): New macro.
3674 (membank_size): Increase from 1MB to 2MB.
3675 (control_c): New function.
3676 (sim_resume): Rename parameter signal to signal_number. Add local
3677 variable prev. Call signal before and after simulate.
3678 (sim_stop_reason): Add simSIGINT support.
3679 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3680 functions always.
3681 (sim_warning): Delete call to SignalException. Do call printf_filtered
3682 if logfh is NULL.
3683 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3684 a call to sim_warning.
3685
3686Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3687
3688 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3689 16 bit instructions.
3690
3691Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3692
3693 Add support for mips16 (16 bit MIPS implementation):
3694 * gencode.c (inst_type): Add mips16 instruction encoding types.
3695 (GETDATASIZEINSN): Define.
3696 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3697 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3698 mtlo.
3699 (MIPS16_DECODE): New table, for mips16 instructions.
3700 (bitmap_val): New static function.
3701 (struct mips16_op): Define.
3702 (mips16_op_table): New table, for mips16 operands.
3703 (build_mips16_operands): New static function.
3704 (process_instructions): If PC is odd, decode a mips16
3705 instruction. Break out instruction handling into new
3706 build_instruction function.
3707 (build_instruction): New static function, broken out of
3708 process_instructions. Check modifiers rather than flags for SHIFT
3709 bit count and m[ft]{hi,lo} direction.
3710 (usage): Pass program name to fprintf.
3711 (main): Remove unused variable this_option_optind. Change
3712 ``*loptarg++'' to ``loptarg++''.
3713 (my_strtoul): Parenthesize && within ||.
3714 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3715 (simulate): If PC is odd, fetch a 16 bit instruction, and
3716 increment PC by 2 rather than 4.
3717 * configure.in: Add case for mips16*-*-*.
3718 * configure: Rebuild.
3719
3720Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3721
3722 * interp.c: Allow -t to enable tracing in standalone simulator.
3723 Fix garbage output in trace file and error messages.
3724
3725Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3726
3727 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3728 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3729 * configure.in: Simplify using macros in ../common/aclocal.m4.
3730 * configure: Regenerated.
3731 * tconfig.in: New file.
3732
3733Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3734
3735 * interp.c: Fix bugs in 64-bit port.
3736 Use ansi function declarations for msvc compiler.
3737 Initialize and test file pointer in trace code.
3738 Prevent duplicate definition of LAST_EMED_REGNUM.
3739
3740Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3741
3742 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3743
3744Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3745
3746 * interp.c (SignalException): Check for explicit terminating
3747 breakpoint value.
3748 * gencode.c: Pass instruction value through SignalException()
3749 calls for Trap, Breakpoint and Syscall.
3750
3751Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3752
3753 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3754 only used on those hosts that provide it.
3755 * configure.in: Add sqrt() to list of functions to be checked for.
3756 * config.in: Re-generated.
3757 * configure: Re-generated.
3758
3759Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3760
3761 * gencode.c (process_instructions): Call build_endian_shift when
3762 expanding STORE RIGHT, to fix swr.
3763 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3764 clear the high bits.
3765 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3766 Fix float to int conversions to produce signed values.
3767
3768Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3769
3770 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3771 (process_instructions): Correct handling of nor instruction.
3772 Correct shift count for 32 bit shift instructions. Correct sign
3773 extension for arithmetic shifts to not shift the number of bits in
3774 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3775 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3776 Fix madd.
3777 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3778 It's OK to have a mult follow a mult. What's not OK is to have a
3779 mult follow an mfhi.
3780 (Convert): Comment out incorrect rounding code.
3781
3782Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3783
3784 * interp.c (sim_monitor): Improved monitor printf
3785 simulation. Tidied up simulator warnings, and added "--log" option
3786 for directing warning message output.
3787 * gencode.c: Use sim_warning() rather than WARNING macro.
3788
3789Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3790
3791 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3792 getopt1.o, rather than on gencode.c. Link objects together.
3793 Don't link against -liberty.
3794 (gencode.o, getopt.o, getopt1.o): New targets.
3795 * gencode.c: Include <ctype.h> and "ansidecl.h".
3796 (AND): Undefine after including "ansidecl.h".
3797 (ULONG_MAX): Define if not defined.
3798 (OP_*): Don't define macros; now defined in opcode/mips.h.
3799 (main): Call my_strtoul rather than strtoul.
3800 (my_strtoul): New static function.
3801
3802Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3803
3804 * gencode.c (process_instructions): Generate word64 and uword64
3805 instead of `long long' and `unsigned long long' data types.
3806 * interp.c: #include sysdep.h to get signals, and define default
3807 for SIGBUS.
3808 * (Convert): Work around for Visual-C++ compiler bug with type
3809 conversion.
3810 * support.h: Make things compile under Visual-C++ by using
3811 __int64 instead of `long long'. Change many refs to long long
3812 into word64/uword64 typedefs.
3813
3814Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3815
72f4393d
L		 3816 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3817 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3818 (docdir): Removed.
3819 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3820 (AC_PROG_INSTALL): Added.
c906108c 3821 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3822 * configure: Rebuilt.
3823
c906108c
SS		 3824Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3825
3826 * configure.in: Define @SIMCONF@ depending on mips target.
3827 * configure: Rebuild.
3828 * Makefile.in (run): Add @SIMCONF@ to control simulator
3829 construction.
3830 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3831 * interp.c: Remove some debugging, provide more detailed error
3832 messages, update memory accesses to use LOADDRMASK.
72f4393d 3833
c906108c
SS		 3834Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3835
3836 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3837 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3838 stamp-h.
3839 * configure: Rebuild.
3840 * config.in: New file, generated by autoheader.
3841 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3842 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3843 HAVE_ANINT and HAVE_AINT, as appropriate.
3844 * Makefile.in (run): Use @LIBS@ rather than -lm.
3845 (interp.o): Depend upon config.h.
3846 (Makefile): Just rebuild Makefile.
3847 (clean): Remove stamp-h.
3848 (mostlyclean): Make the same as clean, not as distclean.
3849 (config.h, stamp-h): New targets.
3850
3851Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3852
3853 * interp.c (ColdReset): Fix boolean test. Make all simulator
3854 globals static.
3855
3856Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3857
3858 * interp.c (xfer_direct_word, xfer_direct_long,
3859 swap_direct_word, swap_direct_long, xfer_big_word,
3860 xfer_big_long, xfer_little_word, xfer_little_long,
3861 swap_word,swap_long): Added.
3862 * interp.c (ColdReset): Provide function indirection to
3863 host<->simulated_target transfer routines.
3864 * interp.c (sim_store_register, sim_fetch_register): Updated to
3865 make use of indirected transfer routines.
3866
3867Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3868
3869 * gencode.c (process_instructions): Ensure FP ABS instruction
3870 recognised.
3871 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3872 system call support.
3873
3874Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3875
3876 * interp.c (sim_do_command): Complain if callback structure not
3877 initialised.
3878
3879Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3880
3881 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3882 support for Sun hosts.
3883 * Makefile.in (gencode): Ensure the host compiler and libraries
3884 used for cross-hosted build.
3885
3886Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3887
3888 * interp.c, gencode.c: Some more (TODO) tidying.
3889
3890Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3891
3892 * gencode.c, interp.c: Replaced explicit long long references with
3893 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3894 * support.h (SET64LO, SET64HI): Macros added.
3895
3896Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3897
3898 * configure: Regenerate with autoconf 2.7.
3899
3900Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3901
3902 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3903 * support.h: Remove superfluous "1" from #if.
3904 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3905
3906Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3907
3908 * interp.c (StoreFPR): Control UndefinedResult() call on
3909 WARN_RESULT manifest.
3910
3911Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3912
3913 * gencode.c: Tidied instruction decoding, and added FP instruction
3914 support.
3915
3916 * interp.c: Added dineroIII, and BSD profiling support. Also
3917 run-time FP handling.
3918
3919Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3920
3921 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3922 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
This page took 1.276503 seconds and 4 git commands to generate.