projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sim: delete dead current_state globals
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
d47f5b30
MF		 12016-01-02 Mike Frysinger <vapier@gentoo.org>
2
3 * dv-tx3904cpu.c (CPU, SD): Delete.
4
e1211e55
MF		 52015-12-30 Mike Frysinger <vapier@gentoo.org>
6
7 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
8 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
9 (sim_store_register): Rename to ...
10 (mips_reg_store): ... this. Delete local cpu var.
11 Update sim_io_eprintf calls.
12 (sim_fetch_register): Rename to ...
13 (mips_reg_fetch): ... this. Delete local cpu var.
14 Update sim_io_eprintf calls.
15
5e744ef8
MF		 162015-12-27 Mike Frysinger <vapier@gentoo.org>
17
18 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
19
1b393626
MF		 202015-12-26 Mike Frysinger <vapier@gentoo.org>
21
22 * config.in, configure: Regenerate.
23
26f8bf63
MF		 242015-12-26 Mike Frysinger <vapier@gentoo.org>
25
26 * interp.c (sim_write, sim_read): Delete.
27 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
28 (load_word): Likewise.
29 * micromips.igen (cache): Likewise.
30 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
31 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
32 do_store_left, do_store_right, do_load_double, do_store_double):
33 Likewise.
34 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
35 (do_prefx): Likewise.
36 * sim-main.c (address_translation, prefetch): Delete.
37 (ifetch32, ifetch16): Delete call to AddressTranslation and set
38 paddr=vaddr.
39 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
40 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
41 (LoadMemory, StoreMemory): Delete CCA arg.
42
ef04e371
MF		 432015-12-24 Mike Frysinger <vapier@gentoo.org>
44
45 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
46 * configure: Regenerated.
47
cb379ede
MF		 482015-12-24 Mike Frysinger <vapier@gentoo.org>
49
50 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
51 * tconfig.h: Delete.
52
26936211
MF		 532015-12-24 Mike Frysinger <vapier@gentoo.org>
54
55 * tconfig.h (SIM_HANDLES_LMA): Delete.
56
84e8e361
MF		 572015-12-24 Mike Frysinger <vapier@gentoo.org>
58
59 * sim-main.h (WITH_WATCHPOINTS): Delete.
60
3cabaf66
MF		 612015-12-24 Mike Frysinger <vapier@gentoo.org>
62
63 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
64
8abe6c66
MF		 652015-12-24 Mike Frysinger <vapier@gentoo.org>
66
67 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
68
1d19cae7
DV		 692015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
70
71 * micromips.igen (process_isa_mode): Fix left shift of negative
72 value.
73
cdf850e9
MF		 742015-11-17 Mike Frysinger <vapier@gentoo.org>
75
76 * sim-main.h (WITH_MODULO_MEMORY): Delete.
77
797eee42
MF		 782015-11-15 Mike Frysinger <vapier@gentoo.org>
79
80 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
81
6e4f085c
MF		 822015-11-14 Mike Frysinger <vapier@gentoo.org>
83
84 * interp.c (sim_close): Rename to ...
85 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
86 sim_io_shutdown.
87 * sim-main.h (mips_sim_close): Declare.
88 (SIM_CLOSE_HOOK): Define.
89
8e394ffc
AB		 902015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
91 Ali Lown <ali.lown@imgtec.com>
92
93 * Makefile.in (tmp-micromips): New rule.
94 (tmp-mach-multi): Add support for micromips.
95 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
96 that works for both mips64 and micromips64.
97 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
98 micromips32.
99 Add build support for micromips.
100 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
101 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
102 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
103 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
104 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
105 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
106 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
107 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
108 Refactored instruction code to use these functions.
109 * dsp2.igen: Refactored instruction code to use the new functions.
110 * interp.c (decode_coproc): Refactored to work with any instruction
111 encoding.
112 (isa_mode): New variable
113 (RSVD_INSTRUCTION): Changed to 0x00000039.
114 * m16.igen (BREAK16): Refactored instruction to use do_break16.
115 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
116 * micromips.dc: New file.
117 * micromips.igen: New file.
118 * micromips16.dc: New file.
119 * micromipsdsp.igen: New file.
120 * micromipsrun.c: New file.
121 * mips.igen (do_swc1): Changed to work with any instruction encoding.
122 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
123 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
124 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
125 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
126 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
127 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
128 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
129 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
130 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
131 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
132 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
133 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
134 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
135 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
136 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
137 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
138 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
139 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
140 instructions.
141 Refactored instruction code to use these functions.
142 (RSVD): Changed to use new reserved instruction.
143 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
144 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
145 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
146 do_store_double): Added micromips32 and micromips64 models.
147 Added include for micromips.igen and micromipsdsp.igen
148 Add micromips32 and micromips64 models.
149 (DecodeCoproc): Updated to use new macro definition.
150 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
151 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
152 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
153 Refactored instruction code to use these functions.
154 * sim-main.h (CP0_operation): New enum.
155 (DecodeCoproc): Updated macro.
156 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
157 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
158 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
159 ISA_MODE_MICROMIPS): New defines.
160 (sim_state): Add isa_mode field.
161
8d0978fb
MF		 1622015-06-23 Mike Frysinger <vapier@gentoo.org>
163
164 * configure: Regenerate.
165
306f4178
MF		 1662015-06-12 Mike Frysinger <vapier@gentoo.org>
167
168 * configure.ac: Change configure.in to configure.ac.
169 * configure: Regenerate.
170
a3487082
MF		 1712015-06-12 Mike Frysinger <vapier@gentoo.org>
172
173 * configure: Regenerate.
174
29bc024d
MF		 1752015-06-12 Mike Frysinger <vapier@gentoo.org>
176
177 * interp.c [TRACE]: Delete.
178 (TRACE): Change to WITH_TRACE_ANY_P.
179 [!WITH_TRACE_ANY_P] (open_trace): Define.
180 (mips_option_handler, open_trace, sim_close, dotrace):
181 Change defined(TRACE) to WITH_TRACE_ANY_P.
182 (sim_open): Delete TRACE ifdef check.
183 * sim-main.c (load_memory): Delete TRACE ifdef check.
184 (store_memory): Likewise.
185 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
186 [!WITH_TRACE_ANY_P] (dotrace): Define.
187
3ebe2863
MF		 1882015-04-18 Mike Frysinger <vapier@gentoo.org>
189
190 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
191 comments.
192
20bca71d
MF		 1932015-04-18 Mike Frysinger <vapier@gentoo.org>
194
195 * sim-main.h (SIM_CPU): Delete.
196
7e83aa92
MF		 1972015-04-18 Mike Frysinger <vapier@gentoo.org>
198
199 * sim-main.h (sim_cia): Delete.
200
034685f9
MF		 2012015-04-17 Mike Frysinger <vapier@gentoo.org>
202
203 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
204 PU_PC_GET.
205 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
206 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
207 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
208 CIA_SET to CPU_PC_SET.
209 * sim-main.h (CIA_GET, CIA_SET): Delete.
210
78e9aa70
MF		 2112015-04-15 Mike Frysinger <vapier@gentoo.org>
212
213 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
214 * sim-main.h (STATE_CPU): Delete.
215
bf12d44e
MF		 2162015-04-13 Mike Frysinger <vapier@gentoo.org>
217
218 * configure: Regenerate.
219
7bebb329
MF		 2202015-04-13 Mike Frysinger <vapier@gentoo.org>
221
222 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
223 * interp.c (mips_pc_get, mips_pc_set): New functions.
224 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
225 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
226 (sim_pc_get): Delete.
227 * sim-main.h (SIM_CPU): Define.
228 (struct sim_state): Change cpu to an array of pointers.
229 (STATE_CPU): Drop &.
230
8ac57fbd
MF		 2312015-04-13 Mike Frysinger <vapier@gentoo.org>
232
233 * interp.c (mips_option_handler, open_trace, sim_close,
234 sim_write, sim_read, sim_store_register, sim_fetch_register,
235 sim_create_inferior, pr_addr, pr_uword64): Convert old style
236 prototypes.
237 (sim_open): Convert old style prototype. Change casts with
238 sim_write to unsigned char *.
239 (fetch_str): Change null to unsigned char, and change cast to
240 unsigned char *.
241 (sim_monitor): Change c & ch to unsigned char. Change cast to
242 unsigned char *.
243
e787f858
MF		 2442015-04-12 Mike Frysinger <vapier@gentoo.org>
245
246 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
247
122bbfb5
MF		 2482015-04-06 Mike Frysinger <vapier@gentoo.org>
249
250 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
251
0fe84f3f
MF		 2522015-04-01 Mike Frysinger <vapier@gentoo.org>
253
254 * tconfig.h (SIM_HAVE_PROFILE): Delete.
255
aadc9410
MF		 2562015-03-31 Mike Frysinger <vapier@gentoo.org>
257
258 * config.in, configure: Regenerate.
259
05f53ed6
MF		 2602015-03-24 Mike Frysinger <vapier@gentoo.org>
261
262 * interp.c (sim_pc_get): New function.
263
c0931f26
MF		 2642015-03-24 Mike Frysinger <vapier@gentoo.org>
265
266 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
267 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
268
30452bbe
MF		 2692015-03-24 Mike Frysinger <vapier@gentoo.org>
270
271 * configure: Regenerate.
272
64dd13df
MF		 2732015-03-23 Mike Frysinger <vapier@gentoo.org>
274
275 * configure: Regenerate.
276
49cd1634
MF		 2772015-03-23 Mike Frysinger <vapier@gentoo.org>
278
279 * configure: Regenerate.
280 * configure.ac (mips_extra_objs): Delete.
281 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
282 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
283
3649cb06
MF		 2842015-03-23 Mike Frysinger <vapier@gentoo.org>
285
286 * configure: Regenerate.
287 * configure.ac: Delete sim_hw checks for dv-sockser.
288
ae7d0cac
MF		 2892015-03-16 Mike Frysinger <vapier@gentoo.org>
290
291 * config.in, configure: Regenerate.
292 * tconfig.in: Rename file ...
293 * tconfig.h: ... here.
294
8406bb59
MF		 2952015-03-15 Mike Frysinger <vapier@gentoo.org>
296
297 * tconfig.in: Delete includes.
298 [HAVE_DV_SOCKSER]: Delete.
299
465fb143
MF		 3002015-03-14 Mike Frysinger <vapier@gentoo.org>
301
302 * Makefile.in (SIM_RUN_OBJS): Delete.
303
5cddc23a
MF		 3042015-03-14 Mike Frysinger <vapier@gentoo.org>
305
306 * configure.ac (AC_CHECK_HEADERS): Delete.
307 * aclocal.m4, configure: Regenerate.
308
2974be62
AM		 3092014-08-19 Alan Modra <amodra@gmail.com>
310
311 * configure: Regenerate.
312
faa743bb
RM		 3132014-08-15 Roland McGrath <mcgrathr@google.com>
314
315 * configure: Regenerate.
316 * config.in: Regenerate.
317
1a8a700e
MF		 3182014-03-04 Mike Frysinger <vapier@gentoo.org>
319
320 * configure: Regenerate.
321
bf3d9781
AM		 3222013-09-23 Alan Modra <amodra@gmail.com>
323
324 * configure: Regenerate.
325
31e6ad7d
MF		 3262013-06-03 Mike Frysinger <vapier@gentoo.org>
327
328 * aclocal.m4, configure: Regenerate.
329
d3685d60
TT		 3302013-05-10 Freddie Chopin <freddie_chopin@op.pl>
331
332 * configure: Rebuild.
333
1517bd27
MF		 3342013-03-26 Mike Frysinger <vapier@gentoo.org>
335
336 * configure: Regenerate.
337
3be31516
JS		 3382013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
339
340 * configure.ac: Address use of dv-sockser.o.
341 * tconfig.in: Conditionalize use of dv_sockser_install.
342 * configure: Regenerated.
343 * config.in: Regenerated.
344
37cb8f8e
SE		 3452012-10-04 Chao-ying Fu <fu@mips.com>
346 Steve Ellcey <sellcey@mips.com>
347
348 * mips/mips3264r2.igen (rdhwr): New.
349
87c8644f
JS		 3502012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
351
352 * configure.ac: Always link against dv-sockser.o.
353 * configure: Regenerate.
354
5f3ef9d0
JB		 3552012-06-15 Joel Brobecker <brobecker@adacore.com>
356
357 * config.in, configure: Regenerate.
358
a6ff997c
NC		 3592012-05-18 Nick Clifton <nickc@redhat.com>
360
361 PR 14072
362 * interp.c: Include config.h before system header files.
363
2232061b
MF		 3642012-03-24 Mike Frysinger <vapier@gentoo.org>
365
366 * aclocal.m4, config.in, configure: Regenerate.
367
db2e4d67
MF		 3682011-12-03 Mike Frysinger <vapier@gentoo.org>
369
370 * aclocal.m4: New file.
371 * configure: Regenerate.
372
4399a56b
MF		 3732011-10-19 Mike Frysinger <vapier@gentoo.org>
374
375 * configure: Regenerate after common/acinclude.m4 update.
376
9c082ca8
MF		 3772011-10-17 Mike Frysinger <vapier@gentoo.org>
378
379 * configure.ac: Change include to common/acinclude.m4.
380
6ffe910a
MF		 3812011-10-17 Mike Frysinger <vapier@gentoo.org>
382
383 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
384 call. Replace common.m4 include with SIM_AC_COMMON.
385 * configure: Regenerate.
386
31b28250
HPN		 3872011-07-08 Hans-Peter Nilsson <hp@axis.com>
388
3faa01e3
HPN		 389 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
390 $(SIM_EXTRA_DEPS).
391 (tmp-mach-multi): Exit early when igen fails.
31b28250 392
2419798b
MF		 3932011-07-05 Mike Frysinger <vapier@gentoo.org>
394
395 * interp.c (sim_do_command): Delete.
396
d79fe0d6
MF		 3972011-02-14 Mike Frysinger <vapier@gentoo.org>
398
399 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
400 (tx3904sio_fifo_reset): Likewise.
401 * interp.c (sim_monitor): Likewise.
402
5558e7e6
MF		 4032010-04-14 Mike Frysinger <vapier@gentoo.org>
404
405 * interp.c (sim_write): Add const to buffer arg.
406
35aafff4
JB		 4072010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
408
409 * interp.c: Don't include sysdep.h
410
3725885a
RW		 4112010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
412
413 * configure: Regenerate.
414
d6416cdc
RW		 4152009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
416
81ecdfbb
RW		 417 * config.in: Regenerate.
418 * configure: Likewise.
419
d6416cdc
RW		 420 * configure: Regenerate.
421
b5bd9624
HPN		 4222008-07-11 Hans-Peter Nilsson <hp@axis.com>
423
424 * configure: Regenerate to track ../common/common.m4 changes.
425 * config.in: Ditto.
426
6efef468 4272008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 428 Daniel Jacobowitz <dan@codesourcery.com>
429 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 430
431 * configure: Regenerate.
432
60dc88db
RS		 4332007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
434
435 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
436 that unconditionally allows fmt_ps.
437 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
438 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
439 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
440 filter from 64,f to 32,f.
441 (PREFX): Change filter from 64 to 32.
442 (LDXC1, LUXC1): Provide separate mips32r2 implementations
443 that use do_load_double instead of do_load. Make both LUXC1
444 versions unpredictable if SizeFGR () != 64.
445 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
446 instead of do_store. Remove unused variable. Make both SUXC1
447 versions unpredictable if SizeFGR () != 64.
448
599ca73e
RS		 4492007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
450
451 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
452 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
453 shifts for that case.
454
2525df03
NC		 4552007-09-04 Nick Clifton <nickc@redhat.com>
456
457 * interp.c (options enum): Add OPTION_INFO_MEMORY.
458 (display_mem_info): New static variable.
459 (mips_option_handler): Handle OPTION_INFO_MEMORY.
460 (mips_options): Add info-memory and memory-info.
461 (sim_open): After processing the command line and board
462 specification, check display_mem_info. If it is set then
463 call the real handler for the --memory-info command line
464 switch.
465
35ee6e1e
JB		 4662007-08-24 Joel Brobecker <brobecker@adacore.com>
467
468 * configure.ac: Change license of multi-run.c to GPL version 3.
469 * configure: Regenerate.
470
d5fb0879
RS		 4712007-06-28 Richard Sandiford <richard@codesourcery.com>
472
473 * configure.ac, configure: Revert last patch.
474
2a2ce21b
RS		 4752007-06-26 Richard Sandiford <richard@codesourcery.com>
476
477 * configure.ac (sim_mipsisa3264_configs): New variable.
478 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
479 every configuration support all four targets, using the triplet to
480 determine the default.
481 * configure: Regenerate.
482
efdcccc9
RS		 4832007-06-25 Richard Sandiford <richard@codesourcery.com>
484
0a7692b2 485 * Makefile.in (m16run.o): New rule.
efdcccc9 486
f532a356
TS		 4872007-05-15 Thiemo Seufer <ths@mips.com>
488
489 * mips3264r2.igen (DSHD): Fix compile warning.
490
bfe9c90b
TS		 4912007-05-14 Thiemo Seufer <ths@mips.com>
492
493 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
494 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
495 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
496 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
497 for mips32r2.
498
53f4826b
TS		 4992007-03-01 Thiemo Seufer <ths@mips.com>
500
501 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
502 and mips64.
503
8bf3ddc8
TS		 5042007-02-20 Thiemo Seufer <ths@mips.com>
505
506 * dsp.igen: Update copyright notice.
507 * dsp2.igen: Fix copyright notice.
508
8b082fb1 5092007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 510 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 511
512 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
513 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
514 Add dsp2 to sim_igen_machine.
515 * configure: Regenerate.
516 * dsp.igen (do_ph_op): Add MUL support when op = 2.
517 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
518 (mulq_rs.ph): Use do_ph_mulq.
519 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
520 * mips.igen: Add dsp2 model and include dsp2.igen.
521 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
522 for *mips32r2, *mips64r2, *dsp.
523 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
524 for *mips32r2, *mips64r2, *dsp2.
525 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
526
b1004875 5272007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 528 Nigel Stephens <nigel@mips.com>
b1004875
TS		 529
530 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
531 jumps with hazard barrier.
532
f8df4c77 5332007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 534 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 535
536 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
537 after each call to sim_io_write.
538
b1004875 5392007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 540 Nigel Stephens <nigel@mips.com>
b1004875
TS		 541
542 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
543 supported by this simulator.
07802d98
TS		 544 (decode_coproc): Recognise additional CP0 Config registers
545 correctly.
546
14fb6c5a 5472007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 548 Nigel Stephens <nigel@mips.com>
549 David Ung <davidu@mips.com>
14fb6c5a
TS		 550
551 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
552 uninterpreted formats. If fmt is one of the uninterpreted types
553 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
554 fmt_word, and fmt_uninterpreted_64 like fmt_long.
555 (store_fpr): When writing an invalid odd register, set the
556 matching even register to fmt_unknown, not the following register.
557 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
558 the the memory window at offset 0 set by --memory-size command
559 line option.
560 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
561 point register.
562 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
563 register.
564 (sim_monitor): When returning the memory size to the MIPS
565 application, use the value in STATE_MEM_SIZE, not an arbitrary
566 hardcoded value.
567 (cop_lw): Don' mess around with FPR_STATE, just pass
568 fmt_uninterpreted_32 to StoreFPR.
569 (cop_sw): Similarly.
570 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
571 (cop_sd): Similarly.
572 * mips.igen (not_word_value): Single version for mips32, mips64
573 and mips16.
574
c8847145 5752007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 576 Nigel Stephens <nigel@mips.com>
c8847145
TS		 577
578 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
579 MBytes.
580
4b5d35ee
TS		 5812007-02-17 Thiemo Seufer <ths@mips.com>
582
583 * configure.ac (mips*-sde-elf*): Move in front of generic machine
584 configuration.
585 * configure: Regenerate.
586
3669427c
TS		 5872007-02-17 Thiemo Seufer <ths@mips.com>
588
589 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
590 Add mdmx to sim_igen_machine.
591 (mipsisa64*-*-*): Likewise. Remove dsp.
592 (mipsisa32*-*-*): Remove dsp.
593 * configure: Regenerate.
594
109ad085
TS		 5952007-02-13 Thiemo Seufer <ths@mips.com>
596
597 * configure.ac: Add mips*-sde-elf* target.
598 * configure: Regenerate.
599
921d7ad3
HPN		 6002006-12-21 Hans-Peter Nilsson <hp@axis.com>
601
602 * acconfig.h: Remove.
603 * config.in, configure: Regenerate.
604
02f97da7
TS		 6052006-11-07 Thiemo Seufer <ths@mips.com>
606
607 * dsp.igen (do_w_op): Fix compiler warning.
608
2d2733fc 6092006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 610 David Ung <davidu@mips.com>
2d2733fc
TS		 611
612 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
613 sim_igen_machine.
614 * configure: Regenerate.
615 * mips.igen (model): Add smartmips.
616 (MADDU): Increment ACX if carry.
617 (do_mult): Clear ACX.
618 (ROR,RORV): Add smartmips.
72f4393d 619 (include): Include smartmips.igen.
2d2733fc
TS		 620 * sim-main.h (ACX): Set to REGISTERS[89].
621 * smartmips.igen: New file.
622
d85c3a10 6232006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 624 David Ung <davidu@mips.com>
d85c3a10
TS		 625
626 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
627 mips3264r2.igen. Add missing dependency rules.
628 * m16e.igen: Support for mips16e save/restore instructions.
629
e85e3205
RE		 6302006-06-13 Richard Earnshaw <rearnsha@arm.com>
631
632 * configure: Regenerated.
633
2f0122dc
DJ		 6342006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
635
636 * configure: Regenerated.
637
20e95c23
DJ		 6382006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
639
640 * configure: Regenerated.
641
69088b17
CF		 6422006-05-15 Chao-ying Fu <fu@mips.com>
643
644 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
645
0275de4e
NC		 6462006-04-18 Nick Clifton <nickc@redhat.com>
647
648 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
649 statement.
650
b3a3ffef
HPN		 6512006-03-29 Hans-Peter Nilsson <hp@axis.com>
652
653 * configure: Regenerate.
654
40a5538e
CF		 6552005-12-14 Chao-ying Fu <fu@mips.com>
656
657 * Makefile.in (SIM_OBJS): Add dsp.o.
658 (dsp.o): New dependency.
659 (IGEN_INCLUDE): Add dsp.igen.
660 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
661 mipsisa64*-*-*): Add dsp to sim_igen_machine.
662 * configure: Regenerate.
663 * mips.igen: Add dsp model and include dsp.igen.
664 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
665 because these instructions are extended in DSP ASE.
666 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
667 adding 6 DSP accumulator registers and 1 DSP control register.
668 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
669 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
670 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
671 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
672 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
673 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
674 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
675 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
676 DSPCR_CCOND_SMASK): New define.
677 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
678 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
679
21d14896
ILT		 6802005-07-08 Ian Lance Taylor <ian@airs.com>
681
682 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
683
b16d63da 6842005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 685 Nigel Stephens <nigel@mips.com>
686
687 * mips.igen: New mips16e model and include m16e.igen.
688 (check_u64): Add mips16e tag.
689 * m16e.igen: New file for MIPS16e instructions.
690 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
691 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
692 models.
693 * configure: Regenerate.
b16d63da 694
e70cb6cd 6952005-05-26 David Ung <davidu@mips.com>
72f4393d 696
e70cb6cd
CD		 697 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
698 tags to all instructions which are applicable to the new ISAs.
699 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
700 vr.igen.
701 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 702 instructions.
e70cb6cd
CD		 703 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
704 to mips.igen.
705 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
706 * configure: Regenerate.
72f4393d 707
2b193c4a
MK		 7082005-03-23 Mark Kettenis <kettenis@gnu.org>
709
710 * configure: Regenerate.
711
35695fd6
AC		 7122005-01-14 Andrew Cagney <cagney@gnu.org>
713
714 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
715 explicit call to AC_CONFIG_HEADER.
716 * configure: Regenerate.
717
f0569246
AC		 7182005-01-12 Andrew Cagney <cagney@gnu.org>
719
720 * configure.ac: Update to use ../common/common.m4.
721 * configure: Re-generate.
722
38f48d72
AC		 7232005-01-11 Andrew Cagney <cagney@localhost.localdomain>
724
725 * configure: Regenerated to track ../common/aclocal.m4 changes.
726
b7026657
AC		 7272005-01-07 Andrew Cagney <cagney@gnu.org>
728
729 * configure.ac: Rename configure.in, require autoconf 2.59.
730 * configure: Re-generate.
731
379832de
HPN		 7322004-12-08 Hans-Peter Nilsson <hp@axis.com>
733
734 * configure: Regenerate for ../common/aclocal.m4 update.
735
cd62154c 7362004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 737
cd62154c
AC		 738 Committed by Andrew Cagney.
739 * m16.igen (CMP, CMPI): Fix assembler.
740
e5da76ec
CD		 7412004-08-18 Chris Demetriou <cgd@broadcom.com>
742
743 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
744 * configure: Regenerate.
745
139181c8
CD		 7462004-06-25 Chris Demetriou <cgd@broadcom.com>
747
748 * configure.in (sim_m16_machine): Include mipsIII.
749 * configure: Regenerate.
750
1a27f959
CD		 7512004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
752
72f4393d 753 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 754 from COP0_BADVADDR.
755 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
756
5dbb7b5a
CD		 7572004-04-10 Chris Demetriou <cgd@broadcom.com>
758
759 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
760
14234056
CD		 7612004-04-09 Chris Demetriou <cgd@broadcom.com>
762
763 * mips.igen (check_fmt): Remove.
764 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
765 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
766 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
767 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
768 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
769 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
770 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
771 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
772 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
773 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
774
c6f9085c
CD		 7752004-04-09 Chris Demetriou <cgd@broadcom.com>
776
777 * sb1.igen (check_sbx): New function.
778 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
779
11d66e66 7802004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 781 Richard Sandiford <rsandifo@redhat.com>
782
783 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
784 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
785 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
786 separate implementations for mipsIV and mipsV. Use new macros to
787 determine whether the restrictions apply.
788
b3208fb8
CD		 7892004-01-19 Chris Demetriou <cgd@broadcom.com>
790
791 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
792 (check_mult_hilo): Improve comments.
793 (check_div_hilo): Likewise. Also, fork off a new version
794 to handle mips32/mips64 (since there are no hazards to check
795 in MIPS32/MIPS64).
796
9a1d84fb
CD		 7972003-06-17 Richard Sandiford <rsandifo@redhat.com>
798
799 * mips.igen (do_dmultx): Fix check for negative operands.
800
ae451ac6
ILT		 8012003-05-16 Ian Lance Taylor <ian@airs.com>
802
803 * Makefile.in (SHELL): Make sure this is defined.
804 (various): Use $(SHELL) whenever we invoke move-if-change.
805
dd69d292
CD		 8062003-05-03 Chris Demetriou <cgd@broadcom.com>
807
808 * cp1.c: Tweak attribution slightly.
809 * cp1.h: Likewise.
810 * mdmx.c: Likewise.
811 * mdmx.igen: Likewise.
812 * mips3d.igen: Likewise.
813 * sb1.igen: Likewise.
814
bcd0068e
CD		 8152003-04-15 Richard Sandiford <rsandifo@redhat.com>
816
817 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
818 unsigned operands.
819
6b4a8935
AC		 8202003-02-27 Andrew Cagney <cagney@redhat.com>
821
601da316
AC		 822 * interp.c (sim_open): Rename _bfd to bfd.
823 (sim_create_inferior): Ditto.
6b4a8935 824
d29e330f
CD		 8252003-01-14 Chris Demetriou <cgd@broadcom.com>
826
827 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
828
a2353a08
CD		 8292003-01-14 Chris Demetriou <cgd@broadcom.com>
830
831 * mips.igen (EI, DI): Remove.
832
80551777
CD		 8332003-01-05 Richard Sandiford <rsandifo@redhat.com>
834
835 * Makefile.in (tmp-run-multi): Fix mips16 filter.
836
4c54fc26
CD		 8372003-01-04 Richard Sandiford <rsandifo@redhat.com>
838 Andrew Cagney <ac131313@redhat.com>
839 Gavin Romig-Koch <gavin@redhat.com>
840 Graydon Hoare <graydon@redhat.com>
841 Aldy Hernandez <aldyh@redhat.com>
842 Dave Brolley <brolley@redhat.com>
843 Chris Demetriou <cgd@broadcom.com>
844
845 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
846 (sim_mach_default): New variable.
847 (mips64vr-*-*, mips64vrel-*-*): New configurations.
848 Add a new simulator generator, MULTI.
849 * configure: Regenerate.
850 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
851 (multi-run.o): New dependency.
852 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
853 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
854 (tmp-multi): Combine them.
855 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
856 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
857 (distclean-extra): New rule.
858 * sim-main.h: Include bfd.h.
859 (MIPS_MACH): New macro.
860 * mips.igen (vr4120, vr5400, vr5500): New models.
861 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
862 * vr.igen: Replace with new version.
863
e6c674b8
CD		 8642003-01-04 Chris Demetriou <cgd@broadcom.com>
865
866 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
867 * configure: Regenerate.
868
28f50ac8
CD		 8692002-12-31 Chris Demetriou <cgd@broadcom.com>
870
871 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
872 * mips.igen: Remove all invocations of check_branch_bug and
873 mark_branch_bug.
874
5071ffe6
CD		 8752002-12-16 Chris Demetriou <cgd@broadcom.com>
876
72f4393d 877 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 878
06e7837e
CD		 8792002-07-30 Chris Demetriou <cgd@broadcom.com>
880
881 * mips.igen (do_load_double, do_store_double): New functions.
882 (LDC1, SDC1): Rename to...
883 (LDC1b, SDC1b): respectively.
884 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
885
2265c243
MS		 8862002-07-29 Michael Snyder <msnyder@redhat.com>
887
888 * cp1.c (fp_recip2): Modify initialization expression so that
889 GCC will recognize it as constant.
890
a2f8b4f3
CD		 8912002-06-18 Chris Demetriou <cgd@broadcom.com>
892
893 * mdmx.c (SD_): Delete.
894 (Unpredictable): Re-define, for now, to directly invoke
895 unpredictable_action().
896 (mdmx_acc_op): Fix error in .ob immediate handling.
897
b4b6c939
AC		 8982002-06-18 Andrew Cagney <cagney@redhat.com>
899
900 * interp.c (sim_firmware_command): Initialize `address'.
901
c8cca39f
AC		 9022002-06-16 Andrew Cagney <ac131313@redhat.com>
903
904 * configure: Regenerated to track ../common/aclocal.m4 changes.
905
e7e81181 9062002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 907 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 908
909 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
910 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
911 * mips.igen: Include mips3d.igen.
912 (mips3d): New model name for MIPS-3D ASE instructions.
913 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 914 instructions.
e7e81181
CD		 915 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
916 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
917 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
918 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
919 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
920 (RSquareRoot1, RSquareRoot2): New macros.
921 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
922 (fp_rsqrt2): New functions.
923 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
924 * configure: Regenerate.
925
3a2b820e 9262002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 927 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 928
929 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
930 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
931 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
932 (convert): Note that this function is not used for paired-single
933 format conversions.
934 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
935 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
936 (check_fmt_p): Enable paired-single support.
937 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
938 (PUU.PS): New instructions.
939 (CVT.S.fmt): Don't use this instruction for paired-single format
940 destinations.
941 * sim-main.h (FP_formats): New value 'fmt_ps.'
942 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
943 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
944
d18ea9c2
CD		 9452002-06-12 Chris Demetriou <cgd@broadcom.com>
946
947 * mips.igen: Fix formatting of function calls in
948 many FP operations.
949
95fd5cee
CD		 9502002-06-12 Chris Demetriou <cgd@broadcom.com>
951
952 * mips.igen (MOVN, MOVZ): Trace result.
953 (TNEI): Print "tnei" as the opcode name in traces.
954 (CEIL.W): Add disassembly string for traces.
955 (RSQRT.fmt): Make location of disassembly string consistent
956 with other instructions.
957
4f0d55ae
CD		 9582002-06-12 Chris Demetriou <cgd@broadcom.com>
959
960 * mips.igen (X): Delete unused function.
961
3c25f8c7
AC		 9622002-06-08 Andrew Cagney <cagney@redhat.com>
963
964 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
965
f3c08b7e 9662002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 967 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 968
969 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
970 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
971 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
972 (fp_nmsub): New prototypes.
973 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
974 (NegMultiplySub): New defines.
975 * mips.igen (RSQRT.fmt): Use RSquareRoot().
976 (MADD.D, MADD.S): Replace with...
977 (MADD.fmt): New instruction.
978 (MSUB.D, MSUB.S): Replace with...
979 (MSUB.fmt): New instruction.
980 (NMADD.D, NMADD.S): Replace with...
981 (NMADD.fmt): New instruction.
982 (NMSUB.D, MSUB.S): Replace with...
983 (NMSUB.fmt): New instruction.
984
52714ff9 9852002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 986 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 987
988 * cp1.c: Fix more comment spelling and formatting.
989 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
990 (denorm_mode): New function.
991 (fpu_unary, fpu_binary): Round results after operation, collect
992 status from rounding operations, and update the FCSR.
993 (convert): Collect status from integer conversions and rounding
994 operations, and update the FCSR. Adjust NaN values that result
995 from conversions. Convert to use sim_io_eprintf rather than
996 fprintf, and remove some debugging code.
997 * cp1.h (fenr_FS): New define.
998
577d8c4b
CD		 9992002-06-07 Chris Demetriou <cgd@broadcom.com>
1000
1001 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1002 rounding mode to sim FP rounding mode flag conversion code into...
1003 (rounding_mode): New function.
1004
196496ed
CD		 10052002-06-07 Chris Demetriou <cgd@broadcom.com>
1006
1007 * cp1.c: Clean up formatting of a few comments.
1008 (value_fpr): Reformat switch statement.
1009
cfe9ea23 10102002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1011 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1012
1013 * cp1.h: New file.
1014 * sim-main.h: Include cp1.h.
1015 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1016 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1017 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1018 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1019 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1020 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1021 * cp1.c: Don't include sim-fpu.h; already included by
1022 sim-main.h. Clean up formatting of some comments.
1023 (NaN, Equal, Less): Remove.
1024 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1025 (fp_cmp): New functions.
1026 * mips.igen (do_c_cond_fmt): Remove.
1027 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1028 Compare. Add result tracing.
1029 (CxC1): Remove, replace with...
1030 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1031 (DMxC1): Remove, replace with...
1032 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1033 (MxC1): Remove, replace with...
1034 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1035
ee7254b0
CD		 10362002-06-04 Chris Demetriou <cgd@broadcom.com>
1037
1038 * sim-main.h (FGRIDX): Remove, replace all uses with...
1039 (FGR_BASE): New macro.
1040 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1041 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1042 (NR_FGR, FGR): Likewise.
1043 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1044 * mips.igen: Likewise.
1045
d3eb724f
CD		 10462002-06-04 Chris Demetriou <cgd@broadcom.com>
1047
1048 * cp1.c: Add an FSF Copyright notice to this file.
1049
ba46ddd0 10502002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1051 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1052
1053 * cp1.c (Infinity): Remove.
1054 * sim-main.h (Infinity): Likewise.
1055
1056 * cp1.c (fp_unary, fp_binary): New functions.
1057 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1058 (fp_sqrt): New functions, implemented in terms of the above.
1059 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1060 (Recip, SquareRoot): Remove (replaced by functions above).
1061 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1062 (fp_recip, fp_sqrt): New prototypes.
1063 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1064 (Recip, SquareRoot): Replace prototypes with #defines which
1065 invoke the functions above.
72f4393d 1066
18d8a52d
CD		 10672002-06-03 Chris Demetriou <cgd@broadcom.com>
1068
1069 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1070 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1071 file, remove PARAMS from prototypes.
1072 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1073 simulator state arguments.
1074 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1075 pass simulator state arguments.
1076 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1077 (store_fpr, convert): Remove 'sd' argument.
1078 (value_fpr): Likewise. Convert to use 'SD' instead.
1079
0f154cbd
CD		 10802002-06-03 Chris Demetriou <cgd@broadcom.com>
1081
1082 * cp1.c (Min, Max): Remove #if 0'd functions.
1083 * sim-main.h (Min, Max): Remove.
1084
e80fc152
CD		 10852002-06-03 Chris Demetriou <cgd@broadcom.com>
1086
1087 * cp1.c: fix formatting of switch case and default labels.
1088 * interp.c: Likewise.
1089 * sim-main.c: Likewise.
1090
bad673a9
CD		 10912002-06-03 Chris Demetriou <cgd@broadcom.com>
1092
1093 * cp1.c: Clean up comments which describe FP formats.
1094 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1095
7cbea089 10962002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1097 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1098
1099 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1100 Broadcom SiByte SB-1 processor configurations.
1101 * configure: Regenerate.
1102 * sb1.igen: New file.
1103 * mips.igen: Include sb1.igen.
1104 (sb1): New model.
1105 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1106 * mdmx.igen: Add "sb1" model to all appropriate functions and
1107 instructions.
1108 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1109 (ob_func, ob_acc): Reference the above.
1110 (qh_acc): Adjust to keep the same size as ob_acc.
1111 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1112 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1113
909daa82
CD		 11142002-06-03 Chris Demetriou <cgd@broadcom.com>
1115
1116 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1117
f4f1b9f1 11182002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1119 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1120
1121 * mips.igen (mdmx): New (pseudo-)model.
1122 * mdmx.c, mdmx.igen: New files.
1123 * Makefile.in (SIM_OBJS): Add mdmx.o.
1124 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1125 New typedefs.
1126 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1127 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1128 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1129 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1130 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1131 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1132 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1133 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1134 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1135 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1136 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1137 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1138 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1139 (qh_fmtsel): New macros.
1140 (_sim_cpu): New member "acc".
1141 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1142 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1143
5accf1ff
CD		 11442002-05-01 Chris Demetriou <cgd@broadcom.com>
1145
1146 * interp.c: Use 'deprecated' rather than 'depreciated.'
1147 * sim-main.h: Likewise.
1148
402586aa
CD		 11492002-05-01 Chris Demetriou <cgd@broadcom.com>
1150
1151 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1152 which wouldn't compile anyway.
1153 * sim-main.h (unpredictable_action): New function prototype.
1154 (Unpredictable): Define to call igen function unpredictable().
1155 (NotWordValue): New macro to call igen function not_word_value().
1156 (UndefinedResult): Remove.
1157 * interp.c (undefined_result): Remove.
1158 (unpredictable_action): New function.
1159 * mips.igen (not_word_value, unpredictable): New functions.
1160 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1161 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1162 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1163 NotWordValue() to check for unpredictable inputs, then
1164 Unpredictable() to handle them.
1165
c9b9995a
CD		 11662002-02-24 Chris Demetriou <cgd@broadcom.com>
1167
1168 * mips.igen: Fix formatting of calls to Unpredictable().
1169
e1015982
AC		 11702002-04-20 Andrew Cagney <ac131313@redhat.com>
1171
1172 * interp.c (sim_open): Revert previous change.
1173
b882a66b
AO		 11742002-04-18 Alexandre Oliva <aoliva@redhat.com>
1175
1176 * interp.c (sim_open): Disable chunk of code that wrote code in
1177 vector table entries.
1178
c429b7dd
CD		 11792002-03-19 Chris Demetriou <cgd@broadcom.com>
1180
1181 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1182 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1183 unused definitions.
1184
37d146fa
CD		 11852002-03-19 Chris Demetriou <cgd@broadcom.com>
1186
1187 * cp1.c: Fix many formatting issues.
1188
07892c0b
CD		 11892002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1190
1191 * cp1.c (fpu_format_name): New function to replace...
1192 (DOFMT): This. Delete, and update all callers.
1193 (fpu_rounding_mode_name): New function to replace...
1194 (RMMODE): This. Delete, and update all callers.
1195
487f79b7
CD		 11962002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1197
1198 * interp.c: Move FPU support routines from here to...
1199 * cp1.c: Here. New file.
1200 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1201 (cp1.o): New target.
1202
1e799e28
CD		 12032002-03-12 Chris Demetriou <cgd@broadcom.com>
1204
1205 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1206 * mips.igen (mips32, mips64): New models, add to all instructions
1207 and functions as appropriate.
1208 (loadstore_ea, check_u64): New variant for model mips64.
1209 (check_fmt_p): New variant for models mipsV and mips64, remove
1210 mipsV model marking fro other variant.
1211 (SLL) Rename to...
1212 (SLLa) this.
1213 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1214 for mips32 and mips64.
1215 (DCLO, DCLZ): New instructions for mips64.
1216
82f728db
CD		 12172002-03-07 Chris Demetriou <cgd@broadcom.com>
1218
1219 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1220 immediate or code as a hex value with the "%#lx" format.
1221 (ANDI): Likewise, and fix printed instruction name.
1222
b96e7ef1
CD		 12232002-03-05 Chris Demetriou <cgd@broadcom.com>
1224
1225 * sim-main.h (UndefinedResult, Unpredictable): New macros
1226 which currently do nothing.
1227
d35d4f70
CD		 12282002-03-05 Chris Demetriou <cgd@broadcom.com>
1229
1230 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1231 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1232 (status_CU3): New definitions.
1233
1234 * sim-main.h (ExceptionCause): Add new values for MIPS32
1235 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1236 for DebugBreakPoint and NMIReset to note their status in
1237 MIPS32 and MIPS64.
1238 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1239 (SignalExceptionCacheErr): New exception macros.
1240
3ad6f714
CD		 12412002-03-05 Chris Demetriou <cgd@broadcom.com>
1242
1243 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1244 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1245 is always enabled.
1246 (SignalExceptionCoProcessorUnusable): Take as argument the
1247 unusable coprocessor number.
1248
86b77b47
CD		 12492002-03-05 Chris Demetriou <cgd@broadcom.com>
1250
1251 * mips.igen: Fix formatting of all SignalException calls.
1252
97a88e93 12532002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1254
1255 * sim-main.h (SIGNEXTEND): Remove.
1256
97a88e93 12572002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1258
1259 * mips.igen: Remove gencode comment from top of file, fix
1260 spelling in another comment.
1261
97a88e93 12622002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1263
1264 * mips.igen (check_fmt, check_fmt_p): New functions to check
1265 whether specific floating point formats are usable.
1266 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1267 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1268 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1269 Use the new functions.
1270 (do_c_cond_fmt): Remove format checks...
1271 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1272
97a88e93 12732002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1274
1275 * mips.igen: Fix formatting of check_fpu calls.
1276
41774c9d
CD		 12772002-03-03 Chris Demetriou <cgd@broadcom.com>
1278
1279 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1280
4a0bd876
CD		 12812002-03-03 Chris Demetriou <cgd@broadcom.com>
1282
1283 * mips.igen: Remove whitespace at end of lines.
1284
09297648
CD		 12852002-03-02 Chris Demetriou <cgd@broadcom.com>
1286
1287 * mips.igen (loadstore_ea): New function to do effective
1288 address calculations.
1289 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1290 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1291 CACHE): Use loadstore_ea to do effective address computations.
1292
043b7057
CD		 12932002-03-02 Chris Demetriou <cgd@broadcom.com>
1294
1295 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1296 * mips.igen (LL, CxC1, MxC1): Likewise.
1297
c1e8ada4
CD		 12982002-03-02 Chris Demetriou <cgd@broadcom.com>
1299
1300 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1301 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1302 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1303 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1304 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1305 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1306 Don't split opcode fields by hand, use the opcode field values
1307 provided by igen.
1308
3e1dca16
CD		 13092002-03-01 Chris Demetriou <cgd@broadcom.com>
1310
1311 * mips.igen (do_divu): Fix spacing.
1312
1313 * mips.igen (do_dsllv): Move to be right before DSLLV,
1314 to match the rest of the do_<shift> functions.
1315
fff8d27d
CD		 13162002-03-01 Chris Demetriou <cgd@broadcom.com>
1317
1318 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1319 DSRL32, do_dsrlv): Trace inputs and results.
1320
0d3e762b
CD		 13212002-03-01 Chris Demetriou <cgd@broadcom.com>
1322
1323 * mips.igen (CACHE): Provide instruction-printing string.
1324
1325 * interp.c (signal_exception): Comment tokens after #endif.
1326
eb5fcf93
CD		 13272002-02-28 Chris Demetriou <cgd@broadcom.com>
1328
1329 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1330 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1331 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1332 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1333 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1334 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1335 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1336 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1337
bb22bd7d
CD		 13382002-02-28 Chris Demetriou <cgd@broadcom.com>
1339
1340 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1341 instruction-printing string.
1342 (LWU): Use '64' as the filter flag.
1343
91a177cf
CD		 13442002-02-28 Chris Demetriou <cgd@broadcom.com>
1345
1346 * mips.igen (SDXC1): Fix instruction-printing string.
1347
387f484a
CD		 13482002-02-28 Chris Demetriou <cgd@broadcom.com>
1349
1350 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1351 filter flags "32,f".
1352
3d81f391
CD		 13532002-02-27 Chris Demetriou <cgd@broadcom.com>
1354
1355 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1356 as the filter flag.
1357
af5107af
CD		 13582002-02-27 Chris Demetriou <cgd@broadcom.com>
1359
1360 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1361 add a comma) so that it more closely match the MIPS ISA
1362 documentation opcode partitioning.
1363 (PREF): Put useful names on opcode fields, and include
1364 instruction-printing string.
1365
ca971540
CD		 13662002-02-27 Chris Demetriou <cgd@broadcom.com>
1367
1368 * mips.igen (check_u64): New function which in the future will
1369 check whether 64-bit instructions are usable and signal an
1370 exception if not. Currently a no-op.
1371 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1372 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1373 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1374 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1375
1376 * mips.igen (check_fpu): New function which in the future will
1377 check whether FPU instructions are usable and signal an exception
1378 if not. Currently a no-op.
1379 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1380 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1381 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1382 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1383 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1384 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1385 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1386 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1387
1c47a468
CD		 13882002-02-27 Chris Demetriou <cgd@broadcom.com>
1389
1390 * mips.igen (do_load_left, do_load_right): Move to be immediately
1391 following do_load.
1392 (do_store_left, do_store_right): Move to be immediately following
1393 do_store.
1394
603a98e7
CD		 13952002-02-27 Chris Demetriou <cgd@broadcom.com>
1396
1397 * mips.igen (mipsV): New model name. Also, add it to
1398 all instructions and functions where it is appropriate.
1399
c5d00cc7
CD		 14002002-02-18 Chris Demetriou <cgd@broadcom.com>
1401
1402 * mips.igen: For all functions and instructions, list model
1403 names that support that instruction one per line.
1404
074e9cb8
CD		 14052002-02-11 Chris Demetriou <cgd@broadcom.com>
1406
1407 * mips.igen: Add some additional comments about supported
1408 models, and about which instructions go where.
1409 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1410 order as is used in the rest of the file.
1411
9805e229
CD		 14122002-02-11 Chris Demetriou <cgd@broadcom.com>
1413
1414 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1415 indicating that ALU32_END or ALU64_END are there to check
1416 for overflow.
1417 (DADD): Likewise, but also remove previous comment about
1418 overflow checking.
1419
f701dad2
CD		 14202002-02-10 Chris Demetriou <cgd@broadcom.com>
1421
1422 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1423 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1424 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1425 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1426 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1427 fields (i.e., add and move commas) so that they more closely
1428 match the MIPS ISA documentation opcode partitioning.
1429
14302002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1431
72f4393d
L		 1432 * mips.igen (ADDI): Print immediate value.
1433 (BREAK): Print code.
1434 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1435 (SLL): Print "nop" specially, and don't run the code
1436 that does the shift for the "nop" case.
20ae0098 1437
9e52972e
FF		 14382001-11-17 Fred Fish <fnf@redhat.com>
1439
1440 * sim-main.h (float_operation): Move enum declaration outside
1441 of _sim_cpu struct declaration.
1442
c0efbca4
JB		 14432001-04-12 Jim Blandy <jimb@redhat.com>
1444
1445 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1446 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1447 set of the FCSR.
1448 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1449 PENDING_FILL, and you can get the intended effect gracefully by
1450 calling PENDING_SCHED directly.
1451
fb891446
BE		 14522001-02-23 Ben Elliston <bje@redhat.com>
1453
1454 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1455 already defined elsewhere.
1456
8030f857
BE		 14572001-02-19 Ben Elliston <bje@redhat.com>
1458
1459 * sim-main.h (sim_monitor): Return an int.
1460 * interp.c (sim_monitor): Add return values.
1461 (signal_exception): Handle error conditions from sim_monitor.
1462
56b48a7a
CD		 14632001-02-08 Ben Elliston <bje@redhat.com>
1464
1465 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1466 (store_memory): Likewise, pass cia to sim_core_write*.
1467
d3ee60d9
FCE		 14682000-10-19 Frank Ch. Eigler <fche@redhat.com>
1469
1470 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1471 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1472
071da002
AC		 1473Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1474
1475 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1476 * Makefile.in: Don't delete *.igen when cleaning directory.
1477
a28c02cd
AC		 1478Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1479
1480 * m16.igen (break): Call SignalException not sim_engine_halt.
1481
80ee11fa
AC		 1482Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1483
1484 From Jason Eckhardt:
1485 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1486
673388c0
AC		 1487Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1488
1489 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1490
4c0deff4
NC		 14912000-05-24 Michael Hayes <mhayes@cygnus.com>
1492
1493 * mips.igen (do_dmultx): Fix typo.
1494
eb2d80b4
AC		 1495Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1496
1497 * configure: Regenerated to track ../common/aclocal.m4 changes.
1498
dd37a34b
AC		 1499Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1500
1501 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1502
4c0deff4
NC		 15032000-04-12 Frank Ch. Eigler <fche@redhat.com>
1504
1505 * sim-main.h (GPR_CLEAR): Define macro.
1506
e30db738
AC		 1507Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1508
1509 * interp.c (decode_coproc): Output long using %lx and not %s.
1510
cb7450ea
FCE		 15112000-03-21 Frank Ch. Eigler <fche@redhat.com>
1512
1513 * interp.c (sim_open): Sort & extend dummy memory regions for
1514 --board=jmr3904 for eCos.
1515
a3027dd7
FCE		 15162000-03-02 Frank Ch. Eigler <fche@redhat.com>
1517
1518 * configure: Regenerated.
1519
1520Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1521
1522 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1523 calls, conditional on the simulator being in verbose mode.
1524
dfcd3bfb
JM		 1525Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1526
1527 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1528 cache don't get ReservedInstruction traps.
1529
c2d11a7d
JM		 15301999-11-29 Mark Salter <msalter@cygnus.com>
1531
1532 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1533 to clear status bits in sdisr register. This is how the hardware works.
1534
1535 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1536 being used by cygmon.
1537
4ce44c66
JM		 15381999-11-11 Andrew Haley <aph@cygnus.com>
1539
1540 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1541 instructions.
1542
cff3e48b
JM		 1543Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1544
1545 * mips.igen (MULT): Correct previous mis-applied patch.
1546
d4f3574e
SS		 1547Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1548
1549 * mips.igen (delayslot32): Handle sequence like
1550 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1551 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1552 (MULT): Actually pass the third register...
1553
15541999-09-03 Mark Salter <msalter@cygnus.com>
1555
1556 * interp.c (sim_open): Added more memory aliases for additional
1557 hardware being touched by cygmon on jmr3904 board.
1558
1559Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1560
1561 * configure: Regenerated to track ../common/aclocal.m4 changes.
1562
a0b3c4fd
JM		 1563Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1564
1565 * interp.c (sim_store_register): Handle case where client - GDB -
1566 specifies that a 4 byte register is 8 bytes in size.
1567 (sim_fetch_register): Ditto.
72f4393d 1568
adf40b2e
JM		 15691999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1570
1571 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1572 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1573 (idt_monitor_base): Base address for IDT monitor traps.
1574 (pmon_monitor_base): Ditto for PMON.
1575 (lsipmon_monitor_base): Ditto for LSI PMON.
1576 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1577 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1578 (sim_firmware_command): New function.
1579 (mips_option_handler): Call it for OPTION_FIRMWARE.
1580 (sim_open): Allocate memory for idt_monitor region. If "--board"
1581 option was given, add no monitor by default. Add BREAK hooks only if
1582 monitors are also there.
72f4393d 1583
43e526b9
JM		 1584Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1585
1586 * interp.c (sim_monitor): Flush output before reading input.
1587
1588Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1589
1590 * tconfig.in (SIM_HANDLES_LMA): Always define.
1591
1592Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1593
1594 From Mark Salter <msalter@cygnus.com>:
1595 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1596 (sim_open): Add setup for BSP board.
1597
9846de1b
JM		 1598Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1599
1600 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1601 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1602 them as unimplemented.
1603
cd0fc7c3
SS		 16041999-05-08 Felix Lee <flee@cygnus.com>
1605
1606 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1607
7a292a7a
SS		 16081999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1609
1610 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1611
1612Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1613
1614 * configure.in: Any mips64vr5*-*-* target should have
1615 -DTARGET_ENABLE_FR=1.
1616 (default_endian): Any mips64vr*el-*-* target should default to
1617 LITTLE_ENDIAN.
1618 * configure: Re-generate.
1619
16201999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1621
1622 * mips.igen (ldl): Extend from _16_, not 32.
1623
1624Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1625
1626 * interp.c (sim_store_register): Force registers written to by GDB
1627 into an un-interpreted state.
1628
c906108c
SS		 16291999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1630
1631 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1632 CPU, start periodic background I/O polls.
72f4393d 1633 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1634
16351998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1636
1637 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1638
c906108c
SS		 1639Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1640
1641 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1642 case statement.
1643
16441998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1645
1646 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1647 (load_word): Call SIM_CORE_SIGNAL hook on error.
1648 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1649 starting. For exception dispatching, pass PC instead of NULL_CIA.
1650 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1651 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1652 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1653 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1654 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1655 * mips.igen (*): Replace memory-related SignalException* calls
1656 with references to SIM_CORE_SIGNAL hook.
72f4393d 1657
c906108c
SS		 1658 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1659 fix.
1660 * sim-main.c (*): Minor warning cleanups.
72f4393d 1661
c906108c
SS		 16621998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1663
1664 * m16.igen (DADDIU5): Correct type-o.
1665
1666Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1667
1668 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1669 variables.
1670
1671Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1672
1673 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1674 to include path.
1675 (interp.o): Add dependency on itable.h
1676 (oengine.c, gencode): Delete remaining references.
1677 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1678
c906108c 16791998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1680
c906108c
SS		 1681 * vr4run.c: New.
1682 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1683 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1684 tmp-run-hack) : New.
1685 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1686 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1687 Drop the "64" qualifier to get the HACK generator working.
1688 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1689 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1690 qualifier to get the hack generator working.
1691 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1692 (DSLL): Use do_dsll.
1693 (DSLLV): Use do_dsllv.
1694 (DSRA): Use do_dsra.
1695 (DSRL): Use do_dsrl.
1696 (DSRLV): Use do_dsrlv.
1697 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1698 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1699 get the HACK generator working.
1700 (MACC) Rename to get the HACK generator working.
1701 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1702
c906108c
SS		 17031998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1704
1705 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1706 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1707
c906108c
SS		 17081998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1709
1710 * mips/interp.c (DEBUG): Cleanups.
1711
17121998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1713
1714 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1715 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1716
c906108c
SS		 17171998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1718
1719 * interp.c (sim_close): Uninstall modules.
1720
1721Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1722
1723 * sim-main.h, interp.c (sim_monitor): Change to global
1724 function.
1725
1726Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1727
1728 * configure.in (vr4100): Only include vr4100 instructions in
1729 simulator.
1730 * configure: Re-generate.
1731 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1732
1733Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1734
1735 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1736 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1737 true alternative.
1738
1739 * configure.in (sim_default_gen, sim_use_gen): Replace with
1740 sim_gen.
1741 (--enable-sim-igen): Delete config option. Always using IGEN.
1742 * configure: Re-generate.
72f4393d 1743
c906108c
SS		 1744 * Makefile.in (gencode): Kill, kill, kill.
1745 * gencode.c: Ditto.
72f4393d 1746
c906108c
SS		 1747Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1748
1749 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1750 bit mips16 igen simulator.
1751 * configure: Re-generate.
1752
1753 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1754 as part of vr4100 ISA.
1755 * vr.igen: Mark all instructions as 64 bit only.
1756
1757Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1758
1759 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1760 Pacify GCC.
1761
1762Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1763
1764 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1765 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1766 * configure: Re-generate.
1767
1768 * m16.igen (BREAK): Define breakpoint instruction.
1769 (JALX32): Mark instruction as mips16 and not r3900.
1770 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1771
1772 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1773
1774Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1775
1776 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1777 insn as a debug breakpoint.
1778
1779 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1780 pending.slot_size.
1781 (PENDING_SCHED): Clean up trace statement.
1782 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1783 (PENDING_FILL): Delay write by only one cycle.
1784 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1785
1786 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1787 of pending writes.
1788 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1789 32 & 64.
1790 (pending_tick): Move incrementing of index to FOR statement.
1791 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1792
c906108c
SS		 1793 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1794 build simulator.
1795 * configure: Re-generate.
72f4393d 1796
c906108c
SS		 1797 * interp.c (sim_engine_run OLD): Delete explicit call to
1798 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1799
c906108c
SS		 1800Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1801
1802 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1803 interrupt level number to match changed SignalExceptionInterrupt
1804 macro.
1805
1806Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1807
1808 * interp.c: #include "itable.h" if WITH_IGEN.
1809 (get_insn_name): New function.
1810 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1811 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1812
1813Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1814
1815 * configure: Rebuilt to inhale new common/aclocal.m4.
1816
1817Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1818
1819 * dv-tx3904sio.c: Include sim-assert.h.
1820
1821Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1822
1823 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1824 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1825 Reorganize target-specific sim-hardware checks.
1826 * configure: rebuilt.
1827 * interp.c (sim_open): For tx39 target boards, set
1828 OPERATING_ENVIRONMENT, add tx3904sio devices.
1829 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1830 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1831
c906108c
SS		 1832 * dv-tx3904irc.c: Compiler warning clean-up.
1833 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1834 frequent hw-trace messages.
1835
1836Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1837
1838 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1839
1840Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1841
1842 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1843
1844 * vr.igen: New file.
1845 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1846 * mips.igen: Define vr4100 model. Include vr.igen.
1847Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1848
1849 * mips.igen (check_mf_hilo): Correct check.
1850
1851Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1852
1853 * sim-main.h (interrupt_event): Add prototype.
1854
1855 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1856 register_ptr, register_value.
1857 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1858
1859 * sim-main.h (tracefh): Make extern.
1860
1861Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1862
1863 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1864 Reduce unnecessarily high timer event frequency.
c906108c 1865 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1866
c906108c
SS		 1867Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1868
1869 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1870 to allay warnings.
1871 (interrupt_event): Made non-static.
72f4393d 1872
c906108c
SS		 1873 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1874 interchange of configuration values for external vs. internal
1875 clock dividers.
72f4393d 1876
c906108c
SS		 1877Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1878
72f4393d 1879 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1880 simulator-reserved break instructions.
1881 * gencode.c (build_instruction): Ditto.
1882 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1883 reserved instructions now use exception vector, rather
c906108c
SS		 1884 than halting sim.
1885 * sim-main.h: Moved magic constants to here.
1886
1887Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1888
1889 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1890 register upon non-zero interrupt event level, clear upon zero
1891 event value.
1892 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1893 by passing zero event value.
1894 (*_io_{read,write}_buffer): Endianness fixes.
1895 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1896 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1897
1898 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1899 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 1900
c906108c
SS		 1901Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1902
72f4393d 1903 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 1904 and BigEndianCPU.
1905
1906Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1907
1908 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1909 parts.
1910 * configure: Update.
1911
1912Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1913
1914 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1915 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1916 * configure.in: Include tx3904tmr in hw_device list.
1917 * configure: Rebuilt.
1918 * interp.c (sim_open): Instantiate three timer instances.
1919 Fix address typo of tx3904irc instance.
1920
1921Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1922
1923 * interp.c (signal_exception): SystemCall exception now uses
1924 the exception vector.
1925
1926Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1927
1928 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1929 to allay warnings.
1930
1931Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1932
1933 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1934
1935Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1936
1937 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1938
1939 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1940 sim-main.h. Declare a struct hw_descriptor instead of struct
1941 hw_device_descriptor.
1942
1943Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1944
1945 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1946 right bits and then re-align left hand bytes to correct byte
1947 lanes. Fix incorrect computation in do_store_left when loading
1948 bytes from second word.
1949
1950Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1951
1952 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1953 * interp.c (sim_open): Only create a device tree when HW is
1954 enabled.
1955
1956 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1957 * interp.c (signal_exception): Ditto.
1958
1959Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1960
1961 * gencode.c: Mark BEGEZALL as LIKELY.
1962
1963Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1964
1965 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1966 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 1967
c906108c
SS		 1968Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1969
1970 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1971 modules. Recognize TX39 target with "mips*tx39" pattern.
1972 * configure: Rebuilt.
1973 * sim-main.h (*): Added many macros defining bits in
1974 TX39 control registers.
1975 (SignalInterrupt): Send actual PC instead of NULL.
1976 (SignalNMIReset): New exception type.
1977 * interp.c (board): New variable for future use to identify
1978 a particular board being simulated.
1979 (mips_option_handler,mips_options): Added "--board" option.
1980 (interrupt_event): Send actual PC.
1981 (sim_open): Make memory layout conditional on board setting.
1982 (signal_exception): Initial implementation of hardware interrupt
1983 handling. Accept another break instruction variant for simulator
1984 exit.
1985 (decode_coproc): Implement RFE instruction for TX39.
1986 (mips.igen): Decode RFE instruction as such.
1987 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1988 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1989 bbegin to implement memory map.
1990 * dv-tx3904cpu.c: New file.
1991 * dv-tx3904irc.c: New file.
1992
1993Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1994
1995 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1996
1997Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1998
1999 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2000 with calls to check_div_hilo.
2001
2002Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2003
2004 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2005 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2006 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2007 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2008 with calls to check_mult_hilo.
2009 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2010 with calls to check_div_hilo.
2011
2012Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2013
2014 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2015 Document a replacement.
2016
2017Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2018
2019 * interp.c (sim_monitor): Make mon_printf work.
2020
2021Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2022
2023 * sim-main.h (INSN_NAME): New arg `cpu'.
2024
2025Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2026
72f4393d 2027 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2028
2029Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2030
2031 * configure: Regenerated to track ../common/aclocal.m4 changes.
2032 * config.in: Ditto.
2033
2034Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2035
2036 * acconfig.h: New file.
2037 * configure.in: Reverted change of Apr 24; use sinclude again.
2038
2039Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2040
2041 * configure: Regenerated to track ../common/aclocal.m4 changes.
2042 * config.in: Ditto.
2043
2044Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2045
2046 * configure.in: Don't call sinclude.
2047
2048Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2049
2050 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2051
2052Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2053
2054 * mips.igen (ERET): Implement.
2055
2056 * interp.c (decode_coproc): Return sign-extended EPC.
2057
2058 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2059
2060 * interp.c (signal_exception): Do not ignore Trap.
2061 (signal_exception): On TRAP, restart at exception address.
2062 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2063 (signal_exception): Update.
2064 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2065 so that TRAP instructions are caught.
2066
2067Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2068
2069 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2070 contains HI/LO access history.
2071 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2072 (HIACCESS, LOACCESS): Delete, replace with
2073 (HIHISTORY, LOHISTORY): New macros.
2074 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2075
c906108c
SS		 2076 * gencode.c (build_instruction): Do not generate checks for
2077 correct HI/LO register usage.
2078
2079 * interp.c (old_engine_run): Delete checks for correct HI/LO
2080 register usage.
2081
2082 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2083 check_mf_cycles): New functions.
2084 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2085 do_divu, domultx, do_mult, do_multu): Use.
2086
2087 * tx.igen ("madd", "maddu"): Use.
72f4393d 2088
c906108c
SS		 2089Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2090
2091 * mips.igen (DSRAV): Use function do_dsrav.
2092 (SRAV): Use new function do_srav.
2093
2094 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2095 (B): Sign extend 11 bit immediate.
2096 (EXT-B*): Shift 16 bit immediate left by 1.
2097 (ADDIU*): Don't sign extend immediate value.
2098
2099Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2100
2101 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2102
2103 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2104 functions.
2105
2106 * mips.igen (delayslot32, nullify_next_insn): New functions.
2107 (m16.igen): Always include.
2108 (do_*): Add more tracing.
2109
2110 * m16.igen (delayslot16): Add NIA argument, could be called by a
2111 32 bit MIPS16 instruction.
72f4393d 2112
c906108c
SS		 2113 * interp.c (ifetch16): Move function from here.
2114 * sim-main.c (ifetch16): To here.
72f4393d 2115
c906108c
SS		 2116 * sim-main.c (ifetch16, ifetch32): Update to match current
2117 implementations of LH, LW.
2118 (signal_exception): Don't print out incorrect hex value of illegal
2119 instruction.
2120
2121Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2122
2123 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2124 instruction.
2125
2126 * m16.igen: Implement MIPS16 instructions.
72f4393d 2127
c906108c
SS		 2128 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2129 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2130 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2131 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2132 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2133 bodies of corresponding code from 32 bit insn to these. Also used
2134 by MIPS16 versions of functions.
72f4393d 2135
c906108c
SS		 2136 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2137 (IMEM16): Drop NR argument from macro.
2138
2139Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2140
2141 * Makefile.in (SIM_OBJS): Add sim-main.o.
2142
2143 * sim-main.h (address_translation, load_memory, store_memory,
2144 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2145 as INLINE_SIM_MAIN.
2146 (pr_addr, pr_uword64): Declare.
2147 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2148
c906108c
SS		 2149 * interp.c (address_translation, load_memory, store_memory,
2150 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2151 from here.
2152 * sim-main.c: To here. Fix compilation problems.
72f4393d 2153
c906108c
SS		 2154 * configure.in: Enable inlining.
2155 * configure: Re-config.
2156
2157Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2158
2159 * configure: Regenerated to track ../common/aclocal.m4 changes.
2160
2161Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2162
2163 * mips.igen: Include tx.igen.
2164 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2165 * tx.igen: New file, contains MADD and MADDU.
2166
2167 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2168 the hardwired constant `7'.
2169 (store_memory): Ditto.
2170 (LOADDRMASK): Move definition to sim-main.h.
2171
2172 mips.igen (MTC0): Enable for r3900.
2173 (ADDU): Add trace.
2174
2175 mips.igen (do_load_byte): Delete.
2176 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2177 do_store_right): New functions.
2178 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2179
2180 configure.in: Let the tx39 use igen again.
2181 configure: Update.
72f4393d 2182
c906108c
SS		 2183Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2184
2185 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2186 not an address sized quantity. Return zero for cache sizes.
2187
2188Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2189
2190 * mips.igen (r3900): r3900 does not support 64 bit integer
2191 operations.
2192
2193Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2194
2195 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2196 than igen one.
2197 * configure : Rebuild.
72f4393d 2198
c906108c
SS		 2199Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2200
2201 * configure: Regenerated to track ../common/aclocal.m4 changes.
2202
2203Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2204
2205 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2206
2207Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2208
2209 * configure: Regenerated to track ../common/aclocal.m4 changes.
2210 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2211
2212Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2213
2214 * configure: Regenerated to track ../common/aclocal.m4 changes.
2215
2216Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2217
2218 * interp.c (Max, Min): Comment out functions. Not yet used.
2219
2220Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2221
2222 * configure: Regenerated to track ../common/aclocal.m4 changes.
2223
2224Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2225
2226 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2227 configurable settings for stand-alone simulator.
72f4393d 2228
c906108c 2229 * configure.in: Added X11 search, just in case.
72f4393d 2230
c906108c
SS		 2231 * configure: Regenerated.
2232
2233Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2234
2235 * interp.c (sim_write, sim_read, load_memory, store_memory):
2236 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2237
2238Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2239
2240 * sim-main.h (GETFCC): Return an unsigned value.
2241
2242Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2243
2244 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2245 (DADD): Result destination is RD not RT.
2246
2247Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2248
2249 * sim-main.h (HIACCESS, LOACCESS): Always define.
2250
2251 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2252
2253 * interp.c (sim_info): Delete.
2254
2255Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2256
2257 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2258 (mips_option_handler): New argument `cpu'.
2259 (sim_open): Update call to sim_add_option_table.
2260
2261Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2262
2263 * mips.igen (CxC1): Add tracing.
2264
2265Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2266
2267 * sim-main.h (Max, Min): Declare.
2268
2269 * interp.c (Max, Min): New functions.
2270
2271 * mips.igen (BC1): Add tracing.
72f4393d 2272
c906108c 2273Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2274
c906108c 2275 * interp.c Added memory map for stack in vr4100
72f4393d 2276
c906108c
SS		 2277Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2278
2279 * interp.c (load_memory): Add missing "break"'s.
2280
2281Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2282
2283 * interp.c (sim_store_register, sim_fetch_register): Pass in
2284 length parameter. Return -1.
2285
2286Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2287
2288 * interp.c: Added hardware init hook, fixed warnings.
2289
2290Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2291
2292 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2293
2294Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2295
2296 * interp.c (ifetch16): New function.
2297
2298 * sim-main.h (IMEM32): Rename IMEM.
2299 (IMEM16_IMMED): Define.
2300 (IMEM16): Define.
2301 (DELAY_SLOT): Update.
72f4393d 2302
c906108c 2303 * m16run.c (sim_engine_run): New file.
72f4393d 2304
c906108c
SS		 2305 * m16.igen: All instructions except LB.
2306 (LB): Call do_load_byte.
2307 * mips.igen (do_load_byte): New function.
2308 (LB): Call do_load_byte.
2309
2310 * mips.igen: Move spec for insn bit size and high bit from here.
2311 * Makefile.in (tmp-igen, tmp-m16): To here.
2312
2313 * m16.dc: New file, decode mips16 instructions.
2314
2315 * Makefile.in (SIM_NO_ALL): Define.
2316 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2317
2318Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2319
2320 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2321 point unit to 32 bit registers.
2322 * configure: Re-generate.
2323
2324Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2325
2326 * configure.in (sim_use_gen): Make IGEN the default simulator
2327 generator for generic 32 and 64 bit mips targets.
2328 * configure: Re-generate.
2329
2330Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2331
2332 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2333 bitsize.
2334
2335 * interp.c (sim_fetch_register, sim_store_register): Read/write
2336 FGR from correct location.
2337 (sim_open): Set size of FGR's according to
2338 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2339
c906108c
SS		 2340 * sim-main.h (FGR): Store floating point registers in a separate
2341 array.
2342
2343Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2344
2345 * configure: Regenerated to track ../common/aclocal.m4 changes.
2346
2347Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2348
2349 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2350
2351 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2352
2353 * interp.c (pending_tick): New function. Deliver pending writes.
2354
2355 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2356 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2357 it can handle mixed sized quantites and single bits.
72f4393d 2358
c906108c
SS		 2359Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2360
2361 * interp.c (oengine.h): Do not include when building with IGEN.
2362 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2363 (sim_info): Ditto for PROCESSOR_64BIT.
2364 (sim_monitor): Replace ut_reg with unsigned_word.
2365 (*): Ditto for t_reg.
2366 (LOADDRMASK): Define.
2367 (sim_open): Remove defunct check that host FP is IEEE compliant,
2368 using software to emulate floating point.
2369 (value_fpr, ...): Always compile, was conditional on HASFPU.
2370
2371Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2372
2373 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2374 size.
2375
2376 * interp.c (SD, CPU): Define.
2377 (mips_option_handler): Set flags in each CPU.
2378 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2379 (sim_close): Do not clear STATE, deleted anyway.
2380 (sim_write, sim_read): Assume CPU zero's vm should be used for
2381 data transfers.
2382 (sim_create_inferior): Set the PC for all processors.
2383 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2384 argument.
2385 (mips16_entry): Pass correct nr of args to store_word, load_word.
2386 (ColdReset): Cold reset all cpu's.
2387 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2388 (sim_monitor, load_memory, store_memory, signal_exception): Use
2389 `CPU' instead of STATE_CPU.
2390
2391
2392 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2393 SD or CPU_.
72f4393d 2394
c906108c
SS		 2395 * sim-main.h (signal_exception): Add sim_cpu arg.
2396 (SignalException*): Pass both SD and CPU to signal_exception.
2397 * interp.c (signal_exception): Update.
72f4393d 2398
c906108c
SS		 2399 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2400 Ditto
2401 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2402 address_translation): Ditto
2403 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2404
c906108c
SS		 2405Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2406
2407 * configure: Regenerated to track ../common/aclocal.m4 changes.
2408
2409Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2410
2411 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2412
72f4393d 2413 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2414
2415 * sim-main.h (CPU_CIA): Delete.
2416 (SET_CIA, GET_CIA): Define
2417
2418Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2419
2420 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2421 regiser.
2422
2423 * configure.in (default_endian): Configure a big-endian simulator
2424 by default.
2425 * configure: Re-generate.
72f4393d 2426
c906108c
SS		 2427Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2428
2429 * configure: Regenerated to track ../common/aclocal.m4 changes.
2430
2431Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2432
2433 * interp.c (sim_monitor): Handle Densan monitor outbyte
2434 and inbyte functions.
2435
24361997-12-29 Felix Lee <flee@cygnus.com>
2437
2438 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2439
2440Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2441
2442 * Makefile.in (tmp-igen): Arrange for $zero to always be
2443 reset to zero after every instruction.
2444
2445Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2446
2447 * configure: Regenerated to track ../common/aclocal.m4 changes.
2448 * config.in: Ditto.
2449
2450Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2451
2452 * mips.igen (MSUB): Fix to work like MADD.
2453 * gencode.c (MSUB): Similarly.
2454
2455Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2456
2457 * configure: Regenerated to track ../common/aclocal.m4 changes.
2458
2459Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2460
2461 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2462
2463Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2464
2465 * sim-main.h (sim-fpu.h): Include.
2466
2467 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2468 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2469 using host independant sim_fpu module.
2470
2471Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2472
2473 * interp.c (signal_exception): Report internal errors with SIGABRT
2474 not SIGQUIT.
2475
2476 * sim-main.h (C0_CONFIG): New register.
2477 (signal.h): No longer include.
2478
2479 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2480
2481Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2482
2483 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2484
2485Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2486
2487 * mips.igen: Tag vr5000 instructions.
2488 (ANDI): Was missing mipsIV model, fix assembler syntax.
2489 (do_c_cond_fmt): New function.
2490 (C.cond.fmt): Handle mips I-III which do not support CC field
2491 separatly.
2492 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2493 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2494 in IV3.2 spec.
2495 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2496 vr5000 which saves LO in a GPR separatly.
72f4393d 2497
c906108c
SS		 2498 * configure.in (enable-sim-igen): For vr5000, select vr5000
2499 specific instructions.
2500 * configure: Re-generate.
72f4393d 2501
c906108c
SS		 2502Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2503
2504 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2505
2506 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2507 fmt_uninterpreted_64 bit cases to switch. Convert to
2508 fmt_formatted,
2509
2510 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2511
2512 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2513 as specified in IV3.2 spec.
2514 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2515
2516Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2517
2518 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2519 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2520 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2521 PENDING_FILL versions of instructions. Simplify.
2522 (X): New function.
2523 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2524 instructions.
2525 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2526 a signed value.
2527 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2528
c906108c
SS		 2529 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2530 global.
2531 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2532
2533Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2534
2535 * gencode.c (build_mips16_operands): Replace IPC with cia.
2536
2537 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2538 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2539 IPC to `cia'.
2540 (UndefinedResult): Replace function with macro/function
2541 combination.
2542 (sim_engine_run): Don't save PC in IPC.
2543
2544 * sim-main.h (IPC): Delete.
2545
2546
2547 * interp.c (signal_exception, store_word, load_word,
2548 address_translation, load_memory, store_memory, cache_op,
2549 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2550 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2551 current instruction address - cia - argument.
2552 (sim_read, sim_write): Call address_translation directly.
2553 (sim_engine_run): Rename variable vaddr to cia.
2554 (signal_exception): Pass cia to sim_monitor
72f4393d 2555
c906108c
SS		 2556 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2557 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2558 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2559
2560 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2561 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2562 SIM_ASSERT.
72f4393d 2563
c906108c
SS		 2564 * interp.c (signal_exception): Pass restart address to
2565 sim_engine_restart.
2566
2567 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2568 idecode.o): Add dependency.
2569
2570 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2571 Delete definitions
2572 (DELAY_SLOT): Update NIA not PC with branch address.
2573 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2574
2575 * mips.igen: Use CIA not PC in branch calculations.
2576 (illegal): Call SignalException.
2577 (BEQ, ADDIU): Fix assembler.
2578
2579Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2580
2581 * m16.igen (JALX): Was missing.
2582
2583 * configure.in (enable-sim-igen): New configuration option.
2584 * configure: Re-generate.
72f4393d 2585
c906108c
SS		 2586 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2587
2588 * interp.c (load_memory, store_memory): Delete parameter RAW.
2589 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2590 bypassing {load,store}_memory.
2591
2592 * sim-main.h (ByteSwapMem): Delete definition.
2593
2594 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2595
2596 * interp.c (sim_do_command, sim_commands): Delete mips specific
2597 commands. Handled by module sim-options.
72f4393d 2598
c906108c
SS		 2599 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2600 (WITH_MODULO_MEMORY): Define.
2601
2602 * interp.c (sim_info): Delete code printing memory size.
2603
2604 * interp.c (mips_size): Nee sim_size, delete function.
2605 (power2): Delete.
2606 (monitor, monitor_base, monitor_size): Delete global variables.
2607 (sim_open, sim_close): Delete code creating monitor and other
2608 memory regions. Use sim-memopts module, via sim_do_commandf, to
2609 manage memory regions.
2610 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2611
c906108c
SS		 2612 * interp.c (address_translation): Delete all memory map code
2613 except line forcing 32 bit addresses.
2614
2615Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2616
2617 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2618 trace options.
2619
2620 * interp.c (logfh, logfile): Delete globals.
2621 (sim_open, sim_close): Delete code opening & closing log file.
2622 (mips_option_handler): Delete -l and -n options.
2623 (OPTION mips_options): Ditto.
2624
2625 * interp.c (OPTION mips_options): Rename option trace to dinero.
2626 (mips_option_handler): Update.
2627
2628Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2629
2630 * interp.c (fetch_str): New function.
2631 (sim_monitor): Rewrite using sim_read & sim_write.
2632 (sim_open): Check magic number.
2633 (sim_open): Write monitor vectors into memory using sim_write.
2634 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2635 (sim_read, sim_write): Simplify - transfer data one byte at a
2636 time.
2637 (load_memory, store_memory): Clarify meaning of parameter RAW.
2638
2639 * sim-main.h (isHOST): Defete definition.
2640 (isTARGET): Mark as depreciated.
2641 (address_translation): Delete parameter HOST.
2642
2643 * interp.c (address_translation): Delete parameter HOST.
2644
2645Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2646
72f4393d 2647 * mips.igen:
c906108c
SS		 2648
2649 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2650 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2651
2652Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2653
2654 * mips.igen: Add model filter field to records.
2655
2656Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2657
2658 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2659
c906108c
SS		 2660 interp.c (sim_engine_run): Do not compile function sim_engine_run
2661 when WITH_IGEN == 1.
2662
2663 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2664 target architecture.
2665
2666 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2667 igen. Replace with configuration variables sim_igen_flags /
2668 sim_m16_flags.
2669
2670 * m16.igen: New file. Copy mips16 insns here.
2671 * mips.igen: From here.
2672
2673Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2674
2675 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2676 to top.
2677 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2678
2679Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2680
2681 * gencode.c (build_instruction): Follow sim_write's lead in using
2682 BigEndianMem instead of !ByteSwapMem.
2683
2684Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2685
2686 * configure.in (sim_gen): Dependent on target, select type of
2687 generator. Always select old style generator.
2688
2689 configure: Re-generate.
2690
2691 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2692 targets.
2693 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2694 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2695 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2696 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2697 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2698
c906108c
SS		 2699Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2700
2701 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2702
2703 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2704 CURRENT_FLOATING_POINT instead.
2705
2706 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2707 (address_translation): Raise exception InstructionFetch when
2708 translation fails and isINSTRUCTION.
72f4393d 2709
c906108c
SS		 2710 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2711 sim_engine_run): Change type of of vaddr and paddr to
2712 address_word.
2713 (address_translation, prefetch, load_memory, store_memory,
2714 cache_op): Change type of vAddr and pAddr to address_word.
2715
2716 * gencode.c (build_instruction): Change type of vaddr and paddr to
2717 address_word.
2718
2719Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2720
2721 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2722 macro to obtain result of ALU op.
2723
2724Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2725
2726 * interp.c (sim_info): Call profile_print.
2727
2728Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2729
2730 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2731
2732 * sim-main.h (WITH_PROFILE): Do not define, defined in
2733 common/sim-config.h. Use sim-profile module.
2734 (simPROFILE): Delete defintion.
2735
2736 * interp.c (PROFILE): Delete definition.
2737 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2738 (sim_close): Delete code writing profile histogram.
2739 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2740 Delete.
2741 (sim_engine_run): Delete code profiling the PC.
2742
2743Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2744
2745 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2746
2747 * interp.c (sim_monitor): Make register pointers of type
2748 unsigned_word*.
2749
2750 * sim-main.h: Make registers of type unsigned_word not
2751 signed_word.
2752
2753Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2754
2755 * interp.c (sync_operation): Rename from SyncOperation, make
2756 global, add SD argument.
2757 (prefetch): Rename from Prefetch, make global, add SD argument.
2758 (decode_coproc): Make global.
2759
2760 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2761
2762 * gencode.c (build_instruction): Generate DecodeCoproc not
2763 decode_coproc calls.
2764
2765 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2766 (SizeFGR): Move to sim-main.h
2767 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2768 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2769 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2770 sim-main.h.
2771 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2772 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2773 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2774 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2775 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2776 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2777
c906108c
SS		 2778 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2779 exception.
2780 (sim-alu.h): Include.
2781 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2782 (sim_cia): Typedef to instruction_address.
72f4393d 2783
c906108c
SS		 2784Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2785
2786 * Makefile.in (interp.o): Rename generated file engine.c to
2787 oengine.c.
72f4393d 2788
c906108c 2789 * interp.c: Update.
72f4393d 2790
c906108c
SS		 2791Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2792
2793 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2794
c906108c
SS		 2795Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2796
2797 * gencode.c (build_instruction): For "FPSQRT", output correct
2798 number of arguments to Recip.
72f4393d 2799
c906108c
SS		 2800Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2801
2802 * Makefile.in (interp.o): Depends on sim-main.h
2803
2804 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2805
2806 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2807 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2808 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2809 STATE, DSSTATE): Define
2810 (GPR, FGRIDX, ..): Define.
2811
2812 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2813 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2814 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2815
c906108c 2816 * interp.c: Update names to match defines from sim-main.h
72f4393d 2817
c906108c
SS		 2818Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2819
2820 * interp.c (sim_monitor): Add SD argument.
2821 (sim_warning): Delete. Replace calls with calls to
2822 sim_io_eprintf.
2823 (sim_error): Delete. Replace calls with sim_io_error.
2824 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2825 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2826 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2827 argument.
2828 (mips_size): Rename from sim_size. Add SD argument.
2829
2830 * interp.c (simulator): Delete global variable.
2831 (callback): Delete global variable.
2832 (mips_option_handler, sim_open, sim_write, sim_read,
2833 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2834 sim_size,sim_monitor): Use sim_io_* not callback->*.
2835 (sim_open): ZALLOC simulator struct.
2836 (PROFILE): Do not define.
2837
2838Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2839
2840 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2841 support.h with corresponding code.
2842
2843 * sim-main.h (word64, uword64), support.h: Move definition to
2844 sim-main.h.
2845 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2846
2847 * support.h: Delete
2848 * Makefile.in: Update dependencies
2849 * interp.c: Do not include.
72f4393d 2850
c906108c
SS		 2851Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2852
2853 * interp.c (address_translation, load_memory, store_memory,
2854 cache_op): Rename to from AddressTranslation et.al., make global,
2855 add SD argument
72f4393d 2856
c906108c
SS		 2857 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2858 CacheOp): Define.
72f4393d 2859
c906108c
SS		 2860 * interp.c (SignalException): Rename to signal_exception, make
2861 global.
2862
2863 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2864
c906108c
SS		 2865 * sim-main.h (SignalException, SignalExceptionInterrupt,
2866 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2867 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2868 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2869 Define.
72f4393d 2870
c906108c 2871 * interp.c, support.h: Use.
72f4393d 2872
c906108c
SS		 2873Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2874
2875 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2876 to value_fpr / store_fpr. Add SD argument.
2877 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2878 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2879
2880 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2881
c906108c
SS		 2882Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2883
2884 * interp.c (sim_engine_run): Check consistency between configure
2885 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2886 and HASFPU.
2887
2888 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 2889 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 2890 (mips_endian): Configure WITH_TARGET_ENDIAN.
2891 * configure: Update.
2892
2893Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2894
2895 * configure: Regenerated to track ../common/aclocal.m4 changes.
2896
2897Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2898
2899 * configure: Regenerated.
2900
2901Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2902
2903 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2904
2905Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2906
2907 * gencode.c (print_igen_insn_models): Assume certain architectures
2908 include all mips* instructions.
2909 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2910 instruction.
2911
2912 * Makefile.in (tmp.igen): Add target. Generate igen input from
2913 gencode file.
2914
2915 * gencode.c (FEATURE_IGEN): Define.
2916 (main): Add --igen option. Generate output in igen format.
2917 (process_instructions): Format output according to igen option.
2918 (print_igen_insn_format): New function.
2919 (print_igen_insn_models): New function.
2920 (process_instructions): Only issue warnings and ignore
2921 instructions when no FEATURE_IGEN.
2922
2923Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2924
2925 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2926 MIPS targets.
2927
2928Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2929
2930 * configure: Regenerated to track ../common/aclocal.m4 changes.
2931
2932Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2933
2934 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2935 SIM_RESERVED_BITS): Delete, moved to common.
2936 (SIM_EXTRA_CFLAGS): Update.
72f4393d 2937
c906108c
SS		 2938Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2939
2940 * configure.in: Configure non-strict memory alignment.
2941 * configure: Regenerated to track ../common/aclocal.m4 changes.
2942
2943Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2944
2945 * configure: Regenerated to track ../common/aclocal.m4 changes.
2946
2947Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2948
2949 * gencode.c (SDBBP,DERET): Added (3900) insns.
2950 (RFE): Turn on for 3900.
2951 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2952 (dsstate): Made global.
2953 (SUBTARGET_R3900): Added.
2954 (CANCELDELAYSLOT): New.
2955 (SignalException): Ignore SystemCall rather than ignore and
2956 terminate. Add DebugBreakPoint handling.
2957 (decode_coproc): New insns RFE, DERET; and new registers Debug
2958 and DEPC protected by SUBTARGET_R3900.
2959 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2960 bits explicitly.
2961 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 2962 * configure: Update.
c906108c
SS		 2963
2964Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2965
2966 * gencode.c: Add r3900 (tx39).
72f4393d 2967
c906108c
SS		 2968
2969Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2970
2971 * gencode.c (build_instruction): Don't need to subtract 4 for
2972 JALR, just 2.
2973
2974Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2975
2976 * interp.c: Correct some HASFPU problems.
2977
2978Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2979
2980 * configure: Regenerated to track ../common/aclocal.m4 changes.
2981
2982Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2983
2984 * interp.c (mips_options): Fix samples option short form, should
2985 be `x'.
2986
2987Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2988
2989 * interp.c (sim_info): Enable info code. Was just returning.
2990
2991Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2992
2993 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2994 MFC0.
2995
2996Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2997
2998 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2999 constants.
3000 (build_instruction): Ditto for LL.
3001
3002Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3003
3004 * configure: Regenerated to track ../common/aclocal.m4 changes.
3005
3006Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3007
3008 * configure: Regenerated to track ../common/aclocal.m4 changes.
3009 * config.in: Ditto.
3010
3011Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3012
3013 * interp.c (sim_open): Add call to sim_analyze_program, update
3014 call to sim_config.
3015
3016Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3017
3018 * interp.c (sim_kill): Delete.
3019 (sim_create_inferior): Add ABFD argument. Set PC from same.
3020 (sim_load): Move code initializing trap handlers from here.
3021 (sim_open): To here.
3022 (sim_load): Delete, use sim-hload.c.
3023
3024 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3025
3026Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3027
3028 * configure: Regenerated to track ../common/aclocal.m4 changes.
3029 * config.in: Ditto.
3030
3031Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3032
3033 * interp.c (sim_open): Add ABFD argument.
3034 (sim_load): Move call to sim_config from here.
3035 (sim_open): To here. Check return status.
3036
3037Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3038
c906108c
SS		 3039 * gencode.c (build_instruction): Two arg MADD should
3040 not assign result to $0.
72f4393d 3041
c906108c
SS		 3042Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3043
3044 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3045 * sim/mips/configure.in: Regenerate.
3046
3047Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3048
3049 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3050 signed8, unsigned8 et.al. types.
3051
3052 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3053 hosts when selecting subreg.
3054
3055Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3056
3057 * interp.c (sim_engine_run): Reset the ZERO register to zero
3058 regardless of FEATURE_WARN_ZERO.
3059 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3060
3061Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3062
3063 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3064 (SignalException): For BreakPoints ignore any mode bits and just
3065 save the PC.
3066 (SignalException): Always set the CAUSE register.
3067
3068Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3069
3070 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3071 exception has been taken.
3072
3073 * interp.c: Implement the ERET and mt/f sr instructions.
3074
3075Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3076
3077 * interp.c (SignalException): Don't bother restarting an
3078 interrupt.
3079
3080Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3081
3082 * interp.c (SignalException): Really take an interrupt.
3083 (interrupt_event): Only deliver interrupts when enabled.
3084
3085Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3086
3087 * interp.c (sim_info): Only print info when verbose.
3088 (sim_info) Use sim_io_printf for output.
72f4393d 3089
c906108c
SS		 3090Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3091
3092 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3093 mips architectures.
3094
3095Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3096
3097 * interp.c (sim_do_command): Check for common commands if a
3098 simulator specific command fails.
3099
3100Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3101
3102 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3103 and simBE when DEBUG is defined.
3104
3105Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3106
3107 * interp.c (interrupt_event): New function. Pass exception event
3108 onto exception handler.
3109
3110 * configure.in: Check for stdlib.h.
3111 * configure: Regenerate.
3112
3113 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3114 variable declaration.
3115 (build_instruction): Initialize memval1.
3116 (build_instruction): Add UNUSED attribute to byte, bigend,
3117 reverse.
3118 (build_operands): Ditto.
3119
3120 * interp.c: Fix GCC warnings.
3121 (sim_get_quit_code): Delete.
3122
3123 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3124 * Makefile.in: Ditto.
3125 * configure: Re-generate.
72f4393d 3126
c906108c
SS		 3127 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3128
3129Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3130
3131 * interp.c (mips_option_handler): New function parse argumes using
3132 sim-options.
3133 (myname): Replace with STATE_MY_NAME.
3134 (sim_open): Delete check for host endianness - performed by
3135 sim_config.
3136 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3137 (sim_open): Move much of the initialization from here.
3138 (sim_load): To here. After the image has been loaded and
3139 endianness set.
3140 (sim_open): Move ColdReset from here.
3141 (sim_create_inferior): To here.
3142 (sim_open): Make FP check less dependant on host endianness.
3143
3144 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3145 run.
3146 * interp.c (sim_set_callbacks): Delete.
3147
3148 * interp.c (membank, membank_base, membank_size): Replace with
3149 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3150 (sim_open): Remove call to callback->init. gdb/run do this.
3151
3152 * interp.c: Update
3153
3154 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3155
3156 * interp.c (big_endian_p): Delete, replaced by
3157 current_target_byte_order.
3158
3159Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3160
3161 * interp.c (host_read_long, host_read_word, host_swap_word,
3162 host_swap_long): Delete. Using common sim-endian.
3163 (sim_fetch_register, sim_store_register): Use H2T.
3164 (pipeline_ticks): Delete. Handled by sim-events.
3165 (sim_info): Update.
3166 (sim_engine_run): Update.
3167
3168Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3169
3170 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3171 reason from here.
3172 (SignalException): To here. Signal using sim_engine_halt.
3173 (sim_stop_reason): Delete, moved to common.
72f4393d 3174
c906108c
SS		 3175Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3176
3177 * interp.c (sim_open): Add callback argument.
3178 (sim_set_callbacks): Delete SIM_DESC argument.
3179 (sim_size): Ditto.
3180
3181Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3182
3183 * Makefile.in (SIM_OBJS): Add common modules.
3184
3185 * interp.c (sim_set_callbacks): Also set SD callback.
3186 (set_endianness, xfer_*, swap_*): Delete.
3187 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3188 Change to functions using sim-endian macros.
3189 (control_c, sim_stop): Delete, use common version.
3190 (simulate): Convert into.
3191 (sim_engine_run): This function.
3192 (sim_resume): Delete.
72f4393d 3193
c906108c
SS		 3194 * interp.c (simulation): New variable - the simulator object.
3195 (sim_kind): Delete global - merged into simulation.
3196 (sim_load): Cleanup. Move PC assignment from here.
3197 (sim_create_inferior): To here.
3198
3199 * sim-main.h: New file.
3200 * interp.c (sim-main.h): Include.
72f4393d 3201
c906108c
SS		 3202Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3203
3204 * configure: Regenerated to track ../common/aclocal.m4 changes.
3205
3206Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3207
3208 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3209
3210Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3211
72f4393d
L		 3212 * gencode.c (build_instruction): DIV instructions: check
3213 for division by zero and integer overflow before using
c906108c
SS		 3214 host's division operation.
3215
3216Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3217
3218 * Makefile.in (SIM_OBJS): Add sim-load.o.
3219 * interp.c: #include bfd.h.
3220 (target_byte_order): Delete.
3221 (sim_kind, myname, big_endian_p): New static locals.
3222 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3223 after argument parsing. Recognize -E arg, set endianness accordingly.
3224 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3225 load file into simulator. Set PC from bfd.
3226 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3227 (set_endianness): Use big_endian_p instead of target_byte_order.
3228
3229Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3230
3231 * interp.c (sim_size): Delete prototype - conflicts with
3232 definition in remote-sim.h. Correct definition.
3233
3234Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3235
3236 * configure: Regenerated to track ../common/aclocal.m4 changes.
3237 * config.in: Ditto.
3238
3239Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3240
3241 * interp.c (sim_open): New arg `kind'.
3242
3243 * configure: Regenerated to track ../common/aclocal.m4 changes.
3244
3245Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3246
3247 * configure: Regenerated to track ../common/aclocal.m4 changes.
3248
3249Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3250
3251 * interp.c (sim_open): Set optind to 0 before calling getopt.
3252
3253Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3254
3255 * configure: Regenerated to track ../common/aclocal.m4 changes.
3256
3257Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3258
3259 * interp.c : Replace uses of pr_addr with pr_uword64
3260 where the bit length is always 64 independent of SIM_ADDR.
3261 (pr_uword64) : added.
3262
3263Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3264
3265 * configure: Re-generate.
3266
3267Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3268
3269 * configure: Regenerate to track ../common/aclocal.m4 changes.
3270
3271Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3272
3273 * interp.c (sim_open): New SIM_DESC result. Argument is now
3274 in argv form.
3275 (other sim_*): New SIM_DESC argument.
3276
3277Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3278
3279 * interp.c: Fix printing of addresses for non-64-bit targets.
3280 (pr_addr): Add function to print address based on size.
3281
3282Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3283
3284 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3285
3286Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3287
3288 * gencode.c (build_mips16_operands): Correct computation of base
3289 address for extended PC relative instruction.
3290
3291Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3292
3293 * interp.c (mips16_entry): Add support for floating point cases.
3294 (SignalException): Pass floating point cases to mips16_entry.
3295 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3296 registers.
3297 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3298 or fmt_word.
3299 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3300 and then set the state to fmt_uninterpreted.
3301 (COP_SW): Temporarily set the state to fmt_word while calling
3302 ValueFPR.
3303
3304Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3305
3306 * gencode.c (build_instruction): The high order may be set in the
3307 comparison flags at any ISA level, not just ISA 4.
3308
3309Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3310
3311 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3312 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3313 * configure.in: sinclude ../common/aclocal.m4.
3314 * configure: Regenerated.
3315
3316Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3317
3318 * configure: Rebuild after change to aclocal.m4.
3319
3320Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3321
3322 * configure configure.in Makefile.in: Update to new configure
3323 scheme which is more compatible with WinGDB builds.
3324 * configure.in: Improve comment on how to run autoconf.
3325 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3326 * Makefile.in: Use autoconf substitution to install common
3327 makefile fragment.
3328
3329Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3330
3331 * gencode.c (build_instruction): Use BigEndianCPU instead of
3332 ByteSwapMem.
3333
3334Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3335
3336 * interp.c (sim_monitor): Make output to stdout visible in
3337 wingdb's I/O log window.
3338
3339Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3340
3341 * support.h: Undo previous change to SIGTRAP
3342 and SIGQUIT values.
3343
3344Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3345
3346 * interp.c (store_word, load_word): New static functions.
3347 (mips16_entry): New static function.
3348 (SignalException): Look for mips16 entry and exit instructions.
3349 (simulate): Use the correct index when setting fpr_state after
3350 doing a pending move.
3351
3352Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3353
3354 * interp.c: Fix byte-swapping code throughout to work on
3355 both little- and big-endian hosts.
3356
3357Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3358
3359 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3360 with gdb/config/i386/xm-windows.h.
3361
3362Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3363
3364 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3365 that messes up arithmetic shifts.
3366
3367Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3368
3369 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3370 SIGTRAP and SIGQUIT for _WIN32.
3371
3372Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3373
3374 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3375 force a 64 bit multiplication.
3376 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3377 destination register is 0, since that is the default mips16 nop
3378 instruction.
3379
3380Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3381
3382 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3383 (build_endian_shift): Don't check proc64.
3384 (build_instruction): Always set memval to uword64. Cast op2 to
3385 uword64 when shifting it left in memory instructions. Always use
3386 the same code for stores--don't special case proc64.
3387
3388 * gencode.c (build_mips16_operands): Fix base PC value for PC
3389 relative operands.
3390 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3391 jal instruction.
3392 * interp.c (simJALDELAYSLOT): Define.
3393 (JALDELAYSLOT): Define.
3394 (INDELAYSLOT, INJALDELAYSLOT): Define.
3395 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3396
3397Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3398
3399 * interp.c (sim_open): add flush_cache as a PMON routine
3400 (sim_monitor): handle flush_cache by ignoring it
3401
3402Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3403
3404 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3405 BigEndianMem.
3406 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3407 (BigEndianMem): Rename to ByteSwapMem and change sense.
3408 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3409 BigEndianMem references to !ByteSwapMem.
3410 (set_endianness): New function, with prototype.
3411 (sim_open): Call set_endianness.
3412 (sim_info): Use simBE instead of BigEndianMem.
3413 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3414 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3415 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3416 ifdefs, keeping the prototype declaration.
3417 (swap_word): Rewrite correctly.
3418 (ColdReset): Delete references to CONFIG. Delete endianness related
3419 code; moved to set_endianness.
72f4393d 3420
c906108c
SS		 3421Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3422
3423 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3424 * interp.c (CHECKHILO): Define away.
3425 (simSIGINT): New macro.
3426 (membank_size): Increase from 1MB to 2MB.
3427 (control_c): New function.
3428 (sim_resume): Rename parameter signal to signal_number. Add local
3429 variable prev. Call signal before and after simulate.
3430 (sim_stop_reason): Add simSIGINT support.
3431 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3432 functions always.
3433 (sim_warning): Delete call to SignalException. Do call printf_filtered
3434 if logfh is NULL.
3435 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3436 a call to sim_warning.
3437
3438Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3439
3440 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3441 16 bit instructions.
3442
3443Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3444
3445 Add support for mips16 (16 bit MIPS implementation):
3446 * gencode.c (inst_type): Add mips16 instruction encoding types.
3447 (GETDATASIZEINSN): Define.
3448 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3449 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3450 mtlo.
3451 (MIPS16_DECODE): New table, for mips16 instructions.
3452 (bitmap_val): New static function.
3453 (struct mips16_op): Define.
3454 (mips16_op_table): New table, for mips16 operands.
3455 (build_mips16_operands): New static function.
3456 (process_instructions): If PC is odd, decode a mips16
3457 instruction. Break out instruction handling into new
3458 build_instruction function.
3459 (build_instruction): New static function, broken out of
3460 process_instructions. Check modifiers rather than flags for SHIFT
3461 bit count and m[ft]{hi,lo} direction.
3462 (usage): Pass program name to fprintf.
3463 (main): Remove unused variable this_option_optind. Change
3464 ``*loptarg++'' to ``loptarg++''.
3465 (my_strtoul): Parenthesize && within ||.
3466 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3467 (simulate): If PC is odd, fetch a 16 bit instruction, and
3468 increment PC by 2 rather than 4.
3469 * configure.in: Add case for mips16*-*-*.
3470 * configure: Rebuild.
3471
3472Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3473
3474 * interp.c: Allow -t to enable tracing in standalone simulator.
3475 Fix garbage output in trace file and error messages.
3476
3477Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3478
3479 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3480 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3481 * configure.in: Simplify using macros in ../common/aclocal.m4.
3482 * configure: Regenerated.
3483 * tconfig.in: New file.
3484
3485Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3486
3487 * interp.c: Fix bugs in 64-bit port.
3488 Use ansi function declarations for msvc compiler.
3489 Initialize and test file pointer in trace code.
3490 Prevent duplicate definition of LAST_EMED_REGNUM.
3491
3492Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3493
3494 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3495
3496Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3497
3498 * interp.c (SignalException): Check for explicit terminating
3499 breakpoint value.
3500 * gencode.c: Pass instruction value through SignalException()
3501 calls for Trap, Breakpoint and Syscall.
3502
3503Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3504
3505 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3506 only used on those hosts that provide it.
3507 * configure.in: Add sqrt() to list of functions to be checked for.
3508 * config.in: Re-generated.
3509 * configure: Re-generated.
3510
3511Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3512
3513 * gencode.c (process_instructions): Call build_endian_shift when
3514 expanding STORE RIGHT, to fix swr.
3515 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3516 clear the high bits.
3517 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3518 Fix float to int conversions to produce signed values.
3519
3520Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3521
3522 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3523 (process_instructions): Correct handling of nor instruction.
3524 Correct shift count for 32 bit shift instructions. Correct sign
3525 extension for arithmetic shifts to not shift the number of bits in
3526 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3527 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3528 Fix madd.
3529 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3530 It's OK to have a mult follow a mult. What's not OK is to have a
3531 mult follow an mfhi.
3532 (Convert): Comment out incorrect rounding code.
3533
3534Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3535
3536 * interp.c (sim_monitor): Improved monitor printf
3537 simulation. Tidied up simulator warnings, and added "--log" option
3538 for directing warning message output.
3539 * gencode.c: Use sim_warning() rather than WARNING macro.
3540
3541Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3542
3543 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3544 getopt1.o, rather than on gencode.c. Link objects together.
3545 Don't link against -liberty.
3546 (gencode.o, getopt.o, getopt1.o): New targets.
3547 * gencode.c: Include <ctype.h> and "ansidecl.h".
3548 (AND): Undefine after including "ansidecl.h".
3549 (ULONG_MAX): Define if not defined.
3550 (OP_*): Don't define macros; now defined in opcode/mips.h.
3551 (main): Call my_strtoul rather than strtoul.
3552 (my_strtoul): New static function.
3553
3554Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3555
3556 * gencode.c (process_instructions): Generate word64 and uword64
3557 instead of `long long' and `unsigned long long' data types.
3558 * interp.c: #include sysdep.h to get signals, and define default
3559 for SIGBUS.
3560 * (Convert): Work around for Visual-C++ compiler bug with type
3561 conversion.
3562 * support.h: Make things compile under Visual-C++ by using
3563 __int64 instead of `long long'. Change many refs to long long
3564 into word64/uword64 typedefs.
3565
3566Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3567
72f4393d
L		 3568 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3569 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3570 (docdir): Removed.
3571 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3572 (AC_PROG_INSTALL): Added.
c906108c 3573 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3574 * configure: Rebuilt.
3575
c906108c
SS		 3576Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3577
3578 * configure.in: Define @SIMCONF@ depending on mips target.
3579 * configure: Rebuild.
3580 * Makefile.in (run): Add @SIMCONF@ to control simulator
3581 construction.
3582 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3583 * interp.c: Remove some debugging, provide more detailed error
3584 messages, update memory accesses to use LOADDRMASK.
72f4393d 3585
c906108c
SS		 3586Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3587
3588 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3589 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3590 stamp-h.
3591 * configure: Rebuild.
3592 * config.in: New file, generated by autoheader.
3593 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3594 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3595 HAVE_ANINT and HAVE_AINT, as appropriate.
3596 * Makefile.in (run): Use @LIBS@ rather than -lm.
3597 (interp.o): Depend upon config.h.
3598 (Makefile): Just rebuild Makefile.
3599 (clean): Remove stamp-h.
3600 (mostlyclean): Make the same as clean, not as distclean.
3601 (config.h, stamp-h): New targets.
3602
3603Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3604
3605 * interp.c (ColdReset): Fix boolean test. Make all simulator
3606 globals static.
3607
3608Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3609
3610 * interp.c (xfer_direct_word, xfer_direct_long,
3611 swap_direct_word, swap_direct_long, xfer_big_word,
3612 xfer_big_long, xfer_little_word, xfer_little_long,
3613 swap_word,swap_long): Added.
3614 * interp.c (ColdReset): Provide function indirection to
3615 host<->simulated_target transfer routines.
3616 * interp.c (sim_store_register, sim_fetch_register): Updated to
3617 make use of indirected transfer routines.
3618
3619Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3620
3621 * gencode.c (process_instructions): Ensure FP ABS instruction
3622 recognised.
3623 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3624 system call support.
3625
3626Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3627
3628 * interp.c (sim_do_command): Complain if callback structure not
3629 initialised.
3630
3631Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3632
3633 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3634 support for Sun hosts.
3635 * Makefile.in (gencode): Ensure the host compiler and libraries
3636 used for cross-hosted build.
3637
3638Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3639
3640 * interp.c, gencode.c: Some more (TODO) tidying.
3641
3642Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3643
3644 * gencode.c, interp.c: Replaced explicit long long references with
3645 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3646 * support.h (SET64LO, SET64HI): Macros added.
3647
3648Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3649
3650 * configure: Regenerate with autoconf 2.7.
3651
3652Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3653
3654 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3655 * support.h: Remove superfluous "1" from #if.
3656 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3657
3658Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3659
3660 * interp.c (StoreFPR): Control UndefinedResult() call on
3661 WARN_RESULT manifest.
3662
3663Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3664
3665 * gencode.c: Tidied instruction decoding, and added FP instruction
3666 support.
3667
3668 * interp.c: Added dineroIII, and BSD profiling support. Also
3669 run-time FP handling.
3670
3671Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3672
3673 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3674 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
This page took 0.985541 seconds and 4 git commands to generate.