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[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
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ee7254b0
CD		 12002-06-04 Chris Demetriou <cgd@broadcom.com>
2
3 * sim-main.h (FGRIDX): Remove, replace all uses with...
4 (FGR_BASE): New macro.
5 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
6 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
7 (NR_FGR, FGR): Likewise.
8 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
9 * mips.igen: Likewise.
10
d3eb724f
CD		 112002-06-04 Chris Demetriou <cgd@broadcom.com>
12
13 * cp1.c: Add an FSF Copyright notice to this file.
14
ba46ddd0
CD		 152002-06-04 Chris Demetriou <cgd@broadcom.com>
16 Ed Satterthwaite <ehs@broadcom.com>
17
18 * cp1.c (Infinity): Remove.
19 * sim-main.h (Infinity): Likewise.
20
21 * cp1.c (fp_unary, fp_binary): New functions.
22 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
23 (fp_sqrt): New functions, implemented in terms of the above.
24 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
25 (Recip, SquareRoot): Remove (replaced by functions above).
26 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
27 (fp_recip, fp_sqrt): New prototypes.
28 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
29 (Recip, SquareRoot): Replace prototypes with #defines which
30 invoke the functions above.
31
18d8a52d
CD		 322002-06-03 Chris Demetriou <cgd@broadcom.com>
33
34 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
35 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
36 file, remove PARAMS from prototypes.
37 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
38 simulator state arguments.
39 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
40 pass simulator state arguments.
41 * cp1.c (SD): Redefine as CPU_STATE(cpu).
42 (store_fpr, convert): Remove 'sd' argument.
43 (value_fpr): Likewise. Convert to use 'SD' instead.
44
0f154cbd
CD		 452002-06-03 Chris Demetriou <cgd@broadcom.com>
46
47 * cp1.c (Min, Max): Remove #if 0'd functions.
48 * sim-main.h (Min, Max): Remove.
49
e80fc152
CD		 502002-06-03 Chris Demetriou <cgd@broadcom.com>
51
52 * cp1.c: fix formatting of switch case and default labels.
53 * interp.c: Likewise.
54 * sim-main.c: Likewise.
55
bad673a9
CD		 562002-06-03 Chris Demetriou <cgd@broadcom.com>
57
58 * cp1.c: Clean up comments which describe FP formats.
59 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
60
7cbea089
CD		 612002-06-03 Chris Demetriou <cgd@broadcom.com>
62 Ed Satterthwaite <ehs@broadcom.com>
63
64 * configure.in (mipsisa64sb1*-*-*): New target for supporting
65 Broadcom SiByte SB-1 processor configurations.
66 * configure: Regenerate.
67 * sb1.igen: New file.
68 * mips.igen: Include sb1.igen.
69 (sb1): New model.
70 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
71 * mdmx.igen: Add "sb1" model to all appropriate functions and
72 instructions.
73 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
74 (ob_func, ob_acc): Reference the above.
75 (qh_acc): Adjust to keep the same size as ob_acc.
76 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
77 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
78
909daa82
CD		 792002-06-03 Chris Demetriou <cgd@broadcom.com>
80
81 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
82
f4f1b9f1
CD		 832002-06-02 Chris Demetriou <cgd@broadcom.com>
84 Ed Satterthwaite <ehs@broadcom.com>
85
86 * mips.igen (mdmx): New (pseudo-)model.
87 * mdmx.c, mdmx.igen: New files.
88 * Makefile.in (SIM_OBJS): Add mdmx.o.
89 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
90 New typedefs.
91 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
92 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
93 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
94 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
95 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
96 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
97 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
98 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
99 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
100 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
101 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
102 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
103 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
104 (qh_fmtsel): New macros.
105 (_sim_cpu): New member "acc".
106 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
107 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
108
5accf1ff
CD		 1092002-05-01 Chris Demetriou <cgd@broadcom.com>
110
111 * interp.c: Use 'deprecated' rather than 'depreciated.'
112 * sim-main.h: Likewise.
113
402586aa
CD		 1142002-05-01 Chris Demetriou <cgd@broadcom.com>
115
116 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
117 which wouldn't compile anyway.
118 * sim-main.h (unpredictable_action): New function prototype.
119 (Unpredictable): Define to call igen function unpredictable().
120 (NotWordValue): New macro to call igen function not_word_value().
121 (UndefinedResult): Remove.
122 * interp.c (undefined_result): Remove.
123 (unpredictable_action): New function.
124 * mips.igen (not_word_value, unpredictable): New functions.
125 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
126 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
127 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
128 NotWordValue() to check for unpredictable inputs, then
129 Unpredictable() to handle them.
130
c9b9995a
CD		 1312002-02-24 Chris Demetriou <cgd@broadcom.com>
132
133 * mips.igen: Fix formatting of calls to Unpredictable().
134
e1015982
AC		 1352002-04-20 Andrew Cagney <ac131313@redhat.com>
136
137 * interp.c (sim_open): Revert previous change.
138
b882a66b
AO		 1392002-04-18 Alexandre Oliva <aoliva@redhat.com>
140
141 * interp.c (sim_open): Disable chunk of code that wrote code in
142 vector table entries.
143
c429b7dd
CD		 1442002-03-19 Chris Demetriou <cgd@broadcom.com>
145
146 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
147 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
148 unused definitions.
149
37d146fa
CD		 1502002-03-19 Chris Demetriou <cgd@broadcom.com>
151
152 * cp1.c: Fix many formatting issues.
153
07892c0b
CD		 1542002-03-19 Chris G. Demetriou <cgd@broadcom.com>
155
156 * cp1.c (fpu_format_name): New function to replace...
157 (DOFMT): This. Delete, and update all callers.
158 (fpu_rounding_mode_name): New function to replace...
159 (RMMODE): This. Delete, and update all callers.
160
487f79b7
CD		 1612002-03-19 Chris G. Demetriou <cgd@broadcom.com>
162
163 * interp.c: Move FPU support routines from here to...
164 * cp1.c: Here. New file.
165 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
166 (cp1.o): New target.
167
1e799e28
CD		 1682002-03-12 Chris Demetriou <cgd@broadcom.com>
169
170 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
171 * mips.igen (mips32, mips64): New models, add to all instructions
172 and functions as appropriate.
173 (loadstore_ea, check_u64): New variant for model mips64.
174 (check_fmt_p): New variant for models mipsV and mips64, remove
175 mipsV model marking fro other variant.
176 (SLL) Rename to...
177 (SLLa) this.
178 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
179 for mips32 and mips64.
180 (DCLO, DCLZ): New instructions for mips64.
181
82f728db
CD		 1822002-03-07 Chris Demetriou <cgd@broadcom.com>
183
184 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
185 immediate or code as a hex value with the "%#lx" format.
186 (ANDI): Likewise, and fix printed instruction name.
187
b96e7ef1
CD		 1882002-03-05 Chris Demetriou <cgd@broadcom.com>
189
190 * sim-main.h (UndefinedResult, Unpredictable): New macros
191 which currently do nothing.
192
d35d4f70
CD		 1932002-03-05 Chris Demetriou <cgd@broadcom.com>
194
195 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
196 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
197 (status_CU3): New definitions.
198
199 * sim-main.h (ExceptionCause): Add new values for MIPS32
200 and MIPS64: MDMX, MCheck, CacheErr. Update comments
201 for DebugBreakPoint and NMIReset to note their status in
202 MIPS32 and MIPS64.
203 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
204 (SignalExceptionCacheErr): New exception macros.
205
3ad6f714
CD		 2062002-03-05 Chris Demetriou <cgd@broadcom.com>
207
208 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
209 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
210 is always enabled.
211 (SignalExceptionCoProcessorUnusable): Take as argument the
212 unusable coprocessor number.
213
86b77b47
CD		 2142002-03-05 Chris Demetriou <cgd@broadcom.com>
215
216 * mips.igen: Fix formatting of all SignalException calls.
217
97a88e93 2182002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 219
220 * sim-main.h (SIGNEXTEND): Remove.
221
97a88e93 2222002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 223
224 * mips.igen: Remove gencode comment from top of file, fix
225 spelling in another comment.
226
97a88e93 2272002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 228
229 * mips.igen (check_fmt, check_fmt_p): New functions to check
230 whether specific floating point formats are usable.
231 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
232 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
233 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
234 Use the new functions.
235 (do_c_cond_fmt): Remove format checks...
236 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
237
97a88e93 2382002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 239
240 * mips.igen: Fix formatting of check_fpu calls.
241
41774c9d
CD		 2422002-03-03 Chris Demetriou <cgd@broadcom.com>
243
244 * mips.igen (FLOOR.L.fmt): Store correct destination register.
245
4a0bd876
CD		 2462002-03-03 Chris Demetriou <cgd@broadcom.com>
247
248 * mips.igen: Remove whitespace at end of lines.
249
09297648
CD		 2502002-03-02 Chris Demetriou <cgd@broadcom.com>
251
252 * mips.igen (loadstore_ea): New function to do effective
253 address calculations.
254 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
255 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
256 CACHE): Use loadstore_ea to do effective address computations.
257
043b7057
CD		 2582002-03-02 Chris Demetriou <cgd@broadcom.com>
259
260 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
261 * mips.igen (LL, CxC1, MxC1): Likewise.
262
c1e8ada4
CD		 2632002-03-02 Chris Demetriou <cgd@broadcom.com>
264
265 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
266 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
267 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
268 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
269 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
270 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
271 Don't split opcode fields by hand, use the opcode field values
272 provided by igen.
273
3e1dca16
CD		 2742002-03-01 Chris Demetriou <cgd@broadcom.com>
275
276 * mips.igen (do_divu): Fix spacing.
277
278 * mips.igen (do_dsllv): Move to be right before DSLLV,
279 to match the rest of the do_<shift> functions.
280
fff8d27d
CD		 2812002-03-01 Chris Demetriou <cgd@broadcom.com>
282
283 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
284 DSRL32, do_dsrlv): Trace inputs and results.
285
0d3e762b
CD		 2862002-03-01 Chris Demetriou <cgd@broadcom.com>
287
288 * mips.igen (CACHE): Provide instruction-printing string.
289
290 * interp.c (signal_exception): Comment tokens after #endif.
291
eb5fcf93
CD		 2922002-02-28 Chris Demetriou <cgd@broadcom.com>
293
294 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
295 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
296 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
297 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
298 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
299 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
300 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
301 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
302
bb22bd7d
CD		 3032002-02-28 Chris Demetriou <cgd@broadcom.com>
304
305 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
306 instruction-printing string.
307 (LWU): Use '64' as the filter flag.
308
91a177cf
CD		 3092002-02-28 Chris Demetriou <cgd@broadcom.com>
310
311 * mips.igen (SDXC1): Fix instruction-printing string.
312
387f484a
CD		 3132002-02-28 Chris Demetriou <cgd@broadcom.com>
314
315 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
316 filter flags "32,f".
317
3d81f391
CD		 3182002-02-27 Chris Demetriou <cgd@broadcom.com>
319
320 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
321 as the filter flag.
322
af5107af
CD		 3232002-02-27 Chris Demetriou <cgd@broadcom.com>
324
325 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
326 add a comma) so that it more closely match the MIPS ISA
327 documentation opcode partitioning.
328 (PREF): Put useful names on opcode fields, and include
329 instruction-printing string.
330
ca971540
CD		 3312002-02-27 Chris Demetriou <cgd@broadcom.com>
332
333 * mips.igen (check_u64): New function which in the future will
334 check whether 64-bit instructions are usable and signal an
335 exception if not. Currently a no-op.
336 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
337 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
338 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
339 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
340
341 * mips.igen (check_fpu): New function which in the future will
342 check whether FPU instructions are usable and signal an exception
343 if not. Currently a no-op.
344 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
345 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
346 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
347 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
348 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
349 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
350 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
351 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
352
1c47a468
CD		 3532002-02-27 Chris Demetriou <cgd@broadcom.com>
354
355 * mips.igen (do_load_left, do_load_right): Move to be immediately
356 following do_load.
357 (do_store_left, do_store_right): Move to be immediately following
358 do_store.
359
603a98e7
CD		 3602002-02-27 Chris Demetriou <cgd@broadcom.com>
361
362 * mips.igen (mipsV): New model name. Also, add it to
363 all instructions and functions where it is appropriate.
364
c5d00cc7
CD		 3652002-02-18 Chris Demetriou <cgd@broadcom.com>
366
367 * mips.igen: For all functions and instructions, list model
368 names that support that instruction one per line.
369
074e9cb8
CD		 3702002-02-11 Chris Demetriou <cgd@broadcom.com>
371
372 * mips.igen: Add some additional comments about supported
373 models, and about which instructions go where.
374 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
375 order as is used in the rest of the file.
376
9805e229
CD		 3772002-02-11 Chris Demetriou <cgd@broadcom.com>
378
379 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
380 indicating that ALU32_END or ALU64_END are there to check
381 for overflow.
382 (DADD): Likewise, but also remove previous comment about
383 overflow checking.
384
f701dad2
CD		 3852002-02-10 Chris Demetriou <cgd@broadcom.com>
386
387 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
388 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
389 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
390 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
391 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
392 fields (i.e., add and move commas) so that they more closely
393 match the MIPS ISA documentation opcode partitioning.
394
3952002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 396
397 * mips.igen (ADDI): Print immediate value.
398 (BREAK): Print code.
399 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
400 (SLL): Print "nop" specially, and don't run the code
401 that does the shift for the "nop" case.
402
9e52972e
FF		 4032001-11-17 Fred Fish <fnf@redhat.com>
404
405 * sim-main.h (float_operation): Move enum declaration outside
406 of _sim_cpu struct declaration.
407
c0efbca4
JB		 4082001-04-12 Jim Blandy <jimb@redhat.com>
409
410 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
411 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
412 set of the FCSR.
413 * sim-main.h (COCIDX): Remove definition; this isn't supported by
414 PENDING_FILL, and you can get the intended effect gracefully by
415 calling PENDING_SCHED directly.
416
fb891446
BE		 4172001-02-23 Ben Elliston <bje@redhat.com>
418
419 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
420 already defined elsewhere.
421
8030f857
BE		 4222001-02-19 Ben Elliston <bje@redhat.com>
423
424 * sim-main.h (sim_monitor): Return an int.
425 * interp.c (sim_monitor): Add return values.
426 (signal_exception): Handle error conditions from sim_monitor.
427
56b48a7a
CD		 4282001-02-08 Ben Elliston <bje@redhat.com>
429
430 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
431 (store_memory): Likewise, pass cia to sim_core_write*.
432
d3ee60d9
FCE		 4332000-10-19 Frank Ch. Eigler <fche@redhat.com>
434
435 On advice from Chris G. Demetriou <cgd@sibyte.com>:
436 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
437
071da002
AC		 438Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
439
440 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
441 * Makefile.in: Don't delete *.igen when cleaning directory.
442
a28c02cd
AC		 443Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
444
445 * m16.igen (break): Call SignalException not sim_engine_halt.
446
80ee11fa
AC		 447Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
448
449 From Jason Eckhardt:
450 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
451
673388c0
AC		 452Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
453
454 * mips.igen (MxC1, DMxC1): Fix printf formatting.
455
4c0deff4
NC		 4562000-05-24 Michael Hayes <mhayes@cygnus.com>
457
458 * mips.igen (do_dmultx): Fix typo.
459
eb2d80b4
AC		 460Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
461
462 * configure: Regenerated to track ../common/aclocal.m4 changes.
463
dd37a34b
AC		 464Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
465
466 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
467
4c0deff4
NC		 4682000-04-12 Frank Ch. Eigler <fche@redhat.com>
469
470 * sim-main.h (GPR_CLEAR): Define macro.
471
e30db738
AC		 472Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
473
474 * interp.c (decode_coproc): Output long using %lx and not %s.
475
cb7450ea
FCE		 4762000-03-21 Frank Ch. Eigler <fche@redhat.com>
477
478 * interp.c (sim_open): Sort & extend dummy memory regions for
479 --board=jmr3904 for eCos.
480
a3027dd7
FCE		 4812000-03-02 Frank Ch. Eigler <fche@redhat.com>
482
483 * configure: Regenerated.
484
485Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
486
487 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
488 calls, conditional on the simulator being in verbose mode.
489
dfcd3bfb
JM		 490Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
491
492 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
493 cache don't get ReservedInstruction traps.
494
c2d11a7d
JM		 4951999-11-29 Mark Salter <msalter@cygnus.com>
496
497 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
498 to clear status bits in sdisr register. This is how the hardware works.
499
500 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
501 being used by cygmon.
502
4ce44c66
JM		 5031999-11-11 Andrew Haley <aph@cygnus.com>
504
505 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
506 instructions.
507
cff3e48b
JM		 508Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
509
510 * mips.igen (MULT): Correct previous mis-applied patch.
511
d4f3574e
SS		 512Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
513
514 * mips.igen (delayslot32): Handle sequence like
515 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
516 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
517 (MULT): Actually pass the third register...
518
5191999-09-03 Mark Salter <msalter@cygnus.com>
520
521 * interp.c (sim_open): Added more memory aliases for additional
522 hardware being touched by cygmon on jmr3904 board.
523
524Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
525
526 * configure: Regenerated to track ../common/aclocal.m4 changes.
527
a0b3c4fd
JM		 528Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
529
530 * interp.c (sim_store_register): Handle case where client - GDB -
531 specifies that a 4 byte register is 8 bytes in size.
532 (sim_fetch_register): Ditto.
533
adf40b2e
JM		 5341999-07-14 Frank Ch. Eigler <fche@cygnus.com>
535
536 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
537 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
538 (idt_monitor_base): Base address for IDT monitor traps.
539 (pmon_monitor_base): Ditto for PMON.
540 (lsipmon_monitor_base): Ditto for LSI PMON.
541 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
542 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
543 (sim_firmware_command): New function.
544 (mips_option_handler): Call it for OPTION_FIRMWARE.
545 (sim_open): Allocate memory for idt_monitor region. If "--board"
546 option was given, add no monitor by default. Add BREAK hooks only if
547 monitors are also there.
548
43e526b9
JM		 549Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
550
551 * interp.c (sim_monitor): Flush output before reading input.
552
553Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
554
555 * tconfig.in (SIM_HANDLES_LMA): Always define.
556
557Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
558
559 From Mark Salter <msalter@cygnus.com>:
560 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
561 (sim_open): Add setup for BSP board.
562
9846de1b
JM		 563Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
564
565 * mips.igen (MULT, MULTU): Add syntax for two operand version.
566 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
567 them as unimplemented.
568
cd0fc7c3
SS		 5691999-05-08 Felix Lee <flee@cygnus.com>
570
571 * configure: Regenerated to track ../common/aclocal.m4 changes.
572
7a292a7a
SS		 5731999-04-21 Frank Ch. Eigler <fche@cygnus.com>
574
575 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
576
577Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
578
579 * configure.in: Any mips64vr5*-*-* target should have
580 -DTARGET_ENABLE_FR=1.
581 (default_endian): Any mips64vr*el-*-* target should default to
582 LITTLE_ENDIAN.
583 * configure: Re-generate.
584
5851999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
586
587 * mips.igen (ldl): Extend from _16_, not 32.
588
589Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
590
591 * interp.c (sim_store_register): Force registers written to by GDB
592 into an un-interpreted state.
593
c906108c
SS		 5941999-02-05 Frank Ch. Eigler <fche@cygnus.com>
595
596 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
597 CPU, start periodic background I/O polls.
598 (tx3904sio_poll): New function: periodic I/O poller.
599
6001998-12-30 Frank Ch. Eigler <fche@cygnus.com>
601
602 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
603
604Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
605
606 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
607 case statement.
608
6091998-12-29 Frank Ch. Eigler <fche@cygnus.com>
610
611 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
612 (load_word): Call SIM_CORE_SIGNAL hook on error.
613 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
614 starting. For exception dispatching, pass PC instead of NULL_CIA.
615 (decode_coproc): Use COP0_BADVADDR to store faulting address.
616 * sim-main.h (COP0_BADVADDR): Define.
617 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
618 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
619 (_sim_cpu): Add exc_* fields to store register value snapshots.
620 * mips.igen (*): Replace memory-related SignalException* calls
621 with references to SIM_CORE_SIGNAL hook.
622
623 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
624 fix.
625 * sim-main.c (*): Minor warning cleanups.
626
6271998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
628
629 * m16.igen (DADDIU5): Correct type-o.
630
631Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
632
633 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
634 variables.
635
636Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
637
638 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
639 to include path.
640 (interp.o): Add dependency on itable.h
641 (oengine.c, gencode): Delete remaining references.
642 (BUILT_SRC_FROM_GEN): Clean up.
643
6441998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
645
646 * vr4run.c: New.
647 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
648 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
649 tmp-run-hack) : New.
650 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
651 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
652 Drop the "64" qualifier to get the HACK generator working.
653 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
654 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
655 qualifier to get the hack generator working.
656 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
657 (DSLL): Use do_dsll.
658 (DSLLV): Use do_dsllv.
659 (DSRA): Use do_dsra.
660 (DSRL): Use do_dsrl.
661 (DSRLV): Use do_dsrlv.
662 (BC1): Move *vr4100 to get the HACK generator working.
663 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
664 get the HACK generator working.
665 (MACC) Rename to get the HACK generator working.
666 (DMACC,MACCS,DMACCS): Add the 64.
667
6681998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
669
670 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
671 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
672
6731998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
674
675 * mips/interp.c (DEBUG): Cleanups.
676
6771998-12-10 Frank Ch. Eigler <fche@cygnus.com>
678
679 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
680 (tx3904sio_tickle): fflush after a stdout character output.
681
6821998-12-03 Frank Ch. Eigler <fche@cygnus.com>
683
684 * interp.c (sim_close): Uninstall modules.
685
686Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
687
688 * sim-main.h, interp.c (sim_monitor): Change to global
689 function.
690
691Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
692
693 * configure.in (vr4100): Only include vr4100 instructions in
694 simulator.
695 * configure: Re-generate.
696 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
697
698Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
699
700 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
701 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
702 true alternative.
703
704 * configure.in (sim_default_gen, sim_use_gen): Replace with
705 sim_gen.
706 (--enable-sim-igen): Delete config option. Always using IGEN.
707 * configure: Re-generate.
708
709 * Makefile.in (gencode): Kill, kill, kill.
710 * gencode.c: Ditto.
711
712Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
713
714 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
715 bit mips16 igen simulator.
716 * configure: Re-generate.
717
718 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
719 as part of vr4100 ISA.
720 * vr.igen: Mark all instructions as 64 bit only.
721
722Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
723
724 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
725 Pacify GCC.
726
727Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
728
729 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
730 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
731 * configure: Re-generate.
732
733 * m16.igen (BREAK): Define breakpoint instruction.
734 (JALX32): Mark instruction as mips16 and not r3900.
735 * mips.igen (C.cond.fmt): Fix typo in instruction format.
736
737 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
738
739Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
740
741 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
742 insn as a debug breakpoint.
743
744 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
745 pending.slot_size.
746 (PENDING_SCHED): Clean up trace statement.
747 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
748 (PENDING_FILL): Delay write by only one cycle.
749 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
750
751 * sim-main.c (pending_tick): Clean up trace statements. Add trace
752 of pending writes.
753 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
754 32 & 64.
755 (pending_tick): Move incrementing of index to FOR statement.
756 (pending_tick): Only update PENDING_OUT after a write has occured.
757
758 * configure.in: Add explicit mips-lsi-* target. Use gencode to
759 build simulator.
760 * configure: Re-generate.
761
762 * interp.c (sim_engine_run OLD): Delete explicit call to
763 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
764
765Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
766
767 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
768 interrupt level number to match changed SignalExceptionInterrupt
769 macro.
770
771Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
772
773 * interp.c: #include "itable.h" if WITH_IGEN.
774 (get_insn_name): New function.
775 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
776 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
777
778Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
779
780 * configure: Rebuilt to inhale new common/aclocal.m4.
781
782Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
783
784 * dv-tx3904sio.c: Include sim-assert.h.
785
786Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
787
788 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
789 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
790 Reorganize target-specific sim-hardware checks.
791 * configure: rebuilt.
792 * interp.c (sim_open): For tx39 target boards, set
793 OPERATING_ENVIRONMENT, add tx3904sio devices.
794 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
795 ROM executables. Install dv-sockser into sim-modules list.
796
797 * dv-tx3904irc.c: Compiler warning clean-up.
798 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
799 frequent hw-trace messages.
800
801Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
802
803 * vr.igen (MulAcc): Identify as a vr4100 specific function.
804
805Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
806
807 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
808
809 * vr.igen: New file.
810 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
811 * mips.igen: Define vr4100 model. Include vr.igen.
812Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
813
814 * mips.igen (check_mf_hilo): Correct check.
815
816Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
817
818 * sim-main.h (interrupt_event): Add prototype.
819
820 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
821 register_ptr, register_value.
822 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
823
824 * sim-main.h (tracefh): Make extern.
825
826Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
827
828 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
829 Reduce unnecessarily high timer event frequency.
830 * dv-tx3904cpu.c: Ditto for interrupt event.
831
832Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
833
834 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
835 to allay warnings.
836 (interrupt_event): Made non-static.
837
838 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
839 interchange of configuration values for external vs. internal
840 clock dividers.
841
842Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
843
844 * mips.igen (BREAK): Moved code to here for
845 simulator-reserved break instructions.
846 * gencode.c (build_instruction): Ditto.
847 * interp.c (signal_exception): Code moved from here. Non-
848 reserved instructions now use exception vector, rather
849 than halting sim.
850 * sim-main.h: Moved magic constants to here.
851
852Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
853
854 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
855 register upon non-zero interrupt event level, clear upon zero
856 event value.
857 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
858 by passing zero event value.
859 (*_io_{read,write}_buffer): Endianness fixes.
860 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
861 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
862
863 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
864 serial I/O and timer module at base address 0xFFFF0000.
865
866Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
867
868 * mips.igen (SWC1) : Correct the handling of ReverseEndian
869 and BigEndianCPU.
870
871Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
872
873 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
874 parts.
875 * configure: Update.
876
877Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
878
879 * dv-tx3904tmr.c: New file - implements tx3904 timer.
880 * dv-tx3904{irc,cpu}.c: Mild reformatting.
881 * configure.in: Include tx3904tmr in hw_device list.
882 * configure: Rebuilt.
883 * interp.c (sim_open): Instantiate three timer instances.
884 Fix address typo of tx3904irc instance.
885
886Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
887
888 * interp.c (signal_exception): SystemCall exception now uses
889 the exception vector.
890
891Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
892
893 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
894 to allay warnings.
895
896Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
897
898 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
899
900Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
901
902 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
903
904 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
905 sim-main.h. Declare a struct hw_descriptor instead of struct
906 hw_device_descriptor.
907
908Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
909
910 * mips.igen (do_store_left, do_load_left): Compute nr of left and
911 right bits and then re-align left hand bytes to correct byte
912 lanes. Fix incorrect computation in do_store_left when loading
913 bytes from second word.
914
915Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
916
917 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
918 * interp.c (sim_open): Only create a device tree when HW is
919 enabled.
920
921 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
922 * interp.c (signal_exception): Ditto.
923
924Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
925
926 * gencode.c: Mark BEGEZALL as LIKELY.
927
928Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
929
930 * sim-main.h (ALU32_END): Sign extend 32 bit results.
931 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
932
933Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
934
935 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
936 modules. Recognize TX39 target with "mips*tx39" pattern.
937 * configure: Rebuilt.
938 * sim-main.h (*): Added many macros defining bits in
939 TX39 control registers.
940 (SignalInterrupt): Send actual PC instead of NULL.
941 (SignalNMIReset): New exception type.
942 * interp.c (board): New variable for future use to identify
943 a particular board being simulated.
944 (mips_option_handler,mips_options): Added "--board" option.
945 (interrupt_event): Send actual PC.
946 (sim_open): Make memory layout conditional on board setting.
947 (signal_exception): Initial implementation of hardware interrupt
948 handling. Accept another break instruction variant for simulator
949 exit.
950 (decode_coproc): Implement RFE instruction for TX39.
951 (mips.igen): Decode RFE instruction as such.
952 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
953 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
954 bbegin to implement memory map.
955 * dv-tx3904cpu.c: New file.
956 * dv-tx3904irc.c: New file.
957
958Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
959
960 * mips.igen (check_mt_hilo): Create a separate r3900 version.
961
962Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
963
964 * tx.igen (madd,maddu): Replace calls to check_op_hilo
965 with calls to check_div_hilo.
966
967Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
968
969 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
970 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
971 Add special r3900 version of do_mult_hilo.
972 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
973 with calls to check_mult_hilo.
974 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
975 with calls to check_div_hilo.
976
977Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
978
979 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
980 Document a replacement.
981
982Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
983
984 * interp.c (sim_monitor): Make mon_printf work.
985
986Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
987
988 * sim-main.h (INSN_NAME): New arg `cpu'.
989
990Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
991
992 * configure: Regenerated to track ../common/aclocal.m4 changes.
993
994Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
995
996 * configure: Regenerated to track ../common/aclocal.m4 changes.
997 * config.in: Ditto.
998
999Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1000
1001 * acconfig.h: New file.
1002 * configure.in: Reverted change of Apr 24; use sinclude again.
1003
1004Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1005
1006 * configure: Regenerated to track ../common/aclocal.m4 changes.
1007 * config.in: Ditto.
1008
1009Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1010
1011 * configure.in: Don't call sinclude.
1012
1013Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1014
1015 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1016
1017Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1018
1019 * mips.igen (ERET): Implement.
1020
1021 * interp.c (decode_coproc): Return sign-extended EPC.
1022
1023 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1024
1025 * interp.c (signal_exception): Do not ignore Trap.
1026 (signal_exception): On TRAP, restart at exception address.
1027 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1028 (signal_exception): Update.
1029 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1030 so that TRAP instructions are caught.
1031
1032Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1033
1034 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1035 contains HI/LO access history.
1036 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1037 (HIACCESS, LOACCESS): Delete, replace with
1038 (HIHISTORY, LOHISTORY): New macros.
1039 (CHECKHILO): Delete all, moved to mips.igen
1040
1041 * gencode.c (build_instruction): Do not generate checks for
1042 correct HI/LO register usage.
1043
1044 * interp.c (old_engine_run): Delete checks for correct HI/LO
1045 register usage.
1046
1047 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1048 check_mf_cycles): New functions.
1049 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1050 do_divu, domultx, do_mult, do_multu): Use.
1051
1052 * tx.igen ("madd", "maddu"): Use.
1053
1054Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1055
1056 * mips.igen (DSRAV): Use function do_dsrav.
1057 (SRAV): Use new function do_srav.
1058
1059 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1060 (B): Sign extend 11 bit immediate.
1061 (EXT-B*): Shift 16 bit immediate left by 1.
1062 (ADDIU*): Don't sign extend immediate value.
1063
1064Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1065
1066 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1067
1068 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1069 functions.
1070
1071 * mips.igen (delayslot32, nullify_next_insn): New functions.
1072 (m16.igen): Always include.
1073 (do_*): Add more tracing.
1074
1075 * m16.igen (delayslot16): Add NIA argument, could be called by a
1076 32 bit MIPS16 instruction.
1077
1078 * interp.c (ifetch16): Move function from here.
1079 * sim-main.c (ifetch16): To here.
1080
1081 * sim-main.c (ifetch16, ifetch32): Update to match current
1082 implementations of LH, LW.
1083 (signal_exception): Don't print out incorrect hex value of illegal
1084 instruction.
1085
1086Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1087
1088 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1089 instruction.
1090
1091 * m16.igen: Implement MIPS16 instructions.
1092
1093 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1094 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1095 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1096 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1097 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1098 bodies of corresponding code from 32 bit insn to these. Also used
1099 by MIPS16 versions of functions.
1100
1101 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1102 (IMEM16): Drop NR argument from macro.
1103
1104Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1105
1106 * Makefile.in (SIM_OBJS): Add sim-main.o.
1107
1108 * sim-main.h (address_translation, load_memory, store_memory,
1109 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1110 as INLINE_SIM_MAIN.
1111 (pr_addr, pr_uword64): Declare.
1112 (sim-main.c): Include when H_REVEALS_MODULE_P.
1113
1114 * interp.c (address_translation, load_memory, store_memory,
1115 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1116 from here.
1117 * sim-main.c: To here. Fix compilation problems.
1118
1119 * configure.in: Enable inlining.
1120 * configure: Re-config.
1121
1122Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1123
1124 * configure: Regenerated to track ../common/aclocal.m4 changes.
1125
1126Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1127
1128 * mips.igen: Include tx.igen.
1129 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1130 * tx.igen: New file, contains MADD and MADDU.
1131
1132 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1133 the hardwired constant `7'.
1134 (store_memory): Ditto.
1135 (LOADDRMASK): Move definition to sim-main.h.
1136
1137 mips.igen (MTC0): Enable for r3900.
1138 (ADDU): Add trace.
1139
1140 mips.igen (do_load_byte): Delete.
1141 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1142 do_store_right): New functions.
1143 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1144
1145 configure.in: Let the tx39 use igen again.
1146 configure: Update.
1147
1148Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1149
1150 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1151 not an address sized quantity. Return zero for cache sizes.
1152
1153Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1154
1155 * mips.igen (r3900): r3900 does not support 64 bit integer
1156 operations.
1157
1158Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1159
1160 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1161 than igen one.
1162 * configure : Rebuild.
1163
1164Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1165
1166 * configure: Regenerated to track ../common/aclocal.m4 changes.
1167
1168Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1169
1170 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1171
1172Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1173
1174 * configure: Regenerated to track ../common/aclocal.m4 changes.
1175 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1176
1177Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1178
1179 * configure: Regenerated to track ../common/aclocal.m4 changes.
1180
1181Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1182
1183 * interp.c (Max, Min): Comment out functions. Not yet used.
1184
1185Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1186
1187 * configure: Regenerated to track ../common/aclocal.m4 changes.
1188
1189Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1190
1191 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1192 configurable settings for stand-alone simulator.
1193
1194 * configure.in: Added X11 search, just in case.
1195
1196 * configure: Regenerated.
1197
1198Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1199
1200 * interp.c (sim_write, sim_read, load_memory, store_memory):
1201 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1202
1203Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1204
1205 * sim-main.h (GETFCC): Return an unsigned value.
1206
1207Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1208
1209 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1210 (DADD): Result destination is RD not RT.
1211
1212Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1213
1214 * sim-main.h (HIACCESS, LOACCESS): Always define.
1215
1216 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1217
1218 * interp.c (sim_info): Delete.
1219
1220Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1221
1222 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1223 (mips_option_handler): New argument `cpu'.
1224 (sim_open): Update call to sim_add_option_table.
1225
1226Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1227
1228 * mips.igen (CxC1): Add tracing.
1229
1230Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1231
1232 * sim-main.h (Max, Min): Declare.
1233
1234 * interp.c (Max, Min): New functions.
1235
1236 * mips.igen (BC1): Add tracing.
1237
1238Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1239
1240 * interp.c Added memory map for stack in vr4100
1241
1242Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1243
1244 * interp.c (load_memory): Add missing "break"'s.
1245
1246Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1247
1248 * interp.c (sim_store_register, sim_fetch_register): Pass in
1249 length parameter. Return -1.
1250
1251Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1252
1253 * interp.c: Added hardware init hook, fixed warnings.
1254
1255Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1256
1257 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1258
1259Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1260
1261 * interp.c (ifetch16): New function.
1262
1263 * sim-main.h (IMEM32): Rename IMEM.
1264 (IMEM16_IMMED): Define.
1265 (IMEM16): Define.
1266 (DELAY_SLOT): Update.
1267
1268 * m16run.c (sim_engine_run): New file.
1269
1270 * m16.igen: All instructions except LB.
1271 (LB): Call do_load_byte.
1272 * mips.igen (do_load_byte): New function.
1273 (LB): Call do_load_byte.
1274
1275 * mips.igen: Move spec for insn bit size and high bit from here.
1276 * Makefile.in (tmp-igen, tmp-m16): To here.
1277
1278 * m16.dc: New file, decode mips16 instructions.
1279
1280 * Makefile.in (SIM_NO_ALL): Define.
1281 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1282
1283Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1284
1285 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1286 point unit to 32 bit registers.
1287 * configure: Re-generate.
1288
1289Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1290
1291 * configure.in (sim_use_gen): Make IGEN the default simulator
1292 generator for generic 32 and 64 bit mips targets.
1293 * configure: Re-generate.
1294
1295Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1296
1297 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1298 bitsize.
1299
1300 * interp.c (sim_fetch_register, sim_store_register): Read/write
1301 FGR from correct location.
1302 (sim_open): Set size of FGR's according to
1303 WITH_TARGET_FLOATING_POINT_BITSIZE.
1304
1305 * sim-main.h (FGR): Store floating point registers in a separate
1306 array.
1307
1308Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1309
1310 * configure: Regenerated to track ../common/aclocal.m4 changes.
1311
1312Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1313
1314 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1315
1316 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1317
1318 * interp.c (pending_tick): New function. Deliver pending writes.
1319
1320 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1321 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1322 it can handle mixed sized quantites and single bits.
1323
1324Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1325
1326 * interp.c (oengine.h): Do not include when building with IGEN.
1327 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1328 (sim_info): Ditto for PROCESSOR_64BIT.
1329 (sim_monitor): Replace ut_reg with unsigned_word.
1330 (*): Ditto for t_reg.
1331 (LOADDRMASK): Define.
1332 (sim_open): Remove defunct check that host FP is IEEE compliant,
1333 using software to emulate floating point.
1334 (value_fpr, ...): Always compile, was conditional on HASFPU.
1335
1336Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1337
1338 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1339 size.
1340
1341 * interp.c (SD, CPU): Define.
1342 (mips_option_handler): Set flags in each CPU.
1343 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1344 (sim_close): Do not clear STATE, deleted anyway.
1345 (sim_write, sim_read): Assume CPU zero's vm should be used for
1346 data transfers.
1347 (sim_create_inferior): Set the PC for all processors.
1348 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1349 argument.
1350 (mips16_entry): Pass correct nr of args to store_word, load_word.
1351 (ColdReset): Cold reset all cpu's.
1352 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1353 (sim_monitor, load_memory, store_memory, signal_exception): Use
1354 `CPU' instead of STATE_CPU.
1355
1356
1357 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1358 SD or CPU_.
1359
1360 * sim-main.h (signal_exception): Add sim_cpu arg.
1361 (SignalException*): Pass both SD and CPU to signal_exception.
1362 * interp.c (signal_exception): Update.
1363
1364 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1365 Ditto
1366 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1367 address_translation): Ditto
1368 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1369
1370Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1371
1372 * configure: Regenerated to track ../common/aclocal.m4 changes.
1373
1374Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1375
1376 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1377
1378 * mips.igen (model): Map processor names onto BFD name.
1379
1380 * sim-main.h (CPU_CIA): Delete.
1381 (SET_CIA, GET_CIA): Define
1382
1383Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1384
1385 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1386 regiser.
1387
1388 * configure.in (default_endian): Configure a big-endian simulator
1389 by default.
1390 * configure: Re-generate.
1391
1392Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1393
1394 * configure: Regenerated to track ../common/aclocal.m4 changes.
1395
1396Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1397
1398 * interp.c (sim_monitor): Handle Densan monitor outbyte
1399 and inbyte functions.
1400
14011997-12-29 Felix Lee <flee@cygnus.com>
1402
1403 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1404
1405Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1406
1407 * Makefile.in (tmp-igen): Arrange for $zero to always be
1408 reset to zero after every instruction.
1409
1410Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1411
1412 * configure: Regenerated to track ../common/aclocal.m4 changes.
1413 * config.in: Ditto.
1414
1415Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1416
1417 * mips.igen (MSUB): Fix to work like MADD.
1418 * gencode.c (MSUB): Similarly.
1419
1420Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1421
1422 * configure: Regenerated to track ../common/aclocal.m4 changes.
1423
1424Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1425
1426 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1427
1428Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1429
1430 * sim-main.h (sim-fpu.h): Include.
1431
1432 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1433 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1434 using host independant sim_fpu module.
1435
1436Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1437
1438 * interp.c (signal_exception): Report internal errors with SIGABRT
1439 not SIGQUIT.
1440
1441 * sim-main.h (C0_CONFIG): New register.
1442 (signal.h): No longer include.
1443
1444 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1445
1446Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1447
1448 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1449
1450Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1451
1452 * mips.igen: Tag vr5000 instructions.
1453 (ANDI): Was missing mipsIV model, fix assembler syntax.
1454 (do_c_cond_fmt): New function.
1455 (C.cond.fmt): Handle mips I-III which do not support CC field
1456 separatly.
1457 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1458 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1459 in IV3.2 spec.
1460 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1461 vr5000 which saves LO in a GPR separatly.
1462
1463 * configure.in (enable-sim-igen): For vr5000, select vr5000
1464 specific instructions.
1465 * configure: Re-generate.
1466
1467Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1468
1469 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1470
1471 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1472 fmt_uninterpreted_64 bit cases to switch. Convert to
1473 fmt_formatted,
1474
1475 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1476
1477 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1478 as specified in IV3.2 spec.
1479 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1480
1481Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1482
1483 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1484 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1485 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1486 PENDING_FILL versions of instructions. Simplify.
1487 (X): New function.
1488 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1489 instructions.
1490 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1491 a signed value.
1492 (MTHI, MFHI): Disable code checking HI-LO.
1493
1494 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1495 global.
1496 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1497
1498Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1499
1500 * gencode.c (build_mips16_operands): Replace IPC with cia.
1501
1502 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1503 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1504 IPC to `cia'.
1505 (UndefinedResult): Replace function with macro/function
1506 combination.
1507 (sim_engine_run): Don't save PC in IPC.
1508
1509 * sim-main.h (IPC): Delete.
1510
1511
1512 * interp.c (signal_exception, store_word, load_word,
1513 address_translation, load_memory, store_memory, cache_op,
1514 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1515 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1516 current instruction address - cia - argument.
1517 (sim_read, sim_write): Call address_translation directly.
1518 (sim_engine_run): Rename variable vaddr to cia.
1519 (signal_exception): Pass cia to sim_monitor
1520
1521 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1522 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1523 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1524
1525 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1526 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1527 SIM_ASSERT.
1528
1529 * interp.c (signal_exception): Pass restart address to
1530 sim_engine_restart.
1531
1532 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1533 idecode.o): Add dependency.
1534
1535 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1536 Delete definitions
1537 (DELAY_SLOT): Update NIA not PC with branch address.
1538 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1539
1540 * mips.igen: Use CIA not PC in branch calculations.
1541 (illegal): Call SignalException.
1542 (BEQ, ADDIU): Fix assembler.
1543
1544Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1545
1546 * m16.igen (JALX): Was missing.
1547
1548 * configure.in (enable-sim-igen): New configuration option.
1549 * configure: Re-generate.
1550
1551 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1552
1553 * interp.c (load_memory, store_memory): Delete parameter RAW.
1554 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1555 bypassing {load,store}_memory.
1556
1557 * sim-main.h (ByteSwapMem): Delete definition.
1558
1559 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1560
1561 * interp.c (sim_do_command, sim_commands): Delete mips specific
1562 commands. Handled by module sim-options.
1563
1564 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1565 (WITH_MODULO_MEMORY): Define.
1566
1567 * interp.c (sim_info): Delete code printing memory size.
1568
1569 * interp.c (mips_size): Nee sim_size, delete function.
1570 (power2): Delete.
1571 (monitor, monitor_base, monitor_size): Delete global variables.
1572 (sim_open, sim_close): Delete code creating monitor and other
1573 memory regions. Use sim-memopts module, via sim_do_commandf, to
1574 manage memory regions.
1575 (load_memory, store_memory): Use sim-core for memory model.
1576
1577 * interp.c (address_translation): Delete all memory map code
1578 except line forcing 32 bit addresses.
1579
1580Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1581
1582 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1583 trace options.
1584
1585 * interp.c (logfh, logfile): Delete globals.
1586 (sim_open, sim_close): Delete code opening & closing log file.
1587 (mips_option_handler): Delete -l and -n options.
1588 (OPTION mips_options): Ditto.
1589
1590 * interp.c (OPTION mips_options): Rename option trace to dinero.
1591 (mips_option_handler): Update.
1592
1593Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1594
1595 * interp.c (fetch_str): New function.
1596 (sim_monitor): Rewrite using sim_read & sim_write.
1597 (sim_open): Check magic number.
1598 (sim_open): Write monitor vectors into memory using sim_write.
1599 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1600 (sim_read, sim_write): Simplify - transfer data one byte at a
1601 time.
1602 (load_memory, store_memory): Clarify meaning of parameter RAW.
1603
1604 * sim-main.h (isHOST): Defete definition.
1605 (isTARGET): Mark as depreciated.
1606 (address_translation): Delete parameter HOST.
1607
1608 * interp.c (address_translation): Delete parameter HOST.
1609
1610Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1611
1612 * mips.igen:
1613
1614 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1615 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1616
1617Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1618
1619 * mips.igen: Add model filter field to records.
1620
1621Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1622
1623 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1624
1625 interp.c (sim_engine_run): Do not compile function sim_engine_run
1626 when WITH_IGEN == 1.
1627
1628 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1629 target architecture.
1630
1631 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1632 igen. Replace with configuration variables sim_igen_flags /
1633 sim_m16_flags.
1634
1635 * m16.igen: New file. Copy mips16 insns here.
1636 * mips.igen: From here.
1637
1638Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1639
1640 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1641 to top.
1642 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1643
1644Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1645
1646 * gencode.c (build_instruction): Follow sim_write's lead in using
1647 BigEndianMem instead of !ByteSwapMem.
1648
1649Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1650
1651 * configure.in (sim_gen): Dependent on target, select type of
1652 generator. Always select old style generator.
1653
1654 configure: Re-generate.
1655
1656 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1657 targets.
1658 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1659 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1660 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1661 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1662 SIM_@sim_gen@_*, set by autoconf.
1663
1664Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1665
1666 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1667
1668 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1669 CURRENT_FLOATING_POINT instead.
1670
1671 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1672 (address_translation): Raise exception InstructionFetch when
1673 translation fails and isINSTRUCTION.
1674
1675 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1676 sim_engine_run): Change type of of vaddr and paddr to
1677 address_word.
1678 (address_translation, prefetch, load_memory, store_memory,
1679 cache_op): Change type of vAddr and pAddr to address_word.
1680
1681 * gencode.c (build_instruction): Change type of vaddr and paddr to
1682 address_word.
1683
1684Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1685
1686 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1687 macro to obtain result of ALU op.
1688
1689Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1690
1691 * interp.c (sim_info): Call profile_print.
1692
1693Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1694
1695 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1696
1697 * sim-main.h (WITH_PROFILE): Do not define, defined in
1698 common/sim-config.h. Use sim-profile module.
1699 (simPROFILE): Delete defintion.
1700
1701 * interp.c (PROFILE): Delete definition.
1702 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1703 (sim_close): Delete code writing profile histogram.
1704 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1705 Delete.
1706 (sim_engine_run): Delete code profiling the PC.
1707
1708Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1709
1710 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1711
1712 * interp.c (sim_monitor): Make register pointers of type
1713 unsigned_word*.
1714
1715 * sim-main.h: Make registers of type unsigned_word not
1716 signed_word.
1717
1718Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1719
1720 * interp.c (sync_operation): Rename from SyncOperation, make
1721 global, add SD argument.
1722 (prefetch): Rename from Prefetch, make global, add SD argument.
1723 (decode_coproc): Make global.
1724
1725 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1726
1727 * gencode.c (build_instruction): Generate DecodeCoproc not
1728 decode_coproc calls.
1729
1730 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1731 (SizeFGR): Move to sim-main.h
1732 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1733 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1734 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1735 sim-main.h.
1736 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1737 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1738 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1739 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1740 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1741 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1742
1743 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1744 exception.
1745 (sim-alu.h): Include.
1746 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1747 (sim_cia): Typedef to instruction_address.
1748
1749Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1750
1751 * Makefile.in (interp.o): Rename generated file engine.c to
1752 oengine.c.
1753
1754 * interp.c: Update.
1755
1756Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1757
1758 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1759
1760Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1761
1762 * gencode.c (build_instruction): For "FPSQRT", output correct
1763 number of arguments to Recip.
1764
1765Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1766
1767 * Makefile.in (interp.o): Depends on sim-main.h
1768
1769 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1770
1771 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1772 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1773 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1774 STATE, DSSTATE): Define
1775 (GPR, FGRIDX, ..): Define.
1776
1777 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1778 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1779 (GPR, FGRIDX, ...): Delete macros.
1780
1781 * interp.c: Update names to match defines from sim-main.h
1782
1783Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1784
1785 * interp.c (sim_monitor): Add SD argument.
1786 (sim_warning): Delete. Replace calls with calls to
1787 sim_io_eprintf.
1788 (sim_error): Delete. Replace calls with sim_io_error.
1789 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1790 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1791 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1792 argument.
1793 (mips_size): Rename from sim_size. Add SD argument.
1794
1795 * interp.c (simulator): Delete global variable.
1796 (callback): Delete global variable.
1797 (mips_option_handler, sim_open, sim_write, sim_read,
1798 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1799 sim_size,sim_monitor): Use sim_io_* not callback->*.
1800 (sim_open): ZALLOC simulator struct.
1801 (PROFILE): Do not define.
1802
1803Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1804
1805 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1806 support.h with corresponding code.
1807
1808 * sim-main.h (word64, uword64), support.h: Move definition to
1809 sim-main.h.
1810 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1811
1812 * support.h: Delete
1813 * Makefile.in: Update dependencies
1814 * interp.c: Do not include.
1815
1816Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1817
1818 * interp.c (address_translation, load_memory, store_memory,
1819 cache_op): Rename to from AddressTranslation et.al., make global,
1820 add SD argument
1821
1822 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1823 CacheOp): Define.
1824
1825 * interp.c (SignalException): Rename to signal_exception, make
1826 global.
1827
1828 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1829
1830 * sim-main.h (SignalException, SignalExceptionInterrupt,
1831 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1832 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1833 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1834 Define.
1835
1836 * interp.c, support.h: Use.
1837
1838Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1839
1840 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1841 to value_fpr / store_fpr. Add SD argument.
1842 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1843 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1844
1845 * sim-main.h (ValueFPR, StoreFPR): Define.
1846
1847Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1848
1849 * interp.c (sim_engine_run): Check consistency between configure
1850 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1851 and HASFPU.
1852
1853 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1854 (mips_fpu): Configure WITH_FLOATING_POINT.
1855 (mips_endian): Configure WITH_TARGET_ENDIAN.
1856 * configure: Update.
1857
1858Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1859
1860 * configure: Regenerated to track ../common/aclocal.m4 changes.
1861
1862Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1863
1864 * configure: Regenerated.
1865
1866Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1867
1868 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1869
1870Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1871
1872 * gencode.c (print_igen_insn_models): Assume certain architectures
1873 include all mips* instructions.
1874 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1875 instruction.
1876
1877 * Makefile.in (tmp.igen): Add target. Generate igen input from
1878 gencode file.
1879
1880 * gencode.c (FEATURE_IGEN): Define.
1881 (main): Add --igen option. Generate output in igen format.
1882 (process_instructions): Format output according to igen option.
1883 (print_igen_insn_format): New function.
1884 (print_igen_insn_models): New function.
1885 (process_instructions): Only issue warnings and ignore
1886 instructions when no FEATURE_IGEN.
1887
1888Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1889
1890 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1891 MIPS targets.
1892
1893Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1894
1895 * configure: Regenerated to track ../common/aclocal.m4 changes.
1896
1897Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1898
1899 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1900 SIM_RESERVED_BITS): Delete, moved to common.
1901 (SIM_EXTRA_CFLAGS): Update.
1902
1903Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1904
1905 * configure.in: Configure non-strict memory alignment.
1906 * configure: Regenerated to track ../common/aclocal.m4 changes.
1907
1908Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1909
1910 * configure: Regenerated to track ../common/aclocal.m4 changes.
1911
1912Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1913
1914 * gencode.c (SDBBP,DERET): Added (3900) insns.
1915 (RFE): Turn on for 3900.
1916 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1917 (dsstate): Made global.
1918 (SUBTARGET_R3900): Added.
1919 (CANCELDELAYSLOT): New.
1920 (SignalException): Ignore SystemCall rather than ignore and
1921 terminate. Add DebugBreakPoint handling.
1922 (decode_coproc): New insns RFE, DERET; and new registers Debug
1923 and DEPC protected by SUBTARGET_R3900.
1924 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1925 bits explicitly.
1926 * Makefile.in,configure.in: Add mips subtarget option.
1927 * configure: Update.
1928
1929Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1930
1931 * gencode.c: Add r3900 (tx39).
1932
1933
1934Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1935
1936 * gencode.c (build_instruction): Don't need to subtract 4 for
1937 JALR, just 2.
1938
1939Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1940
1941 * interp.c: Correct some HASFPU problems.
1942
1943Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1944
1945 * configure: Regenerated to track ../common/aclocal.m4 changes.
1946
1947Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1948
1949 * interp.c (mips_options): Fix samples option short form, should
1950 be `x'.
1951
1952Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1953
1954 * interp.c (sim_info): Enable info code. Was just returning.
1955
1956Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1957
1958 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1959 MFC0.
1960
1961Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1962
1963 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1964 constants.
1965 (build_instruction): Ditto for LL.
1966
1967Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1968
1969 * configure: Regenerated to track ../common/aclocal.m4 changes.
1970
1971Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1972
1973 * configure: Regenerated to track ../common/aclocal.m4 changes.
1974 * config.in: Ditto.
1975
1976Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1977
1978 * interp.c (sim_open): Add call to sim_analyze_program, update
1979 call to sim_config.
1980
1981Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1982
1983 * interp.c (sim_kill): Delete.
1984 (sim_create_inferior): Add ABFD argument. Set PC from same.
1985 (sim_load): Move code initializing trap handlers from here.
1986 (sim_open): To here.
1987 (sim_load): Delete, use sim-hload.c.
1988
1989 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1990
1991Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1992
1993 * configure: Regenerated to track ../common/aclocal.m4 changes.
1994 * config.in: Ditto.
1995
1996Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1997
1998 * interp.c (sim_open): Add ABFD argument.
1999 (sim_load): Move call to sim_config from here.
2000 (sim_open): To here. Check return status.
2001
2002Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2003
2004 * gencode.c (build_instruction): Two arg MADD should
2005 not assign result to $0.
2006
2007Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2008
2009 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2010 * sim/mips/configure.in: Regenerate.
2011
2012Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2013
2014 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2015 signed8, unsigned8 et.al. types.
2016
2017 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2018 hosts when selecting subreg.
2019
2020Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2021
2022 * interp.c (sim_engine_run): Reset the ZERO register to zero
2023 regardless of FEATURE_WARN_ZERO.
2024 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2025
2026Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2027
2028 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2029 (SignalException): For BreakPoints ignore any mode bits and just
2030 save the PC.
2031 (SignalException): Always set the CAUSE register.
2032
2033Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2034
2035 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2036 exception has been taken.
2037
2038 * interp.c: Implement the ERET and mt/f sr instructions.
2039
2040Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2041
2042 * interp.c (SignalException): Don't bother restarting an
2043 interrupt.
2044
2045Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2046
2047 * interp.c (SignalException): Really take an interrupt.
2048 (interrupt_event): Only deliver interrupts when enabled.
2049
2050Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2051
2052 * interp.c (sim_info): Only print info when verbose.
2053 (sim_info) Use sim_io_printf for output.
2054
2055Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2056
2057 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2058 mips architectures.
2059
2060Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2061
2062 * interp.c (sim_do_command): Check for common commands if a
2063 simulator specific command fails.
2064
2065Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2066
2067 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2068 and simBE when DEBUG is defined.
2069
2070Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2071
2072 * interp.c (interrupt_event): New function. Pass exception event
2073 onto exception handler.
2074
2075 * configure.in: Check for stdlib.h.
2076 * configure: Regenerate.
2077
2078 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2079 variable declaration.
2080 (build_instruction): Initialize memval1.
2081 (build_instruction): Add UNUSED attribute to byte, bigend,
2082 reverse.
2083 (build_operands): Ditto.
2084
2085 * interp.c: Fix GCC warnings.
2086 (sim_get_quit_code): Delete.
2087
2088 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2089 * Makefile.in: Ditto.
2090 * configure: Re-generate.
2091
2092 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2093
2094Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2095
2096 * interp.c (mips_option_handler): New function parse argumes using
2097 sim-options.
2098 (myname): Replace with STATE_MY_NAME.
2099 (sim_open): Delete check for host endianness - performed by
2100 sim_config.
2101 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2102 (sim_open): Move much of the initialization from here.
2103 (sim_load): To here. After the image has been loaded and
2104 endianness set.
2105 (sim_open): Move ColdReset from here.
2106 (sim_create_inferior): To here.
2107 (sim_open): Make FP check less dependant on host endianness.
2108
2109 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2110 run.
2111 * interp.c (sim_set_callbacks): Delete.
2112
2113 * interp.c (membank, membank_base, membank_size): Replace with
2114 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2115 (sim_open): Remove call to callback->init. gdb/run do this.
2116
2117 * interp.c: Update
2118
2119 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2120
2121 * interp.c (big_endian_p): Delete, replaced by
2122 current_target_byte_order.
2123
2124Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2125
2126 * interp.c (host_read_long, host_read_word, host_swap_word,
2127 host_swap_long): Delete. Using common sim-endian.
2128 (sim_fetch_register, sim_store_register): Use H2T.
2129 (pipeline_ticks): Delete. Handled by sim-events.
2130 (sim_info): Update.
2131 (sim_engine_run): Update.
2132
2133Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2134
2135 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2136 reason from here.
2137 (SignalException): To here. Signal using sim_engine_halt.
2138 (sim_stop_reason): Delete, moved to common.
2139
2140Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2141
2142 * interp.c (sim_open): Add callback argument.
2143 (sim_set_callbacks): Delete SIM_DESC argument.
2144 (sim_size): Ditto.
2145
2146Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2147
2148 * Makefile.in (SIM_OBJS): Add common modules.
2149
2150 * interp.c (sim_set_callbacks): Also set SD callback.
2151 (set_endianness, xfer_*, swap_*): Delete.
2152 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2153 Change to functions using sim-endian macros.
2154 (control_c, sim_stop): Delete, use common version.
2155 (simulate): Convert into.
2156 (sim_engine_run): This function.
2157 (sim_resume): Delete.
2158
2159 * interp.c (simulation): New variable - the simulator object.
2160 (sim_kind): Delete global - merged into simulation.
2161 (sim_load): Cleanup. Move PC assignment from here.
2162 (sim_create_inferior): To here.
2163
2164 * sim-main.h: New file.
2165 * interp.c (sim-main.h): Include.
2166
2167Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2168
2169 * configure: Regenerated to track ../common/aclocal.m4 changes.
2170
2171Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2172
2173 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2174
2175Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2176
2177 * gencode.c (build_instruction): DIV instructions: check
2178 for division by zero and integer overflow before using
2179 host's division operation.
2180
2181Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2182
2183 * Makefile.in (SIM_OBJS): Add sim-load.o.
2184 * interp.c: #include bfd.h.
2185 (target_byte_order): Delete.
2186 (sim_kind, myname, big_endian_p): New static locals.
2187 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2188 after argument parsing. Recognize -E arg, set endianness accordingly.
2189 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2190 load file into simulator. Set PC from bfd.
2191 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2192 (set_endianness): Use big_endian_p instead of target_byte_order.
2193
2194Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2195
2196 * interp.c (sim_size): Delete prototype - conflicts with
2197 definition in remote-sim.h. Correct definition.
2198
2199Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2200
2201 * configure: Regenerated to track ../common/aclocal.m4 changes.
2202 * config.in: Ditto.
2203
2204Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2205
2206 * interp.c (sim_open): New arg `kind'.
2207
2208 * configure: Regenerated to track ../common/aclocal.m4 changes.
2209
2210Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2211
2212 * configure: Regenerated to track ../common/aclocal.m4 changes.
2213
2214Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2215
2216 * interp.c (sim_open): Set optind to 0 before calling getopt.
2217
2218Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2219
2220 * configure: Regenerated to track ../common/aclocal.m4 changes.
2221
2222Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2223
2224 * interp.c : Replace uses of pr_addr with pr_uword64
2225 where the bit length is always 64 independent of SIM_ADDR.
2226 (pr_uword64) : added.
2227
2228Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2229
2230 * configure: Re-generate.
2231
2232Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2233
2234 * configure: Regenerate to track ../common/aclocal.m4 changes.
2235
2236Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2237
2238 * interp.c (sim_open): New SIM_DESC result. Argument is now
2239 in argv form.
2240 (other sim_*): New SIM_DESC argument.
2241
2242Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2243
2244 * interp.c: Fix printing of addresses for non-64-bit targets.
2245 (pr_addr): Add function to print address based on size.
2246
2247Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2248
2249 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2250
2251Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2252
2253 * gencode.c (build_mips16_operands): Correct computation of base
2254 address for extended PC relative instruction.
2255
2256Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2257
2258 * interp.c (mips16_entry): Add support for floating point cases.
2259 (SignalException): Pass floating point cases to mips16_entry.
2260 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2261 registers.
2262 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2263 or fmt_word.
2264 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2265 and then set the state to fmt_uninterpreted.
2266 (COP_SW): Temporarily set the state to fmt_word while calling
2267 ValueFPR.
2268
2269Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2270
2271 * gencode.c (build_instruction): The high order may be set in the
2272 comparison flags at any ISA level, not just ISA 4.
2273
2274Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2275
2276 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2277 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2278 * configure.in: sinclude ../common/aclocal.m4.
2279 * configure: Regenerated.
2280
2281Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2282
2283 * configure: Rebuild after change to aclocal.m4.
2284
2285Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2286
2287 * configure configure.in Makefile.in: Update to new configure
2288 scheme which is more compatible with WinGDB builds.
2289 * configure.in: Improve comment on how to run autoconf.
2290 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2291 * Makefile.in: Use autoconf substitution to install common
2292 makefile fragment.
2293
2294Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2295
2296 * gencode.c (build_instruction): Use BigEndianCPU instead of
2297 ByteSwapMem.
2298
2299Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2300
2301 * interp.c (sim_monitor): Make output to stdout visible in
2302 wingdb's I/O log window.
2303
2304Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2305
2306 * support.h: Undo previous change to SIGTRAP
2307 and SIGQUIT values.
2308
2309Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2310
2311 * interp.c (store_word, load_word): New static functions.
2312 (mips16_entry): New static function.
2313 (SignalException): Look for mips16 entry and exit instructions.
2314 (simulate): Use the correct index when setting fpr_state after
2315 doing a pending move.
2316
2317Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2318
2319 * interp.c: Fix byte-swapping code throughout to work on
2320 both little- and big-endian hosts.
2321
2322Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2323
2324 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2325 with gdb/config/i386/xm-windows.h.
2326
2327Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2328
2329 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2330 that messes up arithmetic shifts.
2331
2332Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2333
2334 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2335 SIGTRAP and SIGQUIT for _WIN32.
2336
2337Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2338
2339 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2340 force a 64 bit multiplication.
2341 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2342 destination register is 0, since that is the default mips16 nop
2343 instruction.
2344
2345Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2346
2347 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2348 (build_endian_shift): Don't check proc64.
2349 (build_instruction): Always set memval to uword64. Cast op2 to
2350 uword64 when shifting it left in memory instructions. Always use
2351 the same code for stores--don't special case proc64.
2352
2353 * gencode.c (build_mips16_operands): Fix base PC value for PC
2354 relative operands.
2355 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2356 jal instruction.
2357 * interp.c (simJALDELAYSLOT): Define.
2358 (JALDELAYSLOT): Define.
2359 (INDELAYSLOT, INJALDELAYSLOT): Define.
2360 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2361
2362Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2363
2364 * interp.c (sim_open): add flush_cache as a PMON routine
2365 (sim_monitor): handle flush_cache by ignoring it
2366
2367Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2368
2369 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2370 BigEndianMem.
2371 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2372 (BigEndianMem): Rename to ByteSwapMem and change sense.
2373 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2374 BigEndianMem references to !ByteSwapMem.
2375 (set_endianness): New function, with prototype.
2376 (sim_open): Call set_endianness.
2377 (sim_info): Use simBE instead of BigEndianMem.
2378 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2379 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2380 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2381 ifdefs, keeping the prototype declaration.
2382 (swap_word): Rewrite correctly.
2383 (ColdReset): Delete references to CONFIG. Delete endianness related
2384 code; moved to set_endianness.
2385
2386Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2387
2388 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2389 * interp.c (CHECKHILO): Define away.
2390 (simSIGINT): New macro.
2391 (membank_size): Increase from 1MB to 2MB.
2392 (control_c): New function.
2393 (sim_resume): Rename parameter signal to signal_number. Add local
2394 variable prev. Call signal before and after simulate.
2395 (sim_stop_reason): Add simSIGINT support.
2396 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2397 functions always.
2398 (sim_warning): Delete call to SignalException. Do call printf_filtered
2399 if logfh is NULL.
2400 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2401 a call to sim_warning.
2402
2403Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2404
2405 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2406 16 bit instructions.
2407
2408Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2409
2410 Add support for mips16 (16 bit MIPS implementation):
2411 * gencode.c (inst_type): Add mips16 instruction encoding types.
2412 (GETDATASIZEINSN): Define.
2413 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2414 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2415 mtlo.
2416 (MIPS16_DECODE): New table, for mips16 instructions.
2417 (bitmap_val): New static function.
2418 (struct mips16_op): Define.
2419 (mips16_op_table): New table, for mips16 operands.
2420 (build_mips16_operands): New static function.
2421 (process_instructions): If PC is odd, decode a mips16
2422 instruction. Break out instruction handling into new
2423 build_instruction function.
2424 (build_instruction): New static function, broken out of
2425 process_instructions. Check modifiers rather than flags for SHIFT
2426 bit count and m[ft]{hi,lo} direction.
2427 (usage): Pass program name to fprintf.
2428 (main): Remove unused variable this_option_optind. Change
2429 ``*loptarg++'' to ``loptarg++''.
2430 (my_strtoul): Parenthesize && within ||.
2431 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2432 (simulate): If PC is odd, fetch a 16 bit instruction, and
2433 increment PC by 2 rather than 4.
2434 * configure.in: Add case for mips16*-*-*.
2435 * configure: Rebuild.
2436
2437Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2438
2439 * interp.c: Allow -t to enable tracing in standalone simulator.
2440 Fix garbage output in trace file and error messages.
2441
2442Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2443
2444 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2445 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2446 * configure.in: Simplify using macros in ../common/aclocal.m4.
2447 * configure: Regenerated.
2448 * tconfig.in: New file.
2449
2450Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2451
2452 * interp.c: Fix bugs in 64-bit port.
2453 Use ansi function declarations for msvc compiler.
2454 Initialize and test file pointer in trace code.
2455 Prevent duplicate definition of LAST_EMED_REGNUM.
2456
2457Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2458
2459 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2460
2461Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2462
2463 * interp.c (SignalException): Check for explicit terminating
2464 breakpoint value.
2465 * gencode.c: Pass instruction value through SignalException()
2466 calls for Trap, Breakpoint and Syscall.
2467
2468Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2469
2470 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2471 only used on those hosts that provide it.
2472 * configure.in: Add sqrt() to list of functions to be checked for.
2473 * config.in: Re-generated.
2474 * configure: Re-generated.
2475
2476Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2477
2478 * gencode.c (process_instructions): Call build_endian_shift when
2479 expanding STORE RIGHT, to fix swr.
2480 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2481 clear the high bits.
2482 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2483 Fix float to int conversions to produce signed values.
2484
2485Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2486
2487 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2488 (process_instructions): Correct handling of nor instruction.
2489 Correct shift count for 32 bit shift instructions. Correct sign
2490 extension for arithmetic shifts to not shift the number of bits in
2491 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2492 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2493 Fix madd.
2494 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2495 It's OK to have a mult follow a mult. What's not OK is to have a
2496 mult follow an mfhi.
2497 (Convert): Comment out incorrect rounding code.
2498
2499Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2500
2501 * interp.c (sim_monitor): Improved monitor printf
2502 simulation. Tidied up simulator warnings, and added "--log" option
2503 for directing warning message output.
2504 * gencode.c: Use sim_warning() rather than WARNING macro.
2505
2506Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2507
2508 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2509 getopt1.o, rather than on gencode.c. Link objects together.
2510 Don't link against -liberty.
2511 (gencode.o, getopt.o, getopt1.o): New targets.
2512 * gencode.c: Include <ctype.h> and "ansidecl.h".
2513 (AND): Undefine after including "ansidecl.h".
2514 (ULONG_MAX): Define if not defined.
2515 (OP_*): Don't define macros; now defined in opcode/mips.h.
2516 (main): Call my_strtoul rather than strtoul.
2517 (my_strtoul): New static function.
2518
2519Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2520
2521 * gencode.c (process_instructions): Generate word64 and uword64
2522 instead of `long long' and `unsigned long long' data types.
2523 * interp.c: #include sysdep.h to get signals, and define default
2524 for SIGBUS.
2525 * (Convert): Work around for Visual-C++ compiler bug with type
2526 conversion.
2527 * support.h: Make things compile under Visual-C++ by using
2528 __int64 instead of `long long'. Change many refs to long long
2529 into word64/uword64 typedefs.
2530
2531Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2532
2533 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2534 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2535 (docdir): Removed.
2536 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2537 (AC_PROG_INSTALL): Added.
2538 (AC_PROG_CC): Moved to before configure.host call.
2539 * configure: Rebuilt.
2540
2541Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2542
2543 * configure.in: Define @SIMCONF@ depending on mips target.
2544 * configure: Rebuild.
2545 * Makefile.in (run): Add @SIMCONF@ to control simulator
2546 construction.
2547 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2548 * interp.c: Remove some debugging, provide more detailed error
2549 messages, update memory accesses to use LOADDRMASK.
2550
2551Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2552
2553 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2554 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2555 stamp-h.
2556 * configure: Rebuild.
2557 * config.in: New file, generated by autoheader.
2558 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2559 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2560 HAVE_ANINT and HAVE_AINT, as appropriate.
2561 * Makefile.in (run): Use @LIBS@ rather than -lm.
2562 (interp.o): Depend upon config.h.
2563 (Makefile): Just rebuild Makefile.
2564 (clean): Remove stamp-h.
2565 (mostlyclean): Make the same as clean, not as distclean.
2566 (config.h, stamp-h): New targets.
2567
2568Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2569
2570 * interp.c (ColdReset): Fix boolean test. Make all simulator
2571 globals static.
2572
2573Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2574
2575 * interp.c (xfer_direct_word, xfer_direct_long,
2576 swap_direct_word, swap_direct_long, xfer_big_word,
2577 xfer_big_long, xfer_little_word, xfer_little_long,
2578 swap_word,swap_long): Added.
2579 * interp.c (ColdReset): Provide function indirection to
2580 host<->simulated_target transfer routines.
2581 * interp.c (sim_store_register, sim_fetch_register): Updated to
2582 make use of indirected transfer routines.
2583
2584Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2585
2586 * gencode.c (process_instructions): Ensure FP ABS instruction
2587 recognised.
2588 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2589 system call support.
2590
2591Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2592
2593 * interp.c (sim_do_command): Complain if callback structure not
2594 initialised.
2595
2596Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2597
2598 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2599 support for Sun hosts.
2600 * Makefile.in (gencode): Ensure the host compiler and libraries
2601 used for cross-hosted build.
2602
2603Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2604
2605 * interp.c, gencode.c: Some more (TODO) tidying.
2606
2607Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2608
2609 * gencode.c, interp.c: Replaced explicit long long references with
2610 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2611 * support.h (SET64LO, SET64HI): Macros added.
2612
2613Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2614
2615 * configure: Regenerate with autoconf 2.7.
2616
2617Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2618
2619 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2620 * support.h: Remove superfluous "1" from #if.
2621 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2622
2623Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2624
2625 * interp.c (StoreFPR): Control UndefinedResult() call on
2626 WARN_RESULT manifest.
2627
2628Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2629
2630 * gencode.c: Tidied instruction decoding, and added FP instruction
2631 support.
2632
2633 * interp.c: Added dineroIII, and BSD profiling support. Also
2634 run-time FP handling.
2635
2636Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2637
2638 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2639 gencode.c, interp.c, support.h: created.
GDB Binutils - Deliverables
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