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[deliverable/binutils-gdb.git] / sim / mips / interp.c
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c906108c
SS		 1/*> interp.c <*/
2/* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
c906108c
SS		 16NOTEs:
17
18The IDT monitor (found on the VR4300 board), seems to lie about
19register contents. It seems to treat the registers as sign-extended
2032-bit values. This cause *REAL* problems when single-stepping 64-bit
21code on the hardware.
22
23*/
24
25/* The TRACE manifests enable the provision of extra features. If they
26 are not defined then a simpler (quicker) simulator is constructed
27 without the required run-time checks, etc. */
28#if 1 /* 0 to allow user build selection, 1 to force inclusion */
29#define TRACE (1)
30#endif
31
32#include "bfd.h"
33#include "sim-main.h"
34#include "sim-utils.h"
35#include "sim-options.h"
36#include "sim-assert.h"
37#include "sim-hw.h"
38
39#include "itable.h"
40
41
42#include "config.h"
43
44#include <stdio.h>
45#include <stdarg.h>
46#include <ansidecl.h>
47#include <ctype.h>
48#include <limits.h>
49#include <math.h>
50#ifdef HAVE_STDLIB_H
51#include <stdlib.h>
52#endif
53#ifdef HAVE_STRING_H
54#include <string.h>
55#else
56#ifdef HAVE_STRINGS_H
57#include <strings.h>
58#endif
59#endif
60
61#include "getopt.h"
62#include "libiberty.h"
63#include "bfd.h"
3c25f8c7
AC		 64#include "gdb/callback.h" /* GDB simulator callback interface */
65#include "gdb/remote-sim.h" /* GDB simulator interface */
c906108c
SS		 66
67#include "sysdep.h"
68
69#ifndef PARAMS
70#define PARAMS(x)
71#endif
72
73char* pr_addr PARAMS ((SIM_ADDR addr));
74char* pr_uword64 PARAMS ((uword64 addr));
75
76
77/* Within interp.c we refer to the sim_state and sim_cpu directly. */
78#define CPU cpu
79#define SD sd
80
81
82/* The following reserved instruction value is used when a simulator
83 trap is required. NOTE: Care must be taken, since this value may be
84 used in later revisions of the MIPS ISA. */
85
86#define RSVD_INSTRUCTION (0x00000005)
87#define RSVD_INSTRUCTION_MASK (0xFC00003F)
88
89#define RSVD_INSTRUCTION_ARG_SHIFT 6
90#define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
91
92
93/* Bits in the Debug register */
94#define Debug_DBD 0x80000000 /* Debug Branch Delay */
95#define Debug_DM 0x40000000 /* Debug Mode */
96#define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
97
98/*---------------------------------------------------------------------------*/
99/*-- GDB simulator interface ------------------------------------------------*/
100/*---------------------------------------------------------------------------*/
101
102static void ColdReset PARAMS((SIM_DESC sd));
103
104/*---------------------------------------------------------------------------*/
105
106
107
108#define DELAYSLOT() {\
109 if (STATE & simDELAYSLOT)\
110 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
111 STATE |= simDELAYSLOT;\
112 }
113
114#define JALDELAYSLOT() {\
115 DELAYSLOT ();\
116 STATE |= simJALDELAYSLOT;\
117 }
118
119#define NULLIFY() {\
120 STATE &= ~simDELAYSLOT;\
121 STATE |= simSKIPNEXT;\
122 }
123
124#define CANCELDELAYSLOT() {\
125 DSSTATE = 0;\
126 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
127 }
128
129#define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
130#define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
131
adf40b2e
JM		 132/* Note that the monitor code essentially assumes this layout of memory.
133 If you change these, change the monitor code, too. */
14fb6c5a
TS		 134/* FIXME Currently addresses are truncated to 32-bits, see
135 mips/sim-main.c:address_translation(). If that changes, then these
136 values will need to be extended, and tested for more carefully. */
c906108c
SS		 137#define K0BASE (0x80000000)
138#define K0SIZE (0x20000000)
139#define K1BASE (0xA0000000)
140#define K1SIZE (0x20000000)
adf40b2e
JM		 141
142/* Simple run-time monitor support.
143
144 We emulate the monitor by placing magic reserved instructions at
145 the monitor's entry points; when we hit these instructions, instead
146 of raising an exception (as we would normally), we look at the
147 instruction and perform the appropriate monitory operation.
148
149 `*_monitor_base' are the physical addresses at which the corresponding
150 monitor vectors are located. `0' means none. By default,
151 install all three.
152 The RSVD_INSTRUCTION... macros specify the magic instructions we
153 use at the monitor entry points. */
154static int firmware_option_p = 0;
155static SIM_ADDR idt_monitor_base = 0xBFC00000;
156static SIM_ADDR pmon_monitor_base = 0xBFC00500;
157static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
158
159static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
160
161
c8847145 162#define MEM_SIZE (8 << 20) /* 8 MBytes */
c906108c
SS		 163
164
165#if defined(TRACE)
166static char *tracefile = "trace.din"; /* default filename for trace log */
167FILE *tracefh = NULL;
168static void open_trace PARAMS((SIM_DESC sd));
169#endif /* TRACE */
170
171static const char * get_insn_name (sim_cpu *, int);
172
173/* simulation target board. NULL=canonical */
174static char* board = NULL;
175
176
177static DECLARE_OPTION_HANDLER (mips_option_handler);
178
179enum {
180 OPTION_DINERO_TRACE = OPTION_START,
181 OPTION_DINERO_FILE,
adf40b2e 182 OPTION_FIRMWARE,
c906108c
SS		 183 OPTION_BOARD
184};
185
186
187static SIM_RC
188mips_option_handler (sd, cpu, opt, arg, is_command)
189 SIM_DESC sd;
190 sim_cpu *cpu;
191 int opt;
192 char *arg;
193 int is_command;
194{
195 int cpu_nr;
196 switch (opt)
197 {
198 case OPTION_DINERO_TRACE: /* ??? */
199#if defined(TRACE)
200 /* Eventually the simTRACE flag could be treated as a toggle, to
201 allow external control of the program points being traced
202 (i.e. only from main onwards, excluding the run-time setup,
203 etc.). */
204 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
205 {
206 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
207 if (arg == NULL)
208 STATE |= simTRACE;
209 else if (strcmp (arg, "yes") == 0)
210 STATE |= simTRACE;
211 else if (strcmp (arg, "no") == 0)
212 STATE &= ~simTRACE;
213 else if (strcmp (arg, "on") == 0)
214 STATE |= simTRACE;
215 else if (strcmp (arg, "off") == 0)
216 STATE &= ~simTRACE;
217 else
218 {
219 fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
220 return SIM_RC_FAIL;
221 }
222 }
223 return SIM_RC_OK;
224#else /* !TRACE */
225 fprintf(stderr,"\
226Simulator constructed without dinero tracing support (for performance).\n\
227Re-compile simulator with \"-DTRACE\" to enable this option.\n");
228 return SIM_RC_FAIL;
229#endif /* !TRACE */
230
231 case OPTION_DINERO_FILE:
232#if defined(TRACE)
233 if (optarg != NULL) {
234 char *tmp;
235 tmp = (char *)malloc(strlen(optarg) + 1);
236 if (tmp == NULL)
237 {
238 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
239 return SIM_RC_FAIL;
240 }
241 else {
242 strcpy(tmp,optarg);
243 tracefile = tmp;
244 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
245 }
246 }
247#endif /* TRACE */
248 return SIM_RC_OK;
249
adf40b2e
JM		 250 case OPTION_FIRMWARE:
251 return sim_firmware_command (sd, arg);
252
c906108c
SS		 253 case OPTION_BOARD:
254 {
255 if (arg)
256 {
257 board = zalloc(strlen(arg) + 1);
258 strcpy(board, arg);
259 }
260 return SIM_RC_OK;
261 }
262 }
263
264 return SIM_RC_OK;
265}
266
267
268static const OPTION mips_options[] =
269{
270 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
271 '\0', "on|off", "Enable dinero tracing",
272 mips_option_handler },
273 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
274 '\0', "FILE", "Write dinero trace to FILE",
275 mips_option_handler },
adf40b2e
JM		 276 { {"firmware", required_argument, NULL, OPTION_FIRMWARE},
277 '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
278 mips_option_handler },
c906108c
SS		 279 { {"board", required_argument, NULL, OPTION_BOARD},
280 '\0', "none" /* rely on compile-time string concatenation for other options */
281
282#define BOARD_JMR3904 "jmr3904"
283 "|" BOARD_JMR3904
284#define BOARD_JMR3904_PAL "jmr3904pal"
285 "|" BOARD_JMR3904_PAL
286#define BOARD_JMR3904_DEBUG "jmr3904debug"
287 "|" BOARD_JMR3904_DEBUG
43e526b9
JM		 288#define BOARD_BSP "bsp"
289 "|" BOARD_BSP
c906108c
SS		 290
291 , "Customize simulation for a particular board.", mips_option_handler },
292
293 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
294};
295
296
297int interrupt_pending;
298
299void
300interrupt_event (SIM_DESC sd, void *data)
301{
302 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
303 address_word cia = CIA_GET (cpu);
304 if (SR & status_IE)
305 {
306 interrupt_pending = 0;
307 SignalExceptionInterrupt (1); /* interrupt "1" */
308 }
309 else if (!interrupt_pending)
310 sim_events_schedule (sd, 1, interrupt_event, data);
311}
312
313
314/*---------------------------------------------------------------------------*/
315/*-- Device registration hook -----------------------------------------------*/
316/*---------------------------------------------------------------------------*/
317static void device_init(SIM_DESC sd) {
318#ifdef DEVICE_INIT
319 extern void register_devices(SIM_DESC);
320 register_devices(sd);
321#endif
322}
323
324/*---------------------------------------------------------------------------*/
325/*-- GDB simulator interface ------------------------------------------------*/
326/*---------------------------------------------------------------------------*/
327
328SIM_DESC
329sim_open (kind, cb, abfd, argv)
330 SIM_OPEN_KIND kind;
331 host_callback *cb;
6b4a8935 332 struct bfd *abfd;
c906108c
SS		 333 char **argv;
334{
335 SIM_DESC sd = sim_state_alloc (kind, cb);
336 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
337
338 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
339
340 /* FIXME: watchpoints code shouldn't need this */
341 STATE_WATCHPOINTS (sd)->pc = &(PC);
342 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
343 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
344
345 /* Initialize the mechanism for doing insn profiling. */
346 CPU_INSN_NAME (cpu) = get_insn_name;
347 CPU_MAX_INSNS (cpu) = nr_itable_entries;
348
349 STATE = 0;
350
351 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
352 return 0;
353 sim_add_option_table (sd, NULL, mips_options);
354
355
356 /* getopt will print the error message so we just have to exit if this fails.
357 FIXME: Hmmm... in the case of gdb we need getopt to call
358 print_filtered. */
359 if (sim_parse_args (sd, argv) != SIM_RC_OK)
360 {
361 /* Uninstall the modules to avoid memory leaks,
362 file descriptor leaks, etc. */
363 sim_module_uninstall (sd);
364 return 0;
365 }
366
367 /* handle board-specific memory maps */
368 if (board == NULL)
369 {
370 /* Allocate core managed memory */
14fb6c5a
TS		 371 sim_memopt *entry, *match = NULL;
372 address_word mem_size = 0;
373 int mapped = 0;
adf40b2e 374
c906108c
SS		 375 /* For compatibility with the old code - under this (at level one)
376 are the kernel spaces K0 & K1. Both of these map to a single
377 smaller sub region */
378 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
14fb6c5a
TS		 379
380 /* Look for largest memory region defined on command-line at
381 phys address 0. */
382#ifdef SIM_HAVE_FLATMEM
383 mem_size = STATE_MEM_SIZE (sd);
384#endif
385 for (entry = STATE_MEMOPT (sd); entry != NULL; entry = entry->next)
386 {
387 /* If we find an entry at address 0, then we will end up
388 allocating a new buffer in the "memory alias" command
389 below. The region at address 0 will be deleted. */
390 address_word size = (entry->modulo != 0
391 ? entry->modulo : entry->nr_bytes);
392 if (entry->addr == 0
393 && (!match || entry->level < match->level))
394 match = entry;
395 else if (entry->addr == K0BASE || entry->addr == K1BASE)
396 mapped = 1;
397 else
398 {
399 sim_memopt *alias;
400 for (alias = entry->alias; alias != NULL; alias = alias->next)
401 {
402 if (alias->addr == 0
403 && (!match || entry->level < match->level))
404 match = entry;
405 else if (alias->addr == K0BASE || alias->addr == K1BASE)
406 mapped = 1;
407 }
408 }
409 }
410
411 if (!mapped)
412 {
413 if (match)
414 {
415 /* Get existing memory region size. */
416 mem_size = (match->modulo != 0
417 ? match->modulo : match->nr_bytes);
418 /* Delete old region. */
419 sim_do_commandf (sd, "memory delete %d:0x%lx@%d",
420 match->space, match->addr, match->level);
421 }
422 else if (mem_size == 0)
423 mem_size = MEM_SIZE;
424 /* Limit to KSEG1 size (512MB) */
425 if (mem_size > K1SIZE)
426 mem_size = K1SIZE;
427 /* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
428 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
429 K1BASE, K1SIZE, (long)mem_size, K0BASE);
430 }
431
c906108c
SS		 432 device_init(sd);
433 }
43e526b9
JM		 434 else if (board != NULL
435 && (strcmp(board, BOARD_BSP) == 0))
436 {
437 int i;
438
439 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
440
441 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
442 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
443 0x9FC00000,
444 4 * 1024 * 1024, /* 4 MB */
445 0xBFC00000);
446
447 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
448 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
449 0x80000000,
450 4 * 1024 * 1024, /* 4 MB */
451 0xA0000000);
452
453 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
454 for (i=0; i<8; i++) /* 32 MB total */
455 {
456 unsigned size = 4 * 1024 * 1024; /* 4 MB */
457 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
458 0x88000000 + (i * size),
459 size,
460 0xA8000000 + (i * size));
461 }
462 }
c906108c 463#if (WITH_HW)
43e526b9
JM		 464 else if (board != NULL
465 && (strcmp(board, BOARD_JMR3904) == 0 ||
466 strcmp(board, BOARD_JMR3904_PAL) == 0 ||
467 strcmp(board, BOARD_JMR3904_DEBUG) == 0))
c906108c
SS		 468 {
469 /* match VIRTUAL memory layout of JMR-TX3904 board */
470 int i;
471
adf40b2e
JM		 472 /* --- disable monitor unless forced on by user --- */
473
474 if (! firmware_option_p)
475 {
476 idt_monitor_base = 0;
477 pmon_monitor_base = 0;
478 lsipmon_monitor_base = 0;
479 }
480
c906108c
SS		 481 /* --- environment --- */
482
483 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
484
485 /* --- memory --- */
486
487 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
488 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
489 0x9FC00000,
490 4 * 1024 * 1024, /* 4 MB */
491 0xBFC00000);
492
493 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
494 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
495 0x80000000,
496 4 * 1024 * 1024, /* 4 MB */
497 0xA0000000);
498
499 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
500 for (i=0; i<8; i++) /* 32 MB total */
501 {
502 unsigned size = 4 * 1024 * 1024; /* 4 MB */
503 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
504 0x88000000 + (i * size),
505 size,
506 0xA8000000 + (i * size));
507 }
508
cb7450ea 509 /* Dummy memory regions for unsimulated devices - sorted by address */
c906108c 510
d4f3574e 511 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
c2d11a7d
JM		 512 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
513 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
d4f3574e
SS		 514 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
515 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
cb7450ea
FCE		 516 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
517 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
518 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
519 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
520
c906108c
SS		 521
522 /* --- simulated devices --- */
523 sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
524 sim_hw_parse (sd, "/tx3904cpu");
525 sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
526 sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
527 sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
528 sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
529 {
530 /* FIXME: poking at dv-sockser internals, use tcp backend if
531 --sockser_addr option was given.*/
532 extern char* sockser_addr;
533 if(sockser_addr == NULL)
534 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
535 else
536 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
537 }
538 sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
539 sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
540
541 /* -- device connections --- */
542 sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
543 sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
544 sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
545 sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
546 sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
547 sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
548
549 /* add PAL timer & I/O module */
550 if(! strcmp(board, BOARD_JMR3904_PAL))
551 {
552 /* the device */
553 sim_hw_parse (sd, "/pal@0xffff0000");
554 sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
555
556 /* wire up interrupt ports to irc */
557 sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
558 sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
559 sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
560 }
561
562 if(! strcmp(board, BOARD_JMR3904_DEBUG))
563 {
564 /* -- DEBUG: glue interrupt generators --- */
565 sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
566 sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
567 sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
568 sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
569 sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
570 sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
571 sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
572 sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
573 sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
574 sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
575 sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
576 sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
577 sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
578 sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
579 sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
580 sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
581 sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
582 sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
583 sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
584 }
585
586 device_init(sd);
587 }
588#endif
589
590
591 /* check for/establish the a reference program image */
592 if (sim_analyze_program (sd,
593 (STATE_PROG_ARGV (sd) != NULL
594 ? *STATE_PROG_ARGV (sd)
595 : NULL),
596 abfd) != SIM_RC_OK)
597 {
598 sim_module_uninstall (sd);
599 return 0;
600 }
601
602 /* Configure/verify the target byte order and other runtime
603 configuration options */
604 if (sim_config (sd) != SIM_RC_OK)
605 {
606 sim_module_uninstall (sd);
607 return 0;
608 }
609
610 if (sim_post_argv_init (sd) != SIM_RC_OK)
611 {
612 /* Uninstall the modules to avoid memory leaks,
613 file descriptor leaks, etc. */
614 sim_module_uninstall (sd);
615 return 0;
616 }
617
618 /* verify assumptions the simulator made about the host type system.
619 This macro does not return if there is a problem */
620 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
621 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
622
623 /* This is NASTY, in that we are assuming the size of specific
624 registers: */
625 {
626 int rn;
627 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
628 {
629 if (rn < 32)
630 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
ee7254b0 631 else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
c906108c
SS		 632 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
633 else if ((rn >= 33) && (rn <= 37))
634 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
635 else if ((rn == SRIDX)
636 || (rn == FCR0IDX)
637 || (rn == FCR31IDX)
638 || ((rn >= 72) && (rn <= 89)))
639 cpu->register_widths[rn] = 32;
640 else
641 cpu->register_widths[rn] = 0;
642 }
643
644
645 }
646
647#if defined(TRACE)
648 if (STATE & simTRACE)
649 open_trace(sd);
650#endif /* TRACE */
651
adf40b2e
JM		 652 /*
653 sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
654 idt_monitor_base,
655 pmon_monitor_base,
656 lsipmon_monitor_base);
657 */
c906108c
SS		 658
659 /* Write the monitor trap address handlers into the monitor (eeprom)
660 address space. This can only be done once the target endianness
661 has been determined. */
adf40b2e
JM		 662 if (idt_monitor_base != 0)
663 {
664 unsigned loop;
665 unsigned idt_monitor_size = 1 << 11;
666
667 /* the default monitor region */
668 sim_do_commandf (sd, "memory region 0x%x,0x%x",
669 idt_monitor_base, idt_monitor_size);
670
671 /* Entry into the IDT monitor is via fixed address vectors, and
672 not using machine instructions. To avoid clashing with use of
673 the MIPS TRAP system, we place our own (simulator specific)
674 "undefined" instructions into the relevant vector slots. */
675 for (loop = 0; (loop < idt_monitor_size); loop += 4)
676 {
677 address_word vaddr = (idt_monitor_base + loop);
678 unsigned32 insn = (RSVD_INSTRUCTION |
679 (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
680 << RSVD_INSTRUCTION_ARG_SHIFT));
681 H2T (insn);
682 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
683 }
684 }
685
686 if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0))
687 {
c906108c
SS		 688 /* The PMON monitor uses the same address space, but rather than
689 branching into it the address of a routine is loaded. We can
690 cheat for the moment, and direct the PMON routine to IDT style
691 instructions within the monitor space. This relies on the IDT
692 monitor not using the locations from 0xBFC00500 onwards as its
693 entry points.*/
adf40b2e
JM		 694 unsigned loop;
695 for (loop = 0; (loop < 24); loop++)
696 {
697 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
698 switch (loop)
699 {
c906108c
SS		 700 case 0: /* read */
701 value = 7;
702 break;
703 case 1: /* write */
704 value = 8;
705 break;
706 case 2: /* open */
707 value = 6;
708 break;
709 case 3: /* close */
710 value = 10;
711 break;
712 case 5: /* printf */
713 value = ((0x500 - 16) / 8); /* not an IDT reason code */
714 break;
715 case 8: /* cliexit */
716 value = 17;
717 break;
718 case 11: /* flush_cache */
719 value = 28;
720 break;
721 }
adf40b2e
JM		 722
723 SIM_ASSERT (idt_monitor_base != 0);
724 value = ((unsigned int) idt_monitor_base + (value * 8));
c906108c 725 H2T (value);
c906108c 726
adf40b2e
JM		 727 if (pmon_monitor_base != 0)
728 {
729 address_word vaddr = (pmon_monitor_base + (loop * 4));
730 sim_write (sd, vaddr, (char *)&value, sizeof (value));
731 }
732
733 if (lsipmon_monitor_base != 0)
734 {
735 address_word vaddr = (lsipmon_monitor_base + (loop * 4));
736 sim_write (sd, vaddr, (char *)&value, sizeof (value));
737 }
c906108c 738 }
adf40b2e
JM		 739
740 /* Write an abort sequence into the TRAP (common) exception vector
741 addresses. This is to catch code executing a TRAP (et.al.)
742 instruction without installing a trap handler. */
743 if ((idt_monitor_base != 0) ||
744 (pmon_monitor_base != 0) ||
745 (lsipmon_monitor_base != 0))
746 {
747 unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
748 HALT_INSTRUCTION /* BREAK */ };
749 H2T (halt[0]);
750 H2T (halt[1]);
751 sim_write (sd, 0x80000000, (char *) halt, sizeof (halt));
752 sim_write (sd, 0x80000180, (char *) halt, sizeof (halt));
753 sim_write (sd, 0x80000200, (char *) halt, sizeof (halt));
754 /* XXX: Write here unconditionally? */
755 sim_write (sd, 0xBFC00200, (char *) halt, sizeof (halt));
756 sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt));
757 sim_write (sd, 0xBFC00400, (char *) halt, sizeof (halt));
758 }
c906108c
SS		 759 }
760
761
762
763 return sd;
764}
765
766#if defined(TRACE)
767static void
768open_trace(sd)
769 SIM_DESC sd;
770{
771 tracefh = fopen(tracefile,"wb+");
772 if (tracefh == NULL)
773 {
774 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
775 tracefh = stderr;
776 }
777}
778#endif /* TRACE */
779
780/* Return name of an insn, used by insn profiling. */
781static const char *
782get_insn_name (sim_cpu *cpu, int i)
783{
784 return itable[i].name;
785}
786
787void
788sim_close (sd, quitting)
789 SIM_DESC sd;
790 int quitting;
791{
792#ifdef DEBUG
793 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
794#endif
795
796
797 /* "quitting" is non-zero if we cannot hang on errors */
798
799 /* shut down modules */
800 sim_module_uninstall (sd);
801
802 /* Ensure that any resources allocated through the callback
803 mechanism are released: */
804 sim_io_shutdown (sd);
805
806#if defined(TRACE)
807 if (tracefh != NULL && tracefh != stderr)
808 fclose(tracefh);
809 tracefh = NULL;
810#endif /* TRACE */
811
812 /* FIXME - free SD */
813
814 return;
815}
816
817
818int
819sim_write (sd,addr,buffer,size)
820 SIM_DESC sd;
821 SIM_ADDR addr;
822 unsigned char *buffer;
823 int size;
824{
825 int index;
826 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
827
828 /* Return the number of bytes written, or zero if error. */
829#ifdef DEBUG
830 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
831#endif
832
833 /* We use raw read and write routines, since we do not want to count
834 the GDB memory accesses in our statistics gathering. */
835
836 for (index = 0; index < size; index++)
837 {
838 address_word vaddr = (address_word)addr + index;
839 address_word paddr;
840 int cca;
841 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
842 break;
843 if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
844 break;
845 }
846
847 return(index);
848}
849
850int
851sim_read (sd,addr,buffer,size)
852 SIM_DESC sd;
853 SIM_ADDR addr;
854 unsigned char *buffer;
855 int size;
856{
857 int index;
858 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
859
860 /* Return the number of bytes read, or zero if error. */
861#ifdef DEBUG
862 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
863#endif /* DEBUG */
864
865 for (index = 0; (index < size); index++)
866 {
867 address_word vaddr = (address_word)addr + index;
868 address_word paddr;
869 int cca;
870 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
871 break;
872 if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
873 break;
874 }
875
876 return(index);
877}
878
879int
880sim_store_register (sd,rn,memory,length)
881 SIM_DESC sd;
882 int rn;
883 unsigned char *memory;
884 int length;
885{
886 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
887 /* NOTE: gdb (the client) stores registers in target byte order
888 while the simulator uses host byte order */
889#ifdef DEBUG
890 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
891#endif /* DEBUG */
892
893 /* Unfortunately this suffers from the same problem as the register
894 numbering one. We need to know what the width of each logical
895 register number is for the architecture being simulated. */
896
897 if (cpu->register_widths[rn] == 0)
898 {
899 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
900 return 0;
901 }
902
903
904
ee7254b0 905 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
c906108c 906 {
ee7254b0 907 cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
c906108c
SS		 908 if (cpu->register_widths[rn] == 32)
909 {
a0b3c4fd
JM		 910 if (length == 8)
911 {
ee7254b0 912 cpu->fgr[rn - FGR_BASE] =
a0b3c4fd
JM		 913 (unsigned32) T2H_8 (*(unsigned64*)memory);
914 return 8;
915 }
916 else
917 {
ee7254b0 918 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
a0b3c4fd
JM		 919 return 4;
920 }
c906108c
SS		 921 }
922 else
923 {
14fb6c5a
TS		 924 if (length == 8)
925 {
926 cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
927 return 8;
928 }
929 else
930 {
931 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
932 return 4;
933 }
c906108c
SS		 934 }
935 }
936
937 if (cpu->register_widths[rn] == 32)
938 {
a0b3c4fd
JM		 939 if (length == 8)
940 {
941 cpu->registers[rn] =
942 (unsigned32) T2H_8 (*(unsigned64*)memory);
943 return 8;
944 }
945 else
946 {
947 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
948 return 4;
949 }
c906108c
SS		 950 }
951 else
952 {
14fb6c5a
TS		 953 if (length == 8)
954 {
955 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
956 return 8;
957 }
958 else
959 {
960 cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory);
961 return 4;
962 }
c906108c
SS		 963 }
964
965 return 0;
966}
967
968int
969sim_fetch_register (sd,rn,memory,length)
970 SIM_DESC sd;
971 int rn;
972 unsigned char *memory;
973 int length;
974{
975 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
976 /* NOTE: gdb (the client) stores registers in target byte order
977 while the simulator uses host byte order */
978#ifdef DEBUG
979#if 0 /* FIXME: doesn't compile */
980 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
981#endif
982#endif /* DEBUG */
983
984 if (cpu->register_widths[rn] == 0)
985 {
986 sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
987 return 0;
988 }
989
990
991
992 /* Any floating point register */
ee7254b0 993 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
c906108c
SS		 994 {
995 if (cpu->register_widths[rn] == 32)
996 {
a0b3c4fd
JM		 997 if (length == 8)
998 {
999 *(unsigned64*)memory =
ee7254b0 1000 H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
a0b3c4fd
JM		 1001 return 8;
1002 }
1003 else
1004 {
ee7254b0 1005 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
a0b3c4fd
JM		 1006 return 4;
1007 }
c906108c
SS		 1008 }
1009 else
1010 {
14fb6c5a
TS		 1011 if (length == 8)
1012 {
1013 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
1014 return 8;
1015 }
1016 else
1017 {
1018 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE]));
1019 return 4;
1020 }
c906108c
SS		 1021 }
1022 }
1023
1024 if (cpu->register_widths[rn] == 32)
1025 {
a0b3c4fd
JM		 1026 if (length == 8)
1027 {
1028 *(unsigned64*)memory =
1029 H2T_8 ((unsigned32) (cpu->registers[rn]));
1030 return 8;
1031 }
1032 else
1033 {
1034 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
1035 return 4;
1036 }
c906108c
SS		 1037 }
1038 else
1039 {
14fb6c5a
TS		 1040 if (length == 8)
1041 {
1042 *(unsigned64*)memory =
1043 H2T_8 ((unsigned64) (cpu->registers[rn]));
1044 return 8;
1045 }
1046 else
1047 {
1048 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
1049 return 4;
1050 }
c906108c
SS		 1051 }
1052
1053 return 0;
1054}
1055
1056
1057SIM_RC
1058sim_create_inferior (sd, abfd, argv,env)
1059 SIM_DESC sd;
6b4a8935 1060 struct bfd *abfd;
c906108c
SS		 1061 char **argv;
1062 char **env;
1063{
1064
1065#ifdef DEBUG
1066#if 0 /* FIXME: doesn't compile */
1067 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1068 pr_addr(PC));
1069#endif
1070#endif /* DEBUG */
1071
1072 ColdReset(sd);
1073
1074 if (abfd != NULL)
1075 {
1076 /* override PC value set by ColdReset () */
1077 int cpu_nr;
1078 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1079 {
1080 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1081 CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
1082 }
1083 }
1084
1085#if 0 /* def DEBUG */
1086 if (argv || env)
1087 {
1088 /* We should really place the argv slot values into the argument
1089 registers, and onto the stack as required. However, this
1090 assumes that we have a stack defined, which is not
1091 necessarily true at the moment. */
1092 char **cptr;
1093 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
1094 for (cptr = argv; (cptr && *cptr); cptr++)
1095 printf("DBG: arg \"%s\"\n",*cptr);
1096 }
1097#endif /* DEBUG */
1098
1099 return SIM_RC_OK;
1100}
1101
1102void
1103sim_do_command (sd,cmd)
1104 SIM_DESC sd;
1105 char *cmd;
1106{
1107 if (sim_args_command (sd, cmd) != SIM_RC_OK)
1108 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
1109 cmd);
1110}
1111
1112/*---------------------------------------------------------------------------*/
1113/*-- Private simulator support interface ------------------------------------*/
1114/*---------------------------------------------------------------------------*/
1115
1116/* Read a null terminated string from memory, return in a buffer */
1117static char *
1118fetch_str (SIM_DESC sd,
1119 address_word addr)
1120{
1121 char *buf;
1122 int nr = 0;
1123 char null;
1124 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
1125 nr++;
1126 buf = NZALLOC (char, nr + 1);
1127 sim_read (sd, addr, buf, nr);
1128 return buf;
1129}
1130
adf40b2e
JM		 1131
1132/* Implements the "sim firmware" command:
1133 sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
1134 NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
1135 defaults to the normal address for that monitor.
1136 sim firmware none --- don't emulate any ROM monitor. Useful
1137 if you need a clean address space. */
1138static SIM_RC
1139sim_firmware_command (SIM_DESC sd, char *arg)
1140{
1141 int address_present = 0;
1142 SIM_ADDR address;
1143
1144 /* Signal occurrence of this option. */
1145 firmware_option_p = 1;
1146
1147 /* Parse out the address, if present. */
1148 {
1149 char *p = strchr (arg, '@');
1150 if (p)
1151 {
1152 char *q;
1153 address_present = 1;
1154 p ++; /* skip over @ */
1155
1156 address = strtoul (p, &q, 0);
1157 if (*q != '\0')
1158 {
1159 sim_io_printf (sd, "Invalid address given to the"
1160 "`sim firmware NAME@ADDRESS' command: %s\n",
1161 p);
1162 return SIM_RC_FAIL;
1163 }
1164 }
1165 else
b4b6c939
AC		 1166 {
1167 address_present = 0;
1168 address = -1; /* Dummy value. */
1169 }
adf40b2e
JM		 1170 }
1171
1172 if (! strncmp (arg, "idt", 3))
1173 {
1174 idt_monitor_base = address_present ? address : 0xBFC00000;
1175 pmon_monitor_base = 0;
1176 lsipmon_monitor_base = 0;
1177 }
1178 else if (! strncmp (arg, "pmon", 4))
1179 {
1180 /* pmon uses indirect calls. Hook into implied idt. */
1181 pmon_monitor_base = address_present ? address : 0xBFC00500;
1182 idt_monitor_base = pmon_monitor_base - 0x500;
1183 lsipmon_monitor_base = 0;
1184 }
1185 else if (! strncmp (arg, "lsipmon", 7))
1186 {
1187 /* lsipmon uses indirect calls. Hook into implied idt. */
1188 pmon_monitor_base = 0;
1189 lsipmon_monitor_base = address_present ? address : 0xBFC00200;
1190 idt_monitor_base = lsipmon_monitor_base - 0x200;
1191 }
1192 else if (! strncmp (arg, "none", 4))
1193 {
1194 if (address_present)
1195 {
1196 sim_io_printf (sd,
1197 "The `sim firmware none' command does "
1198 "not take an `ADDRESS' argument.\n");
1199 return SIM_RC_FAIL;
1200 }
1201 idt_monitor_base = 0;
1202 pmon_monitor_base = 0;
1203 lsipmon_monitor_base = 0;
1204 }
1205 else
1206 {
1207 sim_io_printf (sd, "\
1208Unrecognized name given to the `sim firmware NAME' command: %s\n\
1209Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
1210 arg);
1211 return SIM_RC_FAIL;
1212 }
1213
1214 return SIM_RC_OK;
1215}
1216
1217
1218
c906108c 1219/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
8030f857 1220int
c906108c
SS		 1221sim_monitor (SIM_DESC sd,
1222 sim_cpu *cpu,
1223 address_word cia,
1224 unsigned int reason)
1225{
1226#ifdef DEBUG
1227 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
1228#endif /* DEBUG */
1229
1230 /* The IDT monitor actually allows two instructions per vector
1231 slot. However, the simulator currently causes a trap on each
1232 individual instruction. We cheat, and lose the bottom bit. */
1233 reason >>= 1;
1234
1235 /* The following callback functions are available, however the
1236 monitor we are simulating does not make use of them: get_errno,
1237 isatty, lseek, rename, system, time and unlink */
1238 switch (reason)
1239 {
1240
1241 case 6: /* int open(char *path,int flags) */
1242 {
1243 char *path = fetch_str (sd, A0);
1244 V0 = sim_io_open (sd, path, (int)A1);
1245 zfree (path);
1246 break;
1247 }
1248
1249 case 7: /* int read(int file,char *ptr,int len) */
1250 {
1251 int fd = A0;
1252 int nr = A2;
1253 char *buf = zalloc (nr);
1254 V0 = sim_io_read (sd, fd, buf, nr);
1255 sim_write (sd, A1, buf, nr);
1256 zfree (buf);
1257 }
1258 break;
1259
1260 case 8: /* int write(int file,char *ptr,int len) */
1261 {
1262 int fd = A0;
1263 int nr = A2;
1264 char *buf = zalloc (nr);
1265 sim_read (sd, A1, buf, nr);
1266 V0 = sim_io_write (sd, fd, buf, nr);
f8df4c77
TS		 1267 if (fd == 1)
1268 sim_io_flush_stdout (sd);
1269 else if (fd == 2)
1270 sim_io_flush_stderr (sd);
c906108c
SS		 1271 zfree (buf);
1272 break;
1273 }
1274
1275 case 10: /* int close(int file) */
1276 {
1277 V0 = sim_io_close (sd, (int)A0);
1278 break;
1279 }
1280
1281 case 2: /* Densan monitor: char inbyte(int waitflag) */
1282 {
1283 if (A0 == 0) /* waitflag == NOWAIT */
1284 V0 = (unsigned_word)-1;
1285 }
1286 /* Drop through to case 11 */
1287
1288 case 11: /* char inbyte(void) */
1289 {
1290 char tmp;
43e526b9
JM		 1291 /* ensure that all output has gone... */
1292 sim_io_flush_stdout (sd);
c906108c
SS		 1293 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
1294 {
1295 sim_io_error(sd,"Invalid return from character read");
1296 V0 = (unsigned_word)-1;
1297 }
1298 else
1299 V0 = (unsigned_word)tmp;
1300 break;
1301 }
1302
1303 case 3: /* Densan monitor: void co(char chr) */
1304 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1305 {
1306 char tmp = (char)(A0 & 0xFF);
1307 sim_io_write_stdout (sd, &tmp, sizeof(char));
1308 break;
1309 }
1310
1311 case 17: /* void _exit() */
1312 {
1313 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
1314 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
1315 (unsigned int)(A0 & 0xFFFFFFFF));
1316 break;
1317 }
1318
e80fc152 1319 case 28: /* PMON flush_cache */
c906108c
SS		 1320 break;
1321
1322 case 55: /* void get_mem_info(unsigned int *ptr) */
1323 /* in: A0 = pointer to three word memory location */
1324 /* out: [A0 + 0] = size */
1325 /* [A0 + 4] = instruction cache size */
1326 /* [A0 + 8] = data cache size */
1327 {
14fb6c5a 1328 unsigned_4 value;
c906108c 1329 unsigned_4 zero = 0;
14fb6c5a
TS		 1330 address_word mem_size;
1331 sim_memopt *entry, *match = NULL;
1332
1333 /* Search for memory region mapped to KSEG0 or KSEG1. */
1334 for (entry = STATE_MEMOPT (sd);
1335 entry != NULL;
1336 entry = entry->next)
1337 {
1338 if ((entry->addr == K0BASE || entry->addr == K1BASE)
1339 && (!match || entry->level < match->level))
1340 match = entry;
1341 else
1342 {
1343 sim_memopt *alias;
1344 for (alias = entry->alias;
1345 alias != NULL;
1346 alias = alias->next)
1347 if ((alias->addr == K0BASE || alias->addr == K1BASE)
1348 && (!match || entry->level < match->level))
1349 match = entry;
1350 }
1351 }
1352
1353 /* Get region size, limit to KSEG1 size (512MB). */
1354 SIM_ASSERT (match != NULL);
1355 mem_size = (match->modulo != 0
1356 ? match->modulo : match->nr_bytes);
1357 if (mem_size > K1SIZE)
1358 mem_size = K1SIZE;
1359
1360 value = mem_size;
c906108c
SS		 1361 H2T (value);
1362 sim_write (sd, A0 + 0, (char *)&value, 4);
1363 sim_write (sd, A0 + 4, (char *)&zero, 4);
1364 sim_write (sd, A0 + 8, (char *)&zero, 4);
5accf1ff 1365 /* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
c906108c
SS		 1366 break;
1367 }
1368
e80fc152 1369 case 158: /* PMON printf */
c906108c
SS		 1370 /* in: A0 = pointer to format string */
1371 /* A1 = optional argument 1 */
1372 /* A2 = optional argument 2 */
1373 /* A3 = optional argument 3 */
1374 /* out: void */
1375 /* The following is based on the PMON printf source */
1376 {
1377 address_word s = A0;
1378 char c;
1379 signed_word *ap = &A1; /* 1st argument */
1380 /* This isn't the quickest way, since we call the host print
1381 routine for every character almost. But it does avoid
1382 having to allocate and manage a temporary string buffer. */
1383 /* TODO: Include check that we only use three arguments (A1,
1384 A2 and A3) */
1385 while (sim_read (sd, s++, &c, 1) && c != '\0')
1386 {
1387 if (c == '%')
1388 {
1389 char tmp[40];
1390 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1391 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1392 while (sim_read (sd, s++, &c, 1) && c != '\0')
1393 {
1394 if (strchr ("dobxXulscefg%", c))
1395 break;
1396 else if (c == '-')
1397 fmt = FMT_LJUST;
1398 else if (c == '0')
1399 fmt = FMT_RJUST0;
1400 else if (c == '~')
1401 fmt = FMT_CENTER;
1402 else if (c == '*')
1403 {
1404 if (haddot)
1405 trunc = (int)*ap++;
1406 else
1407 width = (int)*ap++;
1408 }
1409 else if (c >= '1' && c <= '9')
1410 {
1411 address_word t = s;
1412 unsigned int n;
1413 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1414 tmp[s - t] = c;
1415 tmp[s - t] = '\0';
1416 n = (unsigned int)strtol(tmp,NULL,10);
1417 if (haddot)
1418 trunc = n;
1419 else
1420 width = n;
1421 s--;
1422 }
1423 else if (c == '.')
1424 haddot = 1;
1425 }
1426 switch (c)
1427 {
1428 case '%':
1429 sim_io_printf (sd, "%%");
1430 break;
1431 case 's':
1432 if ((int)*ap != 0)
1433 {
1434 address_word p = *ap++;
1435 char ch;
1436 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1437 sim_io_printf(sd, "%c", ch);
1438 }
1439 else
1440 sim_io_printf(sd,"(null)");
1441 break;
1442 case 'c':
1443 sim_io_printf (sd, "%c", (int)*ap++);
1444 break;
1445 default:
1446 if (c == 'l')
1447 {
1448 sim_read (sd, s++, &c, 1);
1449 if (c == 'l')
1450 {
1451 longlong = 1;
1452 sim_read (sd, s++, &c, 1);
1453 }
1454 }
1455 if (strchr ("dobxXu", c))
1456 {
1457 word64 lv = (word64) *ap++;
1458 if (c == 'b')
1459 sim_io_printf(sd,"<binary not supported>");
1460 else
1461 {
1462 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1463 if (longlong)
1464 sim_io_printf(sd, tmp, lv);
1465 else
1466 sim_io_printf(sd, tmp, (int)lv);
1467 }
1468 }
1469 else if (strchr ("eEfgG", c))
1470 {
1471 double dbl = *(double*)(ap++);
1472 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1473 sim_io_printf (sd, tmp, dbl);
1474 trunc = 0;
1475 }
1476 }
1477 }
1478 else
1479 sim_io_printf(sd, "%c", c);
1480 }
1481 break;
1482 }
1483
1484 default:
8030f857
BE		 1485 /* Unknown reason. */
1486 return 0;
c906108c 1487 }
8030f857 1488 return 1;
c906108c
SS		 1489}
1490
1491/* Store a word into memory. */
1492
1493static void
1494store_word (SIM_DESC sd,
1495 sim_cpu *cpu,
1496 address_word cia,
1497 uword64 vaddr,
1498 signed_word val)
1499{
1500 address_word paddr;
1501 int uncached;
1502
1503 if ((vaddr & 3) != 0)
1504 SignalExceptionAddressStore ();
1505 else
1506 {
1507 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1508 isTARGET, isREAL))
1509 {
1510 const uword64 mask = 7;
1511 uword64 memval;
1512 unsigned int byte;
1513
1514 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1515 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1516 memval = ((uword64) val) << (8 * byte);
1517 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
1518 isREAL);
1519 }
1520 }
1521}
1522
1523/* Load a word from memory. */
1524
1525static signed_word
1526load_word (SIM_DESC sd,
1527 sim_cpu *cpu,
1528 address_word cia,
1529 uword64 vaddr)
1530{
1531 if ((vaddr & 3) != 0)
1532 {
1533 SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
1534 }
1535 else
1536 {
1537 address_word paddr;
1538 int uncached;
1539
1540 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
1541 isTARGET, isREAL))
1542 {
1543 const uword64 mask = 0x7;
1544 const unsigned int reverse = ReverseEndian ? 1 : 0;
1545 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1546 uword64 memval;
1547 unsigned int byte;
1548
1549 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1550 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
1551 isDATA, isREAL);
1552 byte = (vaddr & mask) ^ (bigend << 2);
043b7057 1553 return EXTEND32 (memval >> (8 * byte));
c906108c
SS		 1554 }
1555 }
1556
1557 return 0;
1558}
1559
1560/* Simulate the mips16 entry and exit pseudo-instructions. These
1561 would normally be handled by the reserved instruction exception
1562 code, but for ease of simulation we just handle them directly. */
1563
1564static void
1565mips16_entry (SIM_DESC sd,
1566 sim_cpu *cpu,
1567 address_word cia,
1568 unsigned int insn)
1569{
1570 int aregs, sregs, rreg;
1571
1572#ifdef DEBUG
1573 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1574#endif /* DEBUG */
1575
1576 aregs = (insn & 0x700) >> 8;
1577 sregs = (insn & 0x0c0) >> 6;
1578 rreg = (insn & 0x020) >> 5;
1579
1580 /* This should be checked by the caller. */
1581 if (sregs == 3)
1582 abort ();
1583
1584 if (aregs < 5)
1585 {
1586 int i;
1587 signed_word tsp;
1588
1589 /* This is the entry pseudo-instruction. */
1590
1591 for (i = 0; i < aregs; i++)
1592 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1593
1594 tsp = SP;
1595 SP -= 32;
1596
1597 if (rreg)
1598 {
1599 tsp -= 4;
1600 store_word (SD, CPU, cia, (uword64) tsp, RA);
1601 }
1602
1603 for (i = 0; i < sregs; i++)
1604 {
1605 tsp -= 4;
1606 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1607 }
1608 }
1609 else
1610 {
1611 int i;
1612 signed_word tsp;
1613
1614 /* This is the exit pseudo-instruction. */
1615
1616 tsp = SP + 32;
1617
1618 if (rreg)
1619 {
1620 tsp -= 4;
1621 RA = load_word (SD, CPU, cia, (uword64) tsp);
1622 }
1623
1624 for (i = 0; i < sregs; i++)
1625 {
1626 tsp -= 4;
1627 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1628 }
1629
1630 SP += 32;
1631
1632 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1633 {
1634 if (aregs == 5)
1635 {
1636 FGR[0] = WORD64LO (GPR[4]);
1637 FPR_STATE[0] = fmt_uninterpreted;
1638 }
1639 else if (aregs == 6)
1640 {
1641 FGR[0] = WORD64LO (GPR[5]);
1642 FGR[1] = WORD64LO (GPR[4]);
1643 FPR_STATE[0] = fmt_uninterpreted;
1644 FPR_STATE[1] = fmt_uninterpreted;
1645 }
1646 }
1647
1648 PC = RA;
1649 }
1650
1651}
1652
1653/*-- trace support ----------------------------------------------------------*/
1654
1655/* The TRACE support is provided (if required) in the memory accessing
1656 routines. Since we are also providing the architecture specific
1657 features, the architecture simulation code can also deal with
1658 notifying the TRACE world of cache flushes, etc. Similarly we do
1659 not need to provide profiling support in the simulator engine,
1660 since we can sample in the instruction fetch control loop. By
1661 defining the TRACE manifest, we add tracing as a run-time
1662 option. */
1663
1664#if defined(TRACE)
1665/* Tracing by default produces "din" format (as required by
1666 dineroIII). Each line of such a trace file *MUST* have a din label
1667 and address field. The rest of the line is ignored, so comments can
1668 be included if desired. The first field is the label which must be
1669 one of the following values:
1670
1671 0 read data
1672 1 write data
1673 2 instruction fetch
1674 3 escape record (treated as unknown access type)
1675 4 escape record (causes cache flush)
1676
1677 The address field is a 32bit (lower-case) hexadecimal address
1678 value. The address should *NOT* be preceded by "0x".
1679
1680 The size of the memory transfer is not important when dealing with
1681 cache lines (as long as no more than a cache line can be
1682 transferred in a single operation :-), however more information
1683 could be given following the dineroIII requirement to allow more
1684 complete memory and cache simulators to provide better
1685 results. i.e. the University of Pisa has a cache simulator that can
1686 also take bus size and speed as (variable) inputs to calculate
1687 complete system performance (a much more useful ability when trying
1688 to construct an end product, rather than a processor). They
1689 currently have an ARM version of their tool called ChARM. */
1690
1691
1692void
1693dotrace (SIM_DESC sd,
1694 sim_cpu *cpu,
1695 FILE *tracefh,
1696 int type,
1697 SIM_ADDR address,
1698 int width,
1699 char *comment,...)
1700{
1701 if (STATE & simTRACE) {
1702 va_list ap;
1703 fprintf(tracefh,"%d %s ; width %d ; ",
1704 type,
1705 pr_addr(address),
1706 width);
1707 va_start(ap,comment);
1708 vfprintf(tracefh,comment,ap);
1709 va_end(ap);
1710 fprintf(tracefh,"\n");
1711 }
1712 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1713 we may be generating 64bit ones, we should put the hi-32bits of the
1714 address into the comment field. */
1715
1716 /* TODO: Provide a buffer for the trace lines. We can then avoid
1717 performing writes until the buffer is filled, or the file is
1718 being closed. */
1719
1720 /* NOTE: We could consider adding a comment field to the "din" file
1721 produced using type 3 markers (unknown access). This would then
1722 allow information about the program that the "din" is for, and
1723 the MIPs world that was being simulated, to be placed into the
1724 trace file. */
1725
1726 return;
1727}
1728#endif /* TRACE */
1729
1730/*---------------------------------------------------------------------------*/
1731/*-- simulator engine -------------------------------------------------------*/
1732/*---------------------------------------------------------------------------*/
1733
1734static void
1735ColdReset (SIM_DESC sd)
1736{
1737 int cpu_nr;
1738 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1739 {
1740 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1741 /* RESET: Fixed PC address: */
1742 PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
1743 /* The reset vector address is in the unmapped, uncached memory space. */
1744
1745 SR &= ~(status_SR | status_TS | status_RP);
1746 SR |= (status_ERL | status_BEV);
1747
1748 /* Cheat and allow access to the complete register set immediately */
1749 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1750 && WITH_TARGET_WORD_BITSIZE == 64)
1751 SR |= status_FR; /* 64bit registers */
1752
1753 /* Ensure that any instructions with pending register updates are
1754 cleared: */
1755 PENDING_INVALIDATE();
1756
1757 /* Initialise the FPU registers to the unknown state */
1758 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1759 {
1760 int rn;
1761 for (rn = 0; (rn < 32); rn++)
1762 FPR_STATE[rn] = fmt_uninterpreted;
1763 }
1764
07802d98
TS		 1765 /* Initialise the Config0 register. */
1766 C0_CONFIG = 0x80000000 /* Config1 present */
1767 | 2; /* KSEG0 uncached */
1768 if (WITH_TARGET_WORD_BITSIZE == 64)
1769 {
1770 /* FIXME Currently mips/sim-main.c:address_translation()
1771 truncates all addresses to 32-bits. */
1772 if (0 && WITH_TARGET_ADDRESS_BITSIZE == 64)
1773 C0_CONFIG |= (2 << 13); /* MIPS64, 64-bit addresses */
1774 else
1775 C0_CONFIG |= (1 << 13); /* MIPS64, 32-bit addresses */
1776 }
1777 if (BigEndianMem)
1778 C0_CONFIG |= 0x00008000; /* Big Endian */
c906108c
SS		 1779 }
1780}
1781
1782
1783
1784
1785/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1786/* Signal an exception condition. This will result in an exception
1787 that aborts the instruction. The instruction operation pseudocode
1788 will never see a return from this function call. */
1789
1790void
1791signal_exception (SIM_DESC sd,
1792 sim_cpu *cpu,
1793 address_word cia,
1794 int exception,...)
1795{
1796 /* int vector; */
1797
1798#ifdef DEBUG
1799 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1800#endif /* DEBUG */
1801
1802 /* Ensure that any active atomic read/modify/write operation will fail: */
1803 LLBIT = 0;
1804
1805 /* Save registers before interrupt dispatching */
1806#ifdef SIM_CPU_EXCEPTION_TRIGGER
1807 SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia);
1808#endif
1809
1810 switch (exception) {
1811
e80fc152 1812 case DebugBreakPoint:
c906108c
SS		 1813 if (! (Debug & Debug_DM))
1814 {
1815 if (INDELAYSLOT())
1816 {
1817 CANCELDELAYSLOT();
1818
1819 Debug |= Debug_DBD; /* signaled from within in delay slot */
1820 DEPC = cia - 4; /* reference the branch instruction */
1821 }
1822 else
1823 {
1824 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1825 DEPC = cia;
1826 }
1827
1828 Debug |= Debug_DM; /* in debugging mode */
1829 Debug |= Debug_DBp; /* raising a DBp exception */
1830 PC = 0xBFC00200;
1831 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1832 }
1833 break;
1834
e80fc152 1835 case ReservedInstruction:
c906108c
SS		 1836 {
1837 va_list ap;
1838 unsigned int instruction;
1839 va_start(ap,exception);
1840 instruction = va_arg(ap,unsigned int);
1841 va_end(ap);
1842 /* Provide simple monitor support using ReservedInstruction
1843 exceptions. The following code simulates the fixed vector
1844 entry points into the IDT monitor by causing a simulator
1845 trap, performing the monitor operation, and returning to
1846 the address held in the $ra register (standard PCS return
1847 address). This means we only need to pre-load the vector
1848 space with suitable instruction values. For systems were
1849 actual trap instructions are used, we would not need to
1850 perform this magic. */
1851 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1852 {
8030f857
BE		 1853 int reason = (instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK;
1854 if (!sim_monitor (SD, CPU, cia, reason))
1855 sim_io_error (sd, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason, pr_addr (cia));
1856
c906108c
SS		 1857 /* NOTE: This assumes that a branch-and-link style
1858 instruction was used to enter the vector (which is the
1859 case with the current IDT monitor). */
1860 sim_engine_restart (SD, CPU, NULL, RA);
1861 }
1862 /* Look for the mips16 entry and exit instructions, and
1863 simulate a handler for them. */
1864 else if ((cia & 1) != 0
1865 && (instruction & 0xf81f) == 0xe809
1866 && (instruction & 0x0c0) != 0x0c0)
1867 {
1868 mips16_entry (SD, CPU, cia, instruction);
1869 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1870 }
1871 /* else fall through to normal exception processing */
1872 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
1873 }
1874
1875 default:
1876 /* Store exception code into current exception id variable (used
1877 by exit code): */
1878
1879 /* TODO: If not simulating exceptions then stop the simulator
1880 execution. At the moment we always stop the simulation. */
1881
1882#ifdef SUBTARGET_R3900
1883 /* update interrupt-related registers */
1884
1885 /* insert exception code in bits 6:2 */
1886 CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
1887 /* shift IE/KU history bits left */
1888 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
1889
1890 if (STATE & simDELAYSLOT)
1891 {
1892 STATE &= ~simDELAYSLOT;
1893 CAUSE |= cause_BD;
1894 EPC = (cia - 4); /* reference the branch instruction */
1895 }
1896 else
1897 EPC = cia;
1898
1899 if (SR & status_BEV)
1900 PC = (signed)0xBFC00000 + 0x180;
1901 else
1902 PC = (signed)0x80000000 + 0x080;
1903#else
1904 /* See figure 5-17 for an outline of the code below */
1905 if (! (SR & status_EXL))
1906 {
1907 CAUSE = (exception << 2);
1908 if (STATE & simDELAYSLOT)
1909 {
1910 STATE &= ~simDELAYSLOT;
1911 CAUSE |= cause_BD;
1912 EPC = (cia - 4); /* reference the branch instruction */
1913 }
1914 else
1915 EPC = cia;
1916 /* FIXME: TLB et.al. */
1917 /* vector = 0x180; */
1918 }
1919 else
1920 {
1921 CAUSE = (exception << 2);
1922 /* vector = 0x180; */
1923 }
1924 SR |= status_EXL;
1925 /* Store exception code into current exception id variable (used
1926 by exit code): */
1927
1928 if (SR & status_BEV)
1929 PC = (signed)0xBFC00200 + 0x180;
1930 else
1931 PC = (signed)0x80000000 + 0x180;
1932#endif
1933
1934 switch ((CAUSE >> 2) & 0x1F)
1935 {
1936 case Interrupt:
1937 /* Interrupts arrive during event processing, no need to
1938 restart */
1939 return;
1940
1941 case NMIReset:
1942 /* Ditto */
1943#ifdef SUBTARGET_3900
1944 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1945 PC = (signed)0xBFC00000;
0d3e762b 1946#endif /* SUBTARGET_3900 */
c906108c
SS		 1947 return;
1948
1949 case TLBModification:
1950 case TLBLoad:
1951 case TLBStore:
1952 case AddressLoad:
1953 case AddressStore:
1954 case InstructionFetch:
1955 case DataReference:
1956 /* The following is so that the simulator will continue from the
1957 exception handler address. */
1958 sim_engine_halt (SD, CPU, NULL, PC,
1959 sim_stopped, SIM_SIGBUS);
1960
1961 case ReservedInstruction:
1962 case CoProcessorUnusable:
1963 PC = EPC;
1964 sim_engine_halt (SD, CPU, NULL, PC,
1965 sim_stopped, SIM_SIGILL);
1966
1967 case IntegerOverflow:
1968 case FPE:
1969 sim_engine_halt (SD, CPU, NULL, PC,
1970 sim_stopped, SIM_SIGFPE);
1971
1972 case BreakPoint:
1973 sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
1974 break;
1975
1976 case SystemCall:
1977 case Trap:
1978 sim_engine_restart (SD, CPU, NULL, PC);
1979 break;
1980
1981 case Watch:
1982 PC = EPC;
1983 sim_engine_halt (SD, CPU, NULL, PC,
1984 sim_stopped, SIM_SIGTRAP);
1985
e80fc152 1986 default: /* Unknown internal exception */
c906108c
SS		 1987 PC = EPC;
1988 sim_engine_halt (SD, CPU, NULL, PC,
1989 sim_stopped, SIM_SIGABRT);
1990
1991 }
1992
1993 case SimulatorFault:
1994 {
1995 va_list ap;
1996 char *msg;
1997 va_start(ap,exception);
1998 msg = va_arg(ap,char *);
1999 va_end(ap);
2000 sim_engine_abort (SD, CPU, NULL_CIA,
2001 "FATAL: Simulator error \"%s\"\n",msg);
2002 }
2003 }
2004
2005 return;
2006}
2007
2008
2009
402586aa
CD		 2010/* This function implements what the MIPS32 and MIPS64 ISAs define as
2011 "UNPREDICTABLE" behaviour.
2012
2013 About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
2014 may vary from processor implementation to processor implementation,
2015 instruction to instruction, or as a function of time on the same
2016 implementation or instruction. Software can never depend on results
2017 that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
2018 Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
2019 0.95, page 2.)
2020
2021 For UNPREDICTABLE behaviour, we print a message, if possible print
2022 the offending instructions mips.igen instruction name (provided by
2023 the caller), and stop the simulator.
2024
2025 XXX FIXME: eventually, stopping the simulator should be made conditional
2026 on a command-line option. */
2027void
2028unpredictable_action(sim_cpu *cpu, address_word cia)
c906108c 2029{
402586aa
CD		 2030 SIM_DESC sd = CPU_STATE(cpu);
2031
2032 sim_io_eprintf(sd, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia));
2033 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGABRT);
c906108c 2034}
c906108c 2035
c906108c
SS		 2036
2037/*-- co-processor support routines ------------------------------------------*/
2038
2039static int UNUSED
2040CoProcPresent(unsigned int coproc_number)
2041{
2042 /* Return TRUE if simulator provides a model for the given co-processor number */
2043 return(0);
2044}
2045
2046void
2047cop_lw (SIM_DESC sd,
2048 sim_cpu *cpu,
2049 address_word cia,
2050 int coproc_num,
2051 int coproc_reg,
2052 unsigned int memword)
2053{
2054 switch (coproc_num)
2055 {
2056 case 1:
2057 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2058 {
2059#ifdef DEBUG
2060 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
2061#endif
14fb6c5a 2062 StoreFPR(coproc_reg,fmt_uninterpreted_32,(uword64)memword);
c906108c
SS		 2063 break;
2064 }
2065
2066 default:
2067#if 0 /* this should be controlled by a configuration option */
2068 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
2069#endif
2070 break;
2071 }
2072
2073 return;
2074}
2075
2076void
2077cop_ld (SIM_DESC sd,
2078 sim_cpu *cpu,
2079 address_word cia,
2080 int coproc_num,
2081 int coproc_reg,
2082 uword64 memword)
2083{
2084
2085#ifdef DEBUG
2086 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
2087#endif
2088
2089 switch (coproc_num) {
2090 case 1:
2091 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2092 {
14fb6c5a 2093 StoreFPR(coproc_reg,fmt_uninterpreted_64,memword);
c906108c
SS		 2094 break;
2095 }
2096
2097 default:
2098#if 0 /* this message should be controlled by a configuration option */
2099 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
2100#endif
2101 break;
2102 }
2103
2104 return;
2105}
2106
2107
2108
2109
2110unsigned int
2111cop_sw (SIM_DESC sd,
2112 sim_cpu *cpu,
2113 address_word cia,
2114 int coproc_num,
2115 int coproc_reg)
2116{
2117 unsigned int value = 0;
2118
2119 switch (coproc_num)
2120 {
2121 case 1:
2122 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2123 {
14fb6c5a 2124 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted_32);
c906108c
SS		 2125 break;
2126 }
2127
2128 default:
2129#if 0 /* should be controlled by configuration option */
2130 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2131#endif
2132 break;
2133 }
2134
2135 return(value);
2136}
2137
2138uword64
2139cop_sd (SIM_DESC sd,
2140 sim_cpu *cpu,
2141 address_word cia,
2142 int coproc_num,
2143 int coproc_reg)
2144{
2145 uword64 value = 0;
2146 switch (coproc_num)
2147 {
2148 case 1:
2149 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2150 {
14fb6c5a 2151 value = ValueFPR(coproc_reg,fmt_uninterpreted_64);
c906108c
SS		 2152 break;
2153 }
2154
2155 default:
2156#if 0 /* should be controlled by configuration option */
2157 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2158#endif
2159 break;
2160 }
2161
2162 return(value);
2163}
2164
2165
2166
2167
2168void
2169decode_coproc (SIM_DESC sd,
2170 sim_cpu *cpu,
2171 address_word cia,
2172 unsigned int instruction)
2173{
2174 int coprocnum = ((instruction >> 26) & 3);
2175
2176 switch (coprocnum)
2177 {
2178 case 0: /* standard CPU control and cache registers */
2179 {
2180 int code = ((instruction >> 21) & 0x1F);
2181 int rt = ((instruction >> 16) & 0x1F);
2182 int rd = ((instruction >> 11) & 0x1F);
2183 int tail = instruction & 0x3ff;
2184 /* R4000 Users Manual (second edition) lists the following CP0
2185 instructions:
2186 CODE><-RT><RD-><--TAIL--->
2187 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2188 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2189 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2190 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2191 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2192 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2193 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2194 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2195 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2196 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2197 */
4ce44c66
JM		 2198 if (((code == 0x00) || (code == 0x04) /* MFC0 / MTC0 */
2199 || (code == 0x01) || (code == 0x05)) /* DMFC0 / DMTC0 */
2200 && tail == 0)
c906108c 2201 {
4ce44c66
JM		 2202 /* Clear double/single coprocessor move bit. */
2203 code &= ~1;
2204
2205 /* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */
c906108c
SS		 2206
2207 switch (rd) /* NOTEs: Standard CP0 registers */
2208 {
2209 /* 0 = Index R4000 VR4100 VR4300 */
2210 /* 1 = Random R4000 VR4100 VR4300 */
2211 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2212 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2213 /* 4 = Context R4000 VR4100 VR4300 */
2214 /* 5 = PageMask R4000 VR4100 VR4300 */
2215 /* 6 = Wired R4000 VR4100 VR4300 */
2216 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2217 /* 9 = Count R4000 VR4100 VR4300 */
2218 /* 10 = EntryHi R4000 VR4100 VR4300 */
2219 /* 11 = Compare R4000 VR4100 VR4300 */
2220 /* 12 = SR R4000 VR4100 VR4300 */
2221#ifdef SUBTARGET_R3900
2222 case 3:
2223 /* 3 = Config R3900 */
2224 case 7:
2225 /* 7 = Cache R3900 */
2226 case 15:
2227 /* 15 = PRID R3900 */
2228
2229 /* ignore */
2230 break;
2231
2232 case 8:
2233 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2234 if (code == 0x00)
1a27f959 2235 GPR[rt] = (signed_word) (signed_address) COP0_BADVADDR;
c906108c
SS		 2236 else
2237 COP0_BADVADDR = GPR[rt];
2238 break;
2239
2240#endif /* SUBTARGET_R3900 */
2241 case 12:
2242 if (code == 0x00)
2243 GPR[rt] = SR;
2244 else
2245 SR = GPR[rt];
2246 break;
2247 /* 13 = Cause R4000 VR4100 VR4300 */
2248 case 13:
2249 if (code == 0x00)
2250 GPR[rt] = CAUSE;
2251 else
2252 CAUSE = GPR[rt];
2253 break;
2254 /* 14 = EPC R4000 VR4100 VR4300 */
2255 case 14:
2256 if (code == 0x00)
2257 GPR[rt] = (signed_word) (signed_address) EPC;
2258 else
2259 EPC = GPR[rt];
2260 break;
2261 /* 15 = PRId R4000 VR4100 VR4300 */
2262#ifdef SUBTARGET_R3900
2263 /* 16 = Debug */
2264 case 16:
2265 if (code == 0x00)
2266 GPR[rt] = Debug;
2267 else
2268 Debug = GPR[rt];
2269 break;
2270#else
2271 /* 16 = Config R4000 VR4100 VR4300 */
2272 case 16:
07802d98
TS		 2273 if (code == 0x00)
2274 GPR[rt] = C0_CONFIG;
2275 else
2276 /* only bottom three bits are writable */
2277 C0_CONFIG = (C0_CONFIG & ~0x7) | (GPR[rt] & 0x7);
c906108c
SS		 2278 break;
2279#endif
2280#ifdef SUBTARGET_R3900
2281 /* 17 = Debug */
2282 case 17:
2283 if (code == 0x00)
2284 GPR[rt] = DEPC;
2285 else
2286 DEPC = GPR[rt];
2287 break;
2288#else
2289 /* 17 = LLAddr R4000 VR4100 VR4300 */
2290#endif
2291 /* 18 = WatchLo R4000 VR4100 VR4300 */
2292 /* 19 = WatchHi R4000 VR4100 VR4300 */
2293 /* 20 = XContext R4000 VR4100 VR4300 */
2294 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
2295 /* 27 = CacheErr R4000 VR4100 */
2296 /* 28 = TagLo R4000 VR4100 VR4300 */
2297 /* 29 = TagHi R4000 VR4100 VR4300 */
2298 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
a3027dd7
FCE		 2299 if (STATE_VERBOSE_P(SD))
2300 sim_io_eprintf (SD,
e30db738
AC		 2301 "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
2302 (unsigned long)cia);
c906108c
SS		 2303 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
2304 /* CPR[0,rd] = GPR[rt]; */
2305 default:
2306 if (code == 0x00)
2307 GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
2308 else
2309 COP0_GPR[rd] = GPR[rt];
2310#if 0
2311 if (code == 0x00)
2312 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2313 else
2314 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2315#endif
2316 }
2317 }
07802d98
TS		 2318 else if ((code == 0x00 || code == 0x01)
2319 && rd == 16)
2320 {
2321 /* [D]MFC0 RT,C0_CONFIG,SEL */
2322 signed32 cfg = 0;
2323 switch (tail & 0x07)
2324 {
2325 case 0:
2326 cfg = C0_CONFIG;
2327 break;
2328 case 1:
2329 /* MIPS32 r/o Config1:
2330 Config2 present */
2331 cfg = 0x80000000;
2332 /* MIPS16 implemented.
2333 XXX How to check configuration? */
2334 cfg |= 0x0000004;
2335 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2336 /* MDMX & FPU implemented */
2337 cfg |= 0x00000021;
2338 break;
2339 case 2:
2340 /* MIPS32 r/o Config2:
2341 Config3 present. */
2342 cfg = 0x80000000;
2343 break;
2344 case 3:
2345 /* MIPS32 r/o Config3:
2346 SmartMIPS implemented. */
2347 cfg = 0x00000002;
2348 break;
2349 }
2350 GPR[rt] = cfg;
2351 }
c906108c
SS		 2352 else if (code == 0x10 && (tail & 0x3f) == 0x18)
2353 {
2354 /* ERET */
2355 if (SR & status_ERL)
2356 {
2357 /* Oops, not yet available */
2358 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
2359 PC = EPC;
2360 SR &= ~status_ERL;
2361 }
2362 else
2363 {
2364 PC = EPC;
2365 SR &= ~status_EXL;
2366 }
2367 }
2368 else if (code == 0x10 && (tail & 0x3f) == 0x10)
2369 {
2370 /* RFE */
2371#ifdef SUBTARGET_R3900
2372 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
2373
2374 /* shift IE/KU history bits right */
2375 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
2376
2377 /* TODO: CACHE register */
2378#endif /* SUBTARGET_R3900 */
2379 }
2380 else if (code == 0x10 && (tail & 0x3f) == 0x1F)
2381 {
2382 /* DERET */
2383 Debug &= ~Debug_DM;
2384 DELAYSLOT();
2385 DSPC = DEPC;
2386 }
2387 else
2388 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
2389 /* TODO: When executing an ERET or RFE instruction we should
2390 clear LLBIT, to ensure that any out-standing atomic
2391 read/modify/write sequence fails. */
2392 }
2393 break;
2394
2395 case 2: /* co-processor 2 */
2396 {
2397 int handle = 0;
2398
2399
2400 if(! handle)
2401 {
2402 sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
2403 instruction,pr_addr(cia));
2404 }
2405 }
2406 break;
2407
2408 case 1: /* should not occur (FPU co-processor) */
2409 case 3: /* should not occur (FPU co-processor) */
2410 SignalException(ReservedInstruction,instruction);
2411 break;
2412 }
2413
2414 return;
2415}
2416
2417
2418/* This code copied from gdb's utils.c. Would like to share this code,
2419 but don't know of a common place where both could get to it. */
2420
2421/* Temporary storage using circular buffer */
2422#define NUMCELLS 16
2423#define CELLSIZE 32
2424static char*
2425get_cell (void)
2426{
2427 static char buf[NUMCELLS][CELLSIZE];
2428 static int cell=0;
2429 if (++cell>=NUMCELLS) cell=0;
2430 return buf[cell];
2431}
2432
2433/* Print routines to handle variable size regs, etc */
2434
2435/* Eliminate warning from compiler on 32-bit systems */
2436static int thirty_two = 32;
2437
2438char*
2439pr_addr(addr)
2440 SIM_ADDR addr;
2441{
2442 char *paddr_str=get_cell();
2443 switch (sizeof(addr))
2444 {
2445 case 8:
2446 sprintf(paddr_str,"%08lx%08lx",
2447 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2448 break;
2449 case 4:
2450 sprintf(paddr_str,"%08lx",(unsigned long)addr);
2451 break;
2452 case 2:
2453 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
2454 break;
2455 default:
2456 sprintf(paddr_str,"%x",addr);
2457 }
2458 return paddr_str;
2459}
2460
2461char*
2462pr_uword64(addr)
2463 uword64 addr;
2464{
2465 char *paddr_str=get_cell();
2466 sprintf(paddr_str,"%08lx%08lx",
2467 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2468 return paddr_str;
2469}
2470
2471
2472void
2473mips_core_signal (SIM_DESC sd,
2474 sim_cpu *cpu,
2475 sim_cia cia,
2476 unsigned map,
2477 int nr_bytes,
2478 address_word addr,
2479 transfer_type transfer,
2480 sim_core_signals sig)
2481{
2482 const char *copy = (transfer == read_transfer ? "read" : "write");
2483 address_word ip = CIA_ADDR (cia);
2484
2485 switch (sig)
2486 {
2487 case sim_core_unmapped_signal:
2488 sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
2489 nr_bytes, copy,
2490 (unsigned long) addr, (unsigned long) ip);
2491 COP0_BADVADDR = addr;
2492 SignalExceptionDataReference();
2493 break;
2494
2495 case sim_core_unaligned_signal:
2496 sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
2497 nr_bytes, copy,
2498 (unsigned long) addr, (unsigned long) ip);
2499 COP0_BADVADDR = addr;
2500 if(transfer == read_transfer)
2501 SignalExceptionAddressLoad();
2502 else
2503 SignalExceptionAddressStore();
2504 break;
2505
2506 default:
2507 sim_engine_abort (sd, cpu, cia,
2508 "mips_core_signal - internal error - bad switch");
2509 }
2510}
2511
2512
2513void
2514mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
2515{
2516 ASSERT(cpu != NULL);
2517
2518 if(cpu->exc_suspended > 0)
2519 sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
2520
2521 PC = cia;
2522 memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
2523 cpu->exc_suspended = 0;
2524}
2525
2526void
2527mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
2528{
2529 ASSERT(cpu != NULL);
2530
2531 if(cpu->exc_suspended > 0)
2532 sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
2533 cpu->exc_suspended, exception);
2534
2535 memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
2536 memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
2537 cpu->exc_suspended = exception;
2538}
2539
2540void
2541mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
2542{
2543 ASSERT(cpu != NULL);
2544
2545 if(exception == 0 && cpu->exc_suspended > 0)
2546 {
2547 /* warn not for breakpoints */
2548 if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
2549 sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
2550 cpu->exc_suspended);
2551 }
2552 else if(exception != 0 && cpu->exc_suspended > 0)
2553 {
2554 if(exception != cpu->exc_suspended)
2555 sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
2556 cpu->exc_suspended, exception);
2557
2558 memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
2559 }
2560 else if(exception != 0 && cpu->exc_suspended == 0)
2561 {
2562 sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
2563 }
2564 cpu->exc_suspended = 0;
2565}
2566
2567
2568/*---------------------------------------------------------------------------*/
2569/*> EOF interp.c <*/
GDB Binutils - Deliverables
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