Commit | Line | Data |
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8bae0a0c JSC |
1 | /*> interp.c <*/ |
2 | /* Simulator for the MIPS architecture. | |
3 | ||
4 | This file is part of the MIPS sim | |
5 | ||
6 | THIS SOFTWARE IS NOT COPYRIGHTED | |
7 | ||
8 | Cygnus offers the following for use in the public domain. Cygnus | |
9 | makes no warranty with regard to the software or it's performance | |
10 | and the user accepts the software "AS IS" with all faults. | |
11 | ||
12 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
13 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
14 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
15 | ||
16 | $Revision$ | |
15232df4 | 17 | $Date$ |
8bae0a0c JSC |
18 | |
19 | NOTEs: | |
20 | ||
8bae0a0c JSC |
21 | The IDT monitor (found on the VR4300 board), seems to lie about |
22 | register contents. It seems to treat the registers as sign-extended | |
23 | 32-bit values. This cause *REAL* problems when single-stepping 64-bit | |
24 | code on the hardware. | |
25 | ||
26 | */ | |
27 | ||
e2f8ffb7 AC |
28 | /* The TRACE manifests enable the provision of extra features. If they |
29 | are not defined then a simpler (quicker) simulator is constructed | |
30 | without the required run-time checks, etc. */ | |
8bae0a0c JSC |
31 | #if 1 /* 0 to allow user build selection, 1 to force inclusion */ |
32 | #define TRACE (1) | |
8bae0a0c JSC |
33 | #endif |
34 | ||
2e61a3ad AC |
35 | #include "bfd.h" |
36 | #include "sim-main.h" | |
37 | #include "sim-utils.h" | |
38 | #include "sim-options.h" | |
50a2a691 | 39 | #include "sim-assert.h" |
2e61a3ad | 40 | |
15232df4 FCE |
41 | /* start-sanitize-sky */ |
42 | #ifdef TARGET_SKY | |
43 | #include "sky-vu.h" | |
44 | #include "sky-vpe.h" | |
45 | #include "sky-libvpe.h" | |
46 | #endif | |
47 | /* end-sanitize-sky */ | |
48 | ||
4fa134be ILT |
49 | #include "config.h" |
50 | ||
8bae0a0c JSC |
51 | #include <stdio.h> |
52 | #include <stdarg.h> | |
53 | #include <ansidecl.h> | |
8bae0a0c JSC |
54 | #include <ctype.h> |
55 | #include <limits.h> | |
56 | #include <math.h> | |
4fa134be ILT |
57 | #ifdef HAVE_STDLIB_H |
58 | #include <stdlib.h> | |
59 | #endif | |
60 | #ifdef HAVE_STRING_H | |
61 | #include <string.h> | |
62 | #else | |
63 | #ifdef HAVE_STRINGS_H | |
64 | #include <strings.h> | |
65 | #endif | |
66 | #endif | |
8bae0a0c JSC |
67 | |
68 | #include "getopt.h" | |
69 | #include "libiberty.h" | |
9d52bcb7 | 70 | #include "bfd.h" |
8bae0a0c | 71 | #include "callback.h" /* GDB simulator callback interface */ |
e3d12c65 | 72 | #include "remote-sim.h" /* GDB simulator interface */ |
8bae0a0c | 73 | |
f24b7b69 JSC |
74 | #include "sysdep.h" |
75 | ||
d44859a2 RU |
76 | /* start-sanitize-sky */ |
77 | #ifdef TARGET_SKY | |
78 | #include "sky-vu.h" | |
79 | #endif | |
80 | /* end-sanitize-sky */ | |
81 | ||
53b9417e DE |
82 | #ifndef PARAMS |
83 | #define PARAMS(x) | |
84 | #endif | |
85 | ||
86 | char* pr_addr PARAMS ((SIM_ADDR addr)); | |
87e43259 | 87 | char* pr_uword64 PARAMS ((uword64 addr)); |
53b9417e | 88 | |
f24b7b69 | 89 | |
8bae0a0c | 90 | /* Get the simulator engine description, without including the code: */ |
192ae475 AC |
91 | #if (WITH_IGEN) |
92 | #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3) | |
93 | #else | |
8bae0a0c | 94 | #define SIM_MANIFESTS |
284e759d | 95 | #include "oengine.c" |
8bae0a0c | 96 | #undef SIM_MANIFESTS |
192ae475 | 97 | #endif |
8bae0a0c | 98 | |
01737f42 AC |
99 | /* Within interp.c we refer to the sim_state and sim_cpu directly. */ |
100 | #define SD sd | |
101 | #define CPU cpu | |
102 | ||
f7481d45 | 103 | |
8bae0a0c JSC |
104 | /* The following reserved instruction value is used when a simulator |
105 | trap is required. NOTE: Care must be taken, since this value may be | |
106 | used in later revisions of the MIPS ISA. */ | |
53b9417e DE |
107 | #define RSVD_INSTRUCTION (0x00000005) |
108 | #define RSVD_INSTRUCTION_MASK (0xFC00003F) | |
109 | ||
110 | #define RSVD_INSTRUCTION_ARG_SHIFT 6 | |
111 | #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF | |
112 | ||
8bae0a0c | 113 | |
6eedf3f4 MA |
114 | /* Bits in the Debug register */ |
115 | #define Debug_DBD 0x80000000 /* Debug Branch Delay */ | |
116 | #define Debug_DM 0x40000000 /* Debug Mode */ | |
117 | #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */ | |
118 | ||
119 | ||
120 | ||
8bae0a0c | 121 | |
8bae0a0c | 122 | |
e3d12c65 DE |
123 | /*---------------------------------------------------------------------------*/ |
124 | /*-- GDB simulator interface ------------------------------------------------*/ | |
125 | /*---------------------------------------------------------------------------*/ | |
126 | ||
0c2c5f61 | 127 | static void ColdReset PARAMS((SIM_DESC sd)); |
e3d12c65 DE |
128 | |
129 | /*---------------------------------------------------------------------------*/ | |
130 | ||
8bae0a0c | 131 | |
8bae0a0c | 132 | |
8bae0a0c | 133 | #define DELAYSLOT() {\ |
0c2c5f61 | 134 | if (STATE & simDELAYSLOT)\ |
18c64df6 | 135 | sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\ |
0c2c5f61 | 136 | STATE |= simDELAYSLOT;\ |
8bae0a0c JSC |
137 | } |
138 | ||
aaff8437 ILT |
139 | #define JALDELAYSLOT() {\ |
140 | DELAYSLOT ();\ | |
0c2c5f61 | 141 | STATE |= simJALDELAYSLOT;\ |
aaff8437 ILT |
142 | } |
143 | ||
8bae0a0c | 144 | #define NULLIFY() {\ |
0c2c5f61 AC |
145 | STATE &= ~simDELAYSLOT;\ |
146 | STATE |= simSKIPNEXT;\ | |
8bae0a0c JSC |
147 | } |
148 | ||
6eedf3f4 | 149 | #define CANCELDELAYSLOT() {\ |
0c2c5f61 AC |
150 | DSSTATE = 0;\ |
151 | STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\ | |
6eedf3f4 MA |
152 | } |
153 | ||
0c2c5f61 AC |
154 | #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0) |
155 | #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0) | |
aaff8437 | 156 | |
a9f7253f JSC |
157 | #define K0BASE (0x80000000) |
158 | #define K0SIZE (0x20000000) | |
159 | #define K1BASE (0xA0000000) | |
160 | #define K1SIZE (0x20000000) | |
525d929e AC |
161 | #define MONITOR_BASE (0xBFC00000) |
162 | #define MONITOR_SIZE (1 << 11) | |
163 | #define MEM_SIZE (2 << 20) | |
15232df4 | 164 | |
82ea14fd AC |
165 | /* start-sanitize-sky */ |
166 | #ifdef TARGET_SKY | |
167 | #undef MEM_SIZE | |
168 | #define MEM_SIZE (16 << 20) /* 16 MB */ | |
169 | #endif | |
170 | /* end-sanitize-sky */ | |
a9f7253f | 171 | |
8bae0a0c | 172 | #if defined(TRACE) |
4fa134be | 173 | static char *tracefile = "trace.din"; /* default filename for trace log */ |
030843d7 | 174 | FILE *tracefh = NULL; |
18c64df6 | 175 | static void open_trace PARAMS((SIM_DESC sd)); |
8bae0a0c JSC |
176 | #endif /* TRACE */ |
177 | ||
7c5d88c1 DE |
178 | static DECLARE_OPTION_HANDLER (mips_option_handler); |
179 | ||
22de994d AC |
180 | #define OPTION_DINERO_TRACE 200 |
181 | #define OPTION_DINERO_FILE 201 | |
182 | ||
50a2a691 | 183 | static SIM_RC |
7c5d88c1 | 184 | mips_option_handler (sd, cpu, opt, arg, is_command) |
50a2a691 | 185 | SIM_DESC sd; |
7c5d88c1 | 186 | sim_cpu *cpu; |
50a2a691 AC |
187 | int opt; |
188 | char *arg; | |
7c5d88c1 | 189 | int is_command; |
2e61a3ad | 190 | { |
01737f42 | 191 | int cpu_nr; |
50a2a691 AC |
192 | switch (opt) |
193 | { | |
22de994d | 194 | case OPTION_DINERO_TRACE: /* ??? */ |
50a2a691 AC |
195 | #if defined(TRACE) |
196 | /* Eventually the simTRACE flag could be treated as a toggle, to | |
197 | allow external control of the program points being traced | |
198 | (i.e. only from main onwards, excluding the run-time setup, | |
199 | etc.). */ | |
82ea14fd | 200 | for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++) |
50a2a691 | 201 | { |
01737f42 AC |
202 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); |
203 | if (arg == NULL) | |
204 | STATE |= simTRACE; | |
205 | else if (strcmp (arg, "yes") == 0) | |
206 | STATE |= simTRACE; | |
207 | else if (strcmp (arg, "no") == 0) | |
208 | STATE &= ~simTRACE; | |
209 | else if (strcmp (arg, "on") == 0) | |
210 | STATE |= simTRACE; | |
211 | else if (strcmp (arg, "off") == 0) | |
212 | STATE &= ~simTRACE; | |
213 | else | |
214 | { | |
215 | fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg); | |
216 | return SIM_RC_FAIL; | |
217 | } | |
50a2a691 AC |
218 | } |
219 | return SIM_RC_OK; | |
220 | #else /* !TRACE */ | |
221 | fprintf(stderr,"\ | |
22de994d | 222 | Simulator constructed without dinero tracing support (for performance).\n\ |
50a2a691 AC |
223 | Re-compile simulator with \"-DTRACE\" to enable this option.\n"); |
224 | return SIM_RC_FAIL; | |
225 | #endif /* !TRACE */ | |
226 | ||
22de994d | 227 | case OPTION_DINERO_FILE: |
50a2a691 AC |
228 | #if defined(TRACE) |
229 | if (optarg != NULL) { | |
230 | char *tmp; | |
231 | tmp = (char *)malloc(strlen(optarg) + 1); | |
232 | if (tmp == NULL) | |
233 | { | |
18c64df6 | 234 | sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg); |
50a2a691 AC |
235 | return SIM_RC_FAIL; |
236 | } | |
237 | else { | |
238 | strcpy(tmp,optarg); | |
239 | tracefile = tmp; | |
18c64df6 | 240 | sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile); |
50a2a691 AC |
241 | } |
242 | } | |
243 | #endif /* TRACE */ | |
244 | return SIM_RC_OK; | |
245 | ||
50a2a691 AC |
246 | } |
247 | ||
248 | return SIM_RC_OK; | |
2e61a3ad | 249 | } |
50a2a691 AC |
250 | |
251 | static const OPTION mips_options[] = | |
2e61a3ad | 252 | { |
22de994d AC |
253 | { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE}, |
254 | '\0', "on|off", "Enable dinero tracing", | |
50a2a691 | 255 | mips_option_handler }, |
22de994d AC |
256 | { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE}, |
257 | '\0', "FILE", "Write dinero trace to FILE", | |
50a2a691 | 258 | mips_option_handler }, |
50a2a691 AC |
259 | { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } |
260 | }; | |
261 | ||
262 | ||
56e7c849 AC |
263 | int interrupt_pending; |
264 | ||
50a2a691 AC |
265 | static void |
266 | interrupt_event (SIM_DESC sd, void *data) | |
2e61a3ad | 267 | { |
01737f42 | 268 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
56e7c849 AC |
269 | if (SR & status_IE) |
270 | { | |
271 | interrupt_pending = 0; | |
18c64df6 | 272 | SignalExceptionInterrupt (); |
56e7c849 AC |
273 | } |
274 | else if (!interrupt_pending) | |
275 | sim_events_schedule (sd, 1, interrupt_event, data); | |
2e61a3ad | 276 | } |
f7481d45 | 277 | |
f7481d45 | 278 | |
2c88fae9 IC |
279 | /*---------------------------------------------------------------------------*/ |
280 | /*-- Device registration hook -----------------------------------------------*/ | |
281 | /*---------------------------------------------------------------------------*/ | |
97908603 | 282 | static void device_init(SIM_DESC sd) { |
2c88fae9 IC |
283 | #ifdef DEVICE_INIT |
284 | extern void register_devices(SIM_DESC); | |
285 | register_devices(sd); | |
286 | #endif | |
287 | } | |
50a2a691 | 288 | |
97908603 | 289 | /* start-sanitize-sky */ |
7aa6042f | 290 | #ifdef TARGET_SKY |
97908603 | 291 | static struct { |
a859684b RU |
292 | short i[NUM_VU_INTEGER_REGS]; |
293 | int f[NUM_VU_REGS - NUM_VU_INTEGER_REGS]; | |
97908603 | 294 | } vu_regs[2]; |
7aa6042f | 295 | #endif |
97908603 RU |
296 | /* end-sanitize-sky */ |
297 | ||
8bae0a0c JSC |
298 | /*---------------------------------------------------------------------------*/ |
299 | /*-- GDB simulator interface ------------------------------------------------*/ | |
300 | /*---------------------------------------------------------------------------*/ | |
301 | ||
53b9417e | 302 | SIM_DESC |
247fccde | 303 | sim_open (kind, cb, abfd, argv) |
87e43259 | 304 | SIM_OPEN_KIND kind; |
50a2a691 | 305 | host_callback *cb; |
247fccde | 306 | struct _bfd *abfd; |
53b9417e | 307 | char **argv; |
8bae0a0c | 308 | { |
18c64df6 | 309 | SIM_DESC sd = sim_state_alloc (kind, cb); |
01737f42 | 310 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
2e61a3ad | 311 | |
525d929e AC |
312 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
313 | ||
50a2a691 AC |
314 | /* FIXME: watchpoints code shouldn't need this */ |
315 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
316 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
317 | STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event; | |
318 | ||
0c2c5f61 | 319 | STATE = 0; |
50a2a691 | 320 | |
2e61a3ad AC |
321 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
322 | return 0; | |
7c5d88c1 | 323 | sim_add_option_table (sd, NULL, mips_options); |
2e61a3ad | 324 | |
63be8feb AC |
325 | /* Allocate core managed memory */ |
326 | ||
327 | /* the monitor */ | |
328 | sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE); | |
329 | /* For compatibility with the old code - under this (at level one) | |
330 | are the kernel spaces K0 & K1. Both of these map to a single | |
331 | smaller sub region */ | |
a48e8c8d | 332 | sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */ |
fd909089 FCE |
333 | /* start-sanitize-sky */ |
334 | #ifndef TARGET_SKY | |
335 | /* end-sanitize-sky */ | |
63be8feb AC |
336 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x", |
337 | K1BASE, K0SIZE, | |
338 | MEM_SIZE, /* actual size */ | |
339 | K0BASE); | |
fd909089 FCE |
340 | /* start-sanitize-sky */ |
341 | #else | |
342 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x", | |
343 | K1BASE, K0SIZE, | |
344 | MEM_SIZE, /* actual size */ | |
345 | K0BASE, | |
346 | 0); /* add alias at 0x0000 */ | |
9ce23bf9 | 347 | #endif |
fd909089 | 348 | /* end-sanitize-sky */ |
63be8feb | 349 | |
2c88fae9 IC |
350 | device_init(sd); |
351 | ||
2e61a3ad AC |
352 | /* getopt will print the error message so we just have to exit if this fails. |
353 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
354 | print_filtered. */ | |
355 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
356 | { | |
357 | /* Uninstall the modules to avoid memory leaks, | |
358 | file descriptor leaks, etc. */ | |
359 | sim_module_uninstall (sd); | |
360 | return 0; | |
361 | } | |
2e61a3ad | 362 | |
fafce69a AC |
363 | /* check for/establish the a reference program image */ |
364 | if (sim_analyze_program (sd, | |
365 | (STATE_PROG_ARGV (sd) != NULL | |
366 | ? *STATE_PROG_ARGV (sd) | |
367 | : NULL), | |
368 | abfd) != SIM_RC_OK) | |
369 | { | |
370 | sim_module_uninstall (sd); | |
371 | return 0; | |
372 | } | |
373 | ||
247fccde AC |
374 | /* Configure/verify the target byte order and other runtime |
375 | configuration options */ | |
fafce69a | 376 | if (sim_config (sd) != SIM_RC_OK) |
247fccde AC |
377 | { |
378 | sim_module_uninstall (sd); | |
379 | return 0; | |
380 | } | |
381 | ||
2e61a3ad AC |
382 | if (sim_post_argv_init (sd) != SIM_RC_OK) |
383 | { | |
384 | /* Uninstall the modules to avoid memory leaks, | |
385 | file descriptor leaks, etc. */ | |
386 | sim_module_uninstall (sd); | |
387 | return 0; | |
388 | } | |
389 | ||
50a2a691 AC |
390 | /* verify assumptions the simulator made about the host type system. |
391 | This macro does not return if there is a problem */ | |
7ce8b917 AC |
392 | SIM_ASSERT (sizeof(int) == (4 * sizeof(char))); |
393 | SIM_ASSERT (sizeof(word64) == (8 * sizeof(char))); | |
8bae0a0c | 394 | |
8bae0a0c JSC |
395 | /* This is NASTY, in that we are assuming the size of specific |
396 | registers: */ | |
397 | { | |
398 | int rn; | |
a97f304b AC |
399 | for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) |
400 | { | |
401 | if (rn < 32) | |
402 | cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; | |
403 | else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR))) | |
404 | cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE; | |
405 | else if ((rn >= 33) && (rn <= 37)) | |
406 | cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; | |
a48e8c8d AC |
407 | else if ((rn == SRIDX) |
408 | || (rn == FCR0IDX) | |
409 | || (rn == FCR31IDX) | |
410 | || ((rn >= 72) && (rn <= 89))) | |
a97f304b AC |
411 | cpu->register_widths[rn] = 32; |
412 | else | |
413 | cpu->register_widths[rn] = 0; | |
414 | } | |
18c64df6 AC |
415 | /* start-sanitize-r5900 */ |
416 | ||
417 | /* set the 5900 "upper" registers to 64 bits */ | |
418 | for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++) | |
0c2c5f61 | 419 | cpu->register_widths[rn] = 64; |
18c64df6 | 420 | /* end-sanitize-r5900 */ |
97908603 RU |
421 | |
422 | /* start-sanitize-sky */ | |
423 | #ifdef TARGET_SKY | |
424 | /* Now the VU registers */ | |
a859684b | 425 | for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) { |
97908603 RU |
426 | cpu->register_widths[rn + NUM_R5900_REGS] = 16; |
427 | cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16; | |
428 | ||
429 | /* Hack for now - to test gdb interface */ | |
430 | vu_regs[0].i[rn] = rn + 0x100; | |
431 | vu_regs[1].i[rn] = rn + 0x200; | |
432 | } | |
433 | ||
a859684b | 434 | for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) { |
97908603 | 435 | float f; |
a859684b | 436 | int first_vec_reg = NUM_VU_INTEGER_REGS + 8; |
97908603 RU |
437 | |
438 | cpu->register_widths[rn + NUM_R5900_REGS] = 32; | |
439 | cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32; | |
440 | ||
441 | /* Hack for now - to test gdb interface */ | |
a859684b RU |
442 | if( rn < first_vec_reg ) { |
443 | f = rn - NUM_VU_INTEGER_REGS + 100.0; | |
444 | vu_regs[0].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f); | |
445 | f = rn - NUM_VU_INTEGER_REGS + 200.0; | |
446 | vu_regs[1].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f); | |
97908603 RU |
447 | } |
448 | else { | |
a859684b RU |
449 | f = (rn - first_vec_reg)/4 + (rn - first_vec_reg)%4 + 1000.0; |
450 | vu_regs[0].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f); | |
451 | f = (rn - first_vec_reg)/4 + (rn - first_vec_reg)%4 + 2000.0; | |
452 | vu_regs[1].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f); | |
97908603 RU |
453 | } |
454 | } | |
455 | #endif | |
456 | /* end-sanitize-sky */ | |
8bae0a0c JSC |
457 | } |
458 | ||
8bae0a0c | 459 | #if defined(TRACE) |
0c2c5f61 | 460 | if (STATE & simTRACE) |
18c64df6 | 461 | open_trace(sd); |
8bae0a0c JSC |
462 | #endif /* TRACE */ |
463 | ||
fafce69a AC |
464 | /* Write the monitor trap address handlers into the monitor (eeprom) |
465 | address space. This can only be done once the target endianness | |
466 | has been determined. */ | |
467 | { | |
468 | unsigned loop; | |
469 | /* Entry into the IDT monitor is via fixed address vectors, and | |
470 | not using machine instructions. To avoid clashing with use of | |
471 | the MIPS TRAP system, we place our own (simulator specific) | |
472 | "undefined" instructions into the relevant vector slots. */ | |
525d929e AC |
473 | for (loop = 0; (loop < MONITOR_SIZE); loop += 4) |
474 | { | |
475 | address_word vaddr = (MONITOR_BASE + loop); | |
476 | unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT)); | |
477 | H2T (insn); | |
478 | sim_write (sd, vaddr, (char *)&insn, sizeof (insn)); | |
479 | } | |
fafce69a AC |
480 | /* The PMON monitor uses the same address space, but rather than |
481 | branching into it the address of a routine is loaded. We can | |
482 | cheat for the moment, and direct the PMON routine to IDT style | |
483 | instructions within the monitor space. This relies on the IDT | |
484 | monitor not using the locations from 0xBFC00500 onwards as its | |
485 | entry points.*/ | |
486 | for (loop = 0; (loop < 24); loop++) | |
487 | { | |
525d929e AC |
488 | address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4)); |
489 | unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ | |
fafce69a AC |
490 | switch (loop) |
491 | { | |
492 | case 0: /* read */ | |
493 | value = 7; | |
494 | break; | |
fafce69a AC |
495 | case 1: /* write */ |
496 | value = 8; | |
497 | break; | |
fafce69a AC |
498 | case 2: /* open */ |
499 | value = 6; | |
500 | break; | |
fafce69a AC |
501 | case 3: /* close */ |
502 | value = 10; | |
503 | break; | |
fafce69a AC |
504 | case 5: /* printf */ |
505 | value = ((0x500 - 16) / 8); /* not an IDT reason code */ | |
506 | break; | |
fafce69a AC |
507 | case 8: /* cliexit */ |
508 | value = 17; | |
509 | break; | |
fafce69a AC |
510 | case 11: /* flush_cache */ |
511 | value = 28; | |
512 | break; | |
513 | } | |
525d929e AC |
514 | /* FIXME - should monitor_base be SIM_ADDR?? */ |
515 | value = ((unsigned int)MONITOR_BASE + (value * 8)); | |
516 | H2T (value); | |
517 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); | |
fafce69a AC |
518 | |
519 | /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */ | |
520 | vaddr -= 0x300; | |
525d929e | 521 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); |
fafce69a AC |
522 | } |
523 | } | |
524 | ||
2e61a3ad | 525 | return sd; |
8bae0a0c JSC |
526 | } |
527 | ||
6429b296 JW |
528 | #if defined(TRACE) |
529 | static void | |
18c64df6 AC |
530 | open_trace(sd) |
531 | SIM_DESC sd; | |
6429b296 JW |
532 | { |
533 | tracefh = fopen(tracefile,"wb+"); | |
534 | if (tracefh == NULL) | |
535 | { | |
18c64df6 | 536 | sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile); |
6429b296 JW |
537 | tracefh = stderr; |
538 | } | |
539 | } | |
540 | #endif /* TRACE */ | |
541 | ||
8bae0a0c | 542 | void |
53b9417e DE |
543 | sim_close (sd, quitting) |
544 | SIM_DESC sd; | |
8bae0a0c JSC |
545 | int quitting; |
546 | { | |
547 | #ifdef DEBUG | |
548 | printf("DBG: sim_close: entered (quitting = %d)\n",quitting); | |
549 | #endif | |
550 | ||
8bae0a0c JSC |
551 | /* "quitting" is non-zero if we cannot hang on errors */ |
552 | ||
553 | /* Ensure that any resources allocated through the callback | |
554 | mechanism are released: */ | |
18c64df6 | 555 | sim_io_shutdown (sd); |
8bae0a0c | 556 | |
8bae0a0c | 557 | #if defined(TRACE) |
e3d12c65 | 558 | if (tracefh != NULL && tracefh != stderr) |
8bae0a0c | 559 | fclose(tracefh); |
e3d12c65 | 560 | tracefh = NULL; |
8bae0a0c JSC |
561 | #endif /* TRACE */ |
562 | ||
01737f42 AC |
563 | /* FIXME - free SD */ |
564 | ||
8bae0a0c JSC |
565 | return; |
566 | } | |
567 | ||
8bae0a0c JSC |
568 | |
569 | int | |
53b9417e DE |
570 | sim_write (sd,addr,buffer,size) |
571 | SIM_DESC sd; | |
8bae0a0c JSC |
572 | SIM_ADDR addr; |
573 | unsigned char *buffer; | |
574 | int size; | |
575 | { | |
525d929e | 576 | int index; |
01737f42 | 577 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
8bae0a0c JSC |
578 | |
579 | /* Return the number of bytes written, or zero if error. */ | |
580 | #ifdef DEBUG | |
18c64df6 | 581 | sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
582 | #endif |
583 | ||
525d929e AC |
584 | /* We use raw read and write routines, since we do not want to count |
585 | the GDB memory accesses in our statistics gathering. */ | |
586 | ||
587 | for (index = 0; index < size; index++) | |
588 | { | |
589 | address_word vaddr = (address_word)addr + index; | |
590 | address_word paddr; | |
591 | int cca; | |
01737f42 | 592 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW)) |
525d929e | 593 | break; |
82ea14fd | 594 | if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1) |
63be8feb | 595 | break; |
8bae0a0c | 596 | } |
8bae0a0c | 597 | |
525d929e | 598 | return(index); |
8bae0a0c JSC |
599 | } |
600 | ||
601 | int | |
53b9417e DE |
602 | sim_read (sd,addr,buffer,size) |
603 | SIM_DESC sd; | |
8bae0a0c JSC |
604 | SIM_ADDR addr; |
605 | unsigned char *buffer; | |
606 | int size; | |
607 | { | |
608 | int index; | |
01737f42 | 609 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
8bae0a0c JSC |
610 | |
611 | /* Return the number of bytes read, or zero if error. */ | |
612 | #ifdef DEBUG | |
18c64df6 | 613 | sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
614 | #endif /* DEBUG */ |
615 | ||
525d929e AC |
616 | for (index = 0; (index < size); index++) |
617 | { | |
618 | address_word vaddr = (address_word)addr + index; | |
619 | address_word paddr; | |
525d929e | 620 | int cca; |
01737f42 | 621 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW)) |
525d929e | 622 | break; |
82ea14fd | 623 | if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1) |
63be8feb | 624 | break; |
525d929e | 625 | } |
8bae0a0c JSC |
626 | |
627 | return(index); | |
628 | } | |
629 | ||
f319bab2 GRK |
630 | int |
631 | sim_store_register (sd,rn,memory,length) | |
53b9417e | 632 | SIM_DESC sd; |
8bae0a0c JSC |
633 | int rn; |
634 | unsigned char *memory; | |
f319bab2 | 635 | int length; |
8bae0a0c | 636 | { |
01737f42 | 637 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
50a2a691 AC |
638 | /* NOTE: gdb (the client) stores registers in target byte order |
639 | while the simulator uses host byte order */ | |
8bae0a0c | 640 | #ifdef DEBUG |
18c64df6 | 641 | sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory))); |
8bae0a0c JSC |
642 | #endif /* DEBUG */ |
643 | ||
644 | /* Unfortunately this suffers from the same problem as the register | |
645 | numbering one. We need to know what the width of each logical | |
646 | register number is for the architecture being simulated. */ | |
50a2a691 | 647 | |
0c2c5f61 | 648 | if (cpu->register_widths[rn] == 0) |
a48e8c8d AC |
649 | { |
650 | sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn); | |
651 | return 0; | |
652 | } | |
653 | ||
654 | /* start-sanitize-r5900 */ | |
655 | if (rn >= 90 && rn < 90 + 32) | |
656 | { | |
657 | GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory); | |
658 | return 8; | |
659 | } | |
660 | switch (rn) | |
661 | { | |
662 | case REGISTER_SA: | |
663 | SA = T2H_8(*(unsigned64*)memory); | |
664 | return 8; | |
665 | case 122: /* FIXME */ | |
666 | LO1 = T2H_8(*(unsigned64*)memory); | |
667 | return 8; | |
668 | case 123: /* FIXME */ | |
669 | HI1 = T2H_8(*(unsigned64*)memory); | |
670 | return 8; | |
671 | } | |
a48e8c8d | 672 | /* end-sanitize-r5900 */ |
ce4713dc | 673 | |
97908603 RU |
674 | /* start-sanitize-sky */ |
675 | #ifdef TARGET_SKY | |
a859684b | 676 | if (rn >= NUM_R5900_REGS) |
ce4713dc | 677 | { |
a859684b RU |
678 | int size = 4; /* Default register size */ |
679 | ||
ce4713dc | 680 | rn = rn - NUM_R5900_REGS; |
97908603 | 681 | |
a859684b | 682 | if (rn < NUM_VU_INTEGER_REGS) |
15232df4 | 683 | size = write_vu_int_reg (& vu0_device.state->regs, rn, memory); |
97908603 | 684 | else if( rn < NUM_VU_REGS ) |
a859684b RU |
685 | vu_regs[0].f[rn - NUM_VU_INTEGER_REGS] |
686 | = T2H_4( *(unsigned int *) memory ); | |
ce4713dc RU |
687 | else { |
688 | rn = rn - NUM_VU_REGS; | |
689 | ||
a859684b | 690 | if( rn < NUM_VU_INTEGER_REGS ) |
15232df4 | 691 | size = write_vu_int_reg (& vu1_device.state->regs, rn, memory); |
ce4713dc | 692 | else if( rn < NUM_VU_REGS ) |
a859684b RU |
693 | vu_regs[1].f[rn - NUM_VU_INTEGER_REGS] |
694 | = T2H_4( *(unsigned int *) memory ); | |
ce4713dc RU |
695 | else |
696 | sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" ); | |
697 | } | |
a859684b RU |
698 | |
699 | return size; | |
97908603 | 700 | } |
97908603 RU |
701 | #endif |
702 | /* end-sanitize-sky */ | |
a48e8c8d AC |
703 | |
704 | if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) | |
a97f304b AC |
705 | { |
706 | if (cpu->register_widths[rn] == 32) | |
a48e8c8d AC |
707 | { |
708 | cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory); | |
709 | return 4; | |
710 | } | |
a97f304b | 711 | else |
a48e8c8d AC |
712 | { |
713 | cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory); | |
714 | return 8; | |
715 | } | |
a97f304b | 716 | } |
8bae0a0c | 717 | |
a48e8c8d AC |
718 | if (cpu->register_widths[rn] == 32) |
719 | { | |
720 | cpu->registers[rn] = T2H_4 (*(unsigned32*)memory); | |
721 | return 4; | |
722 | } | |
723 | else | |
724 | { | |
725 | cpu->registers[rn] = T2H_8 (*(unsigned64*)memory); | |
726 | return 8; | |
727 | } | |
8bae0a0c JSC |
728 | } |
729 | ||
f319bab2 GRK |
730 | int |
731 | sim_fetch_register (sd,rn,memory,length) | |
53b9417e | 732 | SIM_DESC sd; |
8bae0a0c JSC |
733 | int rn; |
734 | unsigned char *memory; | |
f319bab2 | 735 | int length; |
8bae0a0c | 736 | { |
01737f42 | 737 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
50a2a691 AC |
738 | /* NOTE: gdb (the client) stores registers in target byte order |
739 | while the simulator uses host byte order */ | |
8bae0a0c | 740 | #ifdef DEBUG |
18c64df6 | 741 | sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn])); |
8bae0a0c JSC |
742 | #endif /* DEBUG */ |
743 | ||
0c2c5f61 | 744 | if (cpu->register_widths[rn] == 0) |
a48e8c8d AC |
745 | { |
746 | sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn); | |
747 | return 0; | |
748 | } | |
749 | ||
750 | /* start-sanitize-r5900 */ | |
751 | if (rn >= 90 && rn < 90 + 32) | |
752 | { | |
753 | *(unsigned64*)memory = GPR1[rn - 90]; | |
754 | return 8; | |
755 | } | |
756 | switch (rn) | |
757 | { | |
758 | case REGISTER_SA: | |
759 | *((unsigned64*)memory) = H2T_8(SA); | |
760 | return 8; | |
761 | case 122: /* FIXME */ | |
762 | *((unsigned64*)memory) = H2T_8(LO1); | |
763 | return 8; | |
764 | case 123: /* FIXME */ | |
765 | *((unsigned64*)memory) = H2T_8(HI1); | |
766 | return 8; | |
767 | } | |
a48e8c8d | 768 | /* end-sanitize-r5900 */ |
ce4713dc | 769 | |
97908603 RU |
770 | /* start-sanitize-sky */ |
771 | #ifdef TARGET_SKY | |
a859684b | 772 | if (rn >= NUM_R5900_REGS) |
ce4713dc | 773 | { |
a859684b RU |
774 | int size = 4; /* default register width */ |
775 | ||
ce4713dc | 776 | rn = rn - NUM_R5900_REGS; |
97908603 | 777 | |
a859684b | 778 | if (rn < NUM_VU_INTEGER_REGS) |
15232df4 | 779 | size = read_vu_int_reg (& vu0_device.state->regs, rn, memory); |
a859684b RU |
780 | else if (rn < NUM_VU_REGS) |
781 | *((unsigned int *) memory) | |
782 | = H2T_4( vu_regs[0].f[rn - NUM_VU_INTEGER_REGS] ); | |
783 | else | |
784 | { | |
785 | rn = rn - NUM_VU_REGS; | |
ce4713dc | 786 | |
a859684b | 787 | if (rn < NUM_VU_INTEGER_REGS) |
15232df4 | 788 | size = read_vu_int_reg (& vu1_device.state->regs, rn, memory); |
a859684b RU |
789 | else if (rn < NUM_VU_REGS) |
790 | (*(unsigned int *) memory) | |
791 | = H2T_4( vu_regs[1].f[rn - NUM_VU_INTEGER_REGS] ); | |
792 | else | |
793 | sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" ); | |
794 | } | |
795 | ||
796 | return size; | |
97908603 | 797 | } |
97908603 RU |
798 | #endif |
799 | /* end-sanitize-sky */ | |
a48e8c8d AC |
800 | |
801 | /* Any floating point register */ | |
802 | if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) | |
a97f304b AC |
803 | { |
804 | if (cpu->register_widths[rn] == 32) | |
a48e8c8d AC |
805 | { |
806 | *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]); | |
807 | return 4; | |
808 | } | |
a97f304b | 809 | else |
a48e8c8d AC |
810 | { |
811 | *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]); | |
812 | return 8; | |
813 | } | |
a97f304b | 814 | } |
50a2a691 | 815 | |
a48e8c8d AC |
816 | if (cpu->register_widths[rn] == 32) |
817 | { | |
818 | *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn])); | |
819 | return 4; | |
820 | } | |
821 | else | |
822 | { | |
823 | *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn])); | |
824 | return 8; | |
825 | } | |
8bae0a0c | 826 | } |
50a2a691 | 827 | |
8bae0a0c | 828 | |
9d52bcb7 | 829 | SIM_RC |
fafce69a | 830 | sim_create_inferior (sd, abfd, argv,env) |
53b9417e | 831 | SIM_DESC sd; |
fafce69a | 832 | struct _bfd *abfd; |
8bae0a0c JSC |
833 | char **argv; |
834 | char **env; | |
835 | { | |
50a2a691 | 836 | |
8bae0a0c | 837 | #ifdef DEBUG |
9d52bcb7 DE |
838 | printf("DBG: sim_create_inferior entered: start_address = 0x%s\n", |
839 | pr_addr(PC)); | |
8bae0a0c JSC |
840 | #endif /* DEBUG */ |
841 | ||
0c2c5f61 | 842 | ColdReset(sd); |
50a2a691 | 843 | |
fafce69a | 844 | if (abfd != NULL) |
01737f42 AC |
845 | { |
846 | /* override PC value set by ColdReset () */ | |
847 | int cpu_nr; | |
848 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
849 | { | |
850 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); | |
851 | CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd)); | |
852 | } | |
853 | } | |
2e61a3ad | 854 | |
f24b7b69 | 855 | #if 0 /* def DEBUG */ |
dad6f1f3 | 856 | if (argv || env) |
8bae0a0c | 857 | { |
dad6f1f3 AC |
858 | /* We should really place the argv slot values into the argument |
859 | registers, and onto the stack as required. However, this | |
860 | assumes that we have a stack defined, which is not | |
861 | necessarily true at the moment. */ | |
862 | char **cptr; | |
863 | sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n"); | |
864 | for (cptr = argv; (cptr && *cptr); cptr++) | |
865 | printf("DBG: arg \"%s\"\n",*cptr); | |
8bae0a0c JSC |
866 | } |
867 | #endif /* DEBUG */ | |
8bae0a0c | 868 | |
9d52bcb7 | 869 | return SIM_RC_OK; |
8bae0a0c JSC |
870 | } |
871 | ||
8bae0a0c | 872 | void |
53b9417e DE |
873 | sim_do_command (sd,cmd) |
874 | SIM_DESC sd; | |
8bae0a0c JSC |
875 | char *cmd; |
876 | { | |
63be8feb AC |
877 | if (sim_args_command (sd, cmd) != SIM_RC_OK) |
878 | sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n", | |
879 | cmd); | |
8bae0a0c JSC |
880 | } |
881 | ||
8bae0a0c JSC |
882 | /*---------------------------------------------------------------------------*/ |
883 | /*-- Private simulator support interface ------------------------------------*/ | |
884 | /*---------------------------------------------------------------------------*/ | |
885 | ||
525d929e AC |
886 | /* Read a null terminated string from memory, return in a buffer */ |
887 | static char * | |
888 | fetch_str (sd, addr) | |
889 | SIM_DESC sd; | |
890 | address_word addr; | |
891 | { | |
892 | char *buf; | |
893 | int nr = 0; | |
894 | char null; | |
895 | while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0) | |
896 | nr++; | |
897 | buf = NZALLOC (char, nr + 1); | |
898 | sim_read (sd, addr, buf, nr); | |
899 | return buf; | |
900 | } | |
901 | ||
a9f7253f | 902 | /* Simple monitor interface (currently setup for the IDT and PMON monitors) */ |
8bae0a0c | 903 | static void |
01737f42 AC |
904 | sim_monitor (SIM_DESC sd, |
905 | sim_cpu *cpu, | |
906 | address_word cia, | |
907 | unsigned int reason) | |
8bae0a0c | 908 | { |
53b9417e DE |
909 | #ifdef DEBUG |
910 | printf("DBG: sim_monitor: entered (reason = %d)\n",reason); | |
911 | #endif /* DEBUG */ | |
912 | ||
8bae0a0c JSC |
913 | /* The IDT monitor actually allows two instructions per vector |
914 | slot. However, the simulator currently causes a trap on each | |
915 | individual instruction. We cheat, and lose the bottom bit. */ | |
916 | reason >>= 1; | |
917 | ||
918 | /* The following callback functions are available, however the | |
919 | monitor we are simulating does not make use of them: get_errno, | |
920 | isatty, lseek, rename, system, time and unlink */ | |
525d929e AC |
921 | switch (reason) |
922 | { | |
923 | ||
8bae0a0c JSC |
924 | case 6: /* int open(char *path,int flags) */ |
925 | { | |
525d929e AC |
926 | char *path = fetch_str (sd, A0); |
927 | V0 = sim_io_open (sd, path, (int)A1); | |
928 | zfree (path); | |
929 | break; | |
8bae0a0c | 930 | } |
8bae0a0c JSC |
931 | |
932 | case 7: /* int read(int file,char *ptr,int len) */ | |
933 | { | |
525d929e AC |
934 | int fd = A0; |
935 | int nr = A2; | |
936 | char *buf = zalloc (nr); | |
937 | V0 = sim_io_read (sd, fd, buf, nr); | |
938 | sim_write (sd, A1, buf, nr); | |
939 | zfree (buf); | |
8bae0a0c JSC |
940 | } |
941 | break; | |
942 | ||
943 | case 8: /* int write(int file,char *ptr,int len) */ | |
944 | { | |
525d929e AC |
945 | int fd = A0; |
946 | int nr = A2; | |
947 | char *buf = zalloc (nr); | |
948 | sim_read (sd, A1, buf, nr); | |
949 | V0 = sim_io_write (sd, fd, buf, nr); | |
950 | zfree (buf); | |
951 | break; | |
8bae0a0c | 952 | } |
8bae0a0c JSC |
953 | |
954 | case 10: /* int close(int file) */ | |
525d929e AC |
955 | { |
956 | V0 = sim_io_close (sd, (int)A0); | |
957 | break; | |
958 | } | |
8bae0a0c | 959 | |
e0e0fc76 MA |
960 | case 2: /* Densan monitor: char inbyte(int waitflag) */ |
961 | { | |
962 | if (A0 == 0) /* waitflag == NOWAIT */ | |
192ae475 | 963 | V0 = (unsigned_word)-1; |
e0e0fc76 MA |
964 | } |
965 | /* Drop through to case 11 */ | |
966 | ||
8bae0a0c JSC |
967 | case 11: /* char inbyte(void) */ |
968 | { | |
969 | char tmp; | |
525d929e AC |
970 | if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char)) |
971 | { | |
972 | sim_io_error(sd,"Invalid return from character read"); | |
192ae475 | 973 | V0 = (unsigned_word)-1; |
525d929e | 974 | } |
8bae0a0c | 975 | else |
192ae475 | 976 | V0 = (unsigned_word)tmp; |
525d929e | 977 | break; |
8bae0a0c | 978 | } |
8bae0a0c | 979 | |
e0e0fc76 | 980 | case 3: /* Densan monitor: void co(char chr) */ |
8bae0a0c JSC |
981 | case 12: /* void outbyte(char chr) : write a byte to "stdout" */ |
982 | { | |
983 | char tmp = (char)(A0 & 0xFF); | |
525d929e AC |
984 | sim_io_write_stdout (sd, &tmp, sizeof(char)); |
985 | break; | |
8bae0a0c | 986 | } |
8bae0a0c JSC |
987 | |
988 | case 17: /* void _exit() */ | |
525d929e AC |
989 | { |
990 | sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n"); | |
01737f42 | 991 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited, |
525d929e AC |
992 | (unsigned int)(A0 & 0xFFFFFFFF)); |
993 | break; | |
994 | } | |
8bae0a0c | 995 | |
280f90e1 AMT |
996 | case 28 : /* PMON flush_cache */ |
997 | break; | |
998 | ||
8bae0a0c JSC |
999 | case 55: /* void get_mem_info(unsigned int *ptr) */ |
1000 | /* in: A0 = pointer to three word memory location */ | |
1001 | /* out: [A0 + 0] = size */ | |
1002 | /* [A0 + 4] = instruction cache size */ | |
1003 | /* [A0 + 8] = data cache size */ | |
1004 | { | |
525d929e AC |
1005 | address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */; |
1006 | H2T (value); | |
1007 | sim_write (sd, A0, (char *)&value, sizeof (value)); | |
030843d7 | 1008 | /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */ |
525d929e | 1009 | break; |
8bae0a0c | 1010 | } |
525d929e | 1011 | |
a9f7253f JSC |
1012 | case 158 : /* PMON printf */ |
1013 | /* in: A0 = pointer to format string */ | |
1014 | /* A1 = optional argument 1 */ | |
1015 | /* A2 = optional argument 2 */ | |
1016 | /* A3 = optional argument 3 */ | |
1017 | /* out: void */ | |
f24b7b69 | 1018 | /* The following is based on the PMON printf source */ |
a9f7253f | 1019 | { |
525d929e AC |
1020 | address_word s = A0; |
1021 | char c; | |
1022 | signed_word *ap = &A1; /* 1st argument */ | |
f24b7b69 JSC |
1023 | /* This isn't the quickest way, since we call the host print |
1024 | routine for every character almost. But it does avoid | |
1025 | having to allocate and manage a temporary string buffer. */ | |
525d929e AC |
1026 | /* TODO: Include check that we only use three arguments (A1, |
1027 | A2 and A3) */ | |
1028 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
1029 | { | |
1030 | if (c == '%') | |
1031 | { | |
1032 | char tmp[40]; | |
1033 | enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST; | |
1034 | int width = 0, trunc = 0, haddot = 0, longlong = 0; | |
1035 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
1036 | { | |
1037 | if (strchr ("dobxXulscefg%", s)) | |
1038 | break; | |
1039 | else if (c == '-') | |
1040 | fmt = FMT_LJUST; | |
1041 | else if (c == '0') | |
1042 | fmt = FMT_RJUST0; | |
1043 | else if (c == '~') | |
1044 | fmt = FMT_CENTER; | |
1045 | else if (c == '*') | |
1046 | { | |
1047 | if (haddot) | |
1048 | trunc = (int)*ap++; | |
1049 | else | |
1050 | width = (int)*ap++; | |
1051 | } | |
1052 | else if (c >= '1' && c <= '9') | |
1053 | { | |
1054 | address_word t = s; | |
1055 | unsigned int n; | |
1056 | while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c)) | |
1057 | tmp[s - t] = c; | |
1058 | tmp[s - t] = '\0'; | |
1059 | n = (unsigned int)strtol(tmp,NULL,10); | |
1060 | if (haddot) | |
1061 | trunc = n; | |
1062 | else | |
1063 | width = n; | |
1064 | s--; | |
1065 | } | |
1066 | else if (c == '.') | |
1067 | haddot = 1; | |
1068 | } | |
1069 | switch (c) | |
1070 | { | |
1071 | case '%': | |
1072 | sim_io_printf (sd, "%%"); | |
1073 | break; | |
1074 | case 's': | |
1075 | if ((int)*ap != 0) | |
1076 | { | |
1077 | address_word p = *ap++; | |
1078 | char ch; | |
1079 | while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0') | |
1080 | sim_io_printf(sd, "%c", ch); | |
1081 | } | |
1082 | else | |
1083 | sim_io_printf(sd,"(null)"); | |
1084 | break; | |
1085 | case 'c': | |
1086 | sim_io_printf (sd, "%c", (int)*ap++); | |
1087 | break; | |
1088 | default: | |
1089 | if (c == 'l') | |
1090 | { | |
1091 | sim_read (sd, s++, &c, 1); | |
1092 | if (c == 'l') | |
1093 | { | |
1094 | longlong = 1; | |
1095 | sim_read (sd, s++, &c, 1); | |
1096 | } | |
1097 | } | |
1098 | if (strchr ("dobxXu", c)) | |
1099 | { | |
1100 | word64 lv = (word64) *ap++; | |
1101 | if (c == 'b') | |
1102 | sim_io_printf(sd,"<binary not supported>"); | |
1103 | else | |
1104 | { | |
1105 | sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c); | |
1106 | if (longlong) | |
1107 | sim_io_printf(sd, tmp, lv); | |
1108 | else | |
1109 | sim_io_printf(sd, tmp, (int)lv); | |
1110 | } | |
1111 | } | |
1112 | else if (strchr ("eEfgG", c)) | |
1113 | { | |
1114 | double dbl = *(double*)(ap++); | |
1115 | sprintf (tmp, "%%%d.%d%c", width, trunc, c); | |
1116 | sim_io_printf (sd, tmp, dbl); | |
1117 | trunc = 0; | |
1118 | } | |
1119 | } | |
1120 | } | |
1121 | else | |
1122 | sim_io_printf(sd, "%c", c); | |
1123 | } | |
1124 | break; | |
a9f7253f | 1125 | } |
a9f7253f | 1126 | |
8bae0a0c | 1127 | default: |
525d929e | 1128 | sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n", |
95469ceb | 1129 | reason, pr_addr(cia)); |
8bae0a0c JSC |
1130 | break; |
1131 | } | |
1132 | return; | |
1133 | } | |
1134 | ||
7e6c297e ILT |
1135 | /* Store a word into memory. */ |
1136 | ||
1137 | static void | |
01737f42 AC |
1138 | store_word (SIM_DESC sd, |
1139 | sim_cpu *cpu, | |
1140 | address_word cia, | |
1141 | uword64 vaddr, | |
192ae475 | 1142 | signed_word val) |
7e6c297e | 1143 | { |
dad6f1f3 | 1144 | address_word paddr; |
7e6c297e ILT |
1145 | int uncached; |
1146 | ||
1147 | if ((vaddr & 3) != 0) | |
18c64df6 | 1148 | SignalExceptionAddressStore (); |
7e6c297e ILT |
1149 | else |
1150 | { | |
1151 | if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, | |
1152 | isTARGET, isREAL)) | |
1153 | { | |
1154 | const uword64 mask = 7; | |
1155 | uword64 memval; | |
1156 | unsigned int byte; | |
1157 | ||
1158 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)); | |
1159 | byte = (vaddr & mask) ^ (BigEndianCPU << 2); | |
1160 | memval = ((uword64) val) << (8 * byte); | |
53b9417e | 1161 | StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, |
7e6c297e ILT |
1162 | isREAL); |
1163 | } | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | /* Load a word from memory. */ | |
1168 | ||
192ae475 | 1169 | static signed_word |
01737f42 AC |
1170 | load_word (SIM_DESC sd, |
1171 | sim_cpu *cpu, | |
1172 | address_word cia, | |
1173 | uword64 vaddr) | |
7e6c297e ILT |
1174 | { |
1175 | if ((vaddr & 3) != 0) | |
18c64df6 | 1176 | SignalExceptionAddressLoad (); |
7e6c297e ILT |
1177 | else |
1178 | { | |
dad6f1f3 | 1179 | address_word paddr; |
7e6c297e ILT |
1180 | int uncached; |
1181 | ||
1182 | if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, | |
1183 | isTARGET, isREAL)) | |
1184 | { | |
1185 | const uword64 mask = 0x7; | |
1186 | const unsigned int reverse = ReverseEndian ? 1 : 0; | |
1187 | const unsigned int bigend = BigEndianCPU ? 1 : 0; | |
1188 | uword64 memval; | |
1189 | unsigned int byte; | |
1190 | ||
1191 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2)); | |
53b9417e | 1192 | LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr, |
7e6c297e ILT |
1193 | isDATA, isREAL); |
1194 | byte = (vaddr & mask) ^ (bigend << 2); | |
1195 | return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32); | |
1196 | } | |
1197 | } | |
1198 | ||
1199 | return 0; | |
1200 | } | |
1201 | ||
1202 | /* Simulate the mips16 entry and exit pseudo-instructions. These | |
1203 | would normally be handled by the reserved instruction exception | |
1204 | code, but for ease of simulation we just handle them directly. */ | |
1205 | ||
1206 | static void | |
01737f42 AC |
1207 | mips16_entry (SIM_DESC sd, |
1208 | sim_cpu *cpu, | |
1209 | address_word cia, | |
1210 | unsigned int insn) | |
7e6c297e ILT |
1211 | { |
1212 | int aregs, sregs, rreg; | |
1213 | ||
53b9417e DE |
1214 | #ifdef DEBUG |
1215 | printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn); | |
1216 | #endif /* DEBUG */ | |
1217 | ||
7e6c297e ILT |
1218 | aregs = (insn & 0x700) >> 8; |
1219 | sregs = (insn & 0x0c0) >> 6; | |
1220 | rreg = (insn & 0x020) >> 5; | |
1221 | ||
da0bce9c ILT |
1222 | /* This should be checked by the caller. */ |
1223 | if (sregs == 3) | |
7e6c297e ILT |
1224 | abort (); |
1225 | ||
da0bce9c | 1226 | if (aregs < 5) |
7e6c297e ILT |
1227 | { |
1228 | int i; | |
192ae475 | 1229 | signed_word tsp; |
7e6c297e ILT |
1230 | |
1231 | /* This is the entry pseudo-instruction. */ | |
1232 | ||
1233 | for (i = 0; i < aregs; i++) | |
01737f42 | 1234 | store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]); |
7e6c297e ILT |
1235 | |
1236 | tsp = SP; | |
1237 | SP -= 32; | |
1238 | ||
1239 | if (rreg) | |
1240 | { | |
1241 | tsp -= 4; | |
01737f42 | 1242 | store_word (SD, CPU, cia, (uword64) tsp, RA); |
7e6c297e ILT |
1243 | } |
1244 | ||
1245 | for (i = 0; i < sregs; i++) | |
1246 | { | |
1247 | tsp -= 4; | |
01737f42 | 1248 | store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]); |
7e6c297e ILT |
1249 | } |
1250 | } | |
1251 | else | |
1252 | { | |
1253 | int i; | |
192ae475 | 1254 | signed_word tsp; |
7e6c297e ILT |
1255 | |
1256 | /* This is the exit pseudo-instruction. */ | |
1257 | ||
1258 | tsp = SP + 32; | |
1259 | ||
1260 | if (rreg) | |
1261 | { | |
1262 | tsp -= 4; | |
01737f42 | 1263 | RA = load_word (SD, CPU, cia, (uword64) tsp); |
7e6c297e ILT |
1264 | } |
1265 | ||
1266 | for (i = 0; i < sregs; i++) | |
1267 | { | |
1268 | tsp -= 4; | |
01737f42 | 1269 | GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp); |
7e6c297e ILT |
1270 | } |
1271 | ||
1272 | SP += 32; | |
1273 | ||
192ae475 | 1274 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
da0bce9c | 1275 | { |
192ae475 AC |
1276 | if (aregs == 5) |
1277 | { | |
1278 | FGR[0] = WORD64LO (GPR[4]); | |
1279 | FPR_STATE[0] = fmt_uninterpreted; | |
1280 | } | |
1281 | else if (aregs == 6) | |
1282 | { | |
1283 | FGR[0] = WORD64LO (GPR[5]); | |
1284 | FGR[1] = WORD64LO (GPR[4]); | |
1285 | FPR_STATE[0] = fmt_uninterpreted; | |
1286 | FPR_STATE[1] = fmt_uninterpreted; | |
1287 | } | |
1288 | } | |
da0bce9c | 1289 | |
7e6c297e ILT |
1290 | PC = RA; |
1291 | } | |
192ae475 | 1292 | |
7e6c297e ILT |
1293 | } |
1294 | ||
8bae0a0c JSC |
1295 | /*-- trace support ----------------------------------------------------------*/ |
1296 | ||
1297 | /* The TRACE support is provided (if required) in the memory accessing | |
1298 | routines. Since we are also providing the architecture specific | |
1299 | features, the architecture simulation code can also deal with | |
1300 | notifying the TRACE world of cache flushes, etc. Similarly we do | |
1301 | not need to provide profiling support in the simulator engine, | |
1302 | since we can sample in the instruction fetch control loop. By | |
1303 | defining the TRACE manifest, we add tracing as a run-time | |
1304 | option. */ | |
1305 | ||
1306 | #if defined(TRACE) | |
1307 | /* Tracing by default produces "din" format (as required by | |
1308 | dineroIII). Each line of such a trace file *MUST* have a din label | |
1309 | and address field. The rest of the line is ignored, so comments can | |
1310 | be included if desired. The first field is the label which must be | |
1311 | one of the following values: | |
1312 | ||
1313 | 0 read data | |
1314 | 1 write data | |
1315 | 2 instruction fetch | |
1316 | 3 escape record (treated as unknown access type) | |
1317 | 4 escape record (causes cache flush) | |
1318 | ||
1319 | The address field is a 32bit (lower-case) hexadecimal address | |
1320 | value. The address should *NOT* be preceded by "0x". | |
1321 | ||
1322 | The size of the memory transfer is not important when dealing with | |
1323 | cache lines (as long as no more than a cache line can be | |
1324 | transferred in a single operation :-), however more information | |
1325 | could be given following the dineroIII requirement to allow more | |
1326 | complete memory and cache simulators to provide better | |
1327 | results. i.e. the University of Pisa has a cache simulator that can | |
1328 | also take bus size and speed as (variable) inputs to calculate | |
1329 | complete system performance (a much more useful ability when trying | |
1330 | to construct an end product, rather than a processor). They | |
1331 | currently have an ARM version of their tool called ChARM. */ | |
1332 | ||
e3d12c65 | 1333 | |
030843d7 | 1334 | void |
01737f42 AC |
1335 | dotrace (SIM_DESC sd, |
1336 | sim_cpu *cpu, | |
1337 | FILE *tracefh, | |
1338 | int type, | |
1339 | SIM_ADDR address, | |
1340 | int width, | |
1341 | char *comment,...) | |
8bae0a0c | 1342 | { |
0c2c5f61 | 1343 | if (STATE & simTRACE) { |
8bae0a0c | 1344 | va_list ap; |
53b9417e | 1345 | fprintf(tracefh,"%d %s ; width %d ; ", |
6429b296 | 1346 | type, |
53b9417e DE |
1347 | pr_addr(address), |
1348 | width); | |
8bae0a0c | 1349 | va_start(ap,comment); |
6429b296 | 1350 | vfprintf(tracefh,comment,ap); |
8bae0a0c JSC |
1351 | va_end(ap); |
1352 | fprintf(tracefh,"\n"); | |
1353 | } | |
1354 | /* NOTE: Since the "din" format will only accept 32bit addresses, and | |
1355 | we may be generating 64bit ones, we should put the hi-32bits of the | |
1356 | address into the comment field. */ | |
1357 | ||
1358 | /* TODO: Provide a buffer for the trace lines. We can then avoid | |
1359 | performing writes until the buffer is filled, or the file is | |
1360 | being closed. */ | |
1361 | ||
1362 | /* NOTE: We could consider adding a comment field to the "din" file | |
1363 | produced using type 3 markers (unknown access). This would then | |
1364 | allow information about the program that the "din" is for, and | |
1365 | the MIPs world that was being simulated, to be placed into the | |
1366 | trace file. */ | |
1367 | ||
1368 | return; | |
1369 | } | |
1370 | #endif /* TRACE */ | |
1371 | ||
1372 | /*---------------------------------------------------------------------------*/ | |
1373 | /*-- simulator engine -------------------------------------------------------*/ | |
1374 | /*---------------------------------------------------------------------------*/ | |
1375 | ||
1376 | static void | |
01737f42 | 1377 | ColdReset (SIM_DESC sd) |
8bae0a0c | 1378 | { |
01737f42 AC |
1379 | int cpu_nr; |
1380 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
dad6f1f3 | 1381 | { |
01737f42 AC |
1382 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); |
1383 | /* RESET: Fixed PC address: */ | |
1384 | PC = UNSIGNED64 (0xFFFFFFFFBFC00000); | |
1385 | /* The reset vector address is in the unmapped, uncached memory space. */ | |
1386 | ||
1387 | SR &= ~(status_SR | status_TS | status_RP); | |
1388 | SR |= (status_ERL | status_BEV); | |
1389 | ||
1390 | /* Cheat and allow access to the complete register set immediately */ | |
1391 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT | |
1392 | && WITH_TARGET_WORD_BITSIZE == 64) | |
1393 | SR |= status_FR; /* 64bit registers */ | |
1394 | ||
1395 | /* Ensure that any instructions with pending register updates are | |
1396 | cleared: */ | |
2acd126a | 1397 | PENDING_INVALIDATE(); |
01737f42 AC |
1398 | |
1399 | /* Initialise the FPU registers to the unknown state */ | |
1400 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) | |
1401 | { | |
1402 | int rn; | |
1403 | for (rn = 0; (rn < 32); rn++) | |
1404 | FPR_STATE[rn] = fmt_uninterpreted; | |
1405 | } | |
1406 | ||
dad6f1f3 | 1407 | } |
8bae0a0c JSC |
1408 | } |
1409 | ||
dad6f1f3 AC |
1410 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual |
1411 | (revision 3.1) */ | |
8bae0a0c JSC |
1412 | /* Translate a virtual address to a physical address and cache |
1413 | coherence algorithm describing the mechanism used to resolve the | |
1414 | memory reference. Given the virtual address vAddr, and whether the | |
1415 | reference is to Instructions ot Data (IorD), find the corresponding | |
1416 | physical address (pAddr) and the cache coherence algorithm (CCA) | |
1417 | used to resolve the reference. If the virtual address is in one of | |
1418 | the unmapped address spaces the physical address and the CCA are | |
1419 | determined directly by the virtual address. If the virtual address | |
1420 | is in one of the mapped address spaces then the TLB is used to | |
1421 | determine the physical address and access type; if the required | |
1422 | translation is not present in the TLB or the desired access is not | |
1423 | permitted the function fails and an exception is taken. | |
1424 | ||
dad6f1f3 AC |
1425 | NOTE: Normally (RAW == 0), when address translation fails, this |
1426 | function raises an exception and does not return. */ | |
8bae0a0c | 1427 | |
18c64df6 | 1428 | int |
01737f42 AC |
1429 | address_translation (SIM_DESC sd, |
1430 | sim_cpu *cpu, | |
1431 | address_word cia, | |
1432 | address_word vAddr, | |
1433 | int IorD, | |
1434 | int LorS, | |
1435 | address_word *pAddr, | |
1436 | int *CCA, | |
1437 | int raw) | |
8bae0a0c JSC |
1438 | { |
1439 | int res = -1; /* TRUE : Assume good return */ | |
1440 | ||
1441 | #ifdef DEBUG | |
18c64df6 | 1442 | sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD")); |
8bae0a0c JSC |
1443 | #endif |
1444 | ||
1445 | /* Check that the address is valid for this memory model */ | |
1446 | ||
1447 | /* For a simple (flat) memory model, we simply pass virtual | |
1448 | addressess through (mostly) unchanged. */ | |
1449 | vAddr &= 0xFFFFFFFF; | |
a9f7253f | 1450 | |
8bae0a0c JSC |
1451 | *pAddr = vAddr; /* default for isTARGET */ |
1452 | *CCA = Uncached; /* not used for isHOST */ | |
1453 | ||
8bae0a0c JSC |
1454 | return(res); |
1455 | } | |
1456 | ||
63be8feb AC |
1457 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual |
1458 | (revision 3.1) */ | |
8bae0a0c JSC |
1459 | /* Prefetch data from memory. Prefetch is an advisory instruction for |
1460 | which an implementation specific action is taken. The action taken | |
1461 | may increase performance, but must not change the meaning of the | |
1462 | program, or alter architecturally-visible state. */ | |
50a2a691 | 1463 | |
ea985d24 | 1464 | void |
01737f42 AC |
1465 | prefetch (SIM_DESC sd, |
1466 | sim_cpu *cpu, | |
1467 | address_word cia, | |
1468 | int CCA, | |
1469 | address_word pAddr, | |
1470 | address_word vAddr, | |
1471 | int DATA, | |
1472 | int hint) | |
8bae0a0c JSC |
1473 | { |
1474 | #ifdef DEBUG | |
18c64df6 | 1475 | sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint); |
8bae0a0c JSC |
1476 | #endif /* DEBUG */ |
1477 | ||
1478 | /* For our simple memory model we do nothing */ | |
1479 | return; | |
1480 | } | |
1481 | ||
63be8feb AC |
1482 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual |
1483 | (revision 3.1) */ | |
8bae0a0c JSC |
1484 | /* Load a value from memory. Use the cache and main memory as |
1485 | specified in the Cache Coherence Algorithm (CCA) and the sort of | |
1486 | access (IorD) to find the contents of AccessLength memory bytes | |
1487 | starting at physical location pAddr. The data is returned in the | |
1488 | fixed width naturally-aligned memory element (MemElem). The | |
1489 | low-order two (or three) bits of the address and the AccessLength | |
1490 | indicate which of the bytes within MemElem needs to be given to the | |
1491 | processor. If the memory access type of the reference is uncached | |
1492 | then only the referenced bytes are read from memory and valid | |
1493 | within the memory element. If the access type is cached, and the | |
1494 | data is not present in cache, an implementation specific size and | |
1495 | alignment block of memory is read and loaded into the cache to | |
1496 | satisfy a load reference. At a minimum, the block is the entire | |
1497 | memory element. */ | |
18c64df6 | 1498 | void |
01737f42 AC |
1499 | load_memory (SIM_DESC sd, |
1500 | sim_cpu *cpu, | |
1501 | address_word cia, | |
1502 | uword64* memvalp, | |
1503 | uword64* memval1p, | |
1504 | int CCA, | |
1505 | int AccessLength, | |
1506 | address_word pAddr, | |
1507 | address_word vAddr, | |
1508 | int IorD) | |
8bae0a0c | 1509 | { |
50a2a691 AC |
1510 | uword64 value = 0; |
1511 | uword64 value1 = 0; | |
8bae0a0c JSC |
1512 | |
1513 | #ifdef DEBUG | |
63be8feb | 1514 | sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION")); |
8bae0a0c JSC |
1515 | #endif /* DEBUG */ |
1516 | ||
1517 | #if defined(WARN_MEM) | |
1518 | if (CCA != uncached) | |
63be8feb | 1519 | sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c JSC |
1520 | #endif /* WARN_MEM */ |
1521 | ||
8bae0a0c JSC |
1522 | /* If instruction fetch then we need to check that the two lo-order |
1523 | bits are zero, otherwise raise a InstructionFetch exception: */ | |
6429b296 JW |
1524 | if ((IorD == isINSTRUCTION) |
1525 | && ((pAddr & 0x3) != 0) | |
1526 | && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0))) | |
63be8feb AC |
1527 | SignalExceptionInstructionFetch (); |
1528 | ||
1529 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
1530 | { | |
1531 | /* In reality this should be a Bus Error */ | |
1532 | sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n", | |
1533 | AccessLength, | |
1534 | (LOADDRMASK + 1) << 2, | |
1535 | pr_addr (pAddr)); | |
1536 | } | |
8bae0a0c | 1537 | |
8bae0a0c | 1538 | #if defined(TRACE) |
01737f42 | 1539 | dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); |
8bae0a0c | 1540 | #endif /* TRACE */ |
63be8feb AC |
1541 | |
1542 | /* Read the specified number of bytes from memory. Adjust for | |
1543 | host/target byte ordering/ Align the least significant byte | |
1544 | read. */ | |
8bae0a0c | 1545 | |
63be8feb AC |
1546 | switch (AccessLength) |
1547 | { | |
1548 | case AccessLength_QUADWORD : | |
1549 | { | |
82ea14fd | 1550 | unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA, read_map, pAddr); |
63be8feb AC |
1551 | value1 = VH8_16 (val); |
1552 | value = VL8_16 (val); | |
1553 | break; | |
8bae0a0c | 1554 | } |
63be8feb | 1555 | case AccessLength_DOUBLEWORD : |
01737f42 | 1556 | value = sim_core_read_aligned_8 (cpu, NULL_CIA, |
82ea14fd | 1557 | read_map, pAddr); |
63be8feb AC |
1558 | break; |
1559 | case AccessLength_SEPTIBYTE : | |
01737f42 | 1560 | value = sim_core_read_misaligned_7 (cpu, NULL_CIA, |
82ea14fd | 1561 | read_map, pAddr); |
f319bab2 | 1562 | break; |
63be8feb | 1563 | case AccessLength_SEXTIBYTE : |
01737f42 | 1564 | value = sim_core_read_misaligned_6 (cpu, NULL_CIA, |
82ea14fd | 1565 | read_map, pAddr); |
f319bab2 | 1566 | break; |
63be8feb | 1567 | case AccessLength_QUINTIBYTE : |
01737f42 | 1568 | value = sim_core_read_misaligned_5 (cpu, NULL_CIA, |
82ea14fd | 1569 | read_map, pAddr); |
f319bab2 | 1570 | break; |
63be8feb | 1571 | case AccessLength_WORD : |
01737f42 | 1572 | value = sim_core_read_aligned_4 (cpu, NULL_CIA, |
82ea14fd | 1573 | read_map, pAddr); |
63be8feb AC |
1574 | break; |
1575 | case AccessLength_TRIPLEBYTE : | |
01737f42 | 1576 | value = sim_core_read_misaligned_3 (cpu, NULL_CIA, |
82ea14fd | 1577 | read_map, pAddr); |
f319bab2 | 1578 | break; |
63be8feb | 1579 | case AccessLength_HALFWORD : |
01737f42 | 1580 | value = sim_core_read_aligned_2 (cpu, NULL_CIA, |
82ea14fd | 1581 | read_map, pAddr); |
63be8feb AC |
1582 | break; |
1583 | case AccessLength_BYTE : | |
01737f42 | 1584 | value = sim_core_read_aligned_1 (cpu, NULL_CIA, |
82ea14fd | 1585 | read_map, pAddr); |
63be8feb AC |
1586 | break; |
1587 | default: | |
1588 | abort (); | |
1589 | } | |
1590 | ||
8bae0a0c | 1591 | #ifdef DEBUG |
63be8feb AC |
1592 | printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n", |
1593 | (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value)); | |
8bae0a0c | 1594 | #endif /* DEBUG */ |
63be8feb AC |
1595 | |
1596 | /* See also store_memory. */ | |
1597 | if (AccessLength <= AccessLength_DOUBLEWORD) | |
1598 | { | |
1599 | if (BigEndianMem) | |
1600 | /* for big endian target, byte (pAddr&LOADDRMASK == 0) is | |
1601 | shifted to the most significant byte position. */ | |
1602 | value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1603 | else | |
1604 | /* For little endian target, byte (pAddr&LOADDRMASK == 0) | |
1605 | is already in the correct postition. */ | |
1606 | value <<= ((pAddr & LOADDRMASK) * 8); | |
1607 | } | |
1608 | ||
8bae0a0c | 1609 | #ifdef DEBUG |
63be8feb AC |
1610 | printf("DBG: LoadMemory() : shifted value = 0x%s%s\n", |
1611 | pr_uword64(value1),pr_uword64(value)); | |
e871dd18 | 1612 | #endif /* DEBUG */ |
63be8feb | 1613 | |
525d929e AC |
1614 | *memvalp = value; |
1615 | if (memval1p) *memval1p = value1; | |
8bae0a0c JSC |
1616 | } |
1617 | ||
53b9417e | 1618 | |
50a2a691 AC |
1619 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual |
1620 | (revision 3.1) */ | |
8bae0a0c JSC |
1621 | /* Store a value to memory. The specified data is stored into the |
1622 | physical location pAddr using the memory hierarchy (data caches and | |
1623 | main memory) as specified by the Cache Coherence Algorithm | |
1624 | (CCA). The MemElem contains the data for an aligned, fixed-width | |
1625 | memory element (word for 32-bit processors, doubleword for 64-bit | |
1626 | processors), though only the bytes that will actually be stored to | |
1627 | memory need to be valid. The low-order two (or three) bits of pAddr | |
1628 | and the AccessLength field indicates which of the bytes within the | |
1629 | MemElem data should actually be stored; only these bytes in memory | |
1630 | will be changed. */ | |
53b9417e | 1631 | |
18c64df6 | 1632 | void |
01737f42 AC |
1633 | store_memory (SIM_DESC sd, |
1634 | sim_cpu *cpu, | |
1635 | address_word cia, | |
1636 | int CCA, | |
1637 | int AccessLength, | |
1638 | uword64 MemElem, | |
1639 | uword64 MemElem1, /* High order 64 bits */ | |
1640 | address_word pAddr, | |
1641 | address_word vAddr) | |
8bae0a0c JSC |
1642 | { |
1643 | #ifdef DEBUG | |
63be8feb | 1644 | sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr)); |
8bae0a0c | 1645 | #endif /* DEBUG */ |
63be8feb | 1646 | |
8bae0a0c JSC |
1647 | #if defined(WARN_MEM) |
1648 | if (CCA != uncached) | |
63be8feb | 1649 | sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c | 1650 | #endif /* WARN_MEM */ |
63be8feb AC |
1651 | |
1652 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
1653 | sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr)); | |
1654 | ||
8bae0a0c | 1655 | #if defined(TRACE) |
01737f42 | 1656 | dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); |
8bae0a0c | 1657 | #endif /* TRACE */ |
63be8feb | 1658 | |
8bae0a0c | 1659 | #ifdef DEBUG |
63be8feb | 1660 | printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c | 1661 | #endif /* DEBUG */ |
63be8feb AC |
1662 | |
1663 | /* See also load_memory */ | |
1664 | if (AccessLength <= AccessLength_DOUBLEWORD) | |
1665 | { | |
1666 | if (BigEndianMem) | |
1667 | /* for big endian target, byte (pAddr&LOADDRMASK == 0) is | |
1668 | shifted to the most significant byte position. */ | |
1669 | MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1670 | else | |
1671 | /* For little endian target, byte (pAddr&LOADDRMASK == 0) | |
1672 | is already in the correct postition. */ | |
1673 | MemElem >>= ((pAddr & LOADDRMASK) * 8); | |
1674 | } | |
1675 | ||
8bae0a0c | 1676 | #ifdef DEBUG |
63be8feb | 1677 | printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c | 1678 | #endif /* DEBUG */ |
63be8feb AC |
1679 | |
1680 | switch (AccessLength) | |
1681 | { | |
1682 | case AccessLength_QUADWORD : | |
1683 | { | |
1684 | unsigned_16 val = U16_8 (MemElem1, MemElem); | |
82ea14fd | 1685 | sim_core_write_aligned_16 (cpu, NULL_CIA, write_map, pAddr, val); |
63be8feb | 1686 | break; |
8bae0a0c | 1687 | } |
63be8feb | 1688 | case AccessLength_DOUBLEWORD : |
01737f42 | 1689 | sim_core_write_aligned_8 (cpu, NULL_CIA, |
82ea14fd | 1690 | write_map, pAddr, MemElem); |
63be8feb AC |
1691 | break; |
1692 | case AccessLength_SEPTIBYTE : | |
01737f42 | 1693 | sim_core_write_misaligned_7 (cpu, NULL_CIA, |
82ea14fd | 1694 | write_map, pAddr, MemElem); |
63be8feb AC |
1695 | break; |
1696 | case AccessLength_SEXTIBYTE : | |
01737f42 | 1697 | sim_core_write_misaligned_6 (cpu, NULL_CIA, |
82ea14fd | 1698 | write_map, pAddr, MemElem); |
63be8feb AC |
1699 | break; |
1700 | case AccessLength_QUINTIBYTE : | |
01737f42 | 1701 | sim_core_write_misaligned_5 (cpu, NULL_CIA, |
82ea14fd | 1702 | write_map, pAddr, MemElem); |
63be8feb AC |
1703 | break; |
1704 | case AccessLength_WORD : | |
01737f42 | 1705 | sim_core_write_aligned_4 (cpu, NULL_CIA, |
82ea14fd | 1706 | write_map, pAddr, MemElem); |
63be8feb AC |
1707 | break; |
1708 | case AccessLength_TRIPLEBYTE : | |
01737f42 | 1709 | sim_core_write_misaligned_3 (cpu, NULL_CIA, |
82ea14fd | 1710 | write_map, pAddr, MemElem); |
63be8feb AC |
1711 | break; |
1712 | case AccessLength_HALFWORD : | |
01737f42 | 1713 | sim_core_write_aligned_2 (cpu, NULL_CIA, |
82ea14fd | 1714 | write_map, pAddr, MemElem); |
63be8feb AC |
1715 | break; |
1716 | case AccessLength_BYTE : | |
01737f42 | 1717 | sim_core_write_aligned_1 (cpu, NULL_CIA, |
82ea14fd | 1718 | write_map, pAddr, MemElem); |
63be8feb AC |
1719 | break; |
1720 | default: | |
1721 | abort (); | |
1722 | } | |
1723 | ||
8bae0a0c JSC |
1724 | return; |
1725 | } | |
1726 | ||
53b9417e | 1727 | |
dad6f1f3 | 1728 | unsigned32 |
7ce8b917 | 1729 | ifetch32 (SIM_DESC sd, |
01737f42 | 1730 | sim_cpu *cpu, |
7ce8b917 AC |
1731 | address_word cia, |
1732 | address_word vaddr) | |
dad6f1f3 AC |
1733 | { |
1734 | /* Copy the action of the LW instruction */ | |
1735 | address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
1736 | address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
1737 | unsigned64 value; | |
1738 | address_word paddr; | |
1739 | unsigned32 instruction; | |
1740 | unsigned byte; | |
1741 | int cca; | |
1742 | AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL); | |
1743 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
37379a25 AC |
1744 | LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL); |
1745 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); | |
1746 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
1747 | return instruction; | |
1748 | } | |
1749 | ||
1750 | ||
1751 | unsigned16 | |
1752 | ifetch16 (SIM_DESC sd, | |
1753 | sim_cpu *cpu, | |
1754 | address_word cia, | |
1755 | address_word vaddr) | |
1756 | { | |
1757 | /* Copy the action of the LW instruction */ | |
1758 | address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
1759 | address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
1760 | unsigned64 value; | |
1761 | address_word paddr; | |
1762 | unsigned16 instruction; | |
1763 | unsigned byte; | |
1764 | int cca; | |
1765 | AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL); | |
1766 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
dad6f1f3 AC |
1767 | LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL); |
1768 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); | |
1769 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
1770 | return instruction; | |
1771 | } | |
1772 | ||
1773 | ||
8bae0a0c JSC |
1774 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ |
1775 | /* Order loads and stores to synchronise shared memory. Perform the | |
1776 | action necessary to make the effects of groups of synchronizable | |
1777 | loads and stores indicated by stype occur in the same order for all | |
1778 | processors. */ | |
ea985d24 | 1779 | void |
01737f42 AC |
1780 | sync_operation (SIM_DESC sd, |
1781 | sim_cpu *cpu, | |
1782 | address_word cia, | |
1783 | int stype) | |
8bae0a0c JSC |
1784 | { |
1785 | #ifdef DEBUG | |
18c64df6 | 1786 | sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype); |
8bae0a0c JSC |
1787 | #endif /* DEBUG */ |
1788 | return; | |
1789 | } | |
1790 | ||
1791 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1792 | /* Signal an exception condition. This will result in an exception | |
1793 | that aborts the instruction. The instruction operation pseudocode | |
50a2a691 | 1794 | will never see a return from this function call. */ |
2e61a3ad | 1795 | |
18c64df6 | 1796 | void |
7ce8b917 | 1797 | signal_exception (SIM_DESC sd, |
01737f42 | 1798 | sim_cpu *cpu, |
7ce8b917 AC |
1799 | address_word cia, |
1800 | int exception,...) | |
8bae0a0c | 1801 | { |
56e7c849 | 1802 | int vector; |
6eedf3f4 MA |
1803 | |
1804 | #ifdef DEBUG | |
95469ceb | 1805 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); |
6eedf3f4 MA |
1806 | #endif /* DEBUG */ |
1807 | ||
8bae0a0c JSC |
1808 | /* Ensure that any active atomic read/modify/write operation will fail: */ |
1809 | LLBIT = 0; | |
1810 | ||
1811 | switch (exception) { | |
1812 | /* TODO: For testing purposes I have been ignoring TRAPs. In | |
1813 | reality we should either simulate them, or allow the user to | |
6eedf3f4 MA |
1814 | ignore them at run-time. |
1815 | Same for SYSCALL */ | |
8bae0a0c | 1816 | case Trap : |
95469ceb | 1817 | sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia)); |
8bae0a0c JSC |
1818 | break; |
1819 | ||
6eedf3f4 MA |
1820 | case SystemCall : |
1821 | { | |
1822 | va_list ap; | |
1823 | unsigned int instruction; | |
1824 | unsigned int code; | |
1825 | ||
1826 | va_start(ap,exception); | |
1827 | instruction = va_arg(ap,unsigned int); | |
1828 | va_end(ap); | |
1829 | ||
1830 | code = (instruction >> 6) & 0xFFFFF; | |
1831 | ||
18c64df6 | 1832 | sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n", |
95469ceb | 1833 | code, pr_addr(cia)); |
6eedf3f4 MA |
1834 | } |
1835 | break; | |
1836 | ||
1837 | case DebugBreakPoint : | |
1838 | if (! (Debug & Debug_DM)) | |
1839 | { | |
1840 | if (INDELAYSLOT()) | |
1841 | { | |
1842 | CANCELDELAYSLOT(); | |
1843 | ||
1844 | Debug |= Debug_DBD; /* signaled from within in delay slot */ | |
95469ceb | 1845 | DEPC = cia - 4; /* reference the branch instruction */ |
6eedf3f4 MA |
1846 | } |
1847 | else | |
1848 | { | |
1849 | Debug &= ~Debug_DBD; /* not signaled from within a delay slot */ | |
95469ceb | 1850 | DEPC = cia; |
6eedf3f4 MA |
1851 | } |
1852 | ||
1853 | Debug |= Debug_DM; /* in debugging mode */ | |
1854 | Debug |= Debug_DBp; /* raising a DBp exception */ | |
1855 | PC = 0xBFC00200; | |
01737f42 | 1856 | sim_engine_restart (SD, CPU, NULL, NULL_CIA); |
6eedf3f4 MA |
1857 | } |
1858 | break; | |
1859 | ||
8bae0a0c JSC |
1860 | case ReservedInstruction : |
1861 | { | |
1862 | va_list ap; | |
1863 | unsigned int instruction; | |
1864 | va_start(ap,exception); | |
1865 | instruction = va_arg(ap,unsigned int); | |
1866 | va_end(ap); | |
1867 | /* Provide simple monitor support using ReservedInstruction | |
1868 | exceptions. The following code simulates the fixed vector | |
1869 | entry points into the IDT monitor by causing a simulator | |
1870 | trap, performing the monitor operation, and returning to | |
1871 | the address held in the $ra register (standard PCS return | |
1872 | address). This means we only need to pre-load the vector | |
1873 | space with suitable instruction values. For systems were | |
1874 | actual trap instructions are used, we would not need to | |
1875 | perform this magic. */ | |
7ce8b917 AC |
1876 | if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) |
1877 | { | |
01737f42 | 1878 | sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) ); |
7ce8b917 AC |
1879 | /* NOTE: This assumes that a branch-and-link style |
1880 | instruction was used to enter the vector (which is the | |
1881 | case with the current IDT monitor). */ | |
01737f42 | 1882 | sim_engine_restart (SD, CPU, NULL, RA); |
7ce8b917 | 1883 | } |
7e6c297e ILT |
1884 | /* Look for the mips16 entry and exit instructions, and |
1885 | simulate a handler for them. */ | |
95469ceb | 1886 | else if ((cia & 1) != 0 |
7e6c297e | 1887 | && (instruction & 0xf81f) == 0xe809 |
7ce8b917 AC |
1888 | && (instruction & 0x0c0) != 0x0c0) |
1889 | { | |
01737f42 | 1890 | mips16_entry (SD, CPU, cia, instruction); |
7ce8b917 AC |
1891 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); |
1892 | } | |
1893 | /* else fall through to normal exception processing */ | |
95469ceb | 1894 | sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia)); |
8bae0a0c JSC |
1895 | } |
1896 | ||
05d1322f | 1897 | case BreakPoint: |
e3d12c65 | 1898 | #ifdef DEBUG |
95469ceb | 1899 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); |
8bae0a0c | 1900 | #endif /* DEBUG */ |
05d1322f JL |
1901 | /* Keep a copy of the current A0 in-case this is the program exit |
1902 | breakpoint: */ | |
1903 | { | |
1904 | va_list ap; | |
1905 | unsigned int instruction; | |
1906 | va_start(ap,exception); | |
1907 | instruction = va_arg(ap,unsigned int); | |
1908 | va_end(ap); | |
1909 | /* Check for our special terminating BREAK: */ | |
1910 | if ((instruction & 0x03FFFFC0) == 0x03ff0000) { | |
01737f42 | 1911 | sim_engine_halt (SD, CPU, NULL, cia, |
05d1322f JL |
1912 | sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); |
1913 | } | |
1914 | } | |
0c2c5f61 | 1915 | if (STATE & simDELAYSLOT) |
95469ceb | 1916 | PC = cia - 4; /* reference the branch instruction */ |
05d1322f | 1917 | else |
95469ceb | 1918 | PC = cia; |
01737f42 | 1919 | sim_engine_halt (SD, CPU, NULL, cia, |
232156de | 1920 | sim_stopped, SIM_SIGTRAP); |
05d1322f JL |
1921 | |
1922 | default: | |
8bae0a0c JSC |
1923 | /* Store exception code into current exception id variable (used |
1924 | by exit code): */ | |
1925 | ||
1926 | /* TODO: If not simulating exceptions then stop the simulator | |
1927 | execution. At the moment we always stop the simulation. */ | |
e3d12c65 | 1928 | |
56e7c849 AC |
1929 | /* See figure 5-17 for an outline of the code below */ |
1930 | if (! (SR & status_EXL)) | |
1931 | { | |
1932 | CAUSE = (exception << 2); | |
0c2c5f61 | 1933 | if (STATE & simDELAYSLOT) |
56e7c849 | 1934 | { |
0c2c5f61 | 1935 | STATE &= ~simDELAYSLOT; |
56e7c849 | 1936 | CAUSE |= cause_BD; |
95469ceb | 1937 | EPC = (cia - 4); /* reference the branch instruction */ |
56e7c849 AC |
1938 | } |
1939 | else | |
95469ceb | 1940 | EPC = cia; |
56e7c849 AC |
1941 | /* FIXME: TLB et.al. */ |
1942 | vector = 0x180; | |
1943 | } | |
1944 | else | |
1945 | { | |
05d1322f | 1946 | CAUSE = (exception << 2); |
56e7c849 AC |
1947 | vector = 0x180; |
1948 | } | |
1949 | SR |= status_EXL; | |
e3d12c65 DE |
1950 | /* Store exception code into current exception id variable (used |
1951 | by exit code): */ | |
56e7c849 AC |
1952 | if (SR & status_BEV) |
1953 | PC = (signed)0xBFC00200 + 0x180; | |
1954 | else | |
1955 | PC = (signed)0x80000000 + 0x180; | |
1956 | ||
50a2a691 AC |
1957 | switch ((CAUSE >> 2) & 0x1F) |
1958 | { | |
1959 | case Interrupt: | |
56e7c849 AC |
1960 | /* Interrupts arrive during event processing, no need to |
1961 | restart */ | |
1962 | return; | |
50a2a691 AC |
1963 | |
1964 | case TLBModification: | |
1965 | case TLBLoad: | |
1966 | case TLBStore: | |
1967 | case AddressLoad: | |
1968 | case AddressStore: | |
1969 | case InstructionFetch: | |
1970 | case DataReference: | |
56e7c849 AC |
1971 | /* The following is so that the simulator will continue from the |
1972 | exception address on breakpoint operations. */ | |
1973 | PC = EPC; | |
01737f42 | 1974 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1975 | sim_stopped, SIM_SIGBUS); |
50a2a691 AC |
1976 | |
1977 | case ReservedInstruction: | |
1978 | case CoProcessorUnusable: | |
56e7c849 | 1979 | PC = EPC; |
01737f42 | 1980 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1981 | sim_stopped, SIM_SIGILL); |
50a2a691 AC |
1982 | |
1983 | case IntegerOverflow: | |
1984 | case FPE: | |
01737f42 | 1985 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1986 | sim_stopped, SIM_SIGFPE); |
50a2a691 AC |
1987 | |
1988 | case Trap: | |
1989 | case Watch: | |
1990 | case SystemCall: | |
56e7c849 | 1991 | PC = EPC; |
01737f42 | 1992 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1993 | sim_stopped, SIM_SIGTRAP); |
50a2a691 | 1994 | |
05d1322f JL |
1995 | case BreakPoint: |
1996 | PC = EPC; | |
01737f42 | 1997 | sim_engine_abort (SD, CPU, NULL_CIA, |
05d1322f JL |
1998 | "FATAL: Should not encounter a breakpoint\n"); |
1999 | ||
50a2a691 | 2000 | default : /* Unknown internal exception */ |
56e7c849 | 2001 | PC = EPC; |
01737f42 | 2002 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 2003 | sim_stopped, SIM_SIGABRT); |
50a2a691 AC |
2004 | |
2005 | } | |
8bae0a0c JSC |
2006 | |
2007 | case SimulatorFault: | |
2008 | { | |
2009 | va_list ap; | |
2010 | char *msg; | |
2011 | va_start(ap,exception); | |
2012 | msg = va_arg(ap,char *); | |
50a2a691 | 2013 | va_end(ap); |
01737f42 | 2014 | sim_engine_abort (SD, CPU, NULL_CIA, |
2e61a3ad | 2015 | "FATAL: Simulator error \"%s\"\n",msg); |
8bae0a0c | 2016 | } |
8bae0a0c JSC |
2017 | } |
2018 | ||
2019 | return; | |
2020 | } | |
2021 | ||
2022 | #if defined(WARN_RESULT) | |
2023 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
2024 | /* This function indicates that the result of the operation is | |
2025 | undefined. However, this should not affect the instruction | |
2026 | stream. All that is meant to happen is that the destination | |
2027 | register is set to an undefined result. To keep the simulator | |
2028 | simple, we just don't bother updating the destination register, so | |
2029 | the overall result will be undefined. If desired we can stop the | |
2030 | simulator by raising a pseudo-exception. */ | |
95469ceb | 2031 | #define UndefinedResult() undefined_result (sd,cia) |
8bae0a0c | 2032 | static void |
95469ceb AC |
2033 | undefined_result(sd,cia) |
2034 | SIM_DESC sd; | |
2035 | address_word cia; | |
8bae0a0c | 2036 | { |
95469ceb | 2037 | sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia)); |
8bae0a0c JSC |
2038 | #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */ |
2039 | state |= simSTOP; | |
2040 | #endif | |
2041 | return; | |
2042 | } | |
2043 | #endif /* WARN_RESULT */ | |
2044 | ||
18c64df6 | 2045 | void |
01737f42 AC |
2046 | cache_op (SIM_DESC sd, |
2047 | sim_cpu *cpu, | |
2048 | address_word cia, | |
2049 | int op, | |
2050 | address_word pAddr, | |
2051 | address_word vAddr, | |
2052 | unsigned int instruction) | |
8bae0a0c | 2053 | { |
f24b7b69 JSC |
2054 | #if 1 /* stop warning message being displayed (we should really just remove the code) */ |
2055 | static int icache_warning = 1; | |
2056 | static int dcache_warning = 1; | |
2057 | #else | |
a9f7253f JSC |
2058 | static int icache_warning = 0; |
2059 | static int dcache_warning = 0; | |
f24b7b69 | 2060 | #endif |
a9f7253f | 2061 | |
8bae0a0c JSC |
2062 | /* If CP0 is not useable (User or Supervisor mode) and the CP0 |
2063 | enable bit in the Status Register is clear - a coprocessor | |
2064 | unusable exception is taken. */ | |
a9f7253f | 2065 | #if 0 |
95469ceb | 2066 | sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia)); |
a9f7253f | 2067 | #endif |
8bae0a0c JSC |
2068 | |
2069 | switch (op & 0x3) { | |
2070 | case 0: /* instruction cache */ | |
2071 | switch (op >> 2) { | |
2072 | case 0: /* Index Invalidate */ | |
2073 | case 1: /* Index Load Tag */ | |
2074 | case 2: /* Index Store Tag */ | |
2075 | case 4: /* Hit Invalidate */ | |
2076 | case 5: /* Fill */ | |
2077 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
2078 | if (!icache_warning) |
2079 | { | |
18c64df6 | 2080 | sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
2081 | icache_warning = 1; |
2082 | } | |
8bae0a0c JSC |
2083 | break; |
2084 | ||
2085 | default: | |
2086 | SignalException(ReservedInstruction,instruction); | |
2087 | break; | |
2088 | } | |
2089 | break; | |
2090 | ||
2091 | case 1: /* data cache */ | |
2092 | switch (op >> 2) { | |
2093 | case 0: /* Index Writeback Invalidate */ | |
2094 | case 1: /* Index Load Tag */ | |
2095 | case 2: /* Index Store Tag */ | |
2096 | case 3: /* Create Dirty */ | |
2097 | case 4: /* Hit Invalidate */ | |
2098 | case 5: /* Hit Writeback Invalidate */ | |
2099 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
2100 | if (!dcache_warning) |
2101 | { | |
18c64df6 | 2102 | sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
2103 | dcache_warning = 1; |
2104 | } | |
8bae0a0c JSC |
2105 | break; |
2106 | ||
2107 | default: | |
2108 | SignalException(ReservedInstruction,instruction); | |
2109 | break; | |
2110 | } | |
2111 | break; | |
2112 | ||
2113 | default: /* unrecognised cache ID */ | |
2114 | SignalException(ReservedInstruction,instruction); | |
2115 | break; | |
2116 | } | |
2117 | ||
2118 | return; | |
2119 | } | |
2120 | ||
2121 | /*-- FPU support routines ---------------------------------------------------*/ | |
2122 | ||
8bae0a0c JSC |
2123 | /* Numbers are held in normalized form. The SINGLE and DOUBLE binary |
2124 | formats conform to ANSI/IEEE Std 754-1985. */ | |
2125 | /* SINGLE precision floating: | |
2126 | * seeeeeeeefffffffffffffffffffffff | |
2127 | * s = 1bit = sign | |
2128 | * e = 8bits = exponent | |
2129 | * f = 23bits = fraction | |
2130 | */ | |
2131 | /* SINGLE precision fixed: | |
2132 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2133 | * s = 1bit = sign | |
2134 | * i = 31bits = integer | |
2135 | */ | |
2136 | /* DOUBLE precision floating: | |
2137 | * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff | |
2138 | * s = 1bit = sign | |
2139 | * e = 11bits = exponent | |
2140 | * f = 52bits = fraction | |
2141 | */ | |
2142 | /* DOUBLE precision fixed: | |
2143 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2144 | * s = 1bit = sign | |
2145 | * i = 63bits = integer | |
2146 | */ | |
2147 | ||
2148 | /* Extract sign-bit: */ | |
2149 | #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0) | |
e871dd18 | 2150 | #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0) |
8bae0a0c JSC |
2151 | /* Extract biased exponent: */ |
2152 | #define FP_S_be(v) (((v) >> 23) & 0xFF) | |
2153 | #define FP_D_be(v) (((v) >> 52) & 0x7FF) | |
2154 | /* Extract unbiased Exponent: */ | |
2155 | #define FP_S_e(v) (FP_S_be(v) - 0x7F) | |
2156 | #define FP_D_e(v) (FP_D_be(v) - 0x3FF) | |
2157 | /* Extract complete fraction field: */ | |
2158 | #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23)) | |
e871dd18 | 2159 | #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52)) |
8bae0a0c JSC |
2160 | /* Extract numbered fraction bit: */ |
2161 | #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0) | |
2162 | #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0) | |
2163 | ||
2164 | /* Explicit QNaN values used when value required: */ | |
2165 | #define FPQNaN_SINGLE (0x7FBFFFFF) | |
2166 | #define FPQNaN_WORD (0x7FFFFFFF) | |
e871dd18 JSC |
2167 | #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF) |
2168 | #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF) | |
8bae0a0c JSC |
2169 | |
2170 | /* Explicit Infinity values used when required: */ | |
2171 | #define FPINF_SINGLE (0x7F800000) | |
e871dd18 | 2172 | #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000) |
8bae0a0c JSC |
2173 | |
2174 | #if 1 /* def DEBUG */ | |
2175 | #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor"))) | |
2176 | #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>")))))) | |
2177 | #endif /* DEBUG */ | |
2178 | ||
18c64df6 | 2179 | uword64 |
01737f42 AC |
2180 | value_fpr (SIM_DESC sd, |
2181 | sim_cpu *cpu, | |
2182 | address_word cia, | |
2183 | int fpr, | |
2184 | FP_formats fmt) | |
8bae0a0c | 2185 | { |
50a2a691 | 2186 | uword64 value = 0; |
8bae0a0c JSC |
2187 | int err = 0; |
2188 | ||
2189 | /* Treat unused register values, as fixed-point 64bit values: */ | |
2190 | if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown)) | |
2191 | #if 1 | |
2192 | /* If request to read data as "uninterpreted", then use the current | |
2193 | encoding: */ | |
0c2c5f61 | 2194 | fmt = FPR_STATE[fpr]; |
8bae0a0c JSC |
2195 | #else |
2196 | fmt = fmt_long; | |
2197 | #endif | |
2198 | ||
2199 | /* For values not yet accessed, set to the desired format: */ | |
0c2c5f61 AC |
2200 | if (FPR_STATE[fpr] == fmt_uninterpreted) { |
2201 | FPR_STATE[fpr] = fmt; | |
8bae0a0c JSC |
2202 | #ifdef DEBUG |
2203 | printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt)); | |
2204 | #endif /* DEBUG */ | |
2205 | } | |
0c2c5f61 | 2206 | if (fmt != FPR_STATE[fpr]) { |
95469ceb | 2207 | sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia)); |
0c2c5f61 | 2208 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2209 | } |
2210 | ||
0c2c5f61 | 2211 | if (FPR_STATE[fpr] == fmt_unknown) { |
8bae0a0c JSC |
2212 | /* Set QNaN value: */ |
2213 | switch (fmt) { | |
2214 | case fmt_single: | |
2215 | value = FPQNaN_SINGLE; | |
2216 | break; | |
2217 | ||
2218 | case fmt_double: | |
2219 | value = FPQNaN_DOUBLE; | |
2220 | break; | |
2221 | ||
2222 | case fmt_word: | |
2223 | value = FPQNaN_WORD; | |
2224 | break; | |
2225 | ||
2226 | case fmt_long: | |
2227 | value = FPQNaN_LONG; | |
2228 | break; | |
2229 | ||
2230 | default: | |
2231 | err = -1; | |
2232 | break; | |
2233 | } | |
2234 | } else if (SizeFGR() == 64) { | |
2235 | switch (fmt) { | |
2236 | case fmt_single: | |
2237 | case fmt_word: | |
2238 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2239 | break; | |
2240 | ||
2241 | case fmt_uninterpreted: | |
2242 | case fmt_double: | |
2243 | case fmt_long: | |
2244 | value = FGR[fpr]; | |
2245 | break; | |
2246 | ||
2247 | default : | |
2248 | err = -1; | |
2249 | break; | |
2250 | } | |
da0bce9c | 2251 | } else { |
8bae0a0c JSC |
2252 | switch (fmt) { |
2253 | case fmt_single: | |
2254 | case fmt_word: | |
2255 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2256 | break; | |
2257 | ||
2258 | case fmt_uninterpreted: | |
2259 | case fmt_double: | |
2260 | case fmt_long: | |
da0bce9c ILT |
2261 | if ((fpr & 1) == 0) { /* even registers only */ |
2262 | value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF)); | |
2263 | } else { | |
18c64df6 | 2264 | SignalException(ReservedInstruction,0); |
da0bce9c | 2265 | } |
8bae0a0c JSC |
2266 | break; |
2267 | ||
2268 | default : | |
2269 | err = -1; | |
2270 | break; | |
2271 | } | |
2272 | } | |
2273 | ||
2274 | if (err) | |
18c64df6 | 2275 | SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()"); |
8bae0a0c JSC |
2276 | |
2277 | #ifdef DEBUG | |
95469ceb | 2278 | printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); |
8bae0a0c JSC |
2279 | #endif /* DEBUG */ |
2280 | ||
2281 | return(value); | |
2282 | } | |
2283 | ||
18c64df6 | 2284 | void |
01737f42 AC |
2285 | store_fpr (SIM_DESC sd, |
2286 | sim_cpu *cpu, | |
2287 | address_word cia, | |
2288 | int fpr, | |
2289 | FP_formats fmt, | |
2290 | uword64 value) | |
8bae0a0c JSC |
2291 | { |
2292 | int err = 0; | |
2293 | ||
2294 | #ifdef DEBUG | |
95469ceb | 2295 | printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); |
8bae0a0c JSC |
2296 | #endif /* DEBUG */ |
2297 | ||
2298 | if (SizeFGR() == 64) { | |
2299 | switch (fmt) { | |
a09a30d2 AC |
2300 | case fmt_uninterpreted_32: |
2301 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2302 | case fmt_single : |
2303 | case fmt_word : | |
e871dd18 | 2304 | FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF)); |
0c2c5f61 | 2305 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2306 | break; |
2307 | ||
a09a30d2 AC |
2308 | case fmt_uninterpreted_64: |
2309 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2310 | case fmt_uninterpreted: |
2311 | case fmt_double : | |
2312 | case fmt_long : | |
2313 | FGR[fpr] = value; | |
0c2c5f61 | 2314 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2315 | break; |
2316 | ||
2317 | default : | |
0c2c5f61 | 2318 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2319 | err = -1; |
2320 | break; | |
2321 | } | |
da0bce9c | 2322 | } else { |
8bae0a0c | 2323 | switch (fmt) { |
a09a30d2 AC |
2324 | case fmt_uninterpreted_32: |
2325 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2326 | case fmt_single : |
2327 | case fmt_word : | |
8bae0a0c | 2328 | FGR[fpr] = (value & 0xFFFFFFFF); |
0c2c5f61 | 2329 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2330 | break; |
2331 | ||
a09a30d2 AC |
2332 | case fmt_uninterpreted_64: |
2333 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2334 | case fmt_uninterpreted: |
2335 | case fmt_double : | |
2336 | case fmt_long : | |
da0bce9c ILT |
2337 | if ((fpr & 1) == 0) { /* even register number only */ |
2338 | FGR[fpr+1] = (value >> 32); | |
2339 | FGR[fpr] = (value & 0xFFFFFFFF); | |
0c2c5f61 AC |
2340 | FPR_STATE[fpr + 1] = fmt; |
2341 | FPR_STATE[fpr] = fmt; | |
da0bce9c | 2342 | } else { |
0c2c5f61 AC |
2343 | FPR_STATE[fpr] = fmt_unknown; |
2344 | FPR_STATE[fpr + 1] = fmt_unknown; | |
18c64df6 | 2345 | SignalException(ReservedInstruction,0); |
da0bce9c | 2346 | } |
8bae0a0c JSC |
2347 | break; |
2348 | ||
2349 | default : | |
0c2c5f61 | 2350 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2351 | err = -1; |
2352 | break; | |
2353 | } | |
e871dd18 JSC |
2354 | } |
2355 | #if defined(WARN_RESULT) | |
2356 | else | |
2357 | UndefinedResult(); | |
2358 | #endif /* WARN_RESULT */ | |
8bae0a0c JSC |
2359 | |
2360 | if (err) | |
18c64df6 | 2361 | SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()"); |
8bae0a0c JSC |
2362 | |
2363 | #ifdef DEBUG | |
53b9417e | 2364 | printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt)); |
8bae0a0c JSC |
2365 | #endif /* DEBUG */ |
2366 | ||
2367 | return; | |
2368 | } | |
2369 | ||
18c64df6 | 2370 | int |
8bae0a0c | 2371 | NaN(op,fmt) |
e871dd18 | 2372 | uword64 op; |
8bae0a0c JSC |
2373 | FP_formats fmt; |
2374 | { | |
2375 | int boolean = 0; | |
8bae0a0c JSC |
2376 | switch (fmt) { |
2377 | case fmt_single: | |
8bae0a0c | 2378 | case fmt_word: |
76ef4165 FL |
2379 | { |
2380 | sim_fpu wop; | |
2381 | sim_fpu_32to (&wop, op); | |
2382 | boolean = sim_fpu_is_nan (&wop); | |
2383 | break; | |
2384 | } | |
2385 | case fmt_double: | |
8bae0a0c | 2386 | case fmt_long: |
76ef4165 FL |
2387 | { |
2388 | sim_fpu wop; | |
2389 | sim_fpu_64to (&wop, op); | |
2390 | boolean = sim_fpu_is_nan (&wop); | |
2391 | break; | |
2392 | } | |
50a2a691 AC |
2393 | default: |
2394 | fprintf (stderr, "Bad switch\n"); | |
2395 | abort (); | |
8bae0a0c JSC |
2396 | } |
2397 | ||
2398 | #ifdef DEBUG | |
53b9417e | 2399 | printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2400 | #endif /* DEBUG */ |
2401 | ||
2402 | return(boolean); | |
2403 | } | |
2404 | ||
18c64df6 | 2405 | int |
8bae0a0c | 2406 | Infinity(op,fmt) |
e871dd18 | 2407 | uword64 op; |
8bae0a0c JSC |
2408 | FP_formats fmt; |
2409 | { | |
2410 | int boolean = 0; | |
2411 | ||
2412 | #ifdef DEBUG | |
95469ceb | 2413 | printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2414 | #endif /* DEBUG */ |
2415 | ||
8bae0a0c JSC |
2416 | switch (fmt) { |
2417 | case fmt_single: | |
76ef4165 FL |
2418 | { |
2419 | sim_fpu wop; | |
2420 | sim_fpu_32to (&wop, op); | |
2421 | boolean = sim_fpu_is_infinity (&wop); | |
2422 | break; | |
2423 | } | |
8bae0a0c | 2424 | case fmt_double: |
76ef4165 FL |
2425 | { |
2426 | sim_fpu wop; | |
2427 | sim_fpu_64to (&wop, op); | |
2428 | boolean = sim_fpu_is_infinity (&wop); | |
2429 | break; | |
2430 | } | |
8bae0a0c JSC |
2431 | default: |
2432 | printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt)); | |
2433 | break; | |
2434 | } | |
2435 | ||
2436 | #ifdef DEBUG | |
53b9417e | 2437 | printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2438 | #endif /* DEBUG */ |
2439 | ||
2440 | return(boolean); | |
2441 | } | |
2442 | ||
18c64df6 | 2443 | int |
8bae0a0c | 2444 | Less(op1,op2,fmt) |
e871dd18 JSC |
2445 | uword64 op1; |
2446 | uword64 op2; | |
8bae0a0c JSC |
2447 | FP_formats fmt; |
2448 | { | |
2449 | int boolean = 0; | |
2450 | ||
e871dd18 JSC |
2451 | /* Argument checking already performed by the FPCOMPARE code */ |
2452 | ||
8bae0a0c | 2453 | #ifdef DEBUG |
53b9417e | 2454 | printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2455 | #endif /* DEBUG */ |
2456 | ||
8bae0a0c JSC |
2457 | /* The format type should already have been checked: */ |
2458 | switch (fmt) { | |
2459 | case fmt_single: | |
2460 | { | |
76ef4165 FL |
2461 | sim_fpu wop1; |
2462 | sim_fpu wop2; | |
2463 | sim_fpu_32to (&wop1, op1); | |
2464 | sim_fpu_32to (&wop2, op2); | |
2465 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2466 | break; | |
8bae0a0c | 2467 | } |
8bae0a0c | 2468 | case fmt_double: |
76ef4165 FL |
2469 | { |
2470 | sim_fpu wop1; | |
2471 | sim_fpu wop2; | |
2472 | sim_fpu_64to (&wop1, op1); | |
2473 | sim_fpu_64to (&wop2, op2); | |
2474 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2475 | break; | |
2476 | } | |
50a2a691 AC |
2477 | default: |
2478 | fprintf (stderr, "Bad switch\n"); | |
2479 | abort (); | |
8bae0a0c JSC |
2480 | } |
2481 | ||
2482 | #ifdef DEBUG | |
2483 | printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2484 | #endif /* DEBUG */ | |
2485 | ||
2486 | return(boolean); | |
2487 | } | |
2488 | ||
18c64df6 | 2489 | int |
8bae0a0c | 2490 | Equal(op1,op2,fmt) |
e871dd18 JSC |
2491 | uword64 op1; |
2492 | uword64 op2; | |
8bae0a0c JSC |
2493 | FP_formats fmt; |
2494 | { | |
2495 | int boolean = 0; | |
2496 | ||
e871dd18 JSC |
2497 | /* Argument checking already performed by the FPCOMPARE code */ |
2498 | ||
8bae0a0c | 2499 | #ifdef DEBUG |
53b9417e | 2500 | printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2501 | #endif /* DEBUG */ |
2502 | ||
8bae0a0c JSC |
2503 | /* The format type should already have been checked: */ |
2504 | switch (fmt) { | |
2505 | case fmt_single: | |
76ef4165 FL |
2506 | { |
2507 | sim_fpu wop1; | |
2508 | sim_fpu wop2; | |
2509 | sim_fpu_32to (&wop1, op1); | |
2510 | sim_fpu_32to (&wop2, op2); | |
2511 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2512 | break; | |
2513 | } | |
8bae0a0c | 2514 | case fmt_double: |
76ef4165 FL |
2515 | { |
2516 | sim_fpu wop1; | |
2517 | sim_fpu wop2; | |
2518 | sim_fpu_64to (&wop1, op1); | |
2519 | sim_fpu_64to (&wop2, op2); | |
2520 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2521 | break; | |
2522 | } | |
50a2a691 AC |
2523 | default: |
2524 | fprintf (stderr, "Bad switch\n"); | |
2525 | abort (); | |
8bae0a0c JSC |
2526 | } |
2527 | ||
2528 | #ifdef DEBUG | |
2529 | printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2530 | #endif /* DEBUG */ | |
2531 | ||
2532 | return(boolean); | |
2533 | } | |
2534 | ||
18c64df6 | 2535 | uword64 |
a9f7253f JSC |
2536 | AbsoluteValue(op,fmt) |
2537 | uword64 op; | |
2538 | FP_formats fmt; | |
2539 | { | |
50a2a691 | 2540 | uword64 result = 0; |
a9f7253f JSC |
2541 | |
2542 | #ifdef DEBUG | |
53b9417e | 2543 | printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
a9f7253f JSC |
2544 | #endif /* DEBUG */ |
2545 | ||
2546 | /* The format type should already have been checked: */ | |
2547 | switch (fmt) { | |
2548 | case fmt_single: | |
2549 | { | |
76ef4165 FL |
2550 | sim_fpu wop; |
2551 | unsigned32 ans; | |
2552 | sim_fpu_32to (&wop, op); | |
2553 | sim_fpu_abs (&wop, &wop); | |
2554 | sim_fpu_to32 (&ans, &wop); | |
2555 | result = ans; | |
2556 | break; | |
a9f7253f | 2557 | } |
a9f7253f JSC |
2558 | case fmt_double: |
2559 | { | |
76ef4165 FL |
2560 | sim_fpu wop; |
2561 | unsigned64 ans; | |
2562 | sim_fpu_64to (&wop, op); | |
2563 | sim_fpu_abs (&wop, &wop); | |
2564 | sim_fpu_to64 (&ans, &wop); | |
2565 | result = ans; | |
2566 | break; | |
a9f7253f | 2567 | } |
50a2a691 AC |
2568 | default: |
2569 | fprintf (stderr, "Bad switch\n"); | |
2570 | abort (); | |
a9f7253f JSC |
2571 | } |
2572 | ||
2573 | return(result); | |
2574 | } | |
2575 | ||
18c64df6 | 2576 | uword64 |
8bae0a0c | 2577 | Negate(op,fmt) |
e871dd18 | 2578 | uword64 op; |
8bae0a0c JSC |
2579 | FP_formats fmt; |
2580 | { | |
50a2a691 | 2581 | uword64 result = 0; |
8bae0a0c JSC |
2582 | |
2583 | #ifdef DEBUG | |
53b9417e | 2584 | printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2585 | #endif /* DEBUG */ |
2586 | ||
2587 | /* The format type should already have been checked: */ | |
2588 | switch (fmt) { | |
2589 | case fmt_single: | |
2590 | { | |
76ef4165 FL |
2591 | sim_fpu wop; |
2592 | unsigned32 ans; | |
2593 | sim_fpu_32to (&wop, op); | |
2594 | sim_fpu_neg (&wop, &wop); | |
2595 | sim_fpu_to32 (&ans, &wop); | |
2596 | result = ans; | |
2597 | break; | |
8bae0a0c | 2598 | } |
8bae0a0c JSC |
2599 | case fmt_double: |
2600 | { | |
76ef4165 FL |
2601 | sim_fpu wop; |
2602 | unsigned64 ans; | |
2603 | sim_fpu_64to (&wop, op); | |
2604 | sim_fpu_neg (&wop, &wop); | |
2605 | sim_fpu_to64 (&ans, &wop); | |
2606 | result = ans; | |
2607 | break; | |
8bae0a0c | 2608 | } |
50a2a691 AC |
2609 | default: |
2610 | fprintf (stderr, "Bad switch\n"); | |
2611 | abort (); | |
8bae0a0c JSC |
2612 | } |
2613 | ||
2614 | return(result); | |
2615 | } | |
2616 | ||
18c64df6 | 2617 | uword64 |
8bae0a0c | 2618 | Add(op1,op2,fmt) |
e871dd18 JSC |
2619 | uword64 op1; |
2620 | uword64 op2; | |
8bae0a0c JSC |
2621 | FP_formats fmt; |
2622 | { | |
50a2a691 | 2623 | uword64 result = 0; |
8bae0a0c JSC |
2624 | |
2625 | #ifdef DEBUG | |
53b9417e | 2626 | printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2627 | #endif /* DEBUG */ |
2628 | ||
e871dd18 JSC |
2629 | /* The registers must specify FPRs valid for operands of type |
2630 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2631 | |
2632 | /* The format type should already have been checked: */ | |
2633 | switch (fmt) { | |
2634 | case fmt_single: | |
2635 | { | |
76ef4165 FL |
2636 | sim_fpu wop1; |
2637 | sim_fpu wop2; | |
2638 | sim_fpu ans; | |
2639 | unsigned32 res; | |
2640 | sim_fpu_32to (&wop1, op1); | |
2641 | sim_fpu_32to (&wop2, op2); | |
2642 | sim_fpu_add (&ans, &wop1, &wop2); | |
2643 | sim_fpu_to32 (&res, &ans); | |
2644 | result = res; | |
2645 | break; | |
8bae0a0c | 2646 | } |
8bae0a0c JSC |
2647 | case fmt_double: |
2648 | { | |
76ef4165 FL |
2649 | sim_fpu wop1; |
2650 | sim_fpu wop2; | |
2651 | sim_fpu ans; | |
2652 | unsigned64 res; | |
2653 | sim_fpu_64to (&wop1, op1); | |
2654 | sim_fpu_64to (&wop2, op2); | |
2655 | sim_fpu_add (&ans, &wop1, &wop2); | |
2656 | sim_fpu_to64 (&res, &ans); | |
2657 | result = res; | |
2658 | break; | |
8bae0a0c | 2659 | } |
50a2a691 AC |
2660 | default: |
2661 | fprintf (stderr, "Bad switch\n"); | |
2662 | abort (); | |
8bae0a0c JSC |
2663 | } |
2664 | ||
2665 | #ifdef DEBUG | |
53b9417e | 2666 | printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2667 | #endif /* DEBUG */ |
2668 | ||
2669 | return(result); | |
2670 | } | |
2671 | ||
18c64df6 | 2672 | uword64 |
8bae0a0c | 2673 | Sub(op1,op2,fmt) |
e871dd18 JSC |
2674 | uword64 op1; |
2675 | uword64 op2; | |
8bae0a0c JSC |
2676 | FP_formats fmt; |
2677 | { | |
50a2a691 | 2678 | uword64 result = 0; |
8bae0a0c JSC |
2679 | |
2680 | #ifdef DEBUG | |
53b9417e | 2681 | printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2682 | #endif /* DEBUG */ |
2683 | ||
e871dd18 JSC |
2684 | /* The registers must specify FPRs valid for operands of type |
2685 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2686 | |
2687 | /* The format type should already have been checked: */ | |
2688 | switch (fmt) { | |
2689 | case fmt_single: | |
2690 | { | |
76ef4165 FL |
2691 | sim_fpu wop1; |
2692 | sim_fpu wop2; | |
2693 | sim_fpu ans; | |
2694 | unsigned32 res; | |
2695 | sim_fpu_32to (&wop1, op1); | |
2696 | sim_fpu_32to (&wop2, op2); | |
2697 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2698 | sim_fpu_to32 (&res, &ans); | |
2699 | result = res; | |
8bae0a0c JSC |
2700 | } |
2701 | break; | |
2702 | case fmt_double: | |
2703 | { | |
76ef4165 FL |
2704 | sim_fpu wop1; |
2705 | sim_fpu wop2; | |
2706 | sim_fpu ans; | |
2707 | unsigned64 res; | |
2708 | sim_fpu_64to (&wop1, op1); | |
2709 | sim_fpu_64to (&wop2, op2); | |
2710 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2711 | sim_fpu_to64 (&res, &ans); | |
2712 | result = res; | |
8bae0a0c JSC |
2713 | } |
2714 | break; | |
50a2a691 AC |
2715 | default: |
2716 | fprintf (stderr, "Bad switch\n"); | |
2717 | abort (); | |
8bae0a0c JSC |
2718 | } |
2719 | ||
2720 | #ifdef DEBUG | |
53b9417e | 2721 | printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2722 | #endif /* DEBUG */ |
2723 | ||
2724 | return(result); | |
2725 | } | |
2726 | ||
18c64df6 | 2727 | uword64 |
8bae0a0c | 2728 | Multiply(op1,op2,fmt) |
e871dd18 JSC |
2729 | uword64 op1; |
2730 | uword64 op2; | |
8bae0a0c JSC |
2731 | FP_formats fmt; |
2732 | { | |
50a2a691 | 2733 | uword64 result = 0; |
8bae0a0c JSC |
2734 | |
2735 | #ifdef DEBUG | |
53b9417e | 2736 | printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2737 | #endif /* DEBUG */ |
2738 | ||
e871dd18 JSC |
2739 | /* The registers must specify FPRs valid for operands of type |
2740 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2741 | |
2742 | /* The format type should already have been checked: */ | |
2743 | switch (fmt) { | |
2744 | case fmt_single: | |
2745 | { | |
76ef4165 FL |
2746 | sim_fpu wop1; |
2747 | sim_fpu wop2; | |
2748 | sim_fpu ans; | |
2749 | unsigned32 res; | |
2750 | sim_fpu_32to (&wop1, op1); | |
2751 | sim_fpu_32to (&wop2, op2); | |
2752 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2753 | sim_fpu_to32 (&res, &ans); | |
2754 | result = res; | |
2755 | break; | |
8bae0a0c | 2756 | } |
8bae0a0c JSC |
2757 | case fmt_double: |
2758 | { | |
76ef4165 FL |
2759 | sim_fpu wop1; |
2760 | sim_fpu wop2; | |
2761 | sim_fpu ans; | |
2762 | unsigned64 res; | |
2763 | sim_fpu_64to (&wop1, op1); | |
2764 | sim_fpu_64to (&wop2, op2); | |
2765 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2766 | sim_fpu_to64 (&res, &ans); | |
2767 | result = res; | |
2768 | break; | |
8bae0a0c | 2769 | } |
50a2a691 AC |
2770 | default: |
2771 | fprintf (stderr, "Bad switch\n"); | |
2772 | abort (); | |
8bae0a0c JSC |
2773 | } |
2774 | ||
2775 | #ifdef DEBUG | |
53b9417e | 2776 | printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2777 | #endif /* DEBUG */ |
2778 | ||
2779 | return(result); | |
2780 | } | |
2781 | ||
18c64df6 | 2782 | uword64 |
8bae0a0c | 2783 | Divide(op1,op2,fmt) |
e871dd18 JSC |
2784 | uword64 op1; |
2785 | uword64 op2; | |
8bae0a0c JSC |
2786 | FP_formats fmt; |
2787 | { | |
50a2a691 | 2788 | uword64 result = 0; |
8bae0a0c JSC |
2789 | |
2790 | #ifdef DEBUG | |
53b9417e | 2791 | printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2792 | #endif /* DEBUG */ |
2793 | ||
e871dd18 JSC |
2794 | /* The registers must specify FPRs valid for operands of type |
2795 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2796 | |
2797 | /* The format type should already have been checked: */ | |
2798 | switch (fmt) { | |
2799 | case fmt_single: | |
2800 | { | |
76ef4165 FL |
2801 | sim_fpu wop1; |
2802 | sim_fpu wop2; | |
2803 | sim_fpu ans; | |
2804 | unsigned32 res; | |
2805 | sim_fpu_32to (&wop1, op1); | |
2806 | sim_fpu_32to (&wop2, op2); | |
2807 | sim_fpu_div (&ans, &wop1, &wop2); | |
2808 | sim_fpu_to32 (&res, &ans); | |
2809 | result = res; | |
2810 | break; | |
8bae0a0c | 2811 | } |
8bae0a0c JSC |
2812 | case fmt_double: |
2813 | { | |
76ef4165 FL |
2814 | sim_fpu wop1; |
2815 | sim_fpu wop2; | |
2816 | sim_fpu ans; | |
2817 | unsigned64 res; | |
2818 | sim_fpu_64to (&wop1, op1); | |
2819 | sim_fpu_64to (&wop2, op2); | |
2820 | sim_fpu_div (&ans, &wop1, &wop2); | |
2821 | sim_fpu_to64 (&res, &ans); | |
2822 | result = res; | |
2823 | break; | |
8bae0a0c | 2824 | } |
50a2a691 AC |
2825 | default: |
2826 | fprintf (stderr, "Bad switch\n"); | |
2827 | abort (); | |
8bae0a0c JSC |
2828 | } |
2829 | ||
2830 | #ifdef DEBUG | |
53b9417e | 2831 | printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2832 | #endif /* DEBUG */ |
2833 | ||
2834 | return(result); | |
2835 | } | |
2836 | ||
18c64df6 | 2837 | uword64 UNUSED |
8bae0a0c | 2838 | Recip(op,fmt) |
e871dd18 | 2839 | uword64 op; |
8bae0a0c JSC |
2840 | FP_formats fmt; |
2841 | { | |
50a2a691 | 2842 | uword64 result = 0; |
8bae0a0c JSC |
2843 | |
2844 | #ifdef DEBUG | |
53b9417e | 2845 | printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2846 | #endif /* DEBUG */ |
2847 | ||
e871dd18 JSC |
2848 | /* The registers must specify FPRs valid for operands of type |
2849 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2850 | |
2851 | /* The format type should already have been checked: */ | |
2852 | switch (fmt) { | |
2853 | case fmt_single: | |
2854 | { | |
76ef4165 FL |
2855 | sim_fpu wop; |
2856 | sim_fpu ans; | |
2857 | unsigned32 res; | |
2858 | sim_fpu_32to (&wop, op); | |
2859 | sim_fpu_inv (&ans, &wop); | |
2860 | sim_fpu_to32 (&res, &ans); | |
2861 | result = res; | |
2862 | break; | |
8bae0a0c | 2863 | } |
8bae0a0c JSC |
2864 | case fmt_double: |
2865 | { | |
76ef4165 FL |
2866 | sim_fpu wop; |
2867 | sim_fpu ans; | |
2868 | unsigned64 res; | |
2869 | sim_fpu_64to (&wop, op); | |
2870 | sim_fpu_inv (&ans, &wop); | |
2871 | sim_fpu_to64 (&res, &ans); | |
2872 | result = res; | |
2873 | break; | |
8bae0a0c | 2874 | } |
50a2a691 AC |
2875 | default: |
2876 | fprintf (stderr, "Bad switch\n"); | |
2877 | abort (); | |
8bae0a0c JSC |
2878 | } |
2879 | ||
2880 | #ifdef DEBUG | |
53b9417e | 2881 | printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2882 | #endif /* DEBUG */ |
2883 | ||
2884 | return(result); | |
2885 | } | |
2886 | ||
18c64df6 | 2887 | uword64 |
8bae0a0c | 2888 | SquareRoot(op,fmt) |
e871dd18 | 2889 | uword64 op; |
8bae0a0c JSC |
2890 | FP_formats fmt; |
2891 | { | |
50a2a691 | 2892 | uword64 result = 0; |
8bae0a0c JSC |
2893 | |
2894 | #ifdef DEBUG | |
53b9417e | 2895 | printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2896 | #endif /* DEBUG */ |
2897 | ||
e871dd18 JSC |
2898 | /* The registers must specify FPRs valid for operands of type |
2899 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2900 | |
2901 | /* The format type should already have been checked: */ | |
2902 | switch (fmt) { | |
2903 | case fmt_single: | |
2904 | { | |
76ef4165 FL |
2905 | sim_fpu wop; |
2906 | sim_fpu ans; | |
2907 | unsigned32 res; | |
2908 | sim_fpu_32to (&wop, op); | |
2909 | sim_fpu_sqrt (&ans, &wop); | |
2910 | sim_fpu_to32 (&res, &ans); | |
2911 | result = res; | |
2912 | break; | |
8bae0a0c | 2913 | } |
8bae0a0c JSC |
2914 | case fmt_double: |
2915 | { | |
76ef4165 FL |
2916 | sim_fpu wop; |
2917 | sim_fpu ans; | |
2918 | unsigned64 res; | |
2919 | sim_fpu_64to (&wop, op); | |
2920 | sim_fpu_sqrt (&ans, &wop); | |
2921 | sim_fpu_to64 (&res, &ans); | |
2922 | result = res; | |
2923 | break; | |
8bae0a0c | 2924 | } |
50a2a691 AC |
2925 | default: |
2926 | fprintf (stderr, "Bad switch\n"); | |
2927 | abort (); | |
8bae0a0c JSC |
2928 | } |
2929 | ||
2930 | #ifdef DEBUG | |
53b9417e | 2931 | printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2932 | #endif /* DEBUG */ |
2933 | ||
2934 | return(result); | |
2935 | } | |
2936 | ||
82ea14fd | 2937 | #if 0 |
a48e8c8d AC |
2938 | uword64 |
2939 | Max (uword64 op1, | |
2940 | uword64 op2, | |
2941 | FP_formats fmt) | |
2942 | { | |
2943 | int cmp; | |
2944 | unsigned64 result; | |
2945 | ||
2946 | #ifdef DEBUG | |
2947 | printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
2948 | #endif /* DEBUG */ | |
2949 | ||
2950 | /* The registers must specify FPRs valid for operands of type | |
2951 | "fmt". If they are not valid, the result is undefined. */ | |
2952 | ||
2953 | /* The format type should already have been checked: */ | |
2954 | switch (fmt) | |
2955 | { | |
2956 | case fmt_single: | |
2957 | { | |
2958 | sim_fpu wop1; | |
2959 | sim_fpu wop2; | |
2960 | sim_fpu_32to (&wop1, op1); | |
2961 | sim_fpu_32to (&wop2, op2); | |
2962 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
2963 | break; | |
2964 | } | |
2965 | case fmt_double: | |
2966 | { | |
2967 | sim_fpu wop1; | |
2968 | sim_fpu wop2; | |
2969 | sim_fpu_64to (&wop1, op1); | |
2970 | sim_fpu_64to (&wop2, op2); | |
2971 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
2972 | break; | |
2973 | } | |
2974 | default: | |
2975 | fprintf (stderr, "Bad switch\n"); | |
2976 | abort (); | |
2977 | } | |
2978 | ||
2979 | switch (cmp) | |
2980 | { | |
2981 | case SIM_FPU_IS_SNAN: | |
2982 | case SIM_FPU_IS_QNAN: | |
2983 | result = op1; | |
2984 | case SIM_FPU_IS_NINF: | |
2985 | case SIM_FPU_IS_NNUMBER: | |
2986 | case SIM_FPU_IS_NDENORM: | |
2987 | case SIM_FPU_IS_NZERO: | |
2988 | result = op2; /* op1 - op2 < 0 */ | |
2989 | case SIM_FPU_IS_PINF: | |
2990 | case SIM_FPU_IS_PNUMBER: | |
2991 | case SIM_FPU_IS_PDENORM: | |
2992 | case SIM_FPU_IS_PZERO: | |
2993 | result = op1; /* op1 - op2 > 0 */ | |
2994 | default: | |
2995 | fprintf (stderr, "Bad switch\n"); | |
2996 | abort (); | |
2997 | } | |
2998 | ||
2999 | #ifdef DEBUG | |
3000 | printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
3001 | #endif /* DEBUG */ | |
3002 | ||
3003 | return(result); | |
3004 | } | |
82ea14fd | 3005 | #endif |
a48e8c8d | 3006 | |
82ea14fd | 3007 | #if 0 |
a48e8c8d AC |
3008 | uword64 |
3009 | Min (uword64 op1, | |
3010 | uword64 op2, | |
3011 | FP_formats fmt) | |
3012 | { | |
3013 | int cmp; | |
3014 | unsigned64 result; | |
3015 | ||
3016 | #ifdef DEBUG | |
3017 | printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
3018 | #endif /* DEBUG */ | |
3019 | ||
3020 | /* The registers must specify FPRs valid for operands of type | |
3021 | "fmt". If they are not valid, the result is undefined. */ | |
3022 | ||
3023 | /* The format type should already have been checked: */ | |
3024 | switch (fmt) | |
3025 | { | |
3026 | case fmt_single: | |
3027 | { | |
3028 | sim_fpu wop1; | |
3029 | sim_fpu wop2; | |
3030 | sim_fpu_32to (&wop1, op1); | |
3031 | sim_fpu_32to (&wop2, op2); | |
3032 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
3033 | break; | |
3034 | } | |
3035 | case fmt_double: | |
3036 | { | |
3037 | sim_fpu wop1; | |
3038 | sim_fpu wop2; | |
3039 | sim_fpu_64to (&wop1, op1); | |
3040 | sim_fpu_64to (&wop2, op2); | |
3041 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
3042 | break; | |
3043 | } | |
3044 | default: | |
3045 | fprintf (stderr, "Bad switch\n"); | |
3046 | abort (); | |
3047 | } | |
3048 | ||
3049 | switch (cmp) | |
3050 | { | |
3051 | case SIM_FPU_IS_SNAN: | |
3052 | case SIM_FPU_IS_QNAN: | |
3053 | result = op1; | |
3054 | case SIM_FPU_IS_NINF: | |
3055 | case SIM_FPU_IS_NNUMBER: | |
3056 | case SIM_FPU_IS_NDENORM: | |
3057 | case SIM_FPU_IS_NZERO: | |
3058 | result = op1; /* op1 - op2 < 0 */ | |
3059 | case SIM_FPU_IS_PINF: | |
3060 | case SIM_FPU_IS_PNUMBER: | |
3061 | case SIM_FPU_IS_PDENORM: | |
3062 | case SIM_FPU_IS_PZERO: | |
3063 | result = op2; /* op1 - op2 > 0 */ | |
3064 | default: | |
3065 | fprintf (stderr, "Bad switch\n"); | |
3066 | abort (); | |
3067 | } | |
3068 | ||
3069 | #ifdef DEBUG | |
3070 | printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
3071 | #endif /* DEBUG */ | |
3072 | ||
3073 | return(result); | |
3074 | } | |
82ea14fd | 3075 | #endif |
a48e8c8d | 3076 | |
18c64df6 | 3077 | uword64 |
01737f42 AC |
3078 | convert (SIM_DESC sd, |
3079 | sim_cpu *cpu, | |
3080 | address_word cia, | |
3081 | int rm, | |
3082 | uword64 op, | |
3083 | FP_formats from, | |
3084 | FP_formats to) | |
8bae0a0c | 3085 | { |
76ef4165 FL |
3086 | sim_fpu wop; |
3087 | sim_fpu_round round; | |
3088 | unsigned32 result32; | |
3089 | unsigned64 result64; | |
8bae0a0c JSC |
3090 | |
3091 | #ifdef DEBUG | |
53b9417e | 3092 | printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC)); |
8bae0a0c JSC |
3093 | #endif /* DEBUG */ |
3094 | ||
76ef4165 | 3095 | switch (rm) |
8bae0a0c | 3096 | { |
76ef4165 FL |
3097 | case FP_RM_NEAREST: |
3098 | /* Round result to nearest representable value. When two | |
3099 | representable values are equally near, round to the value | |
3100 | that has a least significant bit of zero (i.e. is even). */ | |
3101 | round = sim_fpu_round_near; | |
3102 | break; | |
3103 | case FP_RM_TOZERO: | |
3104 | /* Round result to the value closest to, and not greater in | |
3105 | magnitude than, the result. */ | |
3106 | round = sim_fpu_round_zero; | |
3107 | break; | |
3108 | case FP_RM_TOPINF: | |
3109 | /* Round result to the value closest to, and not less than, | |
3110 | the result. */ | |
3111 | round = sim_fpu_round_up; | |
3112 | break; | |
3113 | ||
3114 | case FP_RM_TOMINF: | |
3115 | /* Round result to the value closest to, and not greater than, | |
3116 | the result. */ | |
3117 | round = sim_fpu_round_down; | |
3118 | break; | |
3119 | default: | |
3120 | round = 0; | |
3121 | fprintf (stderr, "Bad switch\n"); | |
3122 | abort (); | |
8bae0a0c | 3123 | } |
76ef4165 FL |
3124 | |
3125 | /* Convert the input to sim_fpu internal format */ | |
3126 | switch (from) | |
8bae0a0c | 3127 | { |
76ef4165 FL |
3128 | case fmt_double: |
3129 | sim_fpu_64to (&wop, op); | |
3130 | break; | |
3131 | case fmt_single: | |
3132 | sim_fpu_32to (&wop, op); | |
3133 | break; | |
3134 | case fmt_word: | |
3135 | sim_fpu_i32to (&wop, op, round); | |
3136 | break; | |
3137 | case fmt_long: | |
3138 | sim_fpu_i64to (&wop, op, round); | |
3139 | break; | |
3140 | default: | |
3141 | fprintf (stderr, "Bad switch\n"); | |
3142 | abort (); | |
8bae0a0c | 3143 | } |
8bae0a0c | 3144 | |
76ef4165 FL |
3145 | /* Convert sim_fpu format into the output */ |
3146 | /* The value WOP is converted to the destination format, rounding | |
3147 | using mode RM. When the destination is a fixed-point format, then | |
3148 | a source value of Infinity, NaN or one which would round to an | |
3149 | integer outside the fixed point range then an IEEE Invalid | |
3150 | Operation condition is raised. */ | |
3151 | switch (to) | |
3152 | { | |
3153 | case fmt_single: | |
3154 | sim_fpu_round_32 (&wop, round, 0); | |
3155 | sim_fpu_to32 (&result32, &wop); | |
3156 | result64 = result32; | |
3157 | break; | |
3158 | case fmt_double: | |
3159 | sim_fpu_round_64 (&wop, round, 0); | |
3160 | sim_fpu_to64 (&result64, &wop); | |
3161 | break; | |
3162 | case fmt_word: | |
3163 | sim_fpu_to32i (&result32, &wop, round); | |
3164 | result64 = result32; | |
3165 | break; | |
3166 | case fmt_long: | |
3167 | sim_fpu_to64i (&result64, &wop, round); | |
3168 | break; | |
3169 | default: | |
3170 | result64 = 0; | |
3171 | fprintf (stderr, "Bad switch\n"); | |
3172 | abort (); | |
8bae0a0c | 3173 | } |
76ef4165 | 3174 | |
8bae0a0c | 3175 | #ifdef DEBUG |
76ef4165 | 3176 | printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to)); |
8bae0a0c JSC |
3177 | #endif /* DEBUG */ |
3178 | ||
76ef4165 | 3179 | return(result64); |
8bae0a0c | 3180 | } |
8bae0a0c | 3181 | |
76ef4165 | 3182 | |
8bae0a0c JSC |
3183 | /*-- co-processor support routines ------------------------------------------*/ |
3184 | ||
2f2e6c5d | 3185 | static int UNUSED |
8bae0a0c JSC |
3186 | CoProcPresent(coproc_number) |
3187 | unsigned int coproc_number; | |
3188 | { | |
3189 | /* Return TRUE if simulator provides a model for the given co-processor number */ | |
3190 | return(0); | |
3191 | } | |
3192 | ||
18c64df6 | 3193 | void |
01737f42 AC |
3194 | cop_lw (SIM_DESC sd, |
3195 | sim_cpu *cpu, | |
3196 | address_word cia, | |
3197 | int coproc_num, | |
3198 | int coproc_reg, | |
3199 | unsigned int memword) | |
8bae0a0c | 3200 | { |
192ae475 AC |
3201 | switch (coproc_num) |
3202 | { | |
8bae0a0c | 3203 | case 1: |
192ae475 AC |
3204 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3205 | { | |
8bae0a0c | 3206 | #ifdef DEBUG |
192ae475 | 3207 | printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword)); |
8bae0a0c | 3208 | #endif |
192ae475 AC |
3209 | StoreFPR(coproc_reg,fmt_word,(uword64)memword); |
3210 | FPR_STATE[coproc_reg] = fmt_uninterpreted; | |
3211 | break; | |
3212 | } | |
8bae0a0c JSC |
3213 | |
3214 | default: | |
f24b7b69 | 3215 | #if 0 /* this should be controlled by a configuration option */ |
192ae475 | 3216 | sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia)); |
f24b7b69 | 3217 | #endif |
192ae475 AC |
3218 | break; |
3219 | } | |
8bae0a0c JSC |
3220 | |
3221 | return; | |
3222 | } | |
3223 | ||
18c64df6 | 3224 | void |
01737f42 AC |
3225 | cop_ld (SIM_DESC sd, |
3226 | sim_cpu *cpu, | |
3227 | address_word cia, | |
3228 | int coproc_num, | |
3229 | int coproc_reg, | |
3230 | uword64 memword) | |
8bae0a0c JSC |
3231 | { |
3232 | switch (coproc_num) { | |
8bae0a0c | 3233 | case 1: |
192ae475 AC |
3234 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3235 | { | |
3236 | StoreFPR(coproc_reg,fmt_uninterpreted,memword); | |
3237 | break; | |
3238 | } | |
8bae0a0c JSC |
3239 | |
3240 | default: | |
f24b7b69 | 3241 | #if 0 /* this message should be controlled by a configuration option */ |
95469ceb | 3242 | sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia)); |
f24b7b69 | 3243 | #endif |
8bae0a0c JSC |
3244 | break; |
3245 | } | |
3246 | ||
3247 | return; | |
3248 | } | |
3249 | ||
15232df4 FCE |
3250 | |
3251 | void | |
3252 | cop_lq (SIM_DESC sd, | |
3253 | sim_cpu *cpu, | |
3254 | address_word cia, | |
3255 | int coproc_num, | |
3256 | int coproc_reg, | |
3257 | unsigned128 memword) | |
3258 | { | |
3259 | switch (coproc_num) | |
3260 | { | |
3261 | /* start-sanitize-sky */ | |
3262 | case 2: | |
3263 | /* XXX COP2 */ | |
3264 | break; | |
3265 | /* end-sanitize-sky */ | |
3266 | ||
3267 | default: | |
3268 | sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n", | |
3269 | coproc_num,coproc_reg,pr_addr(cia)); | |
3270 | break; | |
3271 | } | |
3272 | ||
3273 | return; | |
3274 | } | |
3275 | ||
3276 | ||
18c64df6 | 3277 | unsigned int |
01737f42 AC |
3278 | cop_sw (SIM_DESC sd, |
3279 | sim_cpu *cpu, | |
3280 | address_word cia, | |
3281 | int coproc_num, | |
3282 | int coproc_reg) | |
8bae0a0c JSC |
3283 | { |
3284 | unsigned int value = 0; | |
da0bce9c | 3285 | |
192ae475 AC |
3286 | switch (coproc_num) |
3287 | { | |
8bae0a0c | 3288 | case 1: |
192ae475 AC |
3289 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3290 | { | |
3291 | FP_formats hold; | |
3292 | hold = FPR_STATE[coproc_reg]; | |
3293 | FPR_STATE[coproc_reg] = fmt_word; | |
3294 | value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted); | |
3295 | FPR_STATE[coproc_reg] = hold; | |
3296 | break; | |
3297 | } | |
8bae0a0c JSC |
3298 | |
3299 | default: | |
f24b7b69 | 3300 | #if 0 /* should be controlled by configuration option */ |
192ae475 | 3301 | sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); |
f24b7b69 | 3302 | #endif |
192ae475 AC |
3303 | break; |
3304 | } | |
8bae0a0c JSC |
3305 | |
3306 | return(value); | |
3307 | } | |
3308 | ||
18c64df6 | 3309 | uword64 |
01737f42 AC |
3310 | cop_sd (SIM_DESC sd, |
3311 | sim_cpu *cpu, | |
3312 | address_word cia, | |
3313 | int coproc_num, | |
3314 | int coproc_reg) | |
8bae0a0c | 3315 | { |
e871dd18 | 3316 | uword64 value = 0; |
192ae475 AC |
3317 | switch (coproc_num) |
3318 | { | |
8bae0a0c | 3319 | case 1: |
192ae475 AC |
3320 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3321 | { | |
3322 | value = ValueFPR(coproc_reg,fmt_uninterpreted); | |
3323 | break; | |
3324 | } | |
8bae0a0c JSC |
3325 | |
3326 | default: | |
f24b7b69 | 3327 | #if 0 /* should be controlled by configuration option */ |
192ae475 | 3328 | sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); |
f24b7b69 | 3329 | #endif |
192ae475 AC |
3330 | break; |
3331 | } | |
8bae0a0c JSC |
3332 | |
3333 | return(value); | |
3334 | } | |
3335 | ||
15232df4 FCE |
3336 | |
3337 | unsigned128 | |
3338 | cop_sq (SIM_DESC sd, | |
3339 | sim_cpu *cpu, | |
3340 | address_word cia, | |
3341 | int coproc_num, | |
3342 | int coproc_reg) | |
3343 | { | |
3344 | unsigned128 value = {0, 0}; | |
3345 | switch (coproc_num) | |
3346 | { | |
3347 | /* start-sanitize-sky */ | |
3348 | case 2: | |
3349 | /* XXX COP2 */ | |
3350 | break; | |
3351 | /* end-sanitize-sky */ | |
3352 | ||
3353 | default: | |
3354 | sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n", | |
3355 | coproc_num,coproc_reg,pr_addr(cia)); | |
3356 | break; | |
3357 | } | |
3358 | ||
3359 | return(value); | |
3360 | } | |
3361 | ||
3362 | ||
ea985d24 | 3363 | void |
01737f42 AC |
3364 | decode_coproc (SIM_DESC sd, |
3365 | sim_cpu *cpu, | |
3366 | address_word cia, | |
3367 | unsigned int instruction) | |
8bae0a0c JSC |
3368 | { |
3369 | int coprocnum = ((instruction >> 26) & 3); | |
3370 | ||
56e7c849 AC |
3371 | switch (coprocnum) |
3372 | { | |
8bae0a0c JSC |
3373 | case 0: /* standard CPU control and cache registers */ |
3374 | { | |
8bae0a0c JSC |
3375 | int code = ((instruction >> 21) & 0x1F); |
3376 | /* R4000 Users Manual (second edition) lists the following CP0 | |
3377 | instructions: | |
56e7c849 AC |
3378 | DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000) |
3379 | DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000) | |
3380 | MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000) | |
3381 | MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000) | |
3382 | TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001) | |
3383 | TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010) | |
3384 | TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110) | |
3385 | TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000) | |
3386 | CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) | |
3387 | ERET Exception return (VR4100 = 01000010000000000000000000011000) | |
3388 | */ | |
3389 | if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) | |
3390 | { | |
3391 | int rt = ((instruction >> 16) & 0x1F); | |
3392 | int rd = ((instruction >> 11) & 0x1F); | |
3393 | ||
3394 | switch (rd) /* NOTEs: Standard CP0 registers */ | |
3395 | { | |
3396 | /* 0 = Index R4000 VR4100 VR4300 */ | |
3397 | /* 1 = Random R4000 VR4100 VR4300 */ | |
3398 | /* 2 = EntryLo0 R4000 VR4100 VR4300 */ | |
3399 | /* 3 = EntryLo1 R4000 VR4100 VR4300 */ | |
3400 | /* 4 = Context R4000 VR4100 VR4300 */ | |
3401 | /* 5 = PageMask R4000 VR4100 VR4300 */ | |
3402 | /* 6 = Wired R4000 VR4100 VR4300 */ | |
3403 | /* 8 = BadVAddr R4000 VR4100 VR4300 */ | |
3404 | /* 9 = Count R4000 VR4100 VR4300 */ | |
3405 | /* 10 = EntryHi R4000 VR4100 VR4300 */ | |
3406 | /* 11 = Compare R4000 VR4100 VR4300 */ | |
3407 | /* 12 = SR R4000 VR4100 VR4300 */ | |
3408 | case 12: | |
3409 | if (code == 0x00) | |
3410 | GPR[rt] = SR; | |
3411 | else | |
3412 | SR = GPR[rt]; | |
3413 | break; | |
3414 | /* 13 = Cause R4000 VR4100 VR4300 */ | |
05d1322f JL |
3415 | case 13: |
3416 | if (code == 0x00) | |
3417 | GPR[rt] = CAUSE; | |
3418 | else | |
3419 | CAUSE = GPR[rt]; | |
3420 | break; | |
56e7c849 AC |
3421 | /* 14 = EPC R4000 VR4100 VR4300 */ |
3422 | /* 15 = PRId R4000 VR4100 VR4300 */ | |
6eedf3f4 MA |
3423 | #ifdef SUBTARGET_R3900 |
3424 | /* 16 = Debug */ | |
3425 | case 16: | |
3426 | if (code == 0x00) | |
3427 | GPR[rt] = Debug; | |
3428 | else | |
3429 | Debug = GPR[rt]; | |
3430 | break; | |
3431 | #else | |
56e7c849 | 3432 | /* 16 = Config R4000 VR4100 VR4300 */ |
a09a30d2 AC |
3433 | case 16: |
3434 | if (code == 0x00) | |
3435 | GPR[rt] = C0_CONFIG; | |
3436 | else | |
3437 | C0_CONFIG = GPR[rt]; | |
3438 | break; | |
6eedf3f4 MA |
3439 | #endif |
3440 | #ifdef SUBTARGET_R3900 | |
3441 | /* 17 = Debug */ | |
3442 | case 17: | |
3443 | if (code == 0x00) | |
3444 | GPR[rt] = DEPC; | |
3445 | else | |
3446 | DEPC = GPR[rt]; | |
3447 | break; | |
3448 | #else | |
56e7c849 | 3449 | /* 17 = LLAddr R4000 VR4100 VR4300 */ |
6eedf3f4 | 3450 | #endif |
56e7c849 AC |
3451 | /* 18 = WatchLo R4000 VR4100 VR4300 */ |
3452 | /* 19 = WatchHi R4000 VR4100 VR4300 */ | |
3453 | /* 20 = XContext R4000 VR4100 VR4300 */ | |
3454 | /* 26 = PErr or ECC R4000 VR4100 VR4300 */ | |
3455 | /* 27 = CacheErr R4000 VR4100 */ | |
3456 | /* 28 = TagLo R4000 VR4100 VR4300 */ | |
3457 | /* 29 = TagHi R4000 VR4100 VR4300 */ | |
3458 | /* 30 = ErrorEPC R4000 VR4100 VR4300 */ | |
3459 | GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */ | |
3460 | /* CPR[0,rd] = GPR[rt]; */ | |
3461 | default: | |
3462 | if (code == 0x00) | |
18c64df6 | 3463 | sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 | 3464 | else |
18c64df6 | 3465 | sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 AC |
3466 | } |
3467 | } | |
3468 | else if (code == 0x10 && (instruction & 0x3f) == 0x18) | |
3469 | { | |
3470 | /* ERET */ | |
3471 | if (SR & status_ERL) | |
3472 | { | |
3473 | /* Oops, not yet available */ | |
18c64df6 | 3474 | sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet"); |
56e7c849 AC |
3475 | PC = EPC; |
3476 | SR &= ~status_ERL; | |
3477 | } | |
3478 | else | |
3479 | { | |
3480 | PC = EPC; | |
3481 | SR &= ~status_EXL; | |
3482 | } | |
3483 | } | |
6eedf3f4 MA |
3484 | else if (code == 0x10 && (instruction & 0x3f) == 0x10) |
3485 | { | |
3486 | /* RFE */ | |
3487 | } | |
3488 | else if (code == 0x10 && (instruction & 0x3f) == 0x1F) | |
3489 | { | |
3490 | /* DERET */ | |
3491 | Debug &= ~Debug_DM; | |
3492 | DELAYSLOT(); | |
3493 | DSPC = DEPC; | |
3494 | } | |
56e7c849 | 3495 | else |
95469ceb | 3496 | sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia)); |
e871dd18 | 3497 | /* TODO: When executing an ERET or RFE instruction we should |
8bae0a0c JSC |
3498 | clear LLBIT, to ensure that any out-standing atomic |
3499 | read/modify/write sequence fails. */ | |
3500 | } | |
56e7c849 AC |
3501 | break; |
3502 | ||
8bae0a0c | 3503 | case 2: /* undefined co-processor */ |
15232df4 FCE |
3504 | { |
3505 | int handle = 0; | |
3506 | ||
3507 | /* start-sanitize-sky */ | |
7dd4a466 | 3508 | #ifdef TARGET_SKY |
15232df4 FCE |
3509 | /* On the R5900, this refers to a "VU" vector co-processor. */ |
3510 | ||
3511 | int i_25_21 = (instruction >> 21) & 0x1f; | |
3512 | int i_20_16 = (instruction >> 16) & 0x1f; | |
3513 | int i_15_11 = (instruction >> 11) & 0x1f; | |
3514 | int i_15_0 = instruction & 0xffff; | |
3515 | int i_10_1 = (instruction >> 1) & 0x3ff; | |
3516 | int interlock = instruction & 0x01; | |
3517 | unsigned_4 vpe_status = sim_core_read_aligned_4 (cpu, cia, read_map, VPE0_STAT); | |
3518 | int vpe_busy = (vpe_status & 0x00000001); | |
3519 | /* setup for semantic.c-like actions below */ | |
3520 | typedef unsigned_4 instruction_word; | |
3521 | int CIA = cia; | |
3522 | int NIA = cia + 4; | |
3523 | sim_cpu* CPU_ = cpu; | |
3524 | ||
3525 | handle = 1; | |
3526 | ||
3527 | /* test COP2 usability */ | |
3528 | if(! (SR & status_CU2)) | |
3529 | { | |
3530 | SignalException(CoProcessorUnusable,instruction); | |
3531 | /* NOTREACHED */ | |
3532 | } | |
3533 | ||
3534 | /* classify & execute basic COP2 instructions */ | |
3535 | if(i_25_21 == 0x08 && i_20_16 == 0x00) /* BC2F */ | |
3536 | { | |
3537 | address_word offset = EXTEND16(i_15_0) << 2; | |
3538 | if(! vpe_busy) DELAY_SLOT(cia + 4 + offset); | |
3539 | } | |
3540 | else if(i_25_21 == 0x08 && i_20_16==0x02) /* BC2FL */ | |
3541 | { | |
3542 | address_word offset = EXTEND16(i_15_0) << 2; | |
3543 | if(! vpe_busy) DELAY_SLOT(cia + 4 + offset); | |
3544 | else NULLIFY_NEXT_INSTRUCTION(); | |
3545 | } | |
3546 | else if(i_25_21 == 0x08 && i_20_16 == 0x01) /* BC2T */ | |
3547 | { | |
3548 | address_word offset = EXTEND16(i_15_0) << 2; | |
3549 | if(vpe_busy) DELAY_SLOT(cia + 4 + offset); | |
3550 | } | |
3551 | else if(i_25_21 == 0x08 && i_20_16 == 0x03) /* BC2TL */ | |
3552 | { | |
3553 | address_word offset = EXTEND16(i_15_0) << 2; | |
3554 | if(vpe_busy) DELAY_SLOT(cia + 4 + offset); | |
3555 | else NULLIFY_NEXT_INSTRUCTION(); | |
3556 | } | |
3557 | else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */ | |
3558 | (i_25_21 == 0x06 && i_10_1 == 0x000)) /* CTC2 */ | |
3559 | { | |
3560 | int rt = i_20_16; | |
3561 | int id = i_15_11; | |
3562 | int to_vu = (i_25_21 == 0x06); /* transfer direction */ | |
3563 | address_word vu_cr_addr; /* VU control register address */ | |
3564 | ||
3565 | if(interlock) | |
3566 | while(vpe_busy) | |
3567 | { | |
3568 | vu0_issue(sd); /* advance one clock cycle */ | |
3569 | vpe_status = sim_core_read_aligned_4 (cpu, cia, read_map, VPE0_STAT); | |
3570 | vpe_busy = vpe_status & 0x00000001; | |
3571 | } | |
3572 | ||
3573 | /* compute VU register address */ | |
3574 | vu_cr_addr = VU0_MST + (id * 16); | |
3575 | ||
3576 | /* read or write word */ | |
3577 | if(to_vu) /* CTC2 */ | |
3578 | { | |
3579 | unsigned_4 data = GPR[rt]; | |
3580 | sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data); | |
3581 | } | |
3582 | else /* CFC2 */ | |
3583 | { | |
3584 | unsigned_4 data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr); | |
3585 | GPR[rt] = EXTEND64(data); | |
3586 | } | |
3587 | } | |
3588 | else if((i_25_21 == 0x01) || /* QMFC2 */ | |
3589 | (i_25_21 == 0x05)) /* QMTC2 */ | |
3590 | { | |
3591 | int rt = i_20_16; | |
3592 | int id = i_15_11; | |
3593 | int to_vu = (i_25_21 == 0x05); /* transfer direction */ | |
3594 | address_word vu_cr_addr; /* VU control register address */ | |
3595 | ||
3596 | if(interlock) | |
3597 | while(vpe_busy) | |
3598 | { | |
3599 | vu0_issue(sd); /* advance one clock cycle */ | |
3600 | vpe_status = sim_core_read_aligned_4 (cpu, cia, read_map, VPE0_STAT); | |
3601 | vpe_busy = vpe_status & 0x00000001; | |
3602 | } | |
3603 | ||
3604 | /* compute VU register address */ | |
3605 | vu_cr_addr = VU0_VF00 + (id * 16); | |
3606 | ||
3607 | /* read or write word */ | |
3608 | if(to_vu) /* CTC2 */ | |
3609 | { | |
3610 | unsigned_4 data = GPR[rt]; | |
3611 | sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data); | |
3612 | } | |
3613 | else /* CFC2 */ | |
3614 | { | |
3615 | unsigned_4 data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr); | |
3616 | GPR[rt] = EXTEND64(data); | |
3617 | } | |
3618 | } | |
3619 | /* other COP2 instructions */ | |
3620 | else | |
3621 | { | |
3622 | SignalException(ReservedInstruction,instruction); | |
3623 | /* NOTREACHED */ | |
3624 | } | |
3625 | ||
3626 | /* cleanup for semantic.c-like actions above */ | |
3627 | PC = NIA; | |
3628 | ||
7dd4a466 | 3629 | #endif /* TARGET_SKY */ |
15232df4 FCE |
3630 | /* end-sanitize-sky */ |
3631 | ||
3632 | if(! handle) | |
3633 | { | |
3634 | sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n", | |
3635 | instruction,pr_addr(cia)); | |
3636 | } | |
3637 | } | |
3638 | break; | |
3639 | ||
8bae0a0c JSC |
3640 | case 1: /* should not occur (FPU co-processor) */ |
3641 | case 3: /* should not occur (FPU co-processor) */ | |
3642 | SignalException(ReservedInstruction,instruction); | |
3643 | break; | |
56e7c849 AC |
3644 | } |
3645 | ||
8bae0a0c JSC |
3646 | return; |
3647 | } | |
3648 | ||
15232df4 | 3649 | |
8bae0a0c JSC |
3650 | /*-- instruction simulation -------------------------------------------------*/ |
3651 | ||
16bd5d6e AC |
3652 | /* When the IGEN simulator is being built, the function below is be |
3653 | replaced by a generated version. However, WITH_IGEN == 2 indicates | |
3654 | that the fubction below should be compiled but under a different | |
3655 | name (to allow backward compatibility) */ | |
3656 | ||
3657 | #if (WITH_IGEN != 1) | |
3658 | #if (WITH_IGEN > 1) | |
dad6f1f3 AC |
3659 | void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal)); |
3660 | void | |
9ec6741b | 3661 | old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) |
dad6f1f3 | 3662 | #else |
2e61a3ad | 3663 | void |
9ec6741b | 3664 | sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) |
dad6f1f3 | 3665 | #endif |
2e61a3ad AC |
3666 | SIM_DESC sd; |
3667 | int next_cpu_nr; /* ignore */ | |
9ec6741b | 3668 | int nr_cpus; /* ignore */ |
2e61a3ad | 3669 | int siggnal; /* ignore */ |
8bae0a0c | 3670 | { |
01737f42 | 3671 | sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */ |
50a2a691 | 3672 | #if !defined(FASTSIM) |
8bae0a0c | 3673 | unsigned int pipeline_count = 1; |
50a2a691 | 3674 | #endif |
8bae0a0c JSC |
3675 | |
3676 | #ifdef DEBUG | |
50a2a691 | 3677 | if (STATE_MEMORY (sd) == NULL) { |
8bae0a0c JSC |
3678 | printf("DBG: simulate() entered with no memory\n"); |
3679 | exit(1); | |
3680 | } | |
3681 | #endif /* DEBUG */ | |
3682 | ||
3683 | #if 0 /* Disabled to check that everything works OK */ | |
3684 | /* The VR4300 seems to sign-extend the PC on its first | |
3685 | access. However, this may just be because it is currently | |
3686 | configured in 32bit mode. However... */ | |
3687 | PC = SIGNEXTEND(PC,32); | |
3688 | #endif | |
3689 | ||
3690 | /* main controlling loop */ | |
2e61a3ad | 3691 | while (1) { |
7ce8b917 AC |
3692 | /* vaddr is slowly being replaced with cia - current instruction |
3693 | address */ | |
3694 | address_word cia = (uword64)PC; | |
3695 | address_word vaddr = cia; | |
dad6f1f3 | 3696 | address_word paddr; |
8bae0a0c | 3697 | int cca; |
53b9417e | 3698 | unsigned int instruction; /* uword64? what's this used for? FIXME! */ |
8bae0a0c JSC |
3699 | |
3700 | #ifdef DEBUG | |
3701 | { | |
3702 | printf("DBG: state = 0x%08X :",state); | |
8bae0a0c JSC |
3703 | if (state & simHALTEX) printf(" simHALTEX"); |
3704 | if (state & simHALTIN) printf(" simHALTIN"); | |
53b9417e | 3705 | printf("\n"); |
8bae0a0c JSC |
3706 | } |
3707 | #endif /* DEBUG */ | |
3708 | ||
0c2c5f61 | 3709 | DSSTATE = (STATE & simDELAYSLOT); |
8bae0a0c JSC |
3710 | #ifdef DEBUG |
3711 | if (dsstate) | |
18c64df6 | 3712 | sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3713 | #endif /* DEBUG */ |
3714 | ||
7ce8b917 AC |
3715 | /* Fetch the next instruction from the simulator memory: */ |
3716 | if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { | |
6429b296 JW |
3717 | if ((vaddr & 1) == 0) { |
3718 | /* Copy the action of the LW instruction */ | |
3719 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
3720 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
3721 | uword64 value; | |
3722 | unsigned int byte; | |
3723 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
53b9417e | 3724 | LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL); |
6429b296 JW |
3725 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); |
3726 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
3727 | } else { | |
3728 | /* Copy the action of the LH instruction */ | |
3729 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0); | |
3730 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0); | |
3731 | uword64 value; | |
3732 | unsigned int byte; | |
3733 | paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK) | |
3734 | | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1))); | |
53b9417e | 3735 | LoadMemory(&value,NULL,cca, AccessLength_HALFWORD, |
6429b296 JW |
3736 | paddr & ~ (uword64) 1, |
3737 | vaddr, isINSTRUCTION, isREAL); | |
3738 | byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1)); | |
3739 | instruction = ((value >> (8 * byte)) & 0xFFFF); | |
3740 | } | |
8bae0a0c | 3741 | } else { |
53b9417e | 3742 | fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC)); |
8bae0a0c JSC |
3743 | exit(1); |
3744 | } | |
3745 | ||
3746 | #ifdef DEBUG | |
18c64df6 | 3747 | sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC)); |
8bae0a0c JSC |
3748 | #endif /* DEBUG */ |
3749 | ||
8bae0a0c JSC |
3750 | /* This is required by exception processing, to ensure that we can |
3751 | cope with exceptions in the delay slots of branches that may | |
3752 | already have changed the PC. */ | |
6429b296 JW |
3753 | if ((vaddr & 1) == 0) |
3754 | PC += 4; /* increment ready for the next fetch */ | |
3755 | else | |
3756 | PC += 2; | |
8bae0a0c JSC |
3757 | /* NOTE: If we perform a delay slot change to the PC, this |
3758 | increment is not requuired. However, it would make the | |
3759 | simulator more complicated to try and avoid this small hit. */ | |
3760 | ||
3761 | /* Currently this code provides a simple model. For more | |
3762 | complicated models we could perform exception status checks at | |
3763 | this point, and set the simSTOP state as required. This could | |
3764 | also include processing any hardware interrupts raised by any | |
3765 | I/O model attached to the simulator context. | |
3766 | ||
3767 | Support for "asynchronous" I/O events within the simulated world | |
3768 | could be providing by managing a counter, and calling a I/O | |
3769 | specific handler when a particular threshold is reached. On most | |
3770 | architectures a decrement and check for zero operation is | |
3771 | usually quicker than an increment and compare. However, the | |
3772 | process of managing a known value decrement to zero, is higher | |
3773 | than the cost of using an explicit value UINT_MAX into the | |
3774 | future. Which system is used will depend on how complicated the | |
3775 | I/O model is, and how much it is likely to affect the simulator | |
3776 | bandwidth. | |
3777 | ||
3778 | If events need to be scheduled further in the future than | |
3779 | UINT_MAX event ticks, then the I/O model should just provide its | |
3780 | own counter, triggered from the event system. */ | |
3781 | ||
3782 | /* MIPS pipeline ticks. To allow for future support where the | |
3783 | pipeline hit of individual instructions is known, this control | |
3784 | loop manages a "pipeline_count" variable. It is initialised to | |
3785 | 1 (one), and will only be changed by the simulator engine when | |
3786 | executing an instruction. If the engine does not have access to | |
3787 | pipeline cycle count information then all instructions will be | |
3788 | treated as using a single cycle. NOTE: A standard system is not | |
3789 | provided by the default simulator because different MIPS | |
3790 | architectures have different cycle counts for the same | |
50a2a691 AC |
3791 | instructions. |
3792 | ||
3793 | [NOTE: pipeline_count has been replaced the event queue] */ | |
8bae0a0c | 3794 | |
a09a30d2 AC |
3795 | /* shuffle the floating point status pipeline state */ |
3796 | ENGINE_ISSUE_PREFIX_HOOK(); | |
8bae0a0c JSC |
3797 | |
3798 | /* NOTE: For multi-context simulation environments the "instruction" | |
3799 | variable should be local to this routine. */ | |
3800 | ||
3801 | /* Shorthand accesses for engine. Note: If we wanted to use global | |
3802 | variables (and a single-threaded simulator engine), then we can | |
3803 | create the actual variables with these names. */ | |
3804 | ||
0c2c5f61 | 3805 | if (!(STATE & simSKIPNEXT)) { |
8bae0a0c | 3806 | /* Include the simulator engine */ |
284e759d | 3807 | #include "oengine.c" |
f24b7b69 | 3808 | #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT) |
8bae0a0c JSC |
3809 | #error "Mismatch between run-time simulator code and simulation engine" |
3810 | #endif | |
18c64df6 AC |
3811 | #if (WITH_TARGET_WORD_BITSIZE != GPRLEN) |
3812 | #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN" | |
3813 | #endif | |
76ef4165 | 3814 | #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU)) |
18c64df6 AC |
3815 | #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU" |
3816 | #endif | |
8bae0a0c JSC |
3817 | |
3818 | #if defined(WARN_LOHI) | |
3819 | /* Decrement the HI/LO validity ticks */ | |
3820 | if (HIACCESS > 0) | |
3821 | HIACCESS--; | |
3822 | if (LOACCESS > 0) | |
3823 | LOACCESS--; | |
0425cfb3 | 3824 | /* start-sanitize-r5900 */ |
53b9417e DE |
3825 | if (HI1ACCESS > 0) |
3826 | HI1ACCESS--; | |
3827 | if (LO1ACCESS > 0) | |
3828 | LO1ACCESS--; | |
0425cfb3 | 3829 | /* end-sanitize-r5900 */ |
8bae0a0c JSC |
3830 | #endif /* WARN_LOHI */ |
3831 | ||
8bae0a0c JSC |
3832 | /* For certain MIPS architectures, GPR[0] is hardwired to zero. We |
3833 | should check for it being changed. It is better doing it here, | |
3834 | than within the simulator, since it will help keep the simulator | |
3835 | small. */ | |
3836 | if (ZERO != 0) { | |
05d1322f | 3837 | #if defined(WARN_ZERO) |
95469ceb | 3838 | sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia)); |
05d1322f | 3839 | #endif /* WARN_ZERO */ |
8bae0a0c JSC |
3840 | ZERO = 0; /* reset back to zero before next instruction */ |
3841 | } | |
8bae0a0c | 3842 | } else /* simSKIPNEXT check */ |
0c2c5f61 | 3843 | STATE &= ~simSKIPNEXT; |
8bae0a0c JSC |
3844 | |
3845 | /* If the delay slot was active before the instruction is | |
3846 | executed, then update the PC to its new value: */ | |
0c2c5f61 | 3847 | if (DSSTATE) { |
8bae0a0c | 3848 | #ifdef DEBUG |
53b9417e | 3849 | printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3850 | #endif /* DEBUG */ |
3851 | PC = DSPC; | |
6eedf3f4 | 3852 | CANCELDELAYSLOT(); |
8bae0a0c JSC |
3853 | } |
3854 | ||
2acd126a AC |
3855 | if (MIPSISA < 4) |
3856 | PENDING_TICK(); | |
8bae0a0c JSC |
3857 | |
3858 | #if !defined(FASTSIM) | |
50a2a691 AC |
3859 | if (sim_events_tickn (sd, pipeline_count)) |
3860 | { | |
3861 | /* cpu->cia = cia; */ | |
3862 | sim_events_process (sd); | |
3863 | } | |
3864 | #else | |
2e61a3ad AC |
3865 | if (sim_events_tick (sd)) |
3866 | { | |
3867 | /* cpu->cia = cia; */ | |
3868 | sim_events_process (sd); | |
3869 | } | |
50a2a691 | 3870 | #endif /* FASTSIM */ |
8bae0a0c | 3871 | } |
8bae0a0c | 3872 | } |
16bd5d6e AC |
3873 | #endif |
3874 | ||
8bae0a0c | 3875 | |
53b9417e DE |
3876 | /* This code copied from gdb's utils.c. Would like to share this code, |
3877 | but don't know of a common place where both could get to it. */ | |
3878 | ||
3879 | /* Temporary storage using circular buffer */ | |
3880 | #define NUMCELLS 16 | |
3881 | #define CELLSIZE 32 | |
3882 | static char* | |
3883 | get_cell() | |
3884 | { | |
3885 | static char buf[NUMCELLS][CELLSIZE]; | |
3886 | static int cell=0; | |
3887 | if (++cell>=NUMCELLS) cell=0; | |
3888 | return buf[cell]; | |
3889 | } | |
3890 | ||
3891 | /* Print routines to handle variable size regs, etc */ | |
3892 | ||
3893 | /* Eliminate warning from compiler on 32-bit systems */ | |
3894 | static int thirty_two = 32; | |
3895 | ||
3896 | char* | |
3897 | pr_addr(addr) | |
3898 | SIM_ADDR addr; | |
3899 | { | |
3900 | char *paddr_str=get_cell(); | |
3901 | switch (sizeof(addr)) | |
3902 | { | |
3903 | case 8: | |
50a2a691 | 3904 | sprintf(paddr_str,"%08lx%08lx", |
53b9417e DE |
3905 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3906 | break; | |
3907 | case 4: | |
50a2a691 | 3908 | sprintf(paddr_str,"%08lx",(unsigned long)addr); |
53b9417e DE |
3909 | break; |
3910 | case 2: | |
3911 | sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff)); | |
3912 | break; | |
3913 | default: | |
3914 | sprintf(paddr_str,"%x",addr); | |
3915 | } | |
3916 | return paddr_str; | |
3917 | } | |
3918 | ||
87e43259 AC |
3919 | char* |
3920 | pr_uword64(addr) | |
3921 | uword64 addr; | |
3922 | { | |
3923 | char *paddr_str=get_cell(); | |
50a2a691 | 3924 | sprintf(paddr_str,"%08lx%08lx", |
87e43259 AC |
3925 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3926 | return paddr_str; | |
3927 | } | |
3928 | ||
3929 | ||
2acd126a AC |
3930 | void |
3931 | pending_tick (SIM_DESC sd, | |
3932 | sim_cpu *cpu, | |
3933 | address_word cia) | |
3934 | { | |
3935 | if (PENDING_TRACE) | |
3936 | sim_io_printf (sd, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL); | |
3937 | if (PENDING_OUT != PENDING_IN) | |
3938 | { | |
3939 | int loop; | |
3940 | int index = PENDING_OUT; | |
3941 | int total = PENDING_TOTAL; | |
3942 | if (PENDING_TOTAL == 0) | |
3943 | sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n"); | |
3944 | for (loop = 0; (loop < total); loop++) | |
3945 | { | |
3946 | if (PENDING_SLOT_DEST[index] != NULL) | |
3947 | { | |
3948 | PENDING_SLOT_DELAY[index] -= 1; | |
3949 | if (PENDING_SLOT_DELAY[index] == 0) | |
3950 | { | |
3951 | if (PENDING_SLOT_BIT[index] >= 0) | |
3952 | switch (PENDING_SLOT_SIZE[index]) | |
3953 | { | |
3954 | case 32: | |
3955 | if (PENDING_SLOT_VALUE[index]) | |
3956 | *(unsigned32*)PENDING_SLOT_DEST[index] |= | |
3957 | BIT32 (PENDING_SLOT_BIT[index]); | |
3958 | else | |
3959 | *(unsigned32*)PENDING_SLOT_DEST[index] &= | |
3960 | BIT32 (PENDING_SLOT_BIT[index]); | |
3961 | break; | |
3962 | case 64: | |
3963 | if (PENDING_SLOT_VALUE[index]) | |
3964 | *(unsigned64*)PENDING_SLOT_DEST[index] |= | |
3965 | BIT64 (PENDING_SLOT_BIT[index]); | |
3966 | else | |
3967 | *(unsigned64*)PENDING_SLOT_DEST[index] &= | |
3968 | BIT64 (PENDING_SLOT_BIT[index]); | |
3969 | break; | |
3970 | break; | |
3971 | } | |
3972 | else | |
3973 | switch (PENDING_SLOT_SIZE[index]) | |
3974 | { | |
3975 | case 32: | |
3976 | *(unsigned32*)PENDING_SLOT_DEST[index] = | |
3977 | PENDING_SLOT_VALUE[index]; | |
3978 | break; | |
3979 | case 64: | |
3980 | *(unsigned64*)PENDING_SLOT_DEST[index] = | |
3981 | PENDING_SLOT_VALUE[index]; | |
3982 | break; | |
3983 | } | |
3984 | } | |
3985 | if (PENDING_OUT == index) | |
3986 | { | |
3987 | PENDING_SLOT_DEST[index] = NULL; | |
3988 | PENDING_OUT = (PENDING_OUT + 1) % PSLOTS; | |
3989 | PENDING_TOTAL--; | |
3990 | } | |
3991 | } | |
3992 | } | |
3993 | index = (index + 1) % PSLOTS; | |
3994 | } | |
3995 | } | |
3996 | ||
8bae0a0c JSC |
3997 | /*---------------------------------------------------------------------------*/ |
3998 | /*> EOF interp.c <*/ |