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Always compile FP code (test for FP at run-time).
[deliverable/binutils-gdb.git] / sim / mips / interp.c
CommitLineData
8bae0a0c
JSC		 1/*> interp.c <*/
2/* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 $Revision$
17 $Author$
e3d12c65 18 $Date$
8bae0a0c
JSC		 19
20NOTEs:
21
8bae0a0c
JSC		 22The IDT monitor (found on the VR4300 board), seems to lie about
23register contents. It seems to treat the registers as sign-extended
2432-bit values. This cause *REAL* problems when single-stepping 64-bit
25code on the hardware.
26
27*/
28
e2f8ffb7
AC		 29/* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
8bae0a0c
JSC		 32#if 1 /* 0 to allow user build selection, 1 to force inclusion */
33#define TRACE (1)
8bae0a0c
JSC		 34#endif
35
2e61a3ad
AC		 36#include "bfd.h"
37#include "sim-main.h"
38#include "sim-utils.h"
39#include "sim-options.h"
50a2a691 40#include "sim-assert.h"
2e61a3ad 41
4fa134be
ILT		 42#include "config.h"
43
8bae0a0c
JSC		 44#include <stdio.h>
45#include <stdarg.h>
46#include <ansidecl.h>
8bae0a0c
JSC		 47#include <ctype.h>
48#include <limits.h>
49#include <math.h>
4fa134be
ILT		 50#ifdef HAVE_STDLIB_H
51#include <stdlib.h>
52#endif
53#ifdef HAVE_STRING_H
54#include <string.h>
55#else
56#ifdef HAVE_STRINGS_H
57#include <strings.h>
58#endif
59#endif
8bae0a0c
JSC		 60
61#include "getopt.h"
62#include "libiberty.h"
9d52bcb7 63#include "bfd.h"
8bae0a0c 64#include "callback.h" /* GDB simulator callback interface */
e3d12c65 65#include "remote-sim.h" /* GDB simulator interface */
8bae0a0c 66
f24b7b69
JSC		 67#include "sysdep.h"
68
53b9417e
DE		 69#ifndef PARAMS
70#define PARAMS(x)
71#endif
72
73char* pr_addr PARAMS ((SIM_ADDR addr));
87e43259 74char* pr_uword64 PARAMS ((uword64 addr));
53b9417e 75
f24b7b69 76
8bae0a0c 77/* Get the simulator engine description, without including the code: */
192ae475
AC		 78#if (WITH_IGEN)
79#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
80#else
8bae0a0c 81#define SIM_MANIFESTS
284e759d 82#include "oengine.c"
8bae0a0c 83#undef SIM_MANIFESTS
192ae475 84#endif
8bae0a0c 85
01737f42
AC		 86/* Within interp.c we refer to the sim_state and sim_cpu directly. */
87#define SD sd
88#define CPU cpu
89
f7481d45 90
8bae0a0c
JSC		 91/* The following reserved instruction value is used when a simulator
92 trap is required. NOTE: Care must be taken, since this value may be
93 used in later revisions of the MIPS ISA. */
53b9417e
DE		 94#define RSVD_INSTRUCTION (0x00000005)
95#define RSVD_INSTRUCTION_MASK (0xFC00003F)
96
97#define RSVD_INSTRUCTION_ARG_SHIFT 6
98#define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
99
8bae0a0c 100
6eedf3f4
MA		 101/* Bits in the Debug register */
102#define Debug_DBD 0x80000000 /* Debug Branch Delay */
103#define Debug_DM 0x40000000 /* Debug Mode */
104#define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
105
106
107
8bae0a0c 108
8bae0a0c 109
e3d12c65
DE		 110/*---------------------------------------------------------------------------*/
111/*-- GDB simulator interface ------------------------------------------------*/
112/*---------------------------------------------------------------------------*/
113
0c2c5f61 114static void ColdReset PARAMS((SIM_DESC sd));
e3d12c65
DE		 115
116/*---------------------------------------------------------------------------*/
117
8bae0a0c 118
8bae0a0c 119
8bae0a0c 120#define DELAYSLOT() {\
0c2c5f61 121 if (STATE & simDELAYSLOT)\
18c64df6 122 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
0c2c5f61 123 STATE |= simDELAYSLOT;\
8bae0a0c
JSC		 124 }
125
aaff8437
ILT		 126#define JALDELAYSLOT() {\
127 DELAYSLOT ();\
0c2c5f61 128 STATE |= simJALDELAYSLOT;\
aaff8437
ILT		 129 }
130
8bae0a0c 131#define NULLIFY() {\
0c2c5f61
AC		 132 STATE &= ~simDELAYSLOT;\
133 STATE |= simSKIPNEXT;\
8bae0a0c
JSC		 134 }
135
6eedf3f4 136#define CANCELDELAYSLOT() {\
0c2c5f61
AC		 137 DSSTATE = 0;\
138 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
6eedf3f4
MA		 139 }
140
0c2c5f61
AC		 141#define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
142#define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
aaff8437 143
a9f7253f
JSC		 144#define K0BASE (0x80000000)
145#define K0SIZE (0x20000000)
146#define K1BASE (0xA0000000)
147#define K1SIZE (0x20000000)
525d929e
AC		 148#define MONITOR_BASE (0xBFC00000)
149#define MONITOR_SIZE (1 << 11)
150#define MEM_SIZE (2 << 20)
a9f7253f 151
8bae0a0c 152#if defined(TRACE)
4fa134be 153static char *tracefile = "trace.din"; /* default filename for trace log */
030843d7 154FILE *tracefh = NULL;
18c64df6 155static void open_trace PARAMS((SIM_DESC sd));
8bae0a0c
JSC		 156#endif /* TRACE */
157
22de994d
AC		 158#define OPTION_DINERO_TRACE 200
159#define OPTION_DINERO_FILE 201
160
50a2a691
AC		 161static SIM_RC
162mips_option_handler (sd, opt, arg)
163 SIM_DESC sd;
164 int opt;
165 char *arg;
2e61a3ad 166{
01737f42 167 int cpu_nr;
50a2a691
AC		 168 switch (opt)
169 {
22de994d 170 case OPTION_DINERO_TRACE: /* ??? */
50a2a691
AC		 171#if defined(TRACE)
172 /* Eventually the simTRACE flag could be treated as a toggle, to
173 allow external control of the program points being traced
174 (i.e. only from main onwards, excluding the run-time setup,
175 etc.). */
01737f42 176 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
50a2a691 177 {
01737f42
AC		 178 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
179 if (arg == NULL)
180 STATE |= simTRACE;
181 else if (strcmp (arg, "yes") == 0)
182 STATE |= simTRACE;
183 else if (strcmp (arg, "no") == 0)
184 STATE &= ~simTRACE;
185 else if (strcmp (arg, "on") == 0)
186 STATE |= simTRACE;
187 else if (strcmp (arg, "off") == 0)
188 STATE &= ~simTRACE;
189 else
190 {
191 fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg);
192 return SIM_RC_FAIL;
193 }
50a2a691
AC		 194 }
195 return SIM_RC_OK;
196#else /* !TRACE */
197 fprintf(stderr,"\
22de994d 198Simulator constructed without dinero tracing support (for performance).\n\
50a2a691
AC		 199Re-compile simulator with \"-DTRACE\" to enable this option.\n");
200 return SIM_RC_FAIL;
201#endif /* !TRACE */
202
22de994d 203 case OPTION_DINERO_FILE:
50a2a691
AC		 204#if defined(TRACE)
205 if (optarg != NULL) {
206 char *tmp;
207 tmp = (char *)malloc(strlen(optarg) + 1);
208 if (tmp == NULL)
209 {
18c64df6 210 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
50a2a691
AC		 211 return SIM_RC_FAIL;
212 }
213 else {
214 strcpy(tmp,optarg);
215 tracefile = tmp;
18c64df6 216 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
50a2a691
AC		 217 }
218 }
219#endif /* TRACE */
220 return SIM_RC_OK;
221
50a2a691
AC		 222 }
223
224 return SIM_RC_OK;
2e61a3ad 225}
50a2a691
AC		 226
227static const OPTION mips_options[] =
2e61a3ad 228{
22de994d
AC		 229 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
230 '\0', "on|off", "Enable dinero tracing",
50a2a691 231 mips_option_handler },
22de994d
AC		 232 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
233 '\0', "FILE", "Write dinero trace to FILE",
50a2a691 234 mips_option_handler },
50a2a691
AC		 235 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
236};
237
238
56e7c849
AC		 239int interrupt_pending;
240
50a2a691
AC		 241static void
242interrupt_event (SIM_DESC sd, void *data)
2e61a3ad 243{
01737f42 244 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
56e7c849
AC		 245 if (SR & status_IE)
246 {
247 interrupt_pending = 0;
18c64df6 248 SignalExceptionInterrupt ();
56e7c849
AC		 249 }
250 else if (!interrupt_pending)
251 sim_events_schedule (sd, 1, interrupt_event, data);
2e61a3ad 252}
f7481d45 253
f7481d45 254
50a2a691 255
8bae0a0c
JSC		 256/*---------------------------------------------------------------------------*/
257/*-- GDB simulator interface ------------------------------------------------*/
258/*---------------------------------------------------------------------------*/
259
53b9417e 260SIM_DESC
247fccde 261sim_open (kind, cb, abfd, argv)
87e43259 262 SIM_OPEN_KIND kind;
50a2a691 263 host_callback *cb;
247fccde 264 struct _bfd *abfd;
53b9417e 265 char **argv;
8bae0a0c 266{
18c64df6 267 SIM_DESC sd = sim_state_alloc (kind, cb);
01737f42 268 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
2e61a3ad 269
525d929e
AC		 270 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
271
50a2a691
AC		 272 /* FIXME: watchpoints code shouldn't need this */
273 STATE_WATCHPOINTS (sd)->pc = &(PC);
274 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
275 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
276
0c2c5f61 277 STATE = 0;
50a2a691 278
2e61a3ad
AC		 279 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
280 return 0;
50a2a691 281 sim_add_option_table (sd, mips_options);
2e61a3ad 282
63be8feb
AC		 283 /* Allocate core managed memory */
284
285 /* the monitor */
286 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
287 /* For compatibility with the old code - under this (at level one)
288 are the kernel spaces K0 & K1. Both of these map to a single
289 smaller sub region */
290 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
291 K1BASE, K0SIZE,
292 MEM_SIZE, /* actual size */
293 K0BASE);
294
2e61a3ad
AC		 295 /* getopt will print the error message so we just have to exit if this fails.
296 FIXME: Hmmm... in the case of gdb we need getopt to call
297 print_filtered. */
298 if (sim_parse_args (sd, argv) != SIM_RC_OK)
299 {
300 /* Uninstall the modules to avoid memory leaks,
301 file descriptor leaks, etc. */
302 sim_module_uninstall (sd);
303 return 0;
304 }
2e61a3ad 305
fafce69a
AC		 306 /* check for/establish the a reference program image */
307 if (sim_analyze_program (sd,
308 (STATE_PROG_ARGV (sd) != NULL
309 ? *STATE_PROG_ARGV (sd)
310 : NULL),
311 abfd) != SIM_RC_OK)
312 {
313 sim_module_uninstall (sd);
314 return 0;
315 }
316
247fccde
AC		 317 /* Configure/verify the target byte order and other runtime
318 configuration options */
fafce69a 319 if (sim_config (sd) != SIM_RC_OK)
247fccde
AC		 320 {
321 sim_module_uninstall (sd);
322 return 0;
323 }
324
2e61a3ad
AC		 325 if (sim_post_argv_init (sd) != SIM_RC_OK)
326 {
327 /* Uninstall the modules to avoid memory leaks,
328 file descriptor leaks, etc. */
329 sim_module_uninstall (sd);
330 return 0;
331 }
332
50a2a691
AC		 333 /* verify assumptions the simulator made about the host type system.
334 This macro does not return if there is a problem */
7ce8b917
AC		 335 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
336 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
8bae0a0c 337
8bae0a0c
JSC		 338 /* This is NASTY, in that we are assuming the size of specific
339 registers: */
340 {
341 int rn;
342 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) {
343 if (rn < 32)
192ae475 344 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
8bae0a0c 345 else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32)))
192ae475 346 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
8bae0a0c 347 else if ((rn >= 33) && (rn <= 37))
192ae475 348 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
8bae0a0c 349 else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
0c2c5f61 350 cpu->register_widths[rn] = 32;
8bae0a0c 351 else
0c2c5f61 352 cpu->register_widths[rn] = 0;
8bae0a0c 353 }
18c64df6
AC		 354 /* start-sanitize-r5900 */
355
356 /* set the 5900 "upper" registers to 64 bits */
357 for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
0c2c5f61 358 cpu->register_widths[rn] = 64;
18c64df6 359 /* end-sanitize-r5900 */
8bae0a0c
JSC		 360 }
361
8bae0a0c 362#if defined(TRACE)
0c2c5f61 363 if (STATE & simTRACE)
18c64df6 364 open_trace(sd);
8bae0a0c
JSC		 365#endif /* TRACE */
366
fafce69a
AC		 367 /* Write the monitor trap address handlers into the monitor (eeprom)
368 address space. This can only be done once the target endianness
369 has been determined. */
370 {
371 unsigned loop;
372 /* Entry into the IDT monitor is via fixed address vectors, and
373 not using machine instructions. To avoid clashing with use of
374 the MIPS TRAP system, we place our own (simulator specific)
375 "undefined" instructions into the relevant vector slots. */
525d929e
AC		 376 for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
377 {
378 address_word vaddr = (MONITOR_BASE + loop);
379 unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
380 H2T (insn);
381 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
382 }
fafce69a
AC		 383 /* The PMON monitor uses the same address space, but rather than
384 branching into it the address of a routine is loaded. We can
385 cheat for the moment, and direct the PMON routine to IDT style
386 instructions within the monitor space. This relies on the IDT
387 monitor not using the locations from 0xBFC00500 onwards as its
388 entry points.*/
389 for (loop = 0; (loop < 24); loop++)
390 {
525d929e
AC		 391 address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
392 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
fafce69a
AC		 393 switch (loop)
394 {
395 case 0: /* read */
396 value = 7;
397 break;
fafce69a
AC		 398 case 1: /* write */
399 value = 8;
400 break;
fafce69a
AC		 401 case 2: /* open */
402 value = 6;
403 break;
fafce69a
AC		 404 case 3: /* close */
405 value = 10;
406 break;
fafce69a
AC		 407 case 5: /* printf */
408 value = ((0x500 - 16) / 8); /* not an IDT reason code */
409 break;
fafce69a
AC		 410 case 8: /* cliexit */
411 value = 17;
412 break;
fafce69a
AC		 413 case 11: /* flush_cache */
414 value = 28;
415 break;
416 }
525d929e
AC		 417 /* FIXME - should monitor_base be SIM_ADDR?? */
418 value = ((unsigned int)MONITOR_BASE + (value * 8));
419 H2T (value);
420 sim_write (sd, vaddr, (char *)&value, sizeof (value));
fafce69a
AC		 421
422 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
423 vaddr -= 0x300;
525d929e 424 sim_write (sd, vaddr, (char *)&value, sizeof (value));
fafce69a
AC		 425 }
426 }
427
2e61a3ad 428 return sd;
8bae0a0c
JSC		 429}
430
6429b296
JW		 431#if defined(TRACE)
432static void
18c64df6
AC		 433open_trace(sd)
434 SIM_DESC sd;
6429b296
JW		 435{
436 tracefh = fopen(tracefile,"wb+");
437 if (tracefh == NULL)
438 {
18c64df6 439 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
6429b296
JW		 440 tracefh = stderr;
441 }
442}
443#endif /* TRACE */
444
8bae0a0c 445void
53b9417e
DE		 446sim_close (sd, quitting)
447 SIM_DESC sd;
8bae0a0c
JSC		 448 int quitting;
449{
450#ifdef DEBUG
451 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
452#endif
453
8bae0a0c
JSC		 454 /* "quitting" is non-zero if we cannot hang on errors */
455
456 /* Ensure that any resources allocated through the callback
457 mechanism are released: */
18c64df6 458 sim_io_shutdown (sd);
8bae0a0c 459
8bae0a0c 460#if defined(TRACE)
e3d12c65 461 if (tracefh != NULL && tracefh != stderr)
8bae0a0c 462 fclose(tracefh);
e3d12c65 463 tracefh = NULL;
8bae0a0c
JSC		 464#endif /* TRACE */
465
01737f42
AC		 466 /* FIXME - free SD */
467
8bae0a0c
JSC		 468 return;
469}
470
8bae0a0c
JSC		 471
472int
53b9417e
DE		 473sim_write (sd,addr,buffer,size)
474 SIM_DESC sd;
8bae0a0c
JSC		 475 SIM_ADDR addr;
476 unsigned char *buffer;
477 int size;
478{
525d929e 479 int index;
01737f42 480 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
8bae0a0c
JSC		 481
482 /* Return the number of bytes written, or zero if error. */
483#ifdef DEBUG
18c64df6 484 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
8bae0a0c
JSC		 485#endif
486
525d929e
AC		 487 /* We use raw read and write routines, since we do not want to count
488 the GDB memory accesses in our statistics gathering. */
489
490 for (index = 0; index < size; index++)
491 {
492 address_word vaddr = (address_word)addr + index;
493 address_word paddr;
494 int cca;
01737f42 495 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
525d929e 496 break;
01737f42 497 if (sim_core_write_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1)
63be8feb 498 break;
8bae0a0c 499 }
8bae0a0c 500
525d929e 501 return(index);
8bae0a0c
JSC		 502}
503
504int
53b9417e
DE		 505sim_read (sd,addr,buffer,size)
506 SIM_DESC sd;
8bae0a0c
JSC		 507 SIM_ADDR addr;
508 unsigned char *buffer;
509 int size;
510{
511 int index;
01737f42 512 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
8bae0a0c
JSC		 513
514 /* Return the number of bytes read, or zero if error. */
515#ifdef DEBUG
18c64df6 516 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
8bae0a0c
JSC		 517#endif /* DEBUG */
518
525d929e
AC		 519 for (index = 0; (index < size); index++)
520 {
521 address_word vaddr = (address_word)addr + index;
522 address_word paddr;
525d929e 523 int cca;
01737f42 524 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
525d929e 525 break;
01737f42 526 if (sim_core_read_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1)
63be8feb 527 break;
525d929e 528 }
8bae0a0c
JSC		 529
530 return(index);
531}
532
533void
53b9417e
DE		 534sim_store_register (sd,rn,memory)
535 SIM_DESC sd;
8bae0a0c
JSC		 536 int rn;
537 unsigned char *memory;
538{
01737f42 539 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
50a2a691
AC		 540 /* NOTE: gdb (the client) stores registers in target byte order
541 while the simulator uses host byte order */
8bae0a0c 542#ifdef DEBUG
18c64df6 543 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
8bae0a0c
JSC		 544#endif /* DEBUG */
545
546 /* Unfortunately this suffers from the same problem as the register
547 numbering one. We need to know what the width of each logical
548 register number is for the architecture being simulated. */
50a2a691 549
0c2c5f61 550 if (cpu->register_widths[rn] == 0)
18c64df6
AC		 551 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
552 /* start-sanitize-r5900 */
553 else if (rn == REGISTER_SA)
554 SA = T2H_8(*(uword64*)memory);
555 else if (rn > LAST_EMBED_REGNUM)
0c2c5f61 556 cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(uword64*)memory);
18c64df6 557 /* end-sanitize-r5900 */
0c2c5f61
AC		 558 else if (cpu->register_widths[rn] == 32)
559 cpu->registers[rn] = T2H_4 (*(unsigned int*)memory);
50a2a691 560 else
0c2c5f61 561 cpu->registers[rn] = T2H_8 (*(uword64*)memory);
8bae0a0c
JSC		 562
563 return;
564}
565
566void
53b9417e
DE		 567sim_fetch_register (sd,rn,memory)
568 SIM_DESC sd;
8bae0a0c
JSC		 569 int rn;
570 unsigned char *memory;
571{
01737f42 572 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
50a2a691
AC		 573 /* NOTE: gdb (the client) stores registers in target byte order
574 while the simulator uses host byte order */
8bae0a0c 575#ifdef DEBUG
18c64df6 576 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
8bae0a0c
JSC		 577#endif /* DEBUG */
578
0c2c5f61 579 if (cpu->register_widths[rn] == 0)
18c64df6
AC		 580 sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn);
581 /* start-sanitize-r5900 */
582 else if (rn == REGISTER_SA)
583 *((uword64 *)memory) = H2T_8(SA);
584 else if (rn > LAST_EMBED_REGNUM)
0c2c5f61 585 *((uword64 *)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]);
18c64df6 586 /* end-sanitize-r5900 */
0c2c5f61
AC		 587 else if (cpu->register_widths[rn] == 32)
588 *((unsigned int *)memory) = H2T_4 ((unsigned int)(cpu->registers[rn] & 0xFFFFFFFF));
18c64df6 589 else /* 64bit register */
0c2c5f61 590 *((uword64 *)memory) = H2T_8 (cpu->registers[rn]);
50a2a691 591
8bae0a0c
JSC		 592 return;
593}
50a2a691 594
8bae0a0c
JSC		 595
596void
53b9417e
DE		 597sim_info (sd,verbose)
598 SIM_DESC sd;
8bae0a0c
JSC		 599 int verbose;
600{
601 /* Accessed from the GDB "info files" command: */
56e7c849
AC		 602 if (STATE_VERBOSE_P (sd) || verbose)
603 {
604
605 sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n",
192ae475 606 WITH_TARGET_WORD_BITSIZE,
56e7c849
AC		 607 (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little"));
608
8bae0a0c 609#if !defined(FASTSIM)
56e7c849
AC		 610 /* It would be a useful feature, if when performing multi-cycle
611 simulations (rather than single-stepping) we keep the start and
612 end times of the execution, so that we can give a performance
613 figure for the simulator. */
8bae0a0c 614#endif /* !FASTSIM */
56e7c849
AC		 615 sim_io_printf (sd, "Number of execution cycles = %ld\n",
616 (long) sim_events_time (sd));
617
618 /* print information pertaining to MIPS ISA and architecture being simulated */
619 /* things that may be interesting */
620 /* instructions executed - if available */
621 /* cycles executed - if available */
622 /* pipeline stalls - if available */
623 /* virtual time taken */
624 /* profiling size */
625 /* profiling frequency */
626 /* profile minpc */
627 /* profile maxpc */
628 }
aa324b9b 629 profile_print (sd, STATE_VERBOSE_P (sd), NULL, NULL);
8bae0a0c
JSC		 630}
631
8bae0a0c 632
9d52bcb7 633SIM_RC
fafce69a 634sim_create_inferior (sd, abfd, argv,env)
53b9417e 635 SIM_DESC sd;
fafce69a 636 struct _bfd *abfd;
8bae0a0c
JSC		 637 char **argv;
638 char **env;
639{
50a2a691 640
8bae0a0c 641#ifdef DEBUG
9d52bcb7
DE		 642 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
643 pr_addr(PC));
8bae0a0c
JSC		 644#endif /* DEBUG */
645
0c2c5f61 646 ColdReset(sd);
50a2a691 647
fafce69a 648 if (abfd != NULL)
01737f42
AC		 649 {
650 /* override PC value set by ColdReset () */
651 int cpu_nr;
652 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
653 {
654 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
655 CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
656 }
657 }
2e61a3ad 658
f24b7b69 659#if 0 /* def DEBUG */
dad6f1f3 660 if (argv || env)
8bae0a0c 661 {
dad6f1f3
AC		 662 /* We should really place the argv slot values into the argument
663 registers, and onto the stack as required. However, this
664 assumes that we have a stack defined, which is not
665 necessarily true at the moment. */
666 char **cptr;
667 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
668 for (cptr = argv; (cptr && *cptr); cptr++)
669 printf("DBG: arg \"%s\"\n",*cptr);
8bae0a0c
JSC		 670 }
671#endif /* DEBUG */
8bae0a0c 672
9d52bcb7 673 return SIM_RC_OK;
8bae0a0c
JSC		 674}
675
8bae0a0c 676void
53b9417e
DE		 677sim_do_command (sd,cmd)
678 SIM_DESC sd;
8bae0a0c
JSC		 679 char *cmd;
680{
63be8feb
AC		 681 if (sim_args_command (sd, cmd) != SIM_RC_OK)
682 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
683 cmd);
8bae0a0c
JSC		 684}
685
8bae0a0c
JSC		 686/*---------------------------------------------------------------------------*/
687/*-- Private simulator support interface ------------------------------------*/
688/*---------------------------------------------------------------------------*/
689
525d929e
AC		 690/* Read a null terminated string from memory, return in a buffer */
691static char *
692fetch_str (sd, addr)
693 SIM_DESC sd;
694 address_word addr;
695{
696 char *buf;
697 int nr = 0;
698 char null;
699 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
700 nr++;
701 buf = NZALLOC (char, nr + 1);
702 sim_read (sd, addr, buf, nr);
703 return buf;
704}
705
a9f7253f 706/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
8bae0a0c 707static void
01737f42
AC		 708sim_monitor (SIM_DESC sd,
709 sim_cpu *cpu,
710 address_word cia,
711 unsigned int reason)
8bae0a0c 712{
53b9417e
DE		 713#ifdef DEBUG
714 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
715#endif /* DEBUG */
716
8bae0a0c
JSC		 717 /* The IDT monitor actually allows two instructions per vector
718 slot. However, the simulator currently causes a trap on each
719 individual instruction. We cheat, and lose the bottom bit. */
720 reason >>= 1;
721
722 /* The following callback functions are available, however the
723 monitor we are simulating does not make use of them: get_errno,
724 isatty, lseek, rename, system, time and unlink */
525d929e
AC		 725 switch (reason)
726 {
727
8bae0a0c
JSC		 728 case 6: /* int open(char *path,int flags) */
729 {
525d929e
AC		 730 char *path = fetch_str (sd, A0);
731 V0 = sim_io_open (sd, path, (int)A1);
732 zfree (path);
733 break;
8bae0a0c 734 }
8bae0a0c
JSC		 735
736 case 7: /* int read(int file,char *ptr,int len) */
737 {
525d929e
AC		 738 int fd = A0;
739 int nr = A2;
740 char *buf = zalloc (nr);
741 V0 = sim_io_read (sd, fd, buf, nr);
742 sim_write (sd, A1, buf, nr);
743 zfree (buf);
8bae0a0c
JSC		 744 }
745 break;
746
747 case 8: /* int write(int file,char *ptr,int len) */
748 {
525d929e
AC		 749 int fd = A0;
750 int nr = A2;
751 char *buf = zalloc (nr);
752 sim_read (sd, A1, buf, nr);
753 V0 = sim_io_write (sd, fd, buf, nr);
754 zfree (buf);
755 break;
8bae0a0c 756 }
8bae0a0c
JSC		 757
758 case 10: /* int close(int file) */
525d929e
AC		 759 {
760 V0 = sim_io_close (sd, (int)A0);
761 break;
762 }
8bae0a0c 763
e0e0fc76
MA		 764 case 2: /* Densan monitor: char inbyte(int waitflag) */
765 {
766 if (A0 == 0) /* waitflag == NOWAIT */
192ae475 767 V0 = (unsigned_word)-1;
e0e0fc76
MA		 768 }
769 /* Drop through to case 11 */
770
8bae0a0c
JSC		 771 case 11: /* char inbyte(void) */
772 {
773 char tmp;
525d929e
AC		 774 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
775 {
776 sim_io_error(sd,"Invalid return from character read");
192ae475 777 V0 = (unsigned_word)-1;
525d929e 778 }
8bae0a0c 779 else
192ae475 780 V0 = (unsigned_word)tmp;
525d929e 781 break;
8bae0a0c 782 }
8bae0a0c 783
e0e0fc76 784 case 3: /* Densan monitor: void co(char chr) */
8bae0a0c
JSC		 785 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
786 {
787 char tmp = (char)(A0 & 0xFF);
525d929e
AC		 788 sim_io_write_stdout (sd, &tmp, sizeof(char));
789 break;
8bae0a0c 790 }
8bae0a0c
JSC		 791
792 case 17: /* void _exit() */
525d929e
AC		 793 {
794 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
01737f42 795 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
525d929e
AC		 796 (unsigned int)(A0 & 0xFFFFFFFF));
797 break;
798 }
8bae0a0c 799
280f90e1
AMT		 800 case 28 : /* PMON flush_cache */
801 break;
802
8bae0a0c
JSC		 803 case 55: /* void get_mem_info(unsigned int *ptr) */
804 /* in: A0 = pointer to three word memory location */
805 /* out: [A0 + 0] = size */
806 /* [A0 + 4] = instruction cache size */
807 /* [A0 + 8] = data cache size */
808 {
525d929e
AC		 809 address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
810 H2T (value);
811 sim_write (sd, A0, (char *)&value, sizeof (value));
030843d7 812 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
525d929e 813 break;
8bae0a0c 814 }
525d929e 815
a9f7253f
JSC		 816 case 158 : /* PMON printf */
817 /* in: A0 = pointer to format string */
818 /* A1 = optional argument 1 */
819 /* A2 = optional argument 2 */
820 /* A3 = optional argument 3 */
821 /* out: void */
f24b7b69 822 /* The following is based on the PMON printf source */
a9f7253f 823 {
525d929e
AC		 824 address_word s = A0;
825 char c;
826 signed_word *ap = &A1; /* 1st argument */
f24b7b69
JSC		 827 /* This isn't the quickest way, since we call the host print
828 routine for every character almost. But it does avoid
829 having to allocate and manage a temporary string buffer. */
525d929e
AC		 830 /* TODO: Include check that we only use three arguments (A1,
831 A2 and A3) */
832 while (sim_read (sd, s++, &c, 1) && c != '\0')
833 {
834 if (c == '%')
835 {
836 char tmp[40];
837 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
838 int width = 0, trunc = 0, haddot = 0, longlong = 0;
839 while (sim_read (sd, s++, &c, 1) && c != '\0')
840 {
841 if (strchr ("dobxXulscefg%", s))
842 break;
843 else if (c == '-')
844 fmt = FMT_LJUST;
845 else if (c == '0')
846 fmt = FMT_RJUST0;
847 else if (c == '~')
848 fmt = FMT_CENTER;
849 else if (c == '*')
850 {
851 if (haddot)
852 trunc = (int)*ap++;
853 else
854 width = (int)*ap++;
855 }
856 else if (c >= '1' && c <= '9')
857 {
858 address_word t = s;
859 unsigned int n;
860 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
861 tmp[s - t] = c;
862 tmp[s - t] = '\0';
863 n = (unsigned int)strtol(tmp,NULL,10);
864 if (haddot)
865 trunc = n;
866 else
867 width = n;
868 s--;
869 }
870 else if (c == '.')
871 haddot = 1;
872 }
873 switch (c)
874 {
875 case '%':
876 sim_io_printf (sd, "%%");
877 break;
878 case 's':
879 if ((int)*ap != 0)
880 {
881 address_word p = *ap++;
882 char ch;
883 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
884 sim_io_printf(sd, "%c", ch);
885 }
886 else
887 sim_io_printf(sd,"(null)");
888 break;
889 case 'c':
890 sim_io_printf (sd, "%c", (int)*ap++);
891 break;
892 default:
893 if (c == 'l')
894 {
895 sim_read (sd, s++, &c, 1);
896 if (c == 'l')
897 {
898 longlong = 1;
899 sim_read (sd, s++, &c, 1);
900 }
901 }
902 if (strchr ("dobxXu", c))
903 {
904 word64 lv = (word64) *ap++;
905 if (c == 'b')
906 sim_io_printf(sd,"<binary not supported>");
907 else
908 {
909 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
910 if (longlong)
911 sim_io_printf(sd, tmp, lv);
912 else
913 sim_io_printf(sd, tmp, (int)lv);
914 }
915 }
916 else if (strchr ("eEfgG", c))
917 {
918 double dbl = *(double*)(ap++);
919 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
920 sim_io_printf (sd, tmp, dbl);
921 trunc = 0;
922 }
923 }
924 }
925 else
926 sim_io_printf(sd, "%c", c);
927 }
928 break;
a9f7253f 929 }
a9f7253f 930
8bae0a0c 931 default:
525d929e 932 sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
95469ceb 933 reason, pr_addr(cia));
8bae0a0c
JSC		 934 break;
935 }
936 return;
937}
938
7e6c297e
ILT		 939/* Store a word into memory. */
940
941static void
01737f42
AC		 942store_word (SIM_DESC sd,
943 sim_cpu *cpu,
944 address_word cia,
945 uword64 vaddr,
192ae475 946 signed_word val)
7e6c297e 947{
dad6f1f3 948 address_word paddr;
7e6c297e
ILT		 949 int uncached;
950
951 if ((vaddr & 3) != 0)
18c64df6 952 SignalExceptionAddressStore ();
7e6c297e
ILT		 953 else
954 {
955 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
956 isTARGET, isREAL))
957 {
958 const uword64 mask = 7;
959 uword64 memval;
960 unsigned int byte;
961
962 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
963 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
964 memval = ((uword64) val) << (8 * byte);
53b9417e 965 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
7e6c297e
ILT		 966 isREAL);
967 }
968 }
969}
970
971/* Load a word from memory. */
972
192ae475 973static signed_word
01737f42
AC		 974load_word (SIM_DESC sd,
975 sim_cpu *cpu,
976 address_word cia,
977 uword64 vaddr)
7e6c297e
ILT		 978{
979 if ((vaddr & 3) != 0)
18c64df6 980 SignalExceptionAddressLoad ();
7e6c297e
ILT		 981 else
982 {
dad6f1f3 983 address_word paddr;
7e6c297e
ILT		 984 int uncached;
985
986 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
987 isTARGET, isREAL))
988 {
989 const uword64 mask = 0x7;
990 const unsigned int reverse = ReverseEndian ? 1 : 0;
991 const unsigned int bigend = BigEndianCPU ? 1 : 0;
992 uword64 memval;
993 unsigned int byte;
994
995 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
53b9417e 996 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
7e6c297e
ILT		 997 isDATA, isREAL);
998 byte = (vaddr & mask) ^ (bigend << 2);
999 return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
1000 }
1001 }
1002
1003 return 0;
1004}
1005
1006/* Simulate the mips16 entry and exit pseudo-instructions. These
1007 would normally be handled by the reserved instruction exception
1008 code, but for ease of simulation we just handle them directly. */
1009
1010static void
01737f42
AC		 1011mips16_entry (SIM_DESC sd,
1012 sim_cpu *cpu,
1013 address_word cia,
1014 unsigned int insn)
7e6c297e
ILT		 1015{
1016 int aregs, sregs, rreg;
1017
53b9417e
DE		 1018#ifdef DEBUG
1019 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1020#endif /* DEBUG */
1021
7e6c297e
ILT		 1022 aregs = (insn & 0x700) >> 8;
1023 sregs = (insn & 0x0c0) >> 6;
1024 rreg = (insn & 0x020) >> 5;
1025
da0bce9c
ILT		 1026 /* This should be checked by the caller. */
1027 if (sregs == 3)
7e6c297e
ILT		 1028 abort ();
1029
da0bce9c 1030 if (aregs < 5)
7e6c297e
ILT		 1031 {
1032 int i;
192ae475 1033 signed_word tsp;
7e6c297e
ILT		 1034
1035 /* This is the entry pseudo-instruction. */
1036
1037 for (i = 0; i < aregs; i++)
01737f42 1038 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
7e6c297e
ILT		 1039
1040 tsp = SP;
1041 SP -= 32;
1042
1043 if (rreg)
1044 {
1045 tsp -= 4;
01737f42 1046 store_word (SD, CPU, cia, (uword64) tsp, RA);
7e6c297e
ILT		 1047 }
1048
1049 for (i = 0; i < sregs; i++)
1050 {
1051 tsp -= 4;
01737f42 1052 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
7e6c297e
ILT		 1053 }
1054 }
1055 else
1056 {
1057 int i;
192ae475 1058 signed_word tsp;
7e6c297e
ILT		 1059
1060 /* This is the exit pseudo-instruction. */
1061
1062 tsp = SP + 32;
1063
1064 if (rreg)
1065 {
1066 tsp -= 4;
01737f42 1067 RA = load_word (SD, CPU, cia, (uword64) tsp);
7e6c297e
ILT		 1068 }
1069
1070 for (i = 0; i < sregs; i++)
1071 {
1072 tsp -= 4;
01737f42 1073 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
7e6c297e
ILT		 1074 }
1075
1076 SP += 32;
1077
192ae475 1078 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
da0bce9c 1079 {
192ae475
AC		 1080 if (aregs == 5)
1081 {
1082 FGR[0] = WORD64LO (GPR[4]);
1083 FPR_STATE[0] = fmt_uninterpreted;
1084 }
1085 else if (aregs == 6)
1086 {
1087 FGR[0] = WORD64LO (GPR[5]);
1088 FGR[1] = WORD64LO (GPR[4]);
1089 FPR_STATE[0] = fmt_uninterpreted;
1090 FPR_STATE[1] = fmt_uninterpreted;
1091 }
1092 }
da0bce9c 1093
7e6c297e
ILT		 1094 PC = RA;
1095 }
192ae475 1096
7e6c297e
ILT		 1097}
1098
8bae0a0c
JSC		 1099/*-- trace support ----------------------------------------------------------*/
1100
1101/* The TRACE support is provided (if required) in the memory accessing
1102 routines. Since we are also providing the architecture specific
1103 features, the architecture simulation code can also deal with
1104 notifying the TRACE world of cache flushes, etc. Similarly we do
1105 not need to provide profiling support in the simulator engine,
1106 since we can sample in the instruction fetch control loop. By
1107 defining the TRACE manifest, we add tracing as a run-time
1108 option. */
1109
1110#if defined(TRACE)
1111/* Tracing by default produces "din" format (as required by
1112 dineroIII). Each line of such a trace file *MUST* have a din label
1113 and address field. The rest of the line is ignored, so comments can
1114 be included if desired. The first field is the label which must be
1115 one of the following values:
1116
1117 0 read data
1118 1 write data
1119 2 instruction fetch
1120 3 escape record (treated as unknown access type)
1121 4 escape record (causes cache flush)
1122
1123 The address field is a 32bit (lower-case) hexadecimal address
1124 value. The address should *NOT* be preceded by "0x".
1125
1126 The size of the memory transfer is not important when dealing with
1127 cache lines (as long as no more than a cache line can be
1128 transferred in a single operation :-), however more information
1129 could be given following the dineroIII requirement to allow more
1130 complete memory and cache simulators to provide better
1131 results. i.e. the University of Pisa has a cache simulator that can
1132 also take bus size and speed as (variable) inputs to calculate
1133 complete system performance (a much more useful ability when trying
1134 to construct an end product, rather than a processor). They
1135 currently have an ARM version of their tool called ChARM. */
1136
e3d12c65 1137
030843d7 1138void
01737f42
AC		 1139dotrace (SIM_DESC sd,
1140 sim_cpu *cpu,
1141 FILE *tracefh,
1142 int type,
1143 SIM_ADDR address,
1144 int width,
1145 char *comment,...)
8bae0a0c 1146{
0c2c5f61 1147 if (STATE & simTRACE) {
8bae0a0c 1148 va_list ap;
53b9417e 1149 fprintf(tracefh,"%d %s ; width %d ; ",
6429b296 1150 type,
53b9417e
DE		 1151 pr_addr(address),
1152 width);
8bae0a0c 1153 va_start(ap,comment);
6429b296 1154 vfprintf(tracefh,comment,ap);
8bae0a0c
JSC		 1155 va_end(ap);
1156 fprintf(tracefh,"\n");
1157 }
1158 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1159 we may be generating 64bit ones, we should put the hi-32bits of the
1160 address into the comment field. */
1161
1162 /* TODO: Provide a buffer for the trace lines. We can then avoid
1163 performing writes until the buffer is filled, or the file is
1164 being closed. */
1165
1166 /* NOTE: We could consider adding a comment field to the "din" file
1167 produced using type 3 markers (unknown access). This would then
1168 allow information about the program that the "din" is for, and
1169 the MIPs world that was being simulated, to be placed into the
1170 trace file. */
1171
1172 return;
1173}
1174#endif /* TRACE */
1175
1176/*---------------------------------------------------------------------------*/
1177/*-- simulator engine -------------------------------------------------------*/
1178/*---------------------------------------------------------------------------*/
1179
1180static void
01737f42 1181ColdReset (SIM_DESC sd)
8bae0a0c 1182{
01737f42
AC		 1183 int cpu_nr;
1184 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
dad6f1f3 1185 {
01737f42
AC		 1186 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1187 /* RESET: Fixed PC address: */
1188 PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
1189 /* The reset vector address is in the unmapped, uncached memory space. */
1190
1191 SR &= ~(status_SR | status_TS | status_RP);
1192 SR |= (status_ERL | status_BEV);
1193
1194 /* Cheat and allow access to the complete register set immediately */
1195 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1196 && WITH_TARGET_WORD_BITSIZE == 64)
1197 SR |= status_FR; /* 64bit registers */
1198
1199 /* Ensure that any instructions with pending register updates are
1200 cleared: */
1201 {
1202 int loop;
1203 for (loop = 0; (loop < PSLOTS); loop++)
1204 PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1);
1205 PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0;
1206 }
1207
1208 /* Initialise the FPU registers to the unknown state */
1209 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1210 {
1211 int rn;
1212 for (rn = 0; (rn < 32); rn++)
1213 FPR_STATE[rn] = fmt_uninterpreted;
1214 }
1215
dad6f1f3 1216 }
8bae0a0c
JSC		 1217}
1218
dad6f1f3
AC		 1219/* Description from page A-22 of the "MIPS IV Instruction Set" manual
1220 (revision 3.1) */
8bae0a0c
JSC		 1221/* Translate a virtual address to a physical address and cache
1222 coherence algorithm describing the mechanism used to resolve the
1223 memory reference. Given the virtual address vAddr, and whether the
1224 reference is to Instructions ot Data (IorD), find the corresponding
1225 physical address (pAddr) and the cache coherence algorithm (CCA)
1226 used to resolve the reference. If the virtual address is in one of
1227 the unmapped address spaces the physical address and the CCA are
1228 determined directly by the virtual address. If the virtual address
1229 is in one of the mapped address spaces then the TLB is used to
1230 determine the physical address and access type; if the required
1231 translation is not present in the TLB or the desired access is not
1232 permitted the function fails and an exception is taken.
1233
dad6f1f3
AC		 1234 NOTE: Normally (RAW == 0), when address translation fails, this
1235 function raises an exception and does not return. */
8bae0a0c 1236
18c64df6 1237int
01737f42
AC		 1238address_translation (SIM_DESC sd,
1239 sim_cpu *cpu,
1240 address_word cia,
1241 address_word vAddr,
1242 int IorD,
1243 int LorS,
1244 address_word *pAddr,
1245 int *CCA,
1246 int raw)
8bae0a0c
JSC		 1247{
1248 int res = -1; /* TRUE : Assume good return */
1249
1250#ifdef DEBUG
18c64df6 1251 sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
8bae0a0c
JSC		 1252#endif
1253
1254 /* Check that the address is valid for this memory model */
1255
1256 /* For a simple (flat) memory model, we simply pass virtual
1257 addressess through (mostly) unchanged. */
1258 vAddr &= 0xFFFFFFFF;
a9f7253f 1259
8bae0a0c
JSC		 1260 *pAddr = vAddr; /* default for isTARGET */
1261 *CCA = Uncached; /* not used for isHOST */
1262
8bae0a0c
JSC		 1263 return(res);
1264}
1265
63be8feb
AC		 1266/* Description from page A-23 of the "MIPS IV Instruction Set" manual
1267 (revision 3.1) */
8bae0a0c
JSC		 1268/* Prefetch data from memory. Prefetch is an advisory instruction for
1269 which an implementation specific action is taken. The action taken
1270 may increase performance, but must not change the meaning of the
1271 program, or alter architecturally-visible state. */
50a2a691 1272
ea985d24 1273void
01737f42
AC		 1274prefetch (SIM_DESC sd,
1275 sim_cpu *cpu,
1276 address_word cia,
1277 int CCA,
1278 address_word pAddr,
1279 address_word vAddr,
1280 int DATA,
1281 int hint)
8bae0a0c
JSC		 1282{
1283#ifdef DEBUG
18c64df6 1284 sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
8bae0a0c
JSC		 1285#endif /* DEBUG */
1286
1287 /* For our simple memory model we do nothing */
1288 return;
1289}
1290
63be8feb
AC		 1291/* Description from page A-22 of the "MIPS IV Instruction Set" manual
1292 (revision 3.1) */
8bae0a0c
JSC		 1293/* Load a value from memory. Use the cache and main memory as
1294 specified in the Cache Coherence Algorithm (CCA) and the sort of
1295 access (IorD) to find the contents of AccessLength memory bytes
1296 starting at physical location pAddr. The data is returned in the
1297 fixed width naturally-aligned memory element (MemElem). The
1298 low-order two (or three) bits of the address and the AccessLength
1299 indicate which of the bytes within MemElem needs to be given to the
1300 processor. If the memory access type of the reference is uncached
1301 then only the referenced bytes are read from memory and valid
1302 within the memory element. If the access type is cached, and the
1303 data is not present in cache, an implementation specific size and
1304 alignment block of memory is read and loaded into the cache to
1305 satisfy a load reference. At a minimum, the block is the entire
1306 memory element. */
18c64df6 1307void
01737f42
AC		 1308load_memory (SIM_DESC sd,
1309 sim_cpu *cpu,
1310 address_word cia,
1311 uword64* memvalp,
1312 uword64* memval1p,
1313 int CCA,
1314 int AccessLength,
1315 address_word pAddr,
1316 address_word vAddr,
1317 int IorD)
8bae0a0c 1318{
50a2a691
AC		 1319 uword64 value = 0;
1320 uword64 value1 = 0;
8bae0a0c
JSC		 1321
1322#ifdef DEBUG
63be8feb 1323 sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
8bae0a0c
JSC		 1324#endif /* DEBUG */
1325
1326#if defined(WARN_MEM)
1327 if (CCA != uncached)
63be8feb 1328 sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
8bae0a0c
JSC		 1329#endif /* WARN_MEM */
1330
8bae0a0c
JSC		 1331 /* If instruction fetch then we need to check that the two lo-order
1332 bits are zero, otherwise raise a InstructionFetch exception: */
6429b296
JW		 1333 if ((IorD == isINSTRUCTION)
1334 && ((pAddr & 0x3) != 0)
1335 && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
63be8feb
AC		 1336 SignalExceptionInstructionFetch ();
1337
1338 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1339 {
1340 /* In reality this should be a Bus Error */
1341 sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1342 AccessLength,
1343 (LOADDRMASK + 1) << 2,
1344 pr_addr (pAddr));
1345 }
8bae0a0c 1346
8bae0a0c 1347#if defined(TRACE)
01737f42 1348 dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
8bae0a0c 1349#endif /* TRACE */
63be8feb
AC		 1350
1351 /* Read the specified number of bytes from memory. Adjust for
1352 host/target byte ordering/ Align the least significant byte
1353 read. */
8bae0a0c 1354
63be8feb
AC		 1355 switch (AccessLength)
1356 {
1357 case AccessLength_QUADWORD :
1358 {
01737f42 1359 unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA,
63be8feb
AC		 1360 sim_core_read_map, pAddr);
1361 value1 = VH8_16 (val);
1362 value = VL8_16 (val);
1363 break;
8bae0a0c 1364 }
63be8feb 1365 case AccessLength_DOUBLEWORD :
01737f42 1366 value = sim_core_read_aligned_8 (cpu, NULL_CIA,
63be8feb
AC		 1367 sim_core_read_map, pAddr);
1368 break;
1369 case AccessLength_SEPTIBYTE :
01737f42 1370 value = sim_core_read_misaligned_7 (cpu, NULL_CIA,
63be8feb
AC		 1371 sim_core_read_map, pAddr);
1372 case AccessLength_SEXTIBYTE :
01737f42 1373 value = sim_core_read_misaligned_6 (cpu, NULL_CIA,
63be8feb
AC		 1374 sim_core_read_map, pAddr);
1375 case AccessLength_QUINTIBYTE :
01737f42 1376 value = sim_core_read_misaligned_5 (cpu, NULL_CIA,
63be8feb
AC		 1377 sim_core_read_map, pAddr);
1378 case AccessLength_WORD :
01737f42 1379 value = sim_core_read_aligned_4 (cpu, NULL_CIA,
63be8feb
AC		 1380 sim_core_read_map, pAddr);
1381 break;
1382 case AccessLength_TRIPLEBYTE :
01737f42 1383 value = sim_core_read_misaligned_3 (cpu, NULL_CIA,
63be8feb
AC		 1384 sim_core_read_map, pAddr);
1385 case AccessLength_HALFWORD :
01737f42 1386 value = sim_core_read_aligned_2 (cpu, NULL_CIA,
63be8feb
AC		 1387 sim_core_read_map, pAddr);
1388 break;
1389 case AccessLength_BYTE :
01737f42 1390 value = sim_core_read_aligned_1 (cpu, NULL_CIA,
63be8feb
AC		 1391 sim_core_read_map, pAddr);
1392 break;
1393 default:
1394 abort ();
1395 }
1396
8bae0a0c 1397#ifdef DEBUG
63be8feb
AC		 1398 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1399 (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
8bae0a0c 1400#endif /* DEBUG */
63be8feb
AC		 1401
1402 /* See also store_memory. */
1403 if (AccessLength <= AccessLength_DOUBLEWORD)
1404 {
1405 if (BigEndianMem)
1406 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1407 shifted to the most significant byte position. */
1408 value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1409 else
1410 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1411 is already in the correct postition. */
1412 value <<= ((pAddr & LOADDRMASK) * 8);
1413 }
1414
8bae0a0c 1415#ifdef DEBUG
63be8feb
AC		 1416 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1417 pr_uword64(value1),pr_uword64(value));
e871dd18 1418#endif /* DEBUG */
63be8feb 1419
525d929e
AC		 1420 *memvalp = value;
1421 if (memval1p) *memval1p = value1;
8bae0a0c
JSC		 1422}
1423
53b9417e 1424
50a2a691
AC		 1425/* Description from page A-23 of the "MIPS IV Instruction Set" manual
1426 (revision 3.1) */
8bae0a0c
JSC		 1427/* Store a value to memory. The specified data is stored into the
1428 physical location pAddr using the memory hierarchy (data caches and
1429 main memory) as specified by the Cache Coherence Algorithm
1430 (CCA). The MemElem contains the data for an aligned, fixed-width
1431 memory element (word for 32-bit processors, doubleword for 64-bit
1432 processors), though only the bytes that will actually be stored to
1433 memory need to be valid. The low-order two (or three) bits of pAddr
1434 and the AccessLength field indicates which of the bytes within the
1435 MemElem data should actually be stored; only these bytes in memory
1436 will be changed. */
53b9417e 1437
18c64df6 1438void
01737f42
AC		 1439store_memory (SIM_DESC sd,
1440 sim_cpu *cpu,
1441 address_word cia,
1442 int CCA,
1443 int AccessLength,
1444 uword64 MemElem,
1445 uword64 MemElem1, /* High order 64 bits */
1446 address_word pAddr,
1447 address_word vAddr)
8bae0a0c
JSC		 1448{
1449#ifdef DEBUG
63be8feb 1450 sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
8bae0a0c 1451#endif /* DEBUG */
63be8feb 1452
8bae0a0c
JSC		 1453#if defined(WARN_MEM)
1454 if (CCA != uncached)
63be8feb 1455 sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
8bae0a0c 1456#endif /* WARN_MEM */
63be8feb
AC		 1457
1458 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1459 sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
1460
8bae0a0c 1461#if defined(TRACE)
01737f42 1462 dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
8bae0a0c 1463#endif /* TRACE */
63be8feb 1464
8bae0a0c 1465#ifdef DEBUG
63be8feb 1466 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
8bae0a0c 1467#endif /* DEBUG */
63be8feb
AC		 1468
1469 /* See also load_memory */
1470 if (AccessLength <= AccessLength_DOUBLEWORD)
1471 {
1472 if (BigEndianMem)
1473 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1474 shifted to the most significant byte position. */
1475 MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1476 else
1477 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1478 is already in the correct postition. */
1479 MemElem >>= ((pAddr & LOADDRMASK) * 8);
1480 }
1481
8bae0a0c 1482#ifdef DEBUG
63be8feb 1483 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
8bae0a0c 1484#endif /* DEBUG */
63be8feb
AC		 1485
1486 switch (AccessLength)
1487 {
1488 case AccessLength_QUADWORD :
1489 {
1490 unsigned_16 val = U16_8 (MemElem1, MemElem);
01737f42 1491 sim_core_write_aligned_16 (cpu, NULL_CIA,
63be8feb
AC		 1492 sim_core_write_map, pAddr, val);
1493 break;
8bae0a0c 1494 }
63be8feb 1495 case AccessLength_DOUBLEWORD :
01737f42 1496 sim_core_write_aligned_8 (cpu, NULL_CIA,
63be8feb
AC		 1497 sim_core_write_map, pAddr, MemElem);
1498 break;
1499 case AccessLength_SEPTIBYTE :
01737f42 1500 sim_core_write_misaligned_7 (cpu, NULL_CIA,
63be8feb
AC		 1501 sim_core_write_map, pAddr, MemElem);
1502 break;
1503 case AccessLength_SEXTIBYTE :
01737f42 1504 sim_core_write_misaligned_6 (cpu, NULL_CIA,
63be8feb
AC		 1505 sim_core_write_map, pAddr, MemElem);
1506 break;
1507 case AccessLength_QUINTIBYTE :
01737f42 1508 sim_core_write_misaligned_5 (cpu, NULL_CIA,
63be8feb
AC		 1509 sim_core_write_map, pAddr, MemElem);
1510 break;
1511 case AccessLength_WORD :
01737f42 1512 sim_core_write_aligned_4 (cpu, NULL_CIA,
63be8feb
AC		 1513 sim_core_write_map, pAddr, MemElem);
1514 break;
1515 case AccessLength_TRIPLEBYTE :
01737f42 1516 sim_core_write_misaligned_3 (cpu, NULL_CIA,
63be8feb
AC		 1517 sim_core_write_map, pAddr, MemElem);
1518 break;
1519 case AccessLength_HALFWORD :
01737f42 1520 sim_core_write_aligned_2 (cpu, NULL_CIA,
63be8feb
AC		 1521 sim_core_write_map, pAddr, MemElem);
1522 break;
1523 case AccessLength_BYTE :
01737f42 1524 sim_core_write_aligned_1 (cpu, NULL_CIA,
63be8feb
AC		 1525 sim_core_write_map, pAddr, MemElem);
1526 break;
1527 default:
1528 abort ();
1529 }
1530
8bae0a0c
JSC		 1531 return;
1532}
1533
53b9417e 1534
dad6f1f3 1535unsigned32
7ce8b917 1536ifetch32 (SIM_DESC sd,
01737f42 1537 sim_cpu *cpu,
7ce8b917
AC		 1538 address_word cia,
1539 address_word vaddr)
dad6f1f3
AC		 1540{
1541 /* Copy the action of the LW instruction */
1542 address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
1543 address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
1544 unsigned64 value;
1545 address_word paddr;
1546 unsigned32 instruction;
1547 unsigned byte;
1548 int cca;
1549 AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
1550 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
1551 LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
1552 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
1553 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
1554 return instruction;
1555}
1556
1557
8bae0a0c
JSC		 1558/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1559/* Order loads and stores to synchronise shared memory. Perform the
1560 action necessary to make the effects of groups of synchronizable
1561 loads and stores indicated by stype occur in the same order for all
1562 processors. */
ea985d24 1563void
01737f42
AC		 1564sync_operation (SIM_DESC sd,
1565 sim_cpu *cpu,
1566 address_word cia,
1567 int stype)
8bae0a0c
JSC		 1568{
1569#ifdef DEBUG
18c64df6 1570 sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
8bae0a0c
JSC		 1571#endif /* DEBUG */
1572 return;
1573}
1574
1575/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1576/* Signal an exception condition. This will result in an exception
1577 that aborts the instruction. The instruction operation pseudocode
50a2a691 1578 will never see a return from this function call. */
2e61a3ad 1579
18c64df6 1580void
7ce8b917 1581signal_exception (SIM_DESC sd,
01737f42 1582 sim_cpu *cpu,
7ce8b917
AC		 1583 address_word cia,
1584 int exception,...)
8bae0a0c 1585{
56e7c849 1586 int vector;
6eedf3f4
MA		 1587
1588#ifdef DEBUG
95469ceb 1589 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
6eedf3f4
MA		 1590#endif /* DEBUG */
1591
8bae0a0c
JSC		 1592 /* Ensure that any active atomic read/modify/write operation will fail: */
1593 LLBIT = 0;
1594
1595 switch (exception) {
1596 /* TODO: For testing purposes I have been ignoring TRAPs. In
1597 reality we should either simulate them, or allow the user to
6eedf3f4
MA		 1598 ignore them at run-time.
1599 Same for SYSCALL */
8bae0a0c 1600 case Trap :
95469ceb 1601 sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia));
8bae0a0c
JSC		 1602 break;
1603
6eedf3f4
MA		 1604 case SystemCall :
1605 {
1606 va_list ap;
1607 unsigned int instruction;
1608 unsigned int code;
1609
1610 va_start(ap,exception);
1611 instruction = va_arg(ap,unsigned int);
1612 va_end(ap);
1613
1614 code = (instruction >> 6) & 0xFFFFF;
1615
18c64df6 1616 sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
95469ceb 1617 code, pr_addr(cia));
6eedf3f4
MA		 1618 }
1619 break;
1620
1621 case DebugBreakPoint :
1622 if (! (Debug & Debug_DM))
1623 {
1624 if (INDELAYSLOT())
1625 {
1626 CANCELDELAYSLOT();
1627
1628 Debug |= Debug_DBD; /* signaled from within in delay slot */
95469ceb 1629 DEPC = cia - 4; /* reference the branch instruction */
6eedf3f4
MA		 1630 }
1631 else
1632 {
1633 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
95469ceb 1634 DEPC = cia;
6eedf3f4
MA		 1635 }
1636
1637 Debug |= Debug_DM; /* in debugging mode */
1638 Debug |= Debug_DBp; /* raising a DBp exception */
1639 PC = 0xBFC00200;
01737f42 1640 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
6eedf3f4
MA		 1641 }
1642 break;
1643
8bae0a0c
JSC		 1644 case ReservedInstruction :
1645 {
1646 va_list ap;
1647 unsigned int instruction;
1648 va_start(ap,exception);
1649 instruction = va_arg(ap,unsigned int);
1650 va_end(ap);
1651 /* Provide simple monitor support using ReservedInstruction
1652 exceptions. The following code simulates the fixed vector
1653 entry points into the IDT monitor by causing a simulator
1654 trap, performing the monitor operation, and returning to
1655 the address held in the $ra register (standard PCS return
1656 address). This means we only need to pre-load the vector
1657 space with suitable instruction values. For systems were
1658 actual trap instructions are used, we would not need to
1659 perform this magic. */
7ce8b917
AC		 1660 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1661 {
01737f42 1662 sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
7ce8b917
AC		 1663 /* NOTE: This assumes that a branch-and-link style
1664 instruction was used to enter the vector (which is the
1665 case with the current IDT monitor). */
01737f42 1666 sim_engine_restart (SD, CPU, NULL, RA);
7ce8b917 1667 }
7e6c297e
ILT		 1668 /* Look for the mips16 entry and exit instructions, and
1669 simulate a handler for them. */
95469ceb 1670 else if ((cia & 1) != 0
7e6c297e 1671 && (instruction & 0xf81f) == 0xe809
7ce8b917
AC		 1672 && (instruction & 0x0c0) != 0x0c0)
1673 {
01737f42 1674 mips16_entry (SD, CPU, cia, instruction);
7ce8b917
AC		 1675 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1676 }
1677 /* else fall through to normal exception processing */
95469ceb 1678 sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia));
8bae0a0c
JSC		 1679 }
1680
05d1322f 1681 case BreakPoint:
e3d12c65 1682#ifdef DEBUG
95469ceb 1683 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
8bae0a0c 1684#endif /* DEBUG */
05d1322f
JL		 1685 /* Keep a copy of the current A0 in-case this is the program exit
1686 breakpoint: */
1687 {
1688 va_list ap;
1689 unsigned int instruction;
1690 va_start(ap,exception);
1691 instruction = va_arg(ap,unsigned int);
1692 va_end(ap);
1693 /* Check for our special terminating BREAK: */
1694 if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
01737f42 1695 sim_engine_halt (SD, CPU, NULL, cia,
05d1322f
JL		 1696 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1697 }
1698 }
0c2c5f61 1699 if (STATE & simDELAYSLOT)
95469ceb 1700 PC = cia - 4; /* reference the branch instruction */
05d1322f 1701 else
95469ceb 1702 PC = cia;
01737f42 1703 sim_engine_halt (SD, CPU, NULL, cia,
232156de 1704 sim_stopped, SIM_SIGTRAP);
05d1322f
JL		 1705
1706 default:
8bae0a0c
JSC		 1707 /* Store exception code into current exception id variable (used
1708 by exit code): */
1709
1710 /* TODO: If not simulating exceptions then stop the simulator
1711 execution. At the moment we always stop the simulation. */
e3d12c65 1712
56e7c849
AC		 1713 /* See figure 5-17 for an outline of the code below */
1714 if (! (SR & status_EXL))
1715 {
1716 CAUSE = (exception << 2);
0c2c5f61 1717 if (STATE & simDELAYSLOT)
56e7c849 1718 {
0c2c5f61 1719 STATE &= ~simDELAYSLOT;
56e7c849 1720 CAUSE |= cause_BD;
95469ceb 1721 EPC = (cia - 4); /* reference the branch instruction */
56e7c849
AC		 1722 }
1723 else
95469ceb 1724 EPC = cia;
56e7c849
AC		 1725 /* FIXME: TLB et.al. */
1726 vector = 0x180;
1727 }
1728 else
1729 {
05d1322f 1730 CAUSE = (exception << 2);
56e7c849
AC		 1731 vector = 0x180;
1732 }
1733 SR |= status_EXL;
e3d12c65
DE		 1734 /* Store exception code into current exception id variable (used
1735 by exit code): */
56e7c849
AC		 1736 if (SR & status_BEV)
1737 PC = (signed)0xBFC00200 + 0x180;
1738 else
1739 PC = (signed)0x80000000 + 0x180;
1740
50a2a691
AC		 1741 switch ((CAUSE >> 2) & 0x1F)
1742 {
1743 case Interrupt:
56e7c849
AC		 1744 /* Interrupts arrive during event processing, no need to
1745 restart */
1746 return;
50a2a691
AC		 1747
1748 case TLBModification:
1749 case TLBLoad:
1750 case TLBStore:
1751 case AddressLoad:
1752 case AddressStore:
1753 case InstructionFetch:
1754 case DataReference:
56e7c849
AC		 1755 /* The following is so that the simulator will continue from the
1756 exception address on breakpoint operations. */
1757 PC = EPC;
01737f42 1758 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
232156de 1759 sim_stopped, SIM_SIGBUS);
50a2a691
AC		 1760
1761 case ReservedInstruction:
1762 case CoProcessorUnusable:
56e7c849 1763 PC = EPC;
01737f42 1764 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
232156de 1765 sim_stopped, SIM_SIGILL);
50a2a691
AC		 1766
1767 case IntegerOverflow:
1768 case FPE:
01737f42 1769 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
232156de 1770 sim_stopped, SIM_SIGFPE);
50a2a691
AC		 1771
1772 case Trap:
1773 case Watch:
1774 case SystemCall:
56e7c849 1775 PC = EPC;
01737f42 1776 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
232156de 1777 sim_stopped, SIM_SIGTRAP);
50a2a691 1778
05d1322f
JL		 1779 case BreakPoint:
1780 PC = EPC;
01737f42 1781 sim_engine_abort (SD, CPU, NULL_CIA,
05d1322f
JL		 1782 "FATAL: Should not encounter a breakpoint\n");
1783
50a2a691 1784 default : /* Unknown internal exception */
56e7c849 1785 PC = EPC;
01737f42 1786 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
232156de 1787 sim_stopped, SIM_SIGABRT);
50a2a691
AC		 1788
1789 }
8bae0a0c
JSC		 1790
1791 case SimulatorFault:
1792 {
1793 va_list ap;
1794 char *msg;
1795 va_start(ap,exception);
1796 msg = va_arg(ap,char *);
50a2a691 1797 va_end(ap);
01737f42 1798 sim_engine_abort (SD, CPU, NULL_CIA,
2e61a3ad 1799 "FATAL: Simulator error \"%s\"\n",msg);
8bae0a0c 1800 }
8bae0a0c
JSC		 1801 }
1802
1803 return;
1804}
1805
1806#if defined(WARN_RESULT)
1807/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1808/* This function indicates that the result of the operation is
1809 undefined. However, this should not affect the instruction
1810 stream. All that is meant to happen is that the destination
1811 register is set to an undefined result. To keep the simulator
1812 simple, we just don't bother updating the destination register, so
1813 the overall result will be undefined. If desired we can stop the
1814 simulator by raising a pseudo-exception. */
95469ceb 1815#define UndefinedResult() undefined_result (sd,cia)
8bae0a0c 1816static void
95469ceb
AC		 1817undefined_result(sd,cia)
1818 SIM_DESC sd;
1819 address_word cia;
8bae0a0c 1820{
95469ceb 1821 sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
8bae0a0c
JSC		 1822#if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1823 state |= simSTOP;
1824#endif
1825 return;
1826}
1827#endif /* WARN_RESULT */
1828
18c64df6 1829void
01737f42
AC		 1830cache_op (SIM_DESC sd,
1831 sim_cpu *cpu,
1832 address_word cia,
1833 int op,
1834 address_word pAddr,
1835 address_word vAddr,
1836 unsigned int instruction)
8bae0a0c 1837{
f24b7b69
JSC		 1838#if 1 /* stop warning message being displayed (we should really just remove the code) */
1839 static int icache_warning = 1;
1840 static int dcache_warning = 1;
1841#else
a9f7253f
JSC		 1842 static int icache_warning = 0;
1843 static int dcache_warning = 0;
f24b7b69 1844#endif
a9f7253f 1845
8bae0a0c
JSC		 1846 /* If CP0 is not useable (User or Supervisor mode) and the CP0
1847 enable bit in the Status Register is clear - a coprocessor
1848 unusable exception is taken. */
a9f7253f 1849#if 0
95469ceb 1850 sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia));
a9f7253f 1851#endif
8bae0a0c
JSC		 1852
1853 switch (op & 0x3) {
1854 case 0: /* instruction cache */
1855 switch (op >> 2) {
1856 case 0: /* Index Invalidate */
1857 case 1: /* Index Load Tag */
1858 case 2: /* Index Store Tag */
1859 case 4: /* Hit Invalidate */
1860 case 5: /* Fill */
1861 case 6: /* Hit Writeback */
a9f7253f
JSC		 1862 if (!icache_warning)
1863 {
18c64df6 1864 sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2));
a9f7253f
JSC		 1865 icache_warning = 1;
1866 }
8bae0a0c
JSC		 1867 break;
1868
1869 default:
1870 SignalException(ReservedInstruction,instruction);
1871 break;
1872 }
1873 break;
1874
1875 case 1: /* data cache */
1876 switch (op >> 2) {
1877 case 0: /* Index Writeback Invalidate */
1878 case 1: /* Index Load Tag */
1879 case 2: /* Index Store Tag */
1880 case 3: /* Create Dirty */
1881 case 4: /* Hit Invalidate */
1882 case 5: /* Hit Writeback Invalidate */
1883 case 6: /* Hit Writeback */
a9f7253f
JSC		 1884 if (!dcache_warning)
1885 {
18c64df6 1886 sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2));
a9f7253f
JSC		 1887 dcache_warning = 1;
1888 }
8bae0a0c
JSC		 1889 break;
1890
1891 default:
1892 SignalException(ReservedInstruction,instruction);
1893 break;
1894 }
1895 break;
1896
1897 default: /* unrecognised cache ID */
1898 SignalException(ReservedInstruction,instruction);
1899 break;
1900 }
1901
1902 return;
1903}
1904
1905/*-- FPU support routines ---------------------------------------------------*/
1906
8bae0a0c
JSC		 1907/* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1908 formats conform to ANSI/IEEE Std 754-1985. */
1909/* SINGLE precision floating:
1910 * seeeeeeeefffffffffffffffffffffff
1911 * s = 1bit = sign
1912 * e = 8bits = exponent
1913 * f = 23bits = fraction
1914 */
1915/* SINGLE precision fixed:
1916 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1917 * s = 1bit = sign
1918 * i = 31bits = integer
1919 */
1920/* DOUBLE precision floating:
1921 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1922 * s = 1bit = sign
1923 * e = 11bits = exponent
1924 * f = 52bits = fraction
1925 */
1926/* DOUBLE precision fixed:
1927 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1928 * s = 1bit = sign
1929 * i = 63bits = integer
1930 */
1931
1932/* Extract sign-bit: */
1933#define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
e871dd18 1934#define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
8bae0a0c
JSC		 1935/* Extract biased exponent: */
1936#define FP_S_be(v) (((v) >> 23) & 0xFF)
1937#define FP_D_be(v) (((v) >> 52) & 0x7FF)
1938/* Extract unbiased Exponent: */
1939#define FP_S_e(v) (FP_S_be(v) - 0x7F)
1940#define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1941/* Extract complete fraction field: */
1942#define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
e871dd18 1943#define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
8bae0a0c
JSC		 1944/* Extract numbered fraction bit: */
1945#define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1946#define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1947
1948/* Explicit QNaN values used when value required: */
1949#define FPQNaN_SINGLE (0x7FBFFFFF)
1950#define FPQNaN_WORD (0x7FFFFFFF)
e871dd18
JSC		 1951#define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1952#define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
8bae0a0c
JSC		 1953
1954/* Explicit Infinity values used when required: */
1955#define FPINF_SINGLE (0x7F800000)
e871dd18 1956#define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
8bae0a0c
JSC		 1957
1958#if 1 /* def DEBUG */
1959#define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1960#define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1961#endif /* DEBUG */
1962
18c64df6 1963uword64
01737f42
AC		 1964value_fpr (SIM_DESC sd,
1965 sim_cpu *cpu,
1966 address_word cia,
1967 int fpr,
1968 FP_formats fmt)
8bae0a0c 1969{
50a2a691 1970 uword64 value = 0;
8bae0a0c
JSC		 1971 int err = 0;
1972
1973 /* Treat unused register values, as fixed-point 64bit values: */
1974 if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
1975#if 1
1976 /* If request to read data as "uninterpreted", then use the current
1977 encoding: */
0c2c5f61 1978 fmt = FPR_STATE[fpr];
8bae0a0c
JSC		 1979#else
1980 fmt = fmt_long;
1981#endif
1982
1983 /* For values not yet accessed, set to the desired format: */
0c2c5f61
AC		 1984 if (FPR_STATE[fpr] == fmt_uninterpreted) {
1985 FPR_STATE[fpr] = fmt;
8bae0a0c
JSC		 1986#ifdef DEBUG
1987 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
1988#endif /* DEBUG */
1989 }
0c2c5f61 1990 if (fmt != FPR_STATE[fpr]) {
95469ceb 1991 sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
0c2c5f61 1992 FPR_STATE[fpr] = fmt_unknown;
8bae0a0c
JSC		 1993 }
1994
0c2c5f61 1995 if (FPR_STATE[fpr] == fmt_unknown) {
8bae0a0c
JSC		 1996 /* Set QNaN value: */
1997 switch (fmt) {
1998 case fmt_single:
1999 value = FPQNaN_SINGLE;
2000 break;
2001
2002 case fmt_double:
2003 value = FPQNaN_DOUBLE;
2004 break;
2005
2006 case fmt_word:
2007 value = FPQNaN_WORD;
2008 break;
2009
2010 case fmt_long:
2011 value = FPQNaN_LONG;
2012 break;
2013
2014 default:
2015 err = -1;
2016 break;
2017 }
2018 } else if (SizeFGR() == 64) {
2019 switch (fmt) {
2020 case fmt_single:
2021 case fmt_word:
2022 value = (FGR[fpr] & 0xFFFFFFFF);
2023 break;
2024
2025 case fmt_uninterpreted:
2026 case fmt_double:
2027 case fmt_long:
2028 value = FGR[fpr];
2029 break;
2030
2031 default :
2032 err = -1;
2033 break;
2034 }
da0bce9c 2035 } else {
8bae0a0c
JSC		 2036 switch (fmt) {
2037 case fmt_single:
2038 case fmt_word:
2039 value = (FGR[fpr] & 0xFFFFFFFF);
2040 break;
2041
2042 case fmt_uninterpreted:
2043 case fmt_double:
2044 case fmt_long:
da0bce9c
ILT		 2045 if ((fpr & 1) == 0) { /* even registers only */
2046 value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
2047 } else {
18c64df6 2048 SignalException(ReservedInstruction,0);
da0bce9c 2049 }
8bae0a0c
JSC		 2050 break;
2051
2052 default :
2053 err = -1;
2054 break;
2055 }
2056 }
2057
2058 if (err)
18c64df6 2059 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
8bae0a0c
JSC		 2060
2061#ifdef DEBUG
95469ceb 2062 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
8bae0a0c
JSC		 2063#endif /* DEBUG */
2064
2065 return(value);
2066}
2067
18c64df6 2068void
01737f42
AC		 2069store_fpr (SIM_DESC sd,
2070 sim_cpu *cpu,
2071 address_word cia,
2072 int fpr,
2073 FP_formats fmt,
2074 uword64 value)
8bae0a0c
JSC		 2075{
2076 int err = 0;
2077
2078#ifdef DEBUG
95469ceb 2079 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
8bae0a0c
JSC		 2080#endif /* DEBUG */
2081
2082 if (SizeFGR() == 64) {
2083 switch (fmt) {
a09a30d2
AC		 2084 case fmt_uninterpreted_32:
2085 fmt = fmt_uninterpreted;
8bae0a0c
JSC		 2086 case fmt_single :
2087 case fmt_word :
e871dd18 2088 FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
0c2c5f61 2089 FPR_STATE[fpr] = fmt;
8bae0a0c
JSC		 2090 break;
2091
a09a30d2
AC		 2092 case fmt_uninterpreted_64:
2093 fmt = fmt_uninterpreted;
8bae0a0c
JSC		 2094 case fmt_uninterpreted:
2095 case fmt_double :
2096 case fmt_long :
2097 FGR[fpr] = value;
0c2c5f61 2098 FPR_STATE[fpr] = fmt;
8bae0a0c
JSC		 2099 break;
2100
2101 default :
0c2c5f61 2102 FPR_STATE[fpr] = fmt_unknown;
8bae0a0c
JSC		 2103 err = -1;
2104 break;
2105 }
da0bce9c 2106 } else {
8bae0a0c 2107 switch (fmt) {
a09a30d2
AC		 2108 case fmt_uninterpreted_32:
2109 fmt = fmt_uninterpreted;
8bae0a0c
JSC		 2110 case fmt_single :
2111 case fmt_word :
8bae0a0c 2112 FGR[fpr] = (value & 0xFFFFFFFF);
0c2c5f61 2113 FPR_STATE[fpr] = fmt;
8bae0a0c
JSC		 2114 break;
2115
a09a30d2
AC		 2116 case fmt_uninterpreted_64:
2117 fmt = fmt_uninterpreted;
8bae0a0c
JSC		 2118 case fmt_uninterpreted:
2119 case fmt_double :
2120 case fmt_long :
da0bce9c
ILT		 2121 if ((fpr & 1) == 0) { /* even register number only */
2122 FGR[fpr+1] = (value >> 32);
2123 FGR[fpr] = (value & 0xFFFFFFFF);
0c2c5f61
AC		 2124 FPR_STATE[fpr + 1] = fmt;
2125 FPR_STATE[fpr] = fmt;
da0bce9c 2126 } else {
0c2c5f61
AC		 2127 FPR_STATE[fpr] = fmt_unknown;
2128 FPR_STATE[fpr + 1] = fmt_unknown;
18c64df6 2129 SignalException(ReservedInstruction,0);
da0bce9c 2130 }
8bae0a0c
JSC		 2131 break;
2132
2133 default :
0c2c5f61 2134 FPR_STATE[fpr] = fmt_unknown;
8bae0a0c
JSC		 2135 err = -1;
2136 break;
2137 }
e871dd18
JSC		 2138 }
2139#if defined(WARN_RESULT)
2140 else
2141 UndefinedResult();
2142#endif /* WARN_RESULT */
8bae0a0c
JSC		 2143
2144 if (err)
18c64df6 2145 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
8bae0a0c
JSC		 2146
2147#ifdef DEBUG
53b9417e 2148 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
8bae0a0c
JSC		 2149#endif /* DEBUG */
2150
2151 return;
2152}
2153
18c64df6 2154int
8bae0a0c 2155NaN(op,fmt)
e871dd18 2156 uword64 op;
8bae0a0c
JSC		 2157 FP_formats fmt;
2158{
2159 int boolean = 0;
8bae0a0c
JSC		 2160 switch (fmt) {
2161 case fmt_single:
8bae0a0c 2162 case fmt_word:
76ef4165
FL		 2163 {
2164 sim_fpu wop;
2165 sim_fpu_32to (&wop, op);
2166 boolean = sim_fpu_is_nan (&wop);
2167 break;
2168 }
2169 case fmt_double:
8bae0a0c 2170 case fmt_long:
76ef4165
FL		 2171 {
2172 sim_fpu wop;
2173 sim_fpu_64to (&wop, op);
2174 boolean = sim_fpu_is_nan (&wop);
2175 break;
2176 }
50a2a691
AC		 2177 default:
2178 fprintf (stderr, "Bad switch\n");
2179 abort ();
8bae0a0c
JSC		 2180 }
2181
2182#ifdef DEBUG
53b9417e 2183printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
8bae0a0c
JSC		 2184#endif /* DEBUG */
2185
2186 return(boolean);
2187}
2188
18c64df6 2189int
8bae0a0c 2190Infinity(op,fmt)
e871dd18 2191 uword64 op;
8bae0a0c
JSC		 2192 FP_formats fmt;
2193{
2194 int boolean = 0;
2195
2196#ifdef DEBUG
95469ceb 2197 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
8bae0a0c
JSC		 2198#endif /* DEBUG */
2199
8bae0a0c
JSC		 2200 switch (fmt) {
2201 case fmt_single:
76ef4165
FL		 2202 {
2203 sim_fpu wop;
2204 sim_fpu_32to (&wop, op);
2205 boolean = sim_fpu_is_infinity (&wop);
2206 break;
2207 }
8bae0a0c 2208 case fmt_double:
76ef4165
FL		 2209 {
2210 sim_fpu wop;
2211 sim_fpu_64to (&wop, op);
2212 boolean = sim_fpu_is_infinity (&wop);
2213 break;
2214 }
8bae0a0c
JSC		 2215 default:
2216 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
2217 break;
2218 }
2219
2220#ifdef DEBUG
53b9417e 2221 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
8bae0a0c
JSC		 2222#endif /* DEBUG */
2223
2224 return(boolean);
2225}
2226
18c64df6 2227int
8bae0a0c 2228Less(op1,op2,fmt)
e871dd18
JSC		 2229 uword64 op1;
2230 uword64 op2;
8bae0a0c
JSC		 2231 FP_formats fmt;
2232{
2233 int boolean = 0;
2234
e871dd18
JSC		 2235 /* Argument checking already performed by the FPCOMPARE code */
2236
8bae0a0c 2237#ifdef DEBUG
53b9417e 2238 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2239#endif /* DEBUG */
2240
8bae0a0c
JSC		 2241 /* The format type should already have been checked: */
2242 switch (fmt) {
2243 case fmt_single:
2244 {
76ef4165
FL		 2245 sim_fpu wop1;
2246 sim_fpu wop2;
2247 sim_fpu_32to (&wop1, op1);
2248 sim_fpu_32to (&wop2, op2);
2249 boolean = sim_fpu_is_lt (&wop1, &wop2);
2250 break;
8bae0a0c 2251 }
8bae0a0c 2252 case fmt_double:
76ef4165
FL		 2253 {
2254 sim_fpu wop1;
2255 sim_fpu wop2;
2256 sim_fpu_64to (&wop1, op1);
2257 sim_fpu_64to (&wop2, op2);
2258 boolean = sim_fpu_is_lt (&wop1, &wop2);
2259 break;
2260 }
50a2a691
AC		 2261 default:
2262 fprintf (stderr, "Bad switch\n");
2263 abort ();
8bae0a0c
JSC		 2264 }
2265
2266#ifdef DEBUG
2267 printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2268#endif /* DEBUG */
2269
2270 return(boolean);
2271}
2272
18c64df6 2273int
8bae0a0c 2274Equal(op1,op2,fmt)
e871dd18
JSC		 2275 uword64 op1;
2276 uword64 op2;
8bae0a0c
JSC		 2277 FP_formats fmt;
2278{
2279 int boolean = 0;
2280
e871dd18
JSC		 2281 /* Argument checking already performed by the FPCOMPARE code */
2282
8bae0a0c 2283#ifdef DEBUG
53b9417e 2284 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2285#endif /* DEBUG */
2286
8bae0a0c
JSC		 2287 /* The format type should already have been checked: */
2288 switch (fmt) {
2289 case fmt_single:
76ef4165
FL		 2290 {
2291 sim_fpu wop1;
2292 sim_fpu wop2;
2293 sim_fpu_32to (&wop1, op1);
2294 sim_fpu_32to (&wop2, op2);
2295 boolean = sim_fpu_is_eq (&wop1, &wop2);
2296 break;
2297 }
8bae0a0c 2298 case fmt_double:
76ef4165
FL		 2299 {
2300 sim_fpu wop1;
2301 sim_fpu wop2;
2302 sim_fpu_64to (&wop1, op1);
2303 sim_fpu_64to (&wop2, op2);
2304 boolean = sim_fpu_is_eq (&wop1, &wop2);
2305 break;
2306 }
50a2a691
AC		 2307 default:
2308 fprintf (stderr, "Bad switch\n");
2309 abort ();
8bae0a0c
JSC		 2310 }
2311
2312#ifdef DEBUG
2313 printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2314#endif /* DEBUG */
2315
2316 return(boolean);
2317}
2318
18c64df6 2319uword64
a9f7253f
JSC		 2320AbsoluteValue(op,fmt)
2321 uword64 op;
2322 FP_formats fmt;
2323{
50a2a691 2324 uword64 result = 0;
a9f7253f
JSC		 2325
2326#ifdef DEBUG
53b9417e 2327 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
a9f7253f
JSC		 2328#endif /* DEBUG */
2329
2330 /* The format type should already have been checked: */
2331 switch (fmt) {
2332 case fmt_single:
2333 {
76ef4165
FL		 2334 sim_fpu wop;
2335 unsigned32 ans;
2336 sim_fpu_32to (&wop, op);
2337 sim_fpu_abs (&wop, &wop);
2338 sim_fpu_to32 (&ans, &wop);
2339 result = ans;
2340 break;
a9f7253f 2341 }
a9f7253f
JSC		 2342 case fmt_double:
2343 {
76ef4165
FL		 2344 sim_fpu wop;
2345 unsigned64 ans;
2346 sim_fpu_64to (&wop, op);
2347 sim_fpu_abs (&wop, &wop);
2348 sim_fpu_to64 (&ans, &wop);
2349 result = ans;
2350 break;
a9f7253f 2351 }
50a2a691
AC		 2352 default:
2353 fprintf (stderr, "Bad switch\n");
2354 abort ();
a9f7253f
JSC		 2355 }
2356
2357 return(result);
2358}
2359
18c64df6 2360uword64
8bae0a0c 2361Negate(op,fmt)
e871dd18 2362 uword64 op;
8bae0a0c
JSC		 2363 FP_formats fmt;
2364{
50a2a691 2365 uword64 result = 0;
8bae0a0c
JSC		 2366
2367#ifdef DEBUG
53b9417e 2368 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
8bae0a0c
JSC		 2369#endif /* DEBUG */
2370
2371 /* The format type should already have been checked: */
2372 switch (fmt) {
2373 case fmt_single:
2374 {
76ef4165
FL		 2375 sim_fpu wop;
2376 unsigned32 ans;
2377 sim_fpu_32to (&wop, op);
2378 sim_fpu_neg (&wop, &wop);
2379 sim_fpu_to32 (&ans, &wop);
2380 result = ans;
2381 break;
8bae0a0c 2382 }
8bae0a0c
JSC		 2383 case fmt_double:
2384 {
76ef4165
FL		 2385 sim_fpu wop;
2386 unsigned64 ans;
2387 sim_fpu_64to (&wop, op);
2388 sim_fpu_neg (&wop, &wop);
2389 sim_fpu_to64 (&ans, &wop);
2390 result = ans;
2391 break;
8bae0a0c 2392 }
50a2a691
AC		 2393 default:
2394 fprintf (stderr, "Bad switch\n");
2395 abort ();
8bae0a0c
JSC		 2396 }
2397
2398 return(result);
2399}
2400
18c64df6 2401uword64
8bae0a0c 2402Add(op1,op2,fmt)
e871dd18
JSC		 2403 uword64 op1;
2404 uword64 op2;
8bae0a0c
JSC		 2405 FP_formats fmt;
2406{
50a2a691 2407 uword64 result = 0;
8bae0a0c
JSC		 2408
2409#ifdef DEBUG
53b9417e 2410 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2411#endif /* DEBUG */
2412
e871dd18
JSC		 2413 /* The registers must specify FPRs valid for operands of type
2414 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2415
2416 /* The format type should already have been checked: */
2417 switch (fmt) {
2418 case fmt_single:
2419 {
76ef4165
FL		 2420 sim_fpu wop1;
2421 sim_fpu wop2;
2422 sim_fpu ans;
2423 unsigned32 res;
2424 sim_fpu_32to (&wop1, op1);
2425 sim_fpu_32to (&wop2, op2);
2426 sim_fpu_add (&ans, &wop1, &wop2);
2427 sim_fpu_to32 (&res, &ans);
2428 result = res;
2429 break;
8bae0a0c 2430 }
8bae0a0c
JSC		 2431 case fmt_double:
2432 {
76ef4165
FL		 2433 sim_fpu wop1;
2434 sim_fpu wop2;
2435 sim_fpu ans;
2436 unsigned64 res;
2437 sim_fpu_64to (&wop1, op1);
2438 sim_fpu_64to (&wop2, op2);
2439 sim_fpu_add (&ans, &wop1, &wop2);
2440 sim_fpu_to64 (&res, &ans);
2441 result = res;
2442 break;
8bae0a0c 2443 }
50a2a691
AC		 2444 default:
2445 fprintf (stderr, "Bad switch\n");
2446 abort ();
8bae0a0c
JSC		 2447 }
2448
2449#ifdef DEBUG
53b9417e 2450 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2451#endif /* DEBUG */
2452
2453 return(result);
2454}
2455
18c64df6 2456uword64
8bae0a0c 2457Sub(op1,op2,fmt)
e871dd18
JSC		 2458 uword64 op1;
2459 uword64 op2;
8bae0a0c
JSC		 2460 FP_formats fmt;
2461{
50a2a691 2462 uword64 result = 0;
8bae0a0c
JSC		 2463
2464#ifdef DEBUG
53b9417e 2465 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2466#endif /* DEBUG */
2467
e871dd18
JSC		 2468 /* The registers must specify FPRs valid for operands of type
2469 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2470
2471 /* The format type should already have been checked: */
2472 switch (fmt) {
2473 case fmt_single:
2474 {
76ef4165
FL		 2475 sim_fpu wop1;
2476 sim_fpu wop2;
2477 sim_fpu ans;
2478 unsigned32 res;
2479 sim_fpu_32to (&wop1, op1);
2480 sim_fpu_32to (&wop2, op2);
2481 sim_fpu_sub (&ans, &wop1, &wop2);
2482 sim_fpu_to32 (&res, &ans);
2483 result = res;
8bae0a0c
JSC		 2484 }
2485 break;
2486 case fmt_double:
2487 {
76ef4165
FL		 2488 sim_fpu wop1;
2489 sim_fpu wop2;
2490 sim_fpu ans;
2491 unsigned64 res;
2492 sim_fpu_64to (&wop1, op1);
2493 sim_fpu_64to (&wop2, op2);
2494 sim_fpu_sub (&ans, &wop1, &wop2);
2495 sim_fpu_to64 (&res, &ans);
2496 result = res;
8bae0a0c
JSC		 2497 }
2498 break;
50a2a691
AC		 2499 default:
2500 fprintf (stderr, "Bad switch\n");
2501 abort ();
8bae0a0c
JSC		 2502 }
2503
2504#ifdef DEBUG
53b9417e 2505 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2506#endif /* DEBUG */
2507
2508 return(result);
2509}
2510
18c64df6 2511uword64
8bae0a0c 2512Multiply(op1,op2,fmt)
e871dd18
JSC		 2513 uword64 op1;
2514 uword64 op2;
8bae0a0c
JSC		 2515 FP_formats fmt;
2516{
50a2a691 2517 uword64 result = 0;
8bae0a0c
JSC		 2518
2519#ifdef DEBUG
53b9417e 2520 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2521#endif /* DEBUG */
2522
e871dd18
JSC		 2523 /* The registers must specify FPRs valid for operands of type
2524 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2525
2526 /* The format type should already have been checked: */
2527 switch (fmt) {
2528 case fmt_single:
2529 {
76ef4165
FL		 2530 sim_fpu wop1;
2531 sim_fpu wop2;
2532 sim_fpu ans;
2533 unsigned32 res;
2534 sim_fpu_32to (&wop1, op1);
2535 sim_fpu_32to (&wop2, op2);
2536 sim_fpu_mul (&ans, &wop1, &wop2);
2537 sim_fpu_to32 (&res, &ans);
2538 result = res;
2539 break;
8bae0a0c 2540 }
8bae0a0c
JSC		 2541 case fmt_double:
2542 {
76ef4165
FL		 2543 sim_fpu wop1;
2544 sim_fpu wop2;
2545 sim_fpu ans;
2546 unsigned64 res;
2547 sim_fpu_64to (&wop1, op1);
2548 sim_fpu_64to (&wop2, op2);
2549 sim_fpu_mul (&ans, &wop1, &wop2);
2550 sim_fpu_to64 (&res, &ans);
2551 result = res;
2552 break;
8bae0a0c 2553 }
50a2a691
AC		 2554 default:
2555 fprintf (stderr, "Bad switch\n");
2556 abort ();
8bae0a0c
JSC		 2557 }
2558
2559#ifdef DEBUG
53b9417e 2560 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2561#endif /* DEBUG */
2562
2563 return(result);
2564}
2565
18c64df6 2566uword64
8bae0a0c 2567Divide(op1,op2,fmt)
e871dd18
JSC		 2568 uword64 op1;
2569 uword64 op2;
8bae0a0c
JSC		 2570 FP_formats fmt;
2571{
50a2a691 2572 uword64 result = 0;
8bae0a0c
JSC		 2573
2574#ifdef DEBUG
53b9417e 2575 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2576#endif /* DEBUG */
2577
e871dd18
JSC		 2578 /* The registers must specify FPRs valid for operands of type
2579 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2580
2581 /* The format type should already have been checked: */
2582 switch (fmt) {
2583 case fmt_single:
2584 {
76ef4165
FL		 2585 sim_fpu wop1;
2586 sim_fpu wop2;
2587 sim_fpu ans;
2588 unsigned32 res;
2589 sim_fpu_32to (&wop1, op1);
2590 sim_fpu_32to (&wop2, op2);
2591 sim_fpu_div (&ans, &wop1, &wop2);
2592 sim_fpu_to32 (&res, &ans);
2593 result = res;
2594 break;
8bae0a0c 2595 }
8bae0a0c
JSC		 2596 case fmt_double:
2597 {
76ef4165
FL		 2598 sim_fpu wop1;
2599 sim_fpu wop2;
2600 sim_fpu ans;
2601 unsigned64 res;
2602 sim_fpu_64to (&wop1, op1);
2603 sim_fpu_64to (&wop2, op2);
2604 sim_fpu_div (&ans, &wop1, &wop2);
2605 sim_fpu_to64 (&res, &ans);
2606 result = res;
2607 break;
8bae0a0c 2608 }
50a2a691
AC		 2609 default:
2610 fprintf (stderr, "Bad switch\n");
2611 abort ();
8bae0a0c
JSC		 2612 }
2613
2614#ifdef DEBUG
53b9417e 2615 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2616#endif /* DEBUG */
2617
2618 return(result);
2619}
2620
18c64df6 2621uword64 UNUSED
8bae0a0c 2622Recip(op,fmt)
e871dd18 2623 uword64 op;
8bae0a0c
JSC		 2624 FP_formats fmt;
2625{
50a2a691 2626 uword64 result = 0;
8bae0a0c
JSC		 2627
2628#ifdef DEBUG
53b9417e 2629 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
8bae0a0c
JSC		 2630#endif /* DEBUG */
2631
e871dd18
JSC		 2632 /* The registers must specify FPRs valid for operands of type
2633 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2634
2635 /* The format type should already have been checked: */
2636 switch (fmt) {
2637 case fmt_single:
2638 {
76ef4165
FL		 2639 sim_fpu wop;
2640 sim_fpu ans;
2641 unsigned32 res;
2642 sim_fpu_32to (&wop, op);
2643 sim_fpu_inv (&ans, &wop);
2644 sim_fpu_to32 (&res, &ans);
2645 result = res;
2646 break;
8bae0a0c 2647 }
8bae0a0c
JSC		 2648 case fmt_double:
2649 {
76ef4165
FL		 2650 sim_fpu wop;
2651 sim_fpu ans;
2652 unsigned64 res;
2653 sim_fpu_64to (&wop, op);
2654 sim_fpu_inv (&ans, &wop);
2655 sim_fpu_to64 (&res, &ans);
2656 result = res;
2657 break;
8bae0a0c 2658 }
50a2a691
AC		 2659 default:
2660 fprintf (stderr, "Bad switch\n");
2661 abort ();
8bae0a0c
JSC		 2662 }
2663
2664#ifdef DEBUG
53b9417e 2665 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2666#endif /* DEBUG */
2667
2668 return(result);
2669}
2670
18c64df6 2671uword64
8bae0a0c 2672SquareRoot(op,fmt)
e871dd18 2673 uword64 op;
8bae0a0c
JSC		 2674 FP_formats fmt;
2675{
50a2a691 2676 uword64 result = 0;
8bae0a0c
JSC		 2677
2678#ifdef DEBUG
53b9417e 2679 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
8bae0a0c
JSC		 2680#endif /* DEBUG */
2681
e871dd18
JSC		 2682 /* The registers must specify FPRs valid for operands of type
2683 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2684
2685 /* The format type should already have been checked: */
2686 switch (fmt) {
2687 case fmt_single:
2688 {
76ef4165
FL		 2689 sim_fpu wop;
2690 sim_fpu ans;
2691 unsigned32 res;
2692 sim_fpu_32to (&wop, op);
2693 sim_fpu_sqrt (&ans, &wop);
2694 sim_fpu_to32 (&res, &ans);
2695 result = res;
2696 break;
8bae0a0c 2697 }
8bae0a0c
JSC		 2698 case fmt_double:
2699 {
76ef4165
FL		 2700 sim_fpu wop;
2701 sim_fpu ans;
2702 unsigned64 res;
2703 sim_fpu_64to (&wop, op);
2704 sim_fpu_sqrt (&ans, &wop);
2705 sim_fpu_to64 (&res, &ans);
2706 result = res;
2707 break;
8bae0a0c 2708 }
50a2a691
AC		 2709 default:
2710 fprintf (stderr, "Bad switch\n");
2711 abort ();
8bae0a0c
JSC		 2712 }
2713
2714#ifdef DEBUG
53b9417e 2715 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2716#endif /* DEBUG */
2717
2718 return(result);
2719}
2720
18c64df6 2721uword64
01737f42
AC		 2722convert (SIM_DESC sd,
2723 sim_cpu *cpu,
2724 address_word cia,
2725 int rm,
2726 uword64 op,
2727 FP_formats from,
2728 FP_formats to)
8bae0a0c 2729{
76ef4165
FL		 2730 sim_fpu wop;
2731 sim_fpu_round round;
2732 unsigned32 result32;
2733 unsigned64 result64;
8bae0a0c
JSC		 2734
2735#ifdef DEBUG
53b9417e 2736 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
8bae0a0c
JSC		 2737#endif /* DEBUG */
2738
76ef4165 2739 switch (rm)
8bae0a0c 2740 {
76ef4165
FL		 2741 case FP_RM_NEAREST:
2742 /* Round result to nearest representable value. When two
2743 representable values are equally near, round to the value
2744 that has a least significant bit of zero (i.e. is even). */
2745 round = sim_fpu_round_near;
2746 break;
2747 case FP_RM_TOZERO:
2748 /* Round result to the value closest to, and not greater in
2749 magnitude than, the result. */
2750 round = sim_fpu_round_zero;
2751 break;
2752 case FP_RM_TOPINF:
2753 /* Round result to the value closest to, and not less than,
2754 the result. */
2755 round = sim_fpu_round_up;
2756 break;
2757
2758 case FP_RM_TOMINF:
2759 /* Round result to the value closest to, and not greater than,
2760 the result. */
2761 round = sim_fpu_round_down;
2762 break;
2763 default:
2764 round = 0;
2765 fprintf (stderr, "Bad switch\n");
2766 abort ();
8bae0a0c 2767 }
76ef4165
FL		 2768
2769 /* Convert the input to sim_fpu internal format */
2770 switch (from)
8bae0a0c 2771 {
76ef4165
FL		 2772 case fmt_double:
2773 sim_fpu_64to (&wop, op);
2774 break;
2775 case fmt_single:
2776 sim_fpu_32to (&wop, op);
2777 break;
2778 case fmt_word:
2779 sim_fpu_i32to (&wop, op, round);
2780 break;
2781 case fmt_long:
2782 sim_fpu_i64to (&wop, op, round);
2783 break;
2784 default:
2785 fprintf (stderr, "Bad switch\n");
2786 abort ();
8bae0a0c 2787 }
8bae0a0c 2788
76ef4165
FL		 2789 /* Convert sim_fpu format into the output */
2790 /* The value WOP is converted to the destination format, rounding
2791 using mode RM. When the destination is a fixed-point format, then
2792 a source value of Infinity, NaN or one which would round to an
2793 integer outside the fixed point range then an IEEE Invalid
2794 Operation condition is raised. */
2795 switch (to)
2796 {
2797 case fmt_single:
2798 sim_fpu_round_32 (&wop, round, 0);
2799 sim_fpu_to32 (&result32, &wop);
2800 result64 = result32;
2801 break;
2802 case fmt_double:
2803 sim_fpu_round_64 (&wop, round, 0);
2804 sim_fpu_to64 (&result64, &wop);
2805 break;
2806 case fmt_word:
2807 sim_fpu_to32i (&result32, &wop, round);
2808 result64 = result32;
2809 break;
2810 case fmt_long:
2811 sim_fpu_to64i (&result64, &wop, round);
2812 break;
2813 default:
2814 result64 = 0;
2815 fprintf (stderr, "Bad switch\n");
2816 abort ();
8bae0a0c 2817 }
76ef4165 2818
8bae0a0c 2819#ifdef DEBUG
76ef4165 2820 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
8bae0a0c
JSC		 2821#endif /* DEBUG */
2822
76ef4165 2823 return(result64);
8bae0a0c 2824}
8bae0a0c 2825
76ef4165 2826
8bae0a0c
JSC		 2827/*-- co-processor support routines ------------------------------------------*/
2828
2f2e6c5d 2829static int UNUSED
8bae0a0c
JSC		 2830CoProcPresent(coproc_number)
2831 unsigned int coproc_number;
2832{
2833 /* Return TRUE if simulator provides a model for the given co-processor number */
2834 return(0);
2835}
2836
18c64df6 2837void
01737f42
AC		 2838cop_lw (SIM_DESC sd,
2839 sim_cpu *cpu,
2840 address_word cia,
2841 int coproc_num,
2842 int coproc_reg,
2843 unsigned int memword)
8bae0a0c 2844{
192ae475
AC		 2845 switch (coproc_num)
2846 {
8bae0a0c 2847 case 1:
192ae475
AC		 2848 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2849 {
8bae0a0c 2850#ifdef DEBUG
192ae475 2851 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
8bae0a0c 2852#endif
192ae475
AC		 2853 StoreFPR(coproc_reg,fmt_word,(uword64)memword);
2854 FPR_STATE[coproc_reg] = fmt_uninterpreted;
2855 break;
2856 }
8bae0a0c
JSC		 2857
2858 default:
f24b7b69 2859#if 0 /* this should be controlled by a configuration option */
192ae475 2860 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
f24b7b69 2861#endif
192ae475
AC		 2862 break;
2863 }
8bae0a0c
JSC		 2864
2865 return;
2866}
2867
18c64df6 2868void
01737f42
AC		 2869cop_ld (SIM_DESC sd,
2870 sim_cpu *cpu,
2871 address_word cia,
2872 int coproc_num,
2873 int coproc_reg,
2874 uword64 memword)
8bae0a0c
JSC		 2875{
2876 switch (coproc_num) {
8bae0a0c 2877 case 1:
192ae475
AC		 2878 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2879 {
2880 StoreFPR(coproc_reg,fmt_uninterpreted,memword);
2881 break;
2882 }
8bae0a0c
JSC		 2883
2884 default:
f24b7b69 2885#if 0 /* this message should be controlled by a configuration option */
95469ceb 2886 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
f24b7b69 2887#endif
8bae0a0c
JSC		 2888 break;
2889 }
2890
2891 return;
2892}
2893
18c64df6 2894unsigned int
01737f42
AC		 2895cop_sw (SIM_DESC sd,
2896 sim_cpu *cpu,
2897 address_word cia,
2898 int coproc_num,
2899 int coproc_reg)
8bae0a0c
JSC		 2900{
2901 unsigned int value = 0;
da0bce9c 2902
192ae475
AC		 2903 switch (coproc_num)
2904 {
8bae0a0c 2905 case 1:
192ae475
AC		 2906 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2907 {
2908 FP_formats hold;
2909 hold = FPR_STATE[coproc_reg];
2910 FPR_STATE[coproc_reg] = fmt_word;
2911 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
2912 FPR_STATE[coproc_reg] = hold;
2913 break;
2914 }
8bae0a0c
JSC		 2915
2916 default:
f24b7b69 2917#if 0 /* should be controlled by configuration option */
192ae475 2918 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
f24b7b69 2919#endif
192ae475
AC		 2920 break;
2921 }
8bae0a0c
JSC		 2922
2923 return(value);
2924}
2925
18c64df6 2926uword64
01737f42
AC		 2927cop_sd (SIM_DESC sd,
2928 sim_cpu *cpu,
2929 address_word cia,
2930 int coproc_num,
2931 int coproc_reg)
8bae0a0c 2932{
e871dd18 2933 uword64 value = 0;
192ae475
AC		 2934 switch (coproc_num)
2935 {
8bae0a0c 2936 case 1:
192ae475
AC		 2937 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2938 {
2939 value = ValueFPR(coproc_reg,fmt_uninterpreted);
2940 break;
2941 }
8bae0a0c
JSC		 2942
2943 default:
f24b7b69 2944#if 0 /* should be controlled by configuration option */
192ae475 2945 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
f24b7b69 2946#endif
192ae475
AC		 2947 break;
2948 }
8bae0a0c
JSC		 2949
2950 return(value);
2951}
2952
ea985d24 2953void
01737f42
AC		 2954decode_coproc (SIM_DESC sd,
2955 sim_cpu *cpu,
2956 address_word cia,
2957 unsigned int instruction)
8bae0a0c
JSC		 2958{
2959 int coprocnum = ((instruction >> 26) & 3);
2960
56e7c849
AC		 2961 switch (coprocnum)
2962 {
8bae0a0c
JSC		 2963 case 0: /* standard CPU control and cache registers */
2964 {
8bae0a0c
JSC		 2965 int code = ((instruction >> 21) & 0x1F);
2966 /* R4000 Users Manual (second edition) lists the following CP0
2967 instructions:
56e7c849
AC		 2968 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2969 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2970 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2971 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2972 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2973 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2974 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2975 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2976 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2977 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2978 */
2979 if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
2980 {
2981 int rt = ((instruction >> 16) & 0x1F);
2982 int rd = ((instruction >> 11) & 0x1F);
2983
2984 switch (rd) /* NOTEs: Standard CP0 registers */
2985 {
2986 /* 0 = Index R4000 VR4100 VR4300 */
2987 /* 1 = Random R4000 VR4100 VR4300 */
2988 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2989 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2990 /* 4 = Context R4000 VR4100 VR4300 */
2991 /* 5 = PageMask R4000 VR4100 VR4300 */
2992 /* 6 = Wired R4000 VR4100 VR4300 */
2993 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2994 /* 9 = Count R4000 VR4100 VR4300 */
2995 /* 10 = EntryHi R4000 VR4100 VR4300 */
2996 /* 11 = Compare R4000 VR4100 VR4300 */
2997 /* 12 = SR R4000 VR4100 VR4300 */
2998 case 12:
2999 if (code == 0x00)
3000 GPR[rt] = SR;
3001 else
3002 SR = GPR[rt];
3003 break;
3004 /* 13 = Cause R4000 VR4100 VR4300 */
05d1322f
JL		 3005 case 13:
3006 if (code == 0x00)
3007 GPR[rt] = CAUSE;
3008 else
3009 CAUSE = GPR[rt];
3010 break;
56e7c849
AC		 3011 /* 14 = EPC R4000 VR4100 VR4300 */
3012 /* 15 = PRId R4000 VR4100 VR4300 */
6eedf3f4
MA		 3013#ifdef SUBTARGET_R3900
3014 /* 16 = Debug */
3015 case 16:
3016 if (code == 0x00)
3017 GPR[rt] = Debug;
3018 else
3019 Debug = GPR[rt];
3020 break;
3021#else
56e7c849 3022 /* 16 = Config R4000 VR4100 VR4300 */
a09a30d2
AC		 3023 case 16:
3024 if (code == 0x00)
3025 GPR[rt] = C0_CONFIG;
3026 else
3027 C0_CONFIG = GPR[rt];
3028 break;
6eedf3f4
MA		 3029#endif
3030#ifdef SUBTARGET_R3900
3031 /* 17 = Debug */
3032 case 17:
3033 if (code == 0x00)
3034 GPR[rt] = DEPC;
3035 else
3036 DEPC = GPR[rt];
3037 break;
3038#else
56e7c849 3039 /* 17 = LLAddr R4000 VR4100 VR4300 */
6eedf3f4 3040#endif
56e7c849
AC		 3041 /* 18 = WatchLo R4000 VR4100 VR4300 */
3042 /* 19 = WatchHi R4000 VR4100 VR4300 */
3043 /* 20 = XContext R4000 VR4100 VR4300 */
3044 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3045 /* 27 = CacheErr R4000 VR4100 */
3046 /* 28 = TagLo R4000 VR4100 VR4300 */
3047 /* 29 = TagHi R4000 VR4100 VR4300 */
3048 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3049 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
3050 /* CPR[0,rd] = GPR[rt]; */
3051 default:
3052 if (code == 0x00)
18c64df6 3053 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
56e7c849 3054 else
18c64df6 3055 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
56e7c849
AC		 3056 }
3057 }
3058 else if (code == 0x10 && (instruction & 0x3f) == 0x18)
3059 {
3060 /* ERET */
3061 if (SR & status_ERL)
3062 {
3063 /* Oops, not yet available */
18c64df6 3064 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
56e7c849
AC		 3065 PC = EPC;
3066 SR &= ~status_ERL;
3067 }
3068 else
3069 {
3070 PC = EPC;
3071 SR &= ~status_EXL;
3072 }
3073 }
6eedf3f4
MA		 3074 else if (code == 0x10 && (instruction & 0x3f) == 0x10)
3075 {
3076 /* RFE */
3077 }
3078 else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
3079 {
3080 /* DERET */
3081 Debug &= ~Debug_DM;
3082 DELAYSLOT();
3083 DSPC = DEPC;
3084 }
56e7c849 3085 else
95469ceb 3086 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
e871dd18 3087 /* TODO: When executing an ERET or RFE instruction we should
8bae0a0c
JSC		 3088 clear LLBIT, to ensure that any out-standing atomic
3089 read/modify/write sequence fails. */
3090 }
56e7c849
AC		 3091 break;
3092
8bae0a0c 3093 case 2: /* undefined co-processor */
95469ceb 3094 sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
8bae0a0c 3095 break;
56e7c849 3096
8bae0a0c
JSC		 3097 case 1: /* should not occur (FPU co-processor) */
3098 case 3: /* should not occur (FPU co-processor) */
3099 SignalException(ReservedInstruction,instruction);
3100 break;
56e7c849
AC		 3101 }
3102
8bae0a0c
JSC		 3103 return;
3104}
3105
3106/*-- instruction simulation -------------------------------------------------*/
3107
16bd5d6e
AC		 3108/* When the IGEN simulator is being built, the function below is be
3109 replaced by a generated version. However, WITH_IGEN == 2 indicates
3110 that the fubction below should be compiled but under a different
3111 name (to allow backward compatibility) */
3112
3113#if (WITH_IGEN != 1)
3114#if (WITH_IGEN > 1)
dad6f1f3
AC		 3115void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
3116void
9ec6741b 3117old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
dad6f1f3 3118#else
2e61a3ad 3119void
9ec6741b 3120sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
dad6f1f3 3121#endif
2e61a3ad
AC		 3122 SIM_DESC sd;
3123 int next_cpu_nr; /* ignore */
9ec6741b 3124 int nr_cpus; /* ignore */
2e61a3ad 3125 int siggnal; /* ignore */
8bae0a0c 3126{
01737f42 3127 sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
50a2a691 3128#if !defined(FASTSIM)
8bae0a0c 3129 unsigned int pipeline_count = 1;
50a2a691 3130#endif
8bae0a0c
JSC		 3131
3132#ifdef DEBUG
50a2a691 3133 if (STATE_MEMORY (sd) == NULL) {
8bae0a0c
JSC		 3134 printf("DBG: simulate() entered with no memory\n");
3135 exit(1);
3136 }
3137#endif /* DEBUG */
3138
3139#if 0 /* Disabled to check that everything works OK */
3140 /* The VR4300 seems to sign-extend the PC on its first
3141 access. However, this may just be because it is currently
3142 configured in 32bit mode. However... */
3143 PC = SIGNEXTEND(PC,32);
3144#endif
3145
3146 /* main controlling loop */
2e61a3ad 3147 while (1) {
7ce8b917
AC		 3148 /* vaddr is slowly being replaced with cia - current instruction
3149 address */
3150 address_word cia = (uword64)PC;
3151 address_word vaddr = cia;
dad6f1f3 3152 address_word paddr;
8bae0a0c 3153 int cca;
53b9417e 3154 unsigned int instruction; /* uword64? what's this used for? FIXME! */
8bae0a0c
JSC		 3155
3156#ifdef DEBUG
3157 {
3158 printf("DBG: state = 0x%08X :",state);
8bae0a0c
JSC		 3159 if (state & simHALTEX) printf(" simHALTEX");
3160 if (state & simHALTIN) printf(" simHALTIN");
53b9417e 3161 printf("\n");
8bae0a0c
JSC		 3162 }
3163#endif /* DEBUG */
3164
0c2c5f61 3165 DSSTATE = (STATE & simDELAYSLOT);
8bae0a0c
JSC		 3166#ifdef DEBUG
3167 if (dsstate)
18c64df6 3168 sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
8bae0a0c
JSC		 3169#endif /* DEBUG */
3170
7ce8b917
AC		 3171 /* Fetch the next instruction from the simulator memory: */
3172 if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
6429b296
JW		 3173 if ((vaddr & 1) == 0) {
3174 /* Copy the action of the LW instruction */
3175 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
3176 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
3177 uword64 value;
3178 unsigned int byte;
3179 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
53b9417e 3180 LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
6429b296
JW		 3181 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
3182 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
3183 } else {
3184 /* Copy the action of the LH instruction */
3185 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
3186 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
3187 uword64 value;
3188 unsigned int byte;
3189 paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
3190 | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
53b9417e 3191 LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
6429b296
JW		 3192 paddr & ~ (uword64) 1,
3193 vaddr, isINSTRUCTION, isREAL);
3194 byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
3195 instruction = ((value >> (8 * byte)) & 0xFFFF);
3196 }
8bae0a0c 3197 } else {
53b9417e 3198 fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
8bae0a0c
JSC		 3199 exit(1);
3200 }
3201
3202#ifdef DEBUG
18c64df6 3203 sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
8bae0a0c
JSC		 3204#endif /* DEBUG */
3205
8bae0a0c
JSC		 3206 /* This is required by exception processing, to ensure that we can
3207 cope with exceptions in the delay slots of branches that may
3208 already have changed the PC. */
6429b296
JW		 3209 if ((vaddr & 1) == 0)
3210 PC += 4; /* increment ready for the next fetch */
3211 else
3212 PC += 2;
8bae0a0c
JSC		 3213 /* NOTE: If we perform a delay slot change to the PC, this
3214 increment is not requuired. However, it would make the
3215 simulator more complicated to try and avoid this small hit. */
3216
3217 /* Currently this code provides a simple model. For more
3218 complicated models we could perform exception status checks at
3219 this point, and set the simSTOP state as required. This could
3220 also include processing any hardware interrupts raised by any
3221 I/O model attached to the simulator context.
3222
3223 Support for "asynchronous" I/O events within the simulated world
3224 could be providing by managing a counter, and calling a I/O
3225 specific handler when a particular threshold is reached. On most
3226 architectures a decrement and check for zero operation is
3227 usually quicker than an increment and compare. However, the
3228 process of managing a known value decrement to zero, is higher
3229 than the cost of using an explicit value UINT_MAX into the
3230 future. Which system is used will depend on how complicated the
3231 I/O model is, and how much it is likely to affect the simulator
3232 bandwidth.
3233
3234 If events need to be scheduled further in the future than
3235 UINT_MAX event ticks, then the I/O model should just provide its
3236 own counter, triggered from the event system. */
3237
3238 /* MIPS pipeline ticks. To allow for future support where the
3239 pipeline hit of individual instructions is known, this control
3240 loop manages a "pipeline_count" variable. It is initialised to
3241 1 (one), and will only be changed by the simulator engine when
3242 executing an instruction. If the engine does not have access to
3243 pipeline cycle count information then all instructions will be
3244 treated as using a single cycle. NOTE: A standard system is not
3245 provided by the default simulator because different MIPS
3246 architectures have different cycle counts for the same
50a2a691
AC		 3247 instructions.
3248
3249 [NOTE: pipeline_count has been replaced the event queue] */
8bae0a0c 3250
a09a30d2
AC		 3251 /* shuffle the floating point status pipeline state */
3252 ENGINE_ISSUE_PREFIX_HOOK();
8bae0a0c
JSC		 3253
3254/* NOTE: For multi-context simulation environments the "instruction"
3255 variable should be local to this routine. */
3256
3257/* Shorthand accesses for engine. Note: If we wanted to use global
3258 variables (and a single-threaded simulator engine), then we can
3259 create the actual variables with these names. */
3260
0c2c5f61 3261 if (!(STATE & simSKIPNEXT)) {
8bae0a0c 3262 /* Include the simulator engine */
284e759d 3263#include "oengine.c"
f24b7b69 3264#if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
8bae0a0c
JSC		 3265#error "Mismatch between run-time simulator code and simulation engine"
3266#endif
18c64df6
AC		 3267#if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3268#error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3269#endif
76ef4165 3270#if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
18c64df6
AC		 3271#error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3272#endif
8bae0a0c
JSC		 3273
3274#if defined(WARN_LOHI)
3275 /* Decrement the HI/LO validity ticks */
3276 if (HIACCESS > 0)
3277 HIACCESS--;
3278 if (LOACCESS > 0)
3279 LOACCESS--;
0425cfb3 3280 /* start-sanitize-r5900 */
53b9417e
DE		 3281 if (HI1ACCESS > 0)
3282 HI1ACCESS--;
3283 if (LO1ACCESS > 0)
3284 LO1ACCESS--;
0425cfb3 3285 /* end-sanitize-r5900 */
8bae0a0c
JSC		 3286#endif /* WARN_LOHI */
3287
8bae0a0c
JSC		 3288 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3289 should check for it being changed. It is better doing it here,
3290 than within the simulator, since it will help keep the simulator
3291 small. */
3292 if (ZERO != 0) {
05d1322f 3293#if defined(WARN_ZERO)
95469ceb 3294 sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
05d1322f 3295#endif /* WARN_ZERO */
8bae0a0c
JSC		 3296 ZERO = 0; /* reset back to zero before next instruction */
3297 }
8bae0a0c 3298 } else /* simSKIPNEXT check */
0c2c5f61 3299 STATE &= ~simSKIPNEXT;
8bae0a0c
JSC		 3300
3301 /* If the delay slot was active before the instruction is
3302 executed, then update the PC to its new value: */
0c2c5f61 3303 if (DSSTATE) {
8bae0a0c 3304#ifdef DEBUG
53b9417e 3305 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
8bae0a0c
JSC		 3306#endif /* DEBUG */
3307 PC = DSPC;
6eedf3f4 3308 CANCELDELAYSLOT();
8bae0a0c
JSC		 3309 }
3310
3311 if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */
3312 /* Deal with pending register updates: */
3313#ifdef DEBUG
3314 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);
3315#endif /* DEBUG */
0c2c5f61 3316 if (PENDING_OUT != PENDING_IN) {
8bae0a0c 3317 int loop;
0c2c5f61
AC		 3318 int index = PENDING_OUT;
3319 int total = PENDING_TOTAL;
3320 if (PENDING_TOTAL == 0) {
8bae0a0c
JSC		 3321 fprintf(stderr,"FATAL: Mis-match on pending update pointers\n");
3322 exit(1);
3323 }
3324 for (loop = 0; (loop < total); loop++) {
3325#ifdef DEBUG
3326 printf("DBG: BEFORE index = %d, loop = %d\n",index,loop);
3327#endif /* DEBUG */
0c2c5f61 3328 if (PENDING_SLOT_REG[index] != (LAST_EMBED_REGNUM + 1)) {
8bae0a0c 3329#ifdef DEBUG
0c2c5f61 3330 printf("pending_slot_count[%d] = %d\n",index,PENDING_SLOT_COUNT[index]);
8bae0a0c 3331#endif /* DEBUG */
0c2c5f61 3332 if (--(PENDING_SLOT_COUNT[index]) == 0) {
8bae0a0c 3333#ifdef DEBUG
0c2c5f61
AC		 3334 printf("pending_slot_reg[%d] = %d\n",index,PENDING_SLOT_REG[index]);
3335 printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(PENDING_SLOT_VALUE[index]));
8bae0a0c 3336#endif /* DEBUG */
192ae475
AC		 3337 if (PENDING_SLOT_REG[index] == COCIDX)
3338 {
3339 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3340 {
3341 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3342 }
3343 }
3344 else
3345 {
3346 REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index];
3347 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3348 {
3349 /* The only time we have PENDING updates to FPU
3350 registers, is when performing binary transfers. This
3351 means we should update the register type field. */
3352 if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32)))
3353 FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted;
3354 }
3355 }
8bae0a0c 3356#ifdef DEBUG
0c2c5f61 3357 printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG[index],pr_addr(REGISTERS[PENDING_SLOT_REG[index]]));
8bae0a0c 3358#endif /* DEBUG */
0c2c5f61
AC		 3359 PENDING_SLOT_REG[index] = (LAST_EMBED_REGNUM + 1);
3360 PENDING_OUT++;
3361 if (PENDING_OUT == PSLOTS)
3362 PENDING_OUT = 0;
3363 PENDING_TOTAL--;
8bae0a0c
JSC		 3364 }
3365 }
3366#ifdef DEBUG
3367 printf("DBG: AFTER index = %d, loop = %d\n",index,loop);
3368#endif /* DEBUG */
3369 index++;
3370 if (index == PSLOTS)
3371 index = 0;
3372 }
3373 }
3374#ifdef DEBUG
0c2c5f61 3375 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);
8bae0a0c
JSC		 3376#endif /* DEBUG */
3377 }
3378
3379#if !defined(FASTSIM)
50a2a691
AC		 3380 if (sim_events_tickn (sd, pipeline_count))
3381 {
3382 /* cpu->cia = cia; */
3383 sim_events_process (sd);
3384 }
3385#else
2e61a3ad
AC		 3386 if (sim_events_tick (sd))
3387 {
3388 /* cpu->cia = cia; */
3389 sim_events_process (sd);
3390 }
50a2a691 3391#endif /* FASTSIM */
8bae0a0c 3392 }
8bae0a0c 3393}
16bd5d6e
AC		 3394#endif
3395
8bae0a0c 3396
53b9417e
DE		 3397/* This code copied from gdb's utils.c. Would like to share this code,
3398 but don't know of a common place where both could get to it. */
3399
3400/* Temporary storage using circular buffer */
3401#define NUMCELLS 16
3402#define CELLSIZE 32
3403static char*
3404get_cell()
3405{
3406 static char buf[NUMCELLS][CELLSIZE];
3407 static int cell=0;
3408 if (++cell>=NUMCELLS) cell=0;
3409 return buf[cell];
3410}
3411
3412/* Print routines to handle variable size regs, etc */
3413
3414/* Eliminate warning from compiler on 32-bit systems */
3415static int thirty_two = 32;
3416
3417char*
3418pr_addr(addr)
3419 SIM_ADDR addr;
3420{
3421 char *paddr_str=get_cell();
3422 switch (sizeof(addr))
3423 {
3424 case 8:
50a2a691 3425 sprintf(paddr_str,"%08lx%08lx",
53b9417e
DE		 3426 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3427 break;
3428 case 4:
50a2a691 3429 sprintf(paddr_str,"%08lx",(unsigned long)addr);
53b9417e
DE		 3430 break;
3431 case 2:
3432 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
3433 break;
3434 default:
3435 sprintf(paddr_str,"%x",addr);
3436 }
3437 return paddr_str;
3438}
3439
87e43259
AC		 3440char*
3441pr_uword64(addr)
3442 uword64 addr;
3443{
3444 char *paddr_str=get_cell();
50a2a691 3445 sprintf(paddr_str,"%08lx%08lx",
87e43259
AC		 3446 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3447 return paddr_str;
3448}
3449
3450
8bae0a0c
JSC		 3451/*---------------------------------------------------------------------------*/
3452/*> EOF interp.c <*/
GDB Binutils - Deliverables
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