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8bae0a0c JSC |
1 | /*> interp.c <*/ |
2 | /* Simulator for the MIPS architecture. | |
3 | ||
4 | This file is part of the MIPS sim | |
5 | ||
6 | THIS SOFTWARE IS NOT COPYRIGHTED | |
7 | ||
8 | Cygnus offers the following for use in the public domain. Cygnus | |
9 | makes no warranty with regard to the software or it's performance | |
10 | and the user accepts the software "AS IS" with all faults. | |
11 | ||
12 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
13 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
14 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
15 | ||
16 | $Revision$ | |
17 | $Author$ | |
e3d12c65 | 18 | $Date$ |
8bae0a0c JSC |
19 | |
20 | NOTEs: | |
21 | ||
22 | We only need to take account of the target endianness when moving data | |
23 | between the simulator and the host. We do not need to worry about the | |
24 | endianness of the host, since this sim code and GDB are executing in | |
25 | the same process. | |
26 | ||
27 | The IDT monitor (found on the VR4300 board), seems to lie about | |
28 | register contents. It seems to treat the registers as sign-extended | |
29 | 32-bit values. This cause *REAL* problems when single-stepping 64-bit | |
30 | code on the hardware. | |
31 | ||
32 | */ | |
33 | ||
e2f8ffb7 AC |
34 | /* The TRACE manifests enable the provision of extra features. If they |
35 | are not defined then a simpler (quicker) simulator is constructed | |
36 | without the required run-time checks, etc. */ | |
8bae0a0c JSC |
37 | #if 1 /* 0 to allow user build selection, 1 to force inclusion */ |
38 | #define TRACE (1) | |
8bae0a0c JSC |
39 | #endif |
40 | ||
2e61a3ad AC |
41 | #include "bfd.h" |
42 | #include "sim-main.h" | |
43 | #include "sim-utils.h" | |
44 | #include "sim-options.h" | |
50a2a691 | 45 | #include "sim-assert.h" |
2e61a3ad | 46 | |
4fa134be ILT |
47 | #include "config.h" |
48 | ||
8bae0a0c JSC |
49 | #include <stdio.h> |
50 | #include <stdarg.h> | |
51 | #include <ansidecl.h> | |
8bae0a0c JSC |
52 | #include <ctype.h> |
53 | #include <limits.h> | |
54 | #include <math.h> | |
4fa134be ILT |
55 | #ifdef HAVE_STDLIB_H |
56 | #include <stdlib.h> | |
57 | #endif | |
58 | #ifdef HAVE_STRING_H | |
59 | #include <string.h> | |
60 | #else | |
61 | #ifdef HAVE_STRINGS_H | |
62 | #include <strings.h> | |
63 | #endif | |
64 | #endif | |
8bae0a0c JSC |
65 | |
66 | #include "getopt.h" | |
67 | #include "libiberty.h" | |
9d52bcb7 | 68 | #include "bfd.h" |
8bae0a0c | 69 | #include "callback.h" /* GDB simulator callback interface */ |
e3d12c65 | 70 | #include "remote-sim.h" /* GDB simulator interface */ |
8bae0a0c | 71 | |
f24b7b69 JSC |
72 | #include "sysdep.h" |
73 | ||
53b9417e DE |
74 | #ifndef PARAMS |
75 | #define PARAMS(x) | |
76 | #endif | |
77 | ||
78 | char* pr_addr PARAMS ((SIM_ADDR addr)); | |
87e43259 | 79 | char* pr_uword64 PARAMS ((uword64 addr)); |
53b9417e | 80 | |
f24b7b69 | 81 | |
8bae0a0c JSC |
82 | /* Get the simulator engine description, without including the code: */ |
83 | #define SIM_MANIFESTS | |
284e759d | 84 | #include "oengine.c" |
8bae0a0c JSC |
85 | #undef SIM_MANIFESTS |
86 | ||
f7481d45 | 87 | |
8bae0a0c JSC |
88 | /* The following reserved instruction value is used when a simulator |
89 | trap is required. NOTE: Care must be taken, since this value may be | |
90 | used in later revisions of the MIPS ISA. */ | |
53b9417e DE |
91 | #define RSVD_INSTRUCTION (0x00000005) |
92 | #define RSVD_INSTRUCTION_MASK (0xFC00003F) | |
93 | ||
94 | #define RSVD_INSTRUCTION_ARG_SHIFT 6 | |
95 | #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF | |
96 | ||
8bae0a0c | 97 | |
6eedf3f4 MA |
98 | /* Bits in the Debug register */ |
99 | #define Debug_DBD 0x80000000 /* Debug Branch Delay */ | |
100 | #define Debug_DM 0x40000000 /* Debug Mode */ | |
101 | #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */ | |
102 | ||
103 | ||
104 | ||
8bae0a0c | 105 | |
8bae0a0c | 106 | |
e3d12c65 DE |
107 | /*---------------------------------------------------------------------------*/ |
108 | /*-- GDB simulator interface ------------------------------------------------*/ | |
109 | /*---------------------------------------------------------------------------*/ | |
110 | ||
0c2c5f61 AC |
111 | static void dotrace PARAMS((SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)); |
112 | static void ColdReset PARAMS((SIM_DESC sd)); | |
18c64df6 | 113 | static long getnum PARAMS((SIM_DESC sd, char *value)); |
e3d12c65 | 114 | static unsigned int power2 PARAMS((unsigned int value)); |
18c64df6 | 115 | static void mips_size PARAMS((SIM_DESC sd, int n)); |
e3d12c65 DE |
116 | |
117 | /*---------------------------------------------------------------------------*/ | |
118 | ||
8bae0a0c | 119 | |
8bae0a0c | 120 | |
8bae0a0c | 121 | #define DELAYSLOT() {\ |
0c2c5f61 | 122 | if (STATE & simDELAYSLOT)\ |
18c64df6 | 123 | sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\ |
0c2c5f61 | 124 | STATE |= simDELAYSLOT;\ |
8bae0a0c JSC |
125 | } |
126 | ||
aaff8437 ILT |
127 | #define JALDELAYSLOT() {\ |
128 | DELAYSLOT ();\ | |
0c2c5f61 | 129 | STATE |= simJALDELAYSLOT;\ |
aaff8437 ILT |
130 | } |
131 | ||
8bae0a0c | 132 | #define NULLIFY() {\ |
0c2c5f61 AC |
133 | STATE &= ~simDELAYSLOT;\ |
134 | STATE |= simSKIPNEXT;\ | |
8bae0a0c JSC |
135 | } |
136 | ||
6eedf3f4 | 137 | #define CANCELDELAYSLOT() {\ |
0c2c5f61 AC |
138 | DSSTATE = 0;\ |
139 | STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\ | |
6eedf3f4 MA |
140 | } |
141 | ||
0c2c5f61 AC |
142 | #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0) |
143 | #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0) | |
aaff8437 | 144 | |
a9f7253f JSC |
145 | #define K0BASE (0x80000000) |
146 | #define K0SIZE (0x20000000) | |
147 | #define K1BASE (0xA0000000) | |
148 | #define K1SIZE (0x20000000) | |
149 | ||
8bae0a0c | 150 | /* Simple run-time monitor support */ |
4fa134be ILT |
151 | static unsigned char *monitor = NULL; |
152 | static ut_reg monitor_base = 0xBFC00000; | |
153 | static unsigned monitor_size = (1 << 11); /* power-of-2 */ | |
8bae0a0c | 154 | |
f24b7b69 JSC |
155 | static char *logfile = NULL; /* logging disabled by default */ |
156 | static FILE *logfh = NULL; | |
157 | ||
8bae0a0c | 158 | #if defined(TRACE) |
4fa134be ILT |
159 | static char *tracefile = "trace.din"; /* default filename for trace log */ |
160 | static FILE *tracefh = NULL; | |
18c64df6 | 161 | static void open_trace PARAMS((SIM_DESC sd)); |
8bae0a0c JSC |
162 | #endif /* TRACE */ |
163 | ||
50a2a691 AC |
164 | static SIM_RC |
165 | mips_option_handler (sd, opt, arg) | |
166 | SIM_DESC sd; | |
167 | int opt; | |
168 | char *arg; | |
2e61a3ad | 169 | { |
50a2a691 AC |
170 | switch (opt) |
171 | { | |
172 | case 'l': | |
173 | if (arg != NULL) { | |
174 | char *tmp; | |
175 | tmp = (char *)malloc(strlen(arg) + 1); | |
176 | if (tmp == NULL) | |
18c64df6 | 177 | sim_io_printf(sd,"Failed to allocate buffer for logfile name \"%s\"\n",optarg); |
50a2a691 AC |
178 | else { |
179 | strcpy(tmp,optarg); | |
180 | logfile = tmp; | |
181 | } | |
182 | } | |
183 | return SIM_RC_OK; | |
184 | ||
185 | case 'n': /* OK */ | |
18c64df6 | 186 | sim_io_printf(sd,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg); |
50a2a691 AC |
187 | return SIM_RC_FAIL; |
188 | ||
189 | case 't': /* ??? */ | |
190 | #if defined(TRACE) | |
191 | /* Eventually the simTRACE flag could be treated as a toggle, to | |
192 | allow external control of the program points being traced | |
193 | (i.e. only from main onwards, excluding the run-time setup, | |
194 | etc.). */ | |
195 | if (arg == NULL) | |
0c2c5f61 | 196 | STATE |= simTRACE; |
50a2a691 | 197 | else if (strcmp (arg, "yes") == 0) |
0c2c5f61 | 198 | STATE |= simTRACE; |
50a2a691 | 199 | else if (strcmp (arg, "no") == 0) |
0c2c5f61 | 200 | STATE &= ~simTRACE; |
50a2a691 AC |
201 | else |
202 | { | |
203 | fprintf (stderr, "Unreconized trace option `%s'\n", arg); | |
204 | return SIM_RC_FAIL; | |
205 | } | |
206 | return SIM_RC_OK; | |
207 | #else /* !TRACE */ | |
208 | fprintf(stderr,"\ | |
209 | Simulator constructed without tracing support (for performance).\n\ | |
210 | Re-compile simulator with \"-DTRACE\" to enable this option.\n"); | |
211 | return SIM_RC_FAIL; | |
212 | #endif /* !TRACE */ | |
213 | ||
214 | case 'z': | |
215 | #if defined(TRACE) | |
216 | if (optarg != NULL) { | |
217 | char *tmp; | |
218 | tmp = (char *)malloc(strlen(optarg) + 1); | |
219 | if (tmp == NULL) | |
220 | { | |
18c64df6 | 221 | sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg); |
50a2a691 AC |
222 | return SIM_RC_FAIL; |
223 | } | |
224 | else { | |
225 | strcpy(tmp,optarg); | |
226 | tracefile = tmp; | |
18c64df6 | 227 | sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile); |
50a2a691 AC |
228 | } |
229 | } | |
230 | #endif /* TRACE */ | |
231 | return SIM_RC_OK; | |
232 | ||
50a2a691 AC |
233 | } |
234 | ||
235 | return SIM_RC_OK; | |
2e61a3ad | 236 | } |
50a2a691 AC |
237 | |
238 | static const OPTION mips_options[] = | |
2e61a3ad | 239 | { |
50a2a691 AC |
240 | { {"log", required_argument, NULL,'l'}, |
241 | 'l', "FILE", "Log file", | |
242 | mips_option_handler }, | |
243 | { {"name", required_argument, NULL,'n'}, | |
244 | 'n', "MODEL", "Select arch model", | |
245 | mips_option_handler }, | |
50a2a691 AC |
246 | { {"trace", optional_argument, NULL,'t'}, |
247 | 't', "on|off", "Enable tracing", | |
248 | mips_option_handler }, | |
249 | { {"tracefile",required_argument, NULL,'z'}, | |
250 | 'z', "FILE", "Write trace to file", | |
251 | mips_option_handler }, | |
50a2a691 AC |
252 | { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } |
253 | }; | |
254 | ||
255 | ||
56e7c849 AC |
256 | int interrupt_pending; |
257 | ||
50a2a691 AC |
258 | static void |
259 | interrupt_event (SIM_DESC sd, void *data) | |
2e61a3ad | 260 | { |
56e7c849 AC |
261 | if (SR & status_IE) |
262 | { | |
263 | interrupt_pending = 0; | |
18c64df6 | 264 | SignalExceptionInterrupt (); |
56e7c849 AC |
265 | } |
266 | else if (!interrupt_pending) | |
267 | sim_events_schedule (sd, 1, interrupt_event, data); | |
2e61a3ad | 268 | } |
f7481d45 | 269 | |
f7481d45 | 270 | |
50a2a691 | 271 | |
8bae0a0c JSC |
272 | /*---------------------------------------------------------------------------*/ |
273 | /*-- GDB simulator interface ------------------------------------------------*/ | |
274 | /*---------------------------------------------------------------------------*/ | |
275 | ||
53b9417e | 276 | SIM_DESC |
247fccde | 277 | sim_open (kind, cb, abfd, argv) |
87e43259 | 278 | SIM_OPEN_KIND kind; |
50a2a691 | 279 | host_callback *cb; |
247fccde | 280 | struct _bfd *abfd; |
53b9417e | 281 | char **argv; |
8bae0a0c | 282 | { |
18c64df6 | 283 | SIM_DESC sd = sim_state_alloc (kind, cb); |
0c2c5f61 | 284 | sim_cpu *cpu = STATE_CPU (sd, 0); |
2e61a3ad | 285 | |
50a2a691 AC |
286 | /* FIXME: watchpoints code shouldn't need this */ |
287 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
288 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
289 | STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event; | |
290 | ||
291 | /* memory defaults (unless sim_size was here first) */ | |
292 | if (STATE_MEM_SIZE (sd) == 0) | |
293 | STATE_MEM_SIZE (sd) = (2 << 20); | |
294 | STATE_MEM_BASE (sd) = K1BASE; | |
295 | ||
0c2c5f61 | 296 | STATE = 0; |
50a2a691 | 297 | |
2e61a3ad AC |
298 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
299 | return 0; | |
50a2a691 | 300 | sim_add_option_table (sd, mips_options); |
2e61a3ad | 301 | |
2e61a3ad AC |
302 | /* getopt will print the error message so we just have to exit if this fails. |
303 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
304 | print_filtered. */ | |
305 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
306 | { | |
307 | /* Uninstall the modules to avoid memory leaks, | |
308 | file descriptor leaks, etc. */ | |
309 | sim_module_uninstall (sd); | |
310 | return 0; | |
311 | } | |
2e61a3ad | 312 | |
fafce69a AC |
313 | /* check for/establish the a reference program image */ |
314 | if (sim_analyze_program (sd, | |
315 | (STATE_PROG_ARGV (sd) != NULL | |
316 | ? *STATE_PROG_ARGV (sd) | |
317 | : NULL), | |
318 | abfd) != SIM_RC_OK) | |
319 | { | |
320 | sim_module_uninstall (sd); | |
321 | return 0; | |
322 | } | |
323 | ||
247fccde AC |
324 | /* Configure/verify the target byte order and other runtime |
325 | configuration options */ | |
fafce69a | 326 | if (sim_config (sd) != SIM_RC_OK) |
247fccde AC |
327 | { |
328 | sim_module_uninstall (sd); | |
329 | return 0; | |
330 | } | |
331 | ||
2e61a3ad AC |
332 | if (sim_post_argv_init (sd) != SIM_RC_OK) |
333 | { | |
334 | /* Uninstall the modules to avoid memory leaks, | |
335 | file descriptor leaks, etc. */ | |
336 | sim_module_uninstall (sd); | |
337 | return 0; | |
338 | } | |
339 | ||
50a2a691 AC |
340 | /* verify assumptions the simulator made about the host type system. |
341 | This macro does not return if there is a problem */ | |
18c64df6 AC |
342 | if (sizeof(int) != (4 * sizeof(char))) |
343 | SignalExceptionSimulatorFault ("sizeof(int) != 4"); | |
344 | if (sizeof(word64) != (8 * sizeof(char))) | |
345 | SignalExceptionSimulatorFault ("sizeof(word64) != 8"); | |
8bae0a0c | 346 | |
8bae0a0c JSC |
347 | #if defined(HASFPU) |
348 | /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE | |
349 | and DOUBLE binary formats. This is a bit nasty, requiring that we | |
350 | trust the explicit manifests held in the source: */ | |
50a2a691 AC |
351 | /* TODO: We need to cope with the simulated target and the host not |
352 | having the same endianness. This will require the high and low | |
353 | words of a (double) to be swapped when converting between the | |
354 | host and the simulated target. */ | |
8bae0a0c | 355 | { |
50a2a691 AC |
356 | union { |
357 | unsigned int i[2]; | |
358 | double d; | |
359 | float f[2]; | |
360 | } s; | |
361 | ||
362 | s.d = (double)523.2939453125; | |
363 | ||
364 | if ((s.i[0] == 0 && (s.f[1] != (float)4.01102924346923828125 | |
365 | || s.i[1] != 0x40805A5A)) | |
366 | || (s.i[1] == 0 && (s.f[0] != (float)4.01102924346923828125 | |
367 | || s.i[0] != 0x40805A5A))) | |
368 | { | |
369 | fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n"); | |
370 | return 0; | |
371 | } | |
8bae0a0c JSC |
372 | } |
373 | #endif /* HASFPU */ | |
374 | ||
375 | /* This is NASTY, in that we are assuming the size of specific | |
376 | registers: */ | |
377 | { | |
378 | int rn; | |
379 | for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) { | |
380 | if (rn < 32) | |
0c2c5f61 | 381 | cpu->register_widths[rn] = GPRLEN; |
8bae0a0c | 382 | else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32))) |
0c2c5f61 | 383 | cpu->register_widths[rn] = GPRLEN; |
8bae0a0c | 384 | else if ((rn >= 33) && (rn <= 37)) |
0c2c5f61 | 385 | cpu->register_widths[rn] = GPRLEN; |
8bae0a0c | 386 | else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89))) |
0c2c5f61 | 387 | cpu->register_widths[rn] = 32; |
8bae0a0c | 388 | else |
0c2c5f61 | 389 | cpu->register_widths[rn] = 0; |
8bae0a0c | 390 | } |
18c64df6 AC |
391 | /* start-sanitize-r5900 */ |
392 | ||
393 | /* set the 5900 "upper" registers to 64 bits */ | |
394 | for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++) | |
0c2c5f61 | 395 | cpu->register_widths[rn] = 64; |
18c64df6 | 396 | /* end-sanitize-r5900 */ |
8bae0a0c JSC |
397 | } |
398 | ||
8bae0a0c | 399 | |
f24b7b69 JSC |
400 | if (logfile != NULL) { |
401 | if (strcmp(logfile,"-") == 0) | |
402 | logfh = stdout; | |
403 | else { | |
404 | logfh = fopen(logfile,"wb+"); | |
405 | if (logfh == NULL) { | |
18c64df6 | 406 | sim_io_printf(sd,"Failed to create file \"%s\", writing log information to stderr.\n",tracefile); |
f24b7b69 JSC |
407 | logfh = stderr; |
408 | } | |
409 | } | |
410 | } | |
411 | ||
50a2a691 AC |
412 | /* FIXME: In the future both of these malloc's can be replaced by |
413 | calls to sim-core. */ | |
9d52bcb7 | 414 | |
8bae0a0c JSC |
415 | /* If the host has "mmap" available we could use it to provide a |
416 | very large virtual address space for the simulator, since memory | |
417 | would only be allocated within the "mmap" space as it is | |
418 | accessed. This can also be linked to the architecture specific | |
419 | support, required to simulate the MMU. */ | |
18c64df6 | 420 | mips_size(sd, STATE_MEM_SIZE (sd)); |
50a2a691 | 421 | /* NOTE: The above will also have enabled any profiling state! */ |
18c64df6 | 422 | |
50a2a691 | 423 | /* Create the monitor address space as well */ |
8bae0a0c | 424 | monitor = (unsigned char *)calloc(1,monitor_size); |
50a2a691 AC |
425 | if (!monitor) |
426 | fprintf(stderr,"Not enough VM for monitor simulation (%d bytes)\n", | |
427 | monitor_size); | |
8bae0a0c JSC |
428 | |
429 | #if defined(TRACE) | |
0c2c5f61 | 430 | if (STATE & simTRACE) |
18c64df6 | 431 | open_trace(sd); |
8bae0a0c JSC |
432 | #endif /* TRACE */ |
433 | ||
fafce69a AC |
434 | /* Write the monitor trap address handlers into the monitor (eeprom) |
435 | address space. This can only be done once the target endianness | |
436 | has been determined. */ | |
437 | { | |
438 | unsigned loop; | |
439 | /* Entry into the IDT monitor is via fixed address vectors, and | |
440 | not using machine instructions. To avoid clashing with use of | |
441 | the MIPS TRAP system, we place our own (simulator specific) | |
442 | "undefined" instructions into the relevant vector slots. */ | |
443 | for (loop = 0; (loop < monitor_size); loop += 4) { | |
444 | uword64 vaddr = (monitor_base + loop); | |
445 | uword64 paddr; | |
446 | int cca; | |
447 | if (AddressTranslation(vaddr, isDATA, isSTORE, &paddr, &cca, isTARGET, isRAW)) | |
448 | StoreMemory(cca, AccessLength_WORD, | |
449 | (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT)), | |
450 | 0, paddr, vaddr, isRAW); | |
451 | } | |
452 | /* The PMON monitor uses the same address space, but rather than | |
453 | branching into it the address of a routine is loaded. We can | |
454 | cheat for the moment, and direct the PMON routine to IDT style | |
455 | instructions within the monitor space. This relies on the IDT | |
456 | monitor not using the locations from 0xBFC00500 onwards as its | |
457 | entry points.*/ | |
458 | for (loop = 0; (loop < 24); loop++) | |
459 | { | |
460 | uword64 vaddr = (monitor_base + 0x500 + (loop * 4)); | |
461 | uword64 paddr; | |
462 | int cca; | |
463 | unsigned int value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ | |
464 | switch (loop) | |
465 | { | |
466 | case 0: /* read */ | |
467 | value = 7; | |
468 | break; | |
469 | ||
470 | case 1: /* write */ | |
471 | value = 8; | |
472 | break; | |
473 | ||
474 | case 2: /* open */ | |
475 | value = 6; | |
476 | break; | |
477 | ||
478 | case 3: /* close */ | |
479 | value = 10; | |
480 | break; | |
481 | ||
482 | case 5: /* printf */ | |
483 | value = ((0x500 - 16) / 8); /* not an IDT reason code */ | |
484 | break; | |
485 | ||
486 | case 8: /* cliexit */ | |
487 | value = 17; | |
488 | break; | |
489 | ||
490 | case 11: /* flush_cache */ | |
491 | value = 28; | |
492 | break; | |
493 | } | |
494 | /* FIXME - should monitor_base be SIM_ADDR?? */ | |
495 | value = ((unsigned int)monitor_base + (value * 8)); | |
496 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) | |
497 | StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW); | |
498 | else | |
18c64df6 | 499 | sim_io_error(sd,"Failed to write to monitor space 0x%s",pr_addr(vaddr)); |
fafce69a AC |
500 | |
501 | /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */ | |
502 | vaddr -= 0x300; | |
503 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) | |
504 | StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW); | |
505 | else | |
18c64df6 | 506 | sim_io_error(sd,"Failed to write to monitor space 0x%s",pr_addr(vaddr)); |
fafce69a AC |
507 | } |
508 | } | |
509 | ||
2e61a3ad | 510 | return sd; |
8bae0a0c JSC |
511 | } |
512 | ||
6429b296 JW |
513 | #if defined(TRACE) |
514 | static void | |
18c64df6 AC |
515 | open_trace(sd) |
516 | SIM_DESC sd; | |
6429b296 JW |
517 | { |
518 | tracefh = fopen(tracefile,"wb+"); | |
519 | if (tracefh == NULL) | |
520 | { | |
18c64df6 | 521 | sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile); |
6429b296 JW |
522 | tracefh = stderr; |
523 | } | |
524 | } | |
525 | #endif /* TRACE */ | |
526 | ||
8bae0a0c | 527 | void |
53b9417e DE |
528 | sim_close (sd, quitting) |
529 | SIM_DESC sd; | |
8bae0a0c JSC |
530 | int quitting; |
531 | { | |
532 | #ifdef DEBUG | |
533 | printf("DBG: sim_close: entered (quitting = %d)\n",quitting); | |
534 | #endif | |
535 | ||
8bae0a0c JSC |
536 | /* "quitting" is non-zero if we cannot hang on errors */ |
537 | ||
538 | /* Ensure that any resources allocated through the callback | |
539 | mechanism are released: */ | |
18c64df6 | 540 | sim_io_shutdown (sd); |
8bae0a0c | 541 | |
8bae0a0c | 542 | #if defined(TRACE) |
e3d12c65 | 543 | if (tracefh != NULL && tracefh != stderr) |
8bae0a0c | 544 | fclose(tracefh); |
e3d12c65 | 545 | tracefh = NULL; |
0c2c5f61 | 546 | STATE &= ~simTRACE; |
8bae0a0c JSC |
547 | #endif /* TRACE */ |
548 | ||
f24b7b69 JSC |
549 | if (logfh != NULL && logfh != stdout && logfh != stderr) |
550 | fclose(logfh); | |
551 | logfh = NULL; | |
552 | ||
50a2a691 AC |
553 | if (STATE_MEMORY (sd) != NULL) |
554 | free(STATE_MEMORY (sd)); /* cfree not available on all hosts */ | |
555 | STATE_MEMORY (sd) = NULL; | |
8bae0a0c JSC |
556 | |
557 | return; | |
558 | } | |
559 | ||
8bae0a0c JSC |
560 | |
561 | int | |
53b9417e DE |
562 | sim_write (sd,addr,buffer,size) |
563 | SIM_DESC sd; | |
8bae0a0c JSC |
564 | SIM_ADDR addr; |
565 | unsigned char *buffer; | |
566 | int size; | |
567 | { | |
568 | int index = size; | |
e871dd18 | 569 | uword64 vaddr = (uword64)addr; |
8bae0a0c JSC |
570 | |
571 | /* Return the number of bytes written, or zero if error. */ | |
572 | #ifdef DEBUG | |
18c64df6 | 573 | sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
574 | #endif |
575 | ||
576 | /* We provide raw read and write routines, since we do not want to | |
577 | count the GDB memory accesses in our statistics gathering. */ | |
578 | ||
579 | /* There is a lot of code duplication in the individual blocks | |
580 | below, but the variables are declared locally to a block to give | |
581 | the optimiser the best chance of improving the code. We have to | |
582 | perform slow byte reads from the host memory, to ensure that we | |
583 | get the data into the correct endianness for the (simulated) | |
584 | target memory world. */ | |
585 | ||
586 | /* Mask count to get odd byte, odd halfword, and odd word out of the | |
587 | way. We can then perform doubleword transfers to and from the | |
588 | simulator memory for optimum performance. */ | |
589 | if (index && (index & 1)) { | |
e871dd18 | 590 | uword64 paddr; |
8bae0a0c JSC |
591 | int cca; |
592 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) { | |
e871dd18 | 593 | uword64 value = ((uword64)(*buffer++)); |
53b9417e | 594 | StoreMemory(cca,AccessLength_BYTE,value,0,paddr,vaddr,isRAW); |
8bae0a0c JSC |
595 | } |
596 | vaddr++; | |
597 | index &= ~1; /* logical operations usually quicker than arithmetic on RISC systems */ | |
598 | } | |
599 | if (index && (index & 2)) { | |
e871dd18 | 600 | uword64 paddr; |
8bae0a0c JSC |
601 | int cca; |
602 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) { | |
e871dd18 | 603 | uword64 value; |
8bae0a0c JSC |
604 | /* We need to perform the following magic to ensure that that |
605 | bytes are written into same byte positions in the target memory | |
606 | world, regardless of the endianness of the host. */ | |
0049ba7a | 607 | if (BigEndianMem) { |
e871dd18 JSC |
608 | value = ((uword64)(*buffer++) << 8); |
609 | value |= ((uword64)(*buffer++) << 0); | |
8bae0a0c | 610 | } else { |
e871dd18 JSC |
611 | value = ((uword64)(*buffer++) << 0); |
612 | value |= ((uword64)(*buffer++) << 8); | |
8bae0a0c | 613 | } |
53b9417e | 614 | StoreMemory(cca,AccessLength_HALFWORD,value,0,paddr,vaddr,isRAW); |
8bae0a0c JSC |
615 | } |
616 | vaddr += 2; | |
617 | index &= ~2; | |
618 | } | |
619 | if (index && (index & 4)) { | |
e871dd18 | 620 | uword64 paddr; |
8bae0a0c JSC |
621 | int cca; |
622 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) { | |
e871dd18 | 623 | uword64 value; |
0049ba7a | 624 | if (BigEndianMem) { |
e871dd18 JSC |
625 | value = ((uword64)(*buffer++) << 24); |
626 | value |= ((uword64)(*buffer++) << 16); | |
627 | value |= ((uword64)(*buffer++) << 8); | |
628 | value |= ((uword64)(*buffer++) << 0); | |
8bae0a0c | 629 | } else { |
e871dd18 JSC |
630 | value = ((uword64)(*buffer++) << 0); |
631 | value |= ((uword64)(*buffer++) << 8); | |
632 | value |= ((uword64)(*buffer++) << 16); | |
633 | value |= ((uword64)(*buffer++) << 24); | |
8bae0a0c | 634 | } |
53b9417e | 635 | StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW); |
8bae0a0c JSC |
636 | } |
637 | vaddr += 4; | |
638 | index &= ~4; | |
639 | } | |
640 | for (;index; index -= 8) { | |
e871dd18 | 641 | uword64 paddr; |
8bae0a0c JSC |
642 | int cca; |
643 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) { | |
e871dd18 | 644 | uword64 value; |
0049ba7a | 645 | if (BigEndianMem) { |
e871dd18 JSC |
646 | value = ((uword64)(*buffer++) << 56); |
647 | value |= ((uword64)(*buffer++) << 48); | |
648 | value |= ((uword64)(*buffer++) << 40); | |
649 | value |= ((uword64)(*buffer++) << 32); | |
650 | value |= ((uword64)(*buffer++) << 24); | |
651 | value |= ((uword64)(*buffer++) << 16); | |
652 | value |= ((uword64)(*buffer++) << 8); | |
653 | value |= ((uword64)(*buffer++) << 0); | |
8bae0a0c | 654 | } else { |
e871dd18 JSC |
655 | value = ((uword64)(*buffer++) << 0); |
656 | value |= ((uword64)(*buffer++) << 8); | |
657 | value |= ((uword64)(*buffer++) << 16); | |
658 | value |= ((uword64)(*buffer++) << 24); | |
659 | value |= ((uword64)(*buffer++) << 32); | |
660 | value |= ((uword64)(*buffer++) << 40); | |
661 | value |= ((uword64)(*buffer++) << 48); | |
662 | value |= ((uword64)(*buffer++) << 56); | |
8bae0a0c | 663 | } |
53b9417e | 664 | StoreMemory(cca,AccessLength_DOUBLEWORD,value,0,paddr,vaddr,isRAW); |
8bae0a0c JSC |
665 | } |
666 | vaddr += 8; | |
667 | } | |
668 | ||
669 | return(size); | |
670 | } | |
671 | ||
672 | int | |
53b9417e DE |
673 | sim_read (sd,addr,buffer,size) |
674 | SIM_DESC sd; | |
8bae0a0c JSC |
675 | SIM_ADDR addr; |
676 | unsigned char *buffer; | |
677 | int size; | |
678 | { | |
679 | int index; | |
680 | ||
681 | /* Return the number of bytes read, or zero if error. */ | |
682 | #ifdef DEBUG | |
18c64df6 | 683 | sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
684 | #endif /* DEBUG */ |
685 | ||
686 | /* TODO: Perform same optimisation as the sim_write() code | |
687 | above. NOTE: This will require a bit more work since we will need | |
688 | to ensure that the source physical address is doubleword aligned | |
689 | before, and then deal with trailing bytes. */ | |
690 | for (index = 0; (index < size); index++) { | |
e871dd18 | 691 | uword64 vaddr,paddr,value; |
8bae0a0c | 692 | int cca; |
e871dd18 | 693 | vaddr = (uword64)addr + index; |
8bae0a0c | 694 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&cca,isTARGET,isRAW)) { |
53b9417e | 695 | LoadMemory(&value,NULL,cca,AccessLength_BYTE,paddr,vaddr,isDATA,isRAW); |
8bae0a0c JSC |
696 | buffer[index] = (unsigned char)(value&0xFF); |
697 | } else | |
698 | break; | |
699 | } | |
700 | ||
701 | return(index); | |
702 | } | |
703 | ||
704 | void | |
53b9417e DE |
705 | sim_store_register (sd,rn,memory) |
706 | SIM_DESC sd; | |
8bae0a0c JSC |
707 | int rn; |
708 | unsigned char *memory; | |
709 | { | |
0c2c5f61 | 710 | sim_cpu *cpu = STATE_CPU (sd, 0); |
50a2a691 AC |
711 | /* NOTE: gdb (the client) stores registers in target byte order |
712 | while the simulator uses host byte order */ | |
8bae0a0c | 713 | #ifdef DEBUG |
18c64df6 | 714 | sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory))); |
8bae0a0c JSC |
715 | #endif /* DEBUG */ |
716 | ||
717 | /* Unfortunately this suffers from the same problem as the register | |
718 | numbering one. We need to know what the width of each logical | |
719 | register number is for the architecture being simulated. */ | |
50a2a691 | 720 | |
0c2c5f61 | 721 | if (cpu->register_widths[rn] == 0) |
18c64df6 AC |
722 | sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn); |
723 | /* start-sanitize-r5900 */ | |
724 | else if (rn == REGISTER_SA) | |
725 | SA = T2H_8(*(uword64*)memory); | |
726 | else if (rn > LAST_EMBED_REGNUM) | |
0c2c5f61 | 727 | cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(uword64*)memory); |
18c64df6 | 728 | /* end-sanitize-r5900 */ |
0c2c5f61 AC |
729 | else if (cpu->register_widths[rn] == 32) |
730 | cpu->registers[rn] = T2H_4 (*(unsigned int*)memory); | |
50a2a691 | 731 | else |
0c2c5f61 | 732 | cpu->registers[rn] = T2H_8 (*(uword64*)memory); |
8bae0a0c JSC |
733 | |
734 | return; | |
735 | } | |
736 | ||
737 | void | |
53b9417e DE |
738 | sim_fetch_register (sd,rn,memory) |
739 | SIM_DESC sd; | |
8bae0a0c JSC |
740 | int rn; |
741 | unsigned char *memory; | |
742 | { | |
0c2c5f61 | 743 | sim_cpu *cpu = STATE_CPU (sd, 0); |
50a2a691 AC |
744 | /* NOTE: gdb (the client) stores registers in target byte order |
745 | while the simulator uses host byte order */ | |
8bae0a0c | 746 | #ifdef DEBUG |
18c64df6 | 747 | sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn])); |
8bae0a0c JSC |
748 | #endif /* DEBUG */ |
749 | ||
0c2c5f61 | 750 | if (cpu->register_widths[rn] == 0) |
18c64df6 AC |
751 | sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn); |
752 | /* start-sanitize-r5900 */ | |
753 | else if (rn == REGISTER_SA) | |
754 | *((uword64 *)memory) = H2T_8(SA); | |
755 | else if (rn > LAST_EMBED_REGNUM) | |
0c2c5f61 | 756 | *((uword64 *)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]); |
18c64df6 | 757 | /* end-sanitize-r5900 */ |
0c2c5f61 AC |
758 | else if (cpu->register_widths[rn] == 32) |
759 | *((unsigned int *)memory) = H2T_4 ((unsigned int)(cpu->registers[rn] & 0xFFFFFFFF)); | |
18c64df6 | 760 | else /* 64bit register */ |
0c2c5f61 | 761 | *((uword64 *)memory) = H2T_8 (cpu->registers[rn]); |
50a2a691 | 762 | |
8bae0a0c JSC |
763 | return; |
764 | } | |
50a2a691 | 765 | |
8bae0a0c JSC |
766 | |
767 | void | |
53b9417e DE |
768 | sim_info (sd,verbose) |
769 | SIM_DESC sd; | |
8bae0a0c JSC |
770 | int verbose; |
771 | { | |
772 | /* Accessed from the GDB "info files" command: */ | |
56e7c849 AC |
773 | if (STATE_VERBOSE_P (sd) || verbose) |
774 | { | |
775 | ||
776 | sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n", | |
777 | (PROCESSOR_64BIT ? 64 : 32), | |
778 | (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little")); | |
779 | ||
780 | sim_io_printf (sd, "0x%08X bytes of memory at 0x%s\n", | |
781 | STATE_MEM_SIZE (sd), | |
782 | pr_addr (STATE_MEM_BASE (sd))); | |
783 | ||
8bae0a0c | 784 | #if !defined(FASTSIM) |
56e7c849 AC |
785 | /* It would be a useful feature, if when performing multi-cycle |
786 | simulations (rather than single-stepping) we keep the start and | |
787 | end times of the execution, so that we can give a performance | |
788 | figure for the simulator. */ | |
8bae0a0c | 789 | #endif /* !FASTSIM */ |
56e7c849 AC |
790 | sim_io_printf (sd, "Number of execution cycles = %ld\n", |
791 | (long) sim_events_time (sd)); | |
792 | ||
793 | /* print information pertaining to MIPS ISA and architecture being simulated */ | |
794 | /* things that may be interesting */ | |
795 | /* instructions executed - if available */ | |
796 | /* cycles executed - if available */ | |
797 | /* pipeline stalls - if available */ | |
798 | /* virtual time taken */ | |
799 | /* profiling size */ | |
800 | /* profiling frequency */ | |
801 | /* profile minpc */ | |
802 | /* profile maxpc */ | |
803 | } | |
aa324b9b | 804 | profile_print (sd, STATE_VERBOSE_P (sd), NULL, NULL); |
8bae0a0c JSC |
805 | } |
806 | ||
8bae0a0c | 807 | |
9d52bcb7 | 808 | SIM_RC |
fafce69a | 809 | sim_create_inferior (sd, abfd, argv,env) |
53b9417e | 810 | SIM_DESC sd; |
fafce69a | 811 | struct _bfd *abfd; |
8bae0a0c JSC |
812 | char **argv; |
813 | char **env; | |
814 | { | |
50a2a691 | 815 | |
8bae0a0c | 816 | #ifdef DEBUG |
9d52bcb7 DE |
817 | printf("DBG: sim_create_inferior entered: start_address = 0x%s\n", |
818 | pr_addr(PC)); | |
8bae0a0c JSC |
819 | #endif /* DEBUG */ |
820 | ||
0c2c5f61 | 821 | ColdReset(sd); |
50a2a691 AC |
822 | /* If we were providing a more complete I/O, co-processor or memory |
823 | simulation, we should perform any "device" initialisation at this | |
824 | point. This can include pre-loading memory areas with particular | |
825 | patterns (e.g. simulating ROM monitors). */ | |
826 | ||
2e61a3ad | 827 | #if 1 |
fafce69a AC |
828 | if (abfd != NULL) |
829 | PC = (unsigned64) bfd_get_start_address(abfd); | |
830 | else | |
831 | PC = 0; /* ???? */ | |
2e61a3ad AC |
832 | #else |
833 | /* TODO: Sort this properly. SIM_ADDR may already be a 64bit value: */ | |
fafce69a | 834 | PC = SIGNEXTEND(bfd_get_start_address(abfd),32); |
2e61a3ad AC |
835 | #endif |
836 | ||
8bae0a0c JSC |
837 | /* Prepare to execute the program to be simulated */ |
838 | /* argv and env are NULL terminated lists of pointers */ | |
839 | ||
8bae0a0c | 840 | if (argv || env) { |
f24b7b69 | 841 | #if 0 /* def DEBUG */ |
18c64df6 | 842 | sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n"); |
8bae0a0c JSC |
843 | { |
844 | char **cptr; | |
845 | for (cptr = argv; (cptr && *cptr); cptr++) | |
846 | printf("DBG: arg \"%s\"\n",*cptr); | |
847 | } | |
848 | #endif /* DEBUG */ | |
849 | /* We should really place the argv slot values into the argument | |
850 | registers, and onto the stack as required. However, this | |
851 | assumes that we have a stack defined, which is not necessarily | |
852 | true at the moment. */ | |
853 | } | |
854 | ||
9d52bcb7 | 855 | return SIM_RC_OK; |
8bae0a0c JSC |
856 | } |
857 | ||
8bae0a0c JSC |
858 | typedef enum {e_terminate,e_help,e_setmemsize,e_reset} e_cmds; |
859 | ||
860 | static struct t_sim_command { | |
861 | e_cmds id; | |
862 | const char *name; | |
863 | const char *help; | |
864 | } sim_commands[] = { | |
865 | {e_help, "help", ": Show MIPS simulator private commands"}, | |
866 | {e_setmemsize,"set-memory-size","<n> : Specify amount of memory simulated"}, | |
867 | {e_reset, "reset-system", ": Reset the simulated processor"}, | |
868 | {e_terminate, NULL} | |
869 | }; | |
870 | ||
871 | void | |
53b9417e DE |
872 | sim_do_command (sd,cmd) |
873 | SIM_DESC sd; | |
8bae0a0c JSC |
874 | char *cmd; |
875 | { | |
876 | struct t_sim_command *cptr; | |
877 | ||
878 | if (!(cmd && *cmd != '\0')) | |
879 | cmd = "help"; | |
880 | ||
881 | /* NOTE: Accessed from the GDB "sim" commmand: */ | |
882 | for (cptr = sim_commands; cptr && cptr->name; cptr++) | |
2f2e6c5d AC |
883 | if (strncmp (cmd, cptr->name, strlen(cptr->name)) == 0) |
884 | { | |
885 | cmd += strlen(cptr->name); | |
886 | switch (cptr->id) { | |
887 | case e_help: /* no arguments */ | |
888 | { /* no arguments */ | |
889 | struct t_sim_command *lptr; | |
18c64df6 | 890 | sim_io_printf(sd,"List of MIPS simulator commands:\n"); |
2f2e6c5d | 891 | for (lptr = sim_commands; lptr->name; lptr++) |
18c64df6 | 892 | sim_io_printf(sd,"%s %s\n",lptr->name,lptr->help); |
2f2e6c5d AC |
893 | sim_args_command (sd, "help"); |
894 | } | |
8bae0a0c JSC |
895 | break; |
896 | ||
2f2e6c5d AC |
897 | case e_setmemsize: /* memory size argument */ |
898 | { | |
18c64df6 AC |
899 | unsigned int newsize = (unsigned int)getnum(sd, cmd); |
900 | mips_size(sd, newsize); | |
2f2e6c5d | 901 | } |
8bae0a0c JSC |
902 | break; |
903 | ||
2f2e6c5d | 904 | case e_reset: /* no arguments */ |
0c2c5f61 | 905 | ColdReset(sd); |
2f2e6c5d AC |
906 | /* NOTE: See the comments in sim_open() relating to device |
907 | initialisation. */ | |
908 | break; | |
8bae0a0c | 909 | |
2f2e6c5d | 910 | default: |
18c64df6 | 911 | sim_io_printf(sd,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd,cptr->id); |
2f2e6c5d AC |
912 | break; |
913 | } | |
914 | break; | |
915 | } | |
8bae0a0c JSC |
916 | |
917 | if (!(cptr->name)) | |
2f2e6c5d AC |
918 | { |
919 | /* try for a common command when the sim specific lookup fails */ | |
920 | if (sim_args_command (sd, cmd) != SIM_RC_OK) | |
18c64df6 | 921 | sim_io_printf(sd,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd); |
2f2e6c5d | 922 | } |
8bae0a0c JSC |
923 | |
924 | return; | |
925 | } | |
926 | ||
927 | /*---------------------------------------------------------------------------*/ | |
928 | /* NOTE: The following routines do not seem to be used by GDB at the | |
929 | moment. However, they may be useful to the standalone simulator | |
930 | world. */ | |
931 | ||
932 | ||
18c64df6 AC |
933 | static void |
934 | mips_size(sd, newsize) | |
935 | SIM_DESC sd; | |
87e43259 | 936 | int newsize; |
8bae0a0c JSC |
937 | { |
938 | char *new; | |
939 | /* Used by "run", and internally, to set the simulated memory size */ | |
f24b7b69 | 940 | if (newsize == 0) { |
18c64df6 | 941 | sim_io_printf(sd,"Zero not valid: Memory size still 0x%08X bytes\n",STATE_MEM_SIZE (sd)); |
f24b7b69 JSC |
942 | return; |
943 | } | |
8bae0a0c | 944 | newsize = power2(newsize); |
50a2a691 AC |
945 | if (STATE_MEMORY (sd) == NULL) |
946 | new = (char *)calloc(64,(STATE_MEM_SIZE (sd) / 64)); | |
8bae0a0c | 947 | else |
50a2a691 | 948 | new = (char *)realloc(STATE_MEMORY (sd),newsize); |
8bae0a0c | 949 | if (new == NULL) { |
50a2a691 | 950 | if (STATE_MEMORY (sd) == NULL) |
18c64df6 | 951 | sim_io_error(sd,"Not enough VM for simulation memory of 0x%08X bytes",STATE_MEM_SIZE (sd)); |
8bae0a0c | 952 | else |
18c64df6 | 953 | sim_io_eprintf(sd,"Failed to resize memory (still 0x%08X bytes)\n",STATE_MEM_SIZE (sd)); |
8bae0a0c | 954 | } else { |
50a2a691 AC |
955 | STATE_MEM_SIZE (sd) = (unsigned)newsize; |
956 | STATE_MEMORY (sd) = new; | |
8bae0a0c | 957 | } |
8bae0a0c JSC |
958 | return; |
959 | } | |
960 | ||
8bae0a0c JSC |
961 | |
962 | /*---------------------------------------------------------------------------*/ | |
963 | /*-- Private simulator support interface ------------------------------------*/ | |
964 | /*---------------------------------------------------------------------------*/ | |
965 | ||
a9f7253f | 966 | /* Simple monitor interface (currently setup for the IDT and PMON monitors) */ |
8bae0a0c | 967 | static void |
18c64df6 AC |
968 | sim_monitor(sd,reason) |
969 | SIM_DESC sd; | |
8bae0a0c JSC |
970 | unsigned int reason; |
971 | { | |
53b9417e DE |
972 | #ifdef DEBUG |
973 | printf("DBG: sim_monitor: entered (reason = %d)\n",reason); | |
974 | #endif /* DEBUG */ | |
975 | ||
8bae0a0c JSC |
976 | /* The IDT monitor actually allows two instructions per vector |
977 | slot. However, the simulator currently causes a trap on each | |
978 | individual instruction. We cheat, and lose the bottom bit. */ | |
979 | reason >>= 1; | |
980 | ||
981 | /* The following callback functions are available, however the | |
982 | monitor we are simulating does not make use of them: get_errno, | |
983 | isatty, lseek, rename, system, time and unlink */ | |
984 | switch (reason) { | |
985 | case 6: /* int open(char *path,int flags) */ | |
986 | { | |
e871dd18 | 987 | uword64 paddr; |
8bae0a0c JSC |
988 | int cca; |
989 | if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) | |
18c64df6 | 990 | V0 = sim_io_open(sd,(char *)((int)paddr),(int)A1); |
8bae0a0c | 991 | else |
18c64df6 | 992 | sim_io_error(sd,"Attempt to pass pointer that does not reference simulated memory"); |
8bae0a0c JSC |
993 | } |
994 | break; | |
995 | ||
996 | case 7: /* int read(int file,char *ptr,int len) */ | |
997 | { | |
e871dd18 | 998 | uword64 paddr; |
8bae0a0c JSC |
999 | int cca; |
1000 | if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) | |
18c64df6 | 1001 | V0 = sim_io_read(sd,(int)A0,(char *)((int)paddr),(int)A2); |
8bae0a0c | 1002 | else |
18c64df6 | 1003 | sim_io_error(sd,"Attempt to pass pointer that does not reference simulated memory"); |
8bae0a0c JSC |
1004 | } |
1005 | break; | |
1006 | ||
1007 | case 8: /* int write(int file,char *ptr,int len) */ | |
1008 | { | |
e871dd18 | 1009 | uword64 paddr; |
8bae0a0c JSC |
1010 | int cca; |
1011 | if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) | |
18c64df6 | 1012 | V0 = sim_io_write(sd,(int)A0,(const char *)((int)paddr),(int)A2); |
8bae0a0c | 1013 | else |
18c64df6 | 1014 | sim_io_error(sd,"Attempt to pass pointer that does not reference simulated memory"); |
8bae0a0c JSC |
1015 | } |
1016 | break; | |
1017 | ||
1018 | case 10: /* int close(int file) */ | |
18c64df6 | 1019 | V0 = sim_io_close(sd,(int)A0); |
8bae0a0c JSC |
1020 | break; |
1021 | ||
1022 | case 11: /* char inbyte(void) */ | |
1023 | { | |
1024 | char tmp; | |
18c64df6 AC |
1025 | if (sim_io_read_stdin(sd,&tmp,sizeof(char)) != sizeof(char)) { |
1026 | sim_io_error(sd,"Invalid return from character read"); | |
e3d12c65 | 1027 | V0 = (ut_reg)-1; |
8bae0a0c JSC |
1028 | } |
1029 | else | |
e3d12c65 | 1030 | V0 = (ut_reg)tmp; |
8bae0a0c JSC |
1031 | } |
1032 | break; | |
1033 | ||
1034 | case 12: /* void outbyte(char chr) : write a byte to "stdout" */ | |
1035 | { | |
1036 | char tmp = (char)(A0 & 0xFF); | |
18c64df6 | 1037 | sim_io_write_stdout(sd,&tmp,sizeof(char)); |
8bae0a0c JSC |
1038 | } |
1039 | break; | |
1040 | ||
1041 | case 17: /* void _exit() */ | |
18c64df6 | 1042 | sim_io_eprintf(sd,"sim_monitor(17): _exit(int reason) to be coded\n"); |
2e61a3ad AC |
1043 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, sim_exited, |
1044 | (unsigned int)(A0 & 0xFFFFFFFF)); | |
8bae0a0c JSC |
1045 | break; |
1046 | ||
280f90e1 AMT |
1047 | case 28 : /* PMON flush_cache */ |
1048 | break; | |
1049 | ||
8bae0a0c JSC |
1050 | case 55: /* void get_mem_info(unsigned int *ptr) */ |
1051 | /* in: A0 = pointer to three word memory location */ | |
1052 | /* out: [A0 + 0] = size */ | |
1053 | /* [A0 + 4] = instruction cache size */ | |
1054 | /* [A0 + 8] = data cache size */ | |
1055 | { | |
e871dd18 JSC |
1056 | uword64 vaddr = A0; |
1057 | uword64 paddr, value; | |
8bae0a0c JSC |
1058 | int cca; |
1059 | int failed = 0; | |
1060 | ||
1061 | /* NOTE: We use RAW memory writes here, but since we are not | |
1062 | gathering statistics for the monitor calls we are simulating, | |
1063 | it is not an issue. */ | |
1064 | ||
1065 | /* Memory size */ | |
1066 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) { | |
50a2a691 | 1067 | value = (uword64)STATE_MEM_SIZE (sd); |
53b9417e | 1068 | StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW); |
8bae0a0c JSC |
1069 | /* We re-do the address translations, in-case the block |
1070 | overlaps a memory boundary: */ | |
1071 | value = 0; | |
1072 | vaddr += (AccessLength_WORD + 1); | |
1073 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) { | |
53b9417e | 1074 | StoreMemory(cca,AccessLength_WORD,0,value,paddr,vaddr,isRAW); |
8bae0a0c JSC |
1075 | vaddr += (AccessLength_WORD + 1); |
1076 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) | |
53b9417e | 1077 | StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW); |
8bae0a0c JSC |
1078 | else |
1079 | failed = -1; | |
1080 | } else | |
1081 | failed = -1; | |
1082 | } else | |
1083 | failed = -1; | |
1084 | ||
1085 | if (failed) | |
18c64df6 | 1086 | sim_io_error(sd,"Invalid pointer passed into monitor call"); |
8bae0a0c JSC |
1087 | } |
1088 | break; | |
1089 | ||
a9f7253f JSC |
1090 | case 158 : /* PMON printf */ |
1091 | /* in: A0 = pointer to format string */ | |
1092 | /* A1 = optional argument 1 */ | |
1093 | /* A2 = optional argument 2 */ | |
1094 | /* A3 = optional argument 3 */ | |
1095 | /* out: void */ | |
f24b7b69 | 1096 | /* The following is based on the PMON printf source */ |
a9f7253f JSC |
1097 | { |
1098 | uword64 paddr; | |
1099 | int cca; | |
f24b7b69 JSC |
1100 | /* This isn't the quickest way, since we call the host print |
1101 | routine for every character almost. But it does avoid | |
1102 | having to allocate and manage a temporary string buffer. */ | |
1103 | if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) { | |
1104 | char *s = (char *)((int)paddr); | |
fb5a2a3e | 1105 | signed_word *ap = &A1; /* 1st argument */ |
f24b7b69 JSC |
1106 | /* TODO: Include check that we only use three arguments (A1, A2 and A3) */ |
1107 | for (; *s;) { | |
1108 | if (*s == '%') { | |
1109 | char tmp[40]; | |
1110 | enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST; | |
1111 | int width = 0, trunc = 0, haddot = 0, longlong = 0; | |
f24b7b69 JSC |
1112 | s++; |
1113 | for (; *s; s++) { | |
1114 | if (strchr ("dobxXulscefg%", *s)) | |
1115 | break; | |
1116 | else if (*s == '-') | |
1117 | fmt = FMT_LJUST; | |
1118 | else if (*s == '0') | |
1119 | fmt = FMT_RJUST0; | |
1120 | else if (*s == '~') | |
1121 | fmt = FMT_CENTER; | |
1122 | else if (*s == '*') { | |
1123 | if (haddot) | |
1124 | trunc = (int)*ap++; | |
1125 | else | |
1126 | width = (int)*ap++; | |
1127 | } else if (*s >= '1' && *s <= '9') { | |
1128 | char *t; | |
1129 | unsigned int n; | |
1130 | for (t = s; isdigit (*s); s++); | |
1131 | strncpy (tmp, t, s - t); | |
1132 | tmp[s - t] = '\0'; | |
1133 | n = (unsigned int)strtol(tmp,NULL,10); | |
1134 | if (haddot) | |
1135 | trunc = n; | |
1136 | else | |
1137 | width = n; | |
1138 | s--; | |
1139 | } else if (*s == '.') | |
1140 | haddot = 1; | |
1141 | } | |
1142 | if (*s == '%') { | |
18c64df6 | 1143 | sim_io_printf(sd,"%%"); |
f24b7b69 JSC |
1144 | } else if (*s == 's') { |
1145 | if ((int)*ap != 0) { | |
1146 | if (AddressTranslation(*ap++,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) { | |
1147 | char *p = (char *)((int)paddr);; | |
18c64df6 | 1148 | sim_io_printf(sd,p); |
f24b7b69 JSC |
1149 | } else { |
1150 | ap++; | |
18c64df6 | 1151 | sim_io_error(sd,"Attempt to pass pointer that does not reference simulated memory"); |
f24b7b69 JSC |
1152 | } |
1153 | } | |
1154 | else | |
18c64df6 | 1155 | sim_io_printf(sd,"(null)"); |
f24b7b69 JSC |
1156 | } else if (*s == 'c') { |
1157 | int n = (int)*ap++; | |
18c64df6 | 1158 | sim_io_printf(sd,"%c",n); |
f24b7b69 JSC |
1159 | } else { |
1160 | if (*s == 'l') { | |
1161 | if (*++s == 'l') { | |
1162 | longlong = 1; | |
1163 | ++s; | |
1164 | } | |
1165 | } | |
1166 | if (strchr ("dobxXu", *s)) { | |
e3d12c65 | 1167 | word64 lv = (word64) *ap++; |
f24b7b69 | 1168 | if (*s == 'b') |
18c64df6 | 1169 | sim_io_printf(sd,"<binary not supported>"); |
f24b7b69 JSC |
1170 | else { |
1171 | sprintf(tmp,"%%%s%c",longlong ? "ll" : "",*s); | |
1172 | if (longlong) | |
18c64df6 | 1173 | sim_io_printf(sd,tmp,lv); |
f24b7b69 | 1174 | else |
18c64df6 | 1175 | sim_io_printf(sd,tmp,(int)lv); |
f24b7b69 JSC |
1176 | } |
1177 | } else if (strchr ("eEfgG", *s)) { | |
e3d12c65 DE |
1178 | #ifdef _MSC_VER /* MSVC version 2.x can't convert from uword64 directly */ |
1179 | double dbl = (double)((word64)*ap++); | |
1180 | #else | |
f24b7b69 | 1181 | double dbl = (double)*ap++; |
e3d12c65 | 1182 | #endif |
f24b7b69 | 1183 | sprintf(tmp,"%%%d.%d%c",width,trunc,*s); |
18c64df6 | 1184 | sim_io_printf(sd,tmp,dbl); |
f24b7b69 JSC |
1185 | trunc = 0; |
1186 | } | |
1187 | } | |
1188 | s++; | |
1189 | } else | |
18c64df6 | 1190 | sim_io_printf(sd,"%c",*s++); |
f24b7b69 JSC |
1191 | } |
1192 | } else | |
18c64df6 | 1193 | sim_io_error(sd,"Attempt to pass pointer that does not reference simulated memory"); |
a9f7253f JSC |
1194 | } |
1195 | break; | |
1196 | ||
8bae0a0c | 1197 | default: |
18c64df6 AC |
1198 | sim_io_eprintf(sd,"TODO: sim_monitor(%d) : PC = 0x%s\n",reason,pr_addr(IPC)); |
1199 | sim_io_eprintf(sd,"(Arguments : A0 = 0x%s : A1 = 0x%s : A2 = 0x%s : A3 = 0x%s)\n",pr_addr(A0),pr_addr(A1),pr_addr(A2),pr_addr(A3)); | |
8bae0a0c JSC |
1200 | break; |
1201 | } | |
1202 | return; | |
1203 | } | |
1204 | ||
7e6c297e ILT |
1205 | /* Store a word into memory. */ |
1206 | ||
1207 | static void | |
18c64df6 AC |
1208 | store_word (sd, vaddr, val) |
1209 | SIM_DESC sd; | |
7e6c297e ILT |
1210 | uword64 vaddr; |
1211 | t_reg val; | |
1212 | { | |
1213 | uword64 paddr; | |
1214 | int uncached; | |
1215 | ||
1216 | if ((vaddr & 3) != 0) | |
18c64df6 | 1217 | SignalExceptionAddressStore (); |
7e6c297e ILT |
1218 | else |
1219 | { | |
1220 | if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, | |
1221 | isTARGET, isREAL)) | |
1222 | { | |
1223 | const uword64 mask = 7; | |
1224 | uword64 memval; | |
1225 | unsigned int byte; | |
1226 | ||
1227 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)); | |
1228 | byte = (vaddr & mask) ^ (BigEndianCPU << 2); | |
1229 | memval = ((uword64) val) << (8 * byte); | |
53b9417e | 1230 | StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, |
7e6c297e ILT |
1231 | isREAL); |
1232 | } | |
1233 | } | |
1234 | } | |
1235 | ||
1236 | /* Load a word from memory. */ | |
1237 | ||
1238 | static t_reg | |
18c64df6 AC |
1239 | load_word (sd, vaddr) |
1240 | SIM_DESC sd; | |
7e6c297e ILT |
1241 | uword64 vaddr; |
1242 | { | |
1243 | if ((vaddr & 3) != 0) | |
18c64df6 | 1244 | SignalExceptionAddressLoad (); |
7e6c297e ILT |
1245 | else |
1246 | { | |
1247 | uword64 paddr; | |
1248 | int uncached; | |
1249 | ||
1250 | if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, | |
1251 | isTARGET, isREAL)) | |
1252 | { | |
1253 | const uword64 mask = 0x7; | |
1254 | const unsigned int reverse = ReverseEndian ? 1 : 0; | |
1255 | const unsigned int bigend = BigEndianCPU ? 1 : 0; | |
1256 | uword64 memval; | |
1257 | unsigned int byte; | |
1258 | ||
1259 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2)); | |
53b9417e | 1260 | LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr, |
7e6c297e ILT |
1261 | isDATA, isREAL); |
1262 | byte = (vaddr & mask) ^ (bigend << 2); | |
1263 | return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32); | |
1264 | } | |
1265 | } | |
1266 | ||
1267 | return 0; | |
1268 | } | |
1269 | ||
1270 | /* Simulate the mips16 entry and exit pseudo-instructions. These | |
1271 | would normally be handled by the reserved instruction exception | |
1272 | code, but for ease of simulation we just handle them directly. */ | |
1273 | ||
1274 | static void | |
0c2c5f61 AC |
1275 | mips16_entry (sd,insn) |
1276 | SIM_DESC sd; | |
7e6c297e ILT |
1277 | unsigned int insn; |
1278 | { | |
1279 | int aregs, sregs, rreg; | |
1280 | ||
53b9417e DE |
1281 | #ifdef DEBUG |
1282 | printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn); | |
1283 | #endif /* DEBUG */ | |
1284 | ||
7e6c297e ILT |
1285 | aregs = (insn & 0x700) >> 8; |
1286 | sregs = (insn & 0x0c0) >> 6; | |
1287 | rreg = (insn & 0x020) >> 5; | |
1288 | ||
da0bce9c ILT |
1289 | /* This should be checked by the caller. */ |
1290 | if (sregs == 3) | |
7e6c297e ILT |
1291 | abort (); |
1292 | ||
da0bce9c | 1293 | if (aregs < 5) |
7e6c297e ILT |
1294 | { |
1295 | int i; | |
1296 | t_reg tsp; | |
1297 | ||
1298 | /* This is the entry pseudo-instruction. */ | |
1299 | ||
1300 | for (i = 0; i < aregs; i++) | |
0c2c5f61 | 1301 | store_word ((uword64) (SP + 4 * i), GPR[i + 4]); |
7e6c297e ILT |
1302 | |
1303 | tsp = SP; | |
1304 | SP -= 32; | |
1305 | ||
1306 | if (rreg) | |
1307 | { | |
1308 | tsp -= 4; | |
1309 | store_word ((uword64) tsp, RA); | |
1310 | } | |
1311 | ||
1312 | for (i = 0; i < sregs; i++) | |
1313 | { | |
1314 | tsp -= 4; | |
0c2c5f61 | 1315 | store_word ((uword64) tsp, GPR[16 + i]); |
7e6c297e ILT |
1316 | } |
1317 | } | |
1318 | else | |
1319 | { | |
1320 | int i; | |
1321 | t_reg tsp; | |
1322 | ||
1323 | /* This is the exit pseudo-instruction. */ | |
1324 | ||
1325 | tsp = SP + 32; | |
1326 | ||
1327 | if (rreg) | |
1328 | { | |
1329 | tsp -= 4; | |
1330 | RA = load_word ((uword64) tsp); | |
1331 | } | |
1332 | ||
1333 | for (i = 0; i < sregs; i++) | |
1334 | { | |
1335 | tsp -= 4; | |
0c2c5f61 | 1336 | GPR[i + 16] = load_word ((uword64) tsp); |
7e6c297e ILT |
1337 | } |
1338 | ||
1339 | SP += 32; | |
1340 | ||
9cb8397f | 1341 | #if defined(HASFPU) |
da0bce9c ILT |
1342 | if (aregs == 5) |
1343 | { | |
1344 | FGR[0] = WORD64LO (GPR[4]); | |
0c2c5f61 | 1345 | FPR_STATE[0] = fmt_uninterpreted; |
da0bce9c ILT |
1346 | } |
1347 | else if (aregs == 6) | |
1348 | { | |
1349 | FGR[0] = WORD64LO (GPR[5]); | |
1350 | FGR[1] = WORD64LO (GPR[4]); | |
0c2c5f61 AC |
1351 | FPR_STATE[0] = fmt_uninterpreted; |
1352 | FPR_STATE[1] = fmt_uninterpreted; | |
da0bce9c | 1353 | } |
9cb8397f | 1354 | #endif /* defined(HASFPU) */ |
da0bce9c | 1355 | |
7e6c297e ILT |
1356 | PC = RA; |
1357 | } | |
1358 | } | |
1359 | ||
8bae0a0c JSC |
1360 | static unsigned int |
1361 | power2(value) | |
1362 | unsigned int value; | |
1363 | { | |
1364 | int loop,tmp; | |
1365 | ||
1366 | /* Round *UP* to the nearest power-of-2 if not already one */ | |
1367 | if (value != (value & ~(value - 1))) { | |
1368 | for (tmp = value, loop = 0; (tmp != 0); loop++) | |
1369 | tmp >>= 1; | |
1370 | value = (1 << loop); | |
1371 | } | |
1372 | ||
1373 | return(value); | |
1374 | } | |
1375 | ||
1376 | static long | |
18c64df6 AC |
1377 | getnum(sd,value) |
1378 | SIM_DESC sd; | |
8bae0a0c JSC |
1379 | char *value; |
1380 | { | |
1381 | long num; | |
1382 | char *end; | |
1383 | ||
1384 | num = strtol(value,&end,10); | |
1385 | if (end == value) | |
18c64df6 | 1386 | sim_io_printf(sd,"Warning: Invalid number \"%s\" ignored, using zero\n",value); |
8bae0a0c JSC |
1387 | else { |
1388 | if (*end && ((tolower(*end) == 'k') || (tolower(*end) == 'm'))) { | |
1389 | if (tolower(*end) == 'k') | |
1390 | num *= (1 << 10); | |
1391 | else | |
1392 | num *= (1 << 20); | |
1393 | end++; | |
1394 | } | |
1395 | if (*end) | |
18c64df6 | 1396 | sim_io_printf(sd,"Warning: Spurious characters \"%s\" at end of number ignored\n",end); |
8bae0a0c JSC |
1397 | } |
1398 | ||
1399 | return(num); | |
1400 | } | |
1401 | ||
1402 | /*-- trace support ----------------------------------------------------------*/ | |
1403 | ||
1404 | /* The TRACE support is provided (if required) in the memory accessing | |
1405 | routines. Since we are also providing the architecture specific | |
1406 | features, the architecture simulation code can also deal with | |
1407 | notifying the TRACE world of cache flushes, etc. Similarly we do | |
1408 | not need to provide profiling support in the simulator engine, | |
1409 | since we can sample in the instruction fetch control loop. By | |
1410 | defining the TRACE manifest, we add tracing as a run-time | |
1411 | option. */ | |
1412 | ||
1413 | #if defined(TRACE) | |
1414 | /* Tracing by default produces "din" format (as required by | |
1415 | dineroIII). Each line of such a trace file *MUST* have a din label | |
1416 | and address field. The rest of the line is ignored, so comments can | |
1417 | be included if desired. The first field is the label which must be | |
1418 | one of the following values: | |
1419 | ||
1420 | 0 read data | |
1421 | 1 write data | |
1422 | 2 instruction fetch | |
1423 | 3 escape record (treated as unknown access type) | |
1424 | 4 escape record (causes cache flush) | |
1425 | ||
1426 | The address field is a 32bit (lower-case) hexadecimal address | |
1427 | value. The address should *NOT* be preceded by "0x". | |
1428 | ||
1429 | The size of the memory transfer is not important when dealing with | |
1430 | cache lines (as long as no more than a cache line can be | |
1431 | transferred in a single operation :-), however more information | |
1432 | could be given following the dineroIII requirement to allow more | |
1433 | complete memory and cache simulators to provide better | |
1434 | results. i.e. the University of Pisa has a cache simulator that can | |
1435 | also take bus size and speed as (variable) inputs to calculate | |
1436 | complete system performance (a much more useful ability when trying | |
1437 | to construct an end product, rather than a processor). They | |
1438 | currently have an ARM version of their tool called ChARM. */ | |
1439 | ||
e3d12c65 | 1440 | |
8bae0a0c | 1441 | static |
0c2c5f61 | 1442 | void dotrace(SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...) |
8bae0a0c | 1443 | { |
0c2c5f61 | 1444 | if (STATE & simTRACE) { |
8bae0a0c | 1445 | va_list ap; |
53b9417e | 1446 | fprintf(tracefh,"%d %s ; width %d ; ", |
6429b296 | 1447 | type, |
53b9417e DE |
1448 | pr_addr(address), |
1449 | width); | |
8bae0a0c | 1450 | va_start(ap,comment); |
6429b296 | 1451 | vfprintf(tracefh,comment,ap); |
8bae0a0c JSC |
1452 | va_end(ap); |
1453 | fprintf(tracefh,"\n"); | |
1454 | } | |
1455 | /* NOTE: Since the "din" format will only accept 32bit addresses, and | |
1456 | we may be generating 64bit ones, we should put the hi-32bits of the | |
1457 | address into the comment field. */ | |
1458 | ||
1459 | /* TODO: Provide a buffer for the trace lines. We can then avoid | |
1460 | performing writes until the buffer is filled, or the file is | |
1461 | being closed. */ | |
1462 | ||
1463 | /* NOTE: We could consider adding a comment field to the "din" file | |
1464 | produced using type 3 markers (unknown access). This would then | |
1465 | allow information about the program that the "din" is for, and | |
1466 | the MIPs world that was being simulated, to be placed into the | |
1467 | trace file. */ | |
1468 | ||
1469 | return; | |
1470 | } | |
1471 | #endif /* TRACE */ | |
1472 | ||
1473 | /*---------------------------------------------------------------------------*/ | |
1474 | /*-- simulator engine -------------------------------------------------------*/ | |
1475 | /*---------------------------------------------------------------------------*/ | |
1476 | ||
1477 | static void | |
0c2c5f61 AC |
1478 | ColdReset(sd) |
1479 | SIM_DESC sd; | |
8bae0a0c JSC |
1480 | { |
1481 | /* RESET: Fixed PC address: */ | |
e871dd18 | 1482 | PC = (((uword64)0xFFFFFFFF<<32) | 0xBFC00000); |
8bae0a0c JSC |
1483 | /* The reset vector address is in the unmapped, uncached memory space. */ |
1484 | ||
1485 | SR &= ~(status_SR | status_TS | status_RP); | |
1486 | SR |= (status_ERL | status_BEV); | |
8bae0a0c JSC |
1487 | |
1488 | #if defined(HASFPU) && (GPRLEN == (64)) | |
1489 | /* Cheat and allow access to the complete register set immediately: */ | |
1490 | SR |= status_FR; /* 64bit registers */ | |
1491 | #endif /* HASFPU and 64bit FP registers */ | |
1492 | ||
1493 | /* Ensure that any instructions with pending register updates are | |
1494 | cleared: */ | |
1495 | { | |
1496 | int loop; | |
1497 | for (loop = 0; (loop < PSLOTS); loop++) | |
0c2c5f61 AC |
1498 | PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1); |
1499 | PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0; | |
8bae0a0c JSC |
1500 | } |
1501 | ||
1502 | #if defined(HASFPU) | |
1503 | /* Initialise the FPU registers to the unknown state */ | |
1504 | { | |
1505 | int rn; | |
1506 | for (rn = 0; (rn < 32); rn++) | |
0c2c5f61 | 1507 | FPR_STATE[rn] = fmt_uninterpreted; |
8bae0a0c JSC |
1508 | } |
1509 | #endif /* HASFPU */ | |
1510 | ||
1511 | return; | |
1512 | } | |
1513 | ||
1514 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1515 | /* Translate a virtual address to a physical address and cache | |
1516 | coherence algorithm describing the mechanism used to resolve the | |
1517 | memory reference. Given the virtual address vAddr, and whether the | |
1518 | reference is to Instructions ot Data (IorD), find the corresponding | |
1519 | physical address (pAddr) and the cache coherence algorithm (CCA) | |
1520 | used to resolve the reference. If the virtual address is in one of | |
1521 | the unmapped address spaces the physical address and the CCA are | |
1522 | determined directly by the virtual address. If the virtual address | |
1523 | is in one of the mapped address spaces then the TLB is used to | |
1524 | determine the physical address and access type; if the required | |
1525 | translation is not present in the TLB or the desired access is not | |
1526 | permitted the function fails and an exception is taken. | |
1527 | ||
1528 | NOTE: This function is extended to return an exception state. This, | |
1529 | along with the exception generation is used to notify whether a | |
1530 | valid address translation occured */ | |
1531 | ||
18c64df6 AC |
1532 | int |
1533 | address_translation(sd,vAddr,IorD,LorS,pAddr,CCA,host,raw) | |
1534 | SIM_DESC sd; | |
e871dd18 | 1535 | uword64 vAddr; |
8bae0a0c JSC |
1536 | int IorD; |
1537 | int LorS; | |
e871dd18 | 1538 | uword64 *pAddr; |
8bae0a0c JSC |
1539 | int *CCA; |
1540 | int host; | |
1541 | int raw; | |
1542 | { | |
1543 | int res = -1; /* TRUE : Assume good return */ | |
1544 | ||
1545 | #ifdef DEBUG | |
18c64df6 | 1546 | sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD")); |
8bae0a0c JSC |
1547 | #endif |
1548 | ||
1549 | /* Check that the address is valid for this memory model */ | |
1550 | ||
1551 | /* For a simple (flat) memory model, we simply pass virtual | |
1552 | addressess through (mostly) unchanged. */ | |
1553 | vAddr &= 0xFFFFFFFF; | |
a9f7253f JSC |
1554 | |
1555 | /* Treat the kernel memory spaces identically for the moment: */ | |
50a2a691 | 1556 | if ((STATE_MEM_BASE (sd) == K1BASE) && (vAddr >= K0BASE) && (vAddr < (K0BASE + K0SIZE))) |
a9f7253f JSC |
1557 | vAddr += (K1BASE - K0BASE); |
1558 | ||
1559 | /* Also assume that the K1BASE memory wraps. This is required to | |
1560 | allow the PMON run-time __sizemem() routine to function (without | |
1561 | having to provide exception simulation). NOTE: A kludge to work | |
1562 | around the fact that the monitor memory is currently held in the | |
1563 | K1BASE space. */ | |
1564 | if (((vAddr < monitor_base) || (vAddr >= (monitor_base + monitor_size))) && (vAddr >= K1BASE && vAddr < (K1BASE + K1SIZE))) | |
50a2a691 | 1565 | vAddr = (K1BASE | (vAddr & (STATE_MEM_SIZE (sd) - 1))); |
a9f7253f | 1566 | |
8bae0a0c JSC |
1567 | *pAddr = vAddr; /* default for isTARGET */ |
1568 | *CCA = Uncached; /* not used for isHOST */ | |
1569 | ||
1570 | /* NOTE: This is a duplicate of the code that appears in the | |
1571 | LoadMemory and StoreMemory functions. They should be merged into | |
1572 | a single function (that can be in-lined if required). */ | |
50a2a691 | 1573 | if ((vAddr >= STATE_MEM_BASE (sd)) && (vAddr < (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd)))) { |
8bae0a0c | 1574 | if (host) |
50a2a691 | 1575 | *pAddr = (int)&STATE_MEMORY (sd)[((unsigned int)(vAddr - STATE_MEM_BASE (sd)) & (STATE_MEM_SIZE (sd) - 1))]; |
8bae0a0c JSC |
1576 | } else if ((vAddr >= monitor_base) && (vAddr < (monitor_base + monitor_size))) { |
1577 | if (host) | |
1578 | *pAddr = (int)&monitor[((unsigned int)(vAddr - monitor_base) & (monitor_size - 1))]; | |
1579 | } else { | |
6429b296 | 1580 | #ifdef DEBUG |
18c64df6 | 1581 | sim_io_eprintf(sd,"Failed: AddressTranslation(0x%s,%s,%s,...) IPC = 0x%s\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD"),pr_addr(IPC)); |
8bae0a0c JSC |
1582 | #endif /* DEBUG */ |
1583 | res = 0; /* AddressTranslation has failed */ | |
e3d12c65 | 1584 | *pAddr = (SIM_ADDR)-1; |
8bae0a0c | 1585 | if (!raw) /* only generate exceptions on real memory transfers */ |
18c64df6 AC |
1586 | if (LorS == isSTORE) |
1587 | SignalExceptionAddressStore (); | |
1588 | else | |
1589 | SignalExceptionAddressLoad (); | |
6429b296 | 1590 | #ifdef DEBUG |
8bae0a0c | 1591 | else |
6429b296 JW |
1592 | /* This is a normal occurance during gdb operation, for instance trying |
1593 | to print parameters at function start before they have been setup, | |
1594 | and hence we should not print a warning except when debugging the | |
1595 | simulator. */ | |
18c64df6 | 1596 | sim_io_eprintf(sd,"AddressTranslation for %s %s from 0x%s failed\n",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),pr_addr(vAddr)); |
6429b296 | 1597 | #endif |
8bae0a0c JSC |
1598 | } |
1599 | ||
1600 | return(res); | |
1601 | } | |
1602 | ||
1603 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1604 | /* Prefetch data from memory. Prefetch is an advisory instruction for | |
1605 | which an implementation specific action is taken. The action taken | |
1606 | may increase performance, but must not change the meaning of the | |
1607 | program, or alter architecturally-visible state. */ | |
50a2a691 | 1608 | |
ea985d24 AC |
1609 | void |
1610 | prefetch(sd,CCA,pAddr,vAddr,DATA,hint) | |
1611 | SIM_DESC sd; | |
8bae0a0c | 1612 | int CCA; |
e871dd18 JSC |
1613 | uword64 pAddr; |
1614 | uword64 vAddr; | |
8bae0a0c JSC |
1615 | int DATA; |
1616 | int hint; | |
1617 | { | |
1618 | #ifdef DEBUG | |
18c64df6 | 1619 | sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint); |
8bae0a0c JSC |
1620 | #endif /* DEBUG */ |
1621 | ||
1622 | /* For our simple memory model we do nothing */ | |
1623 | return; | |
1624 | } | |
1625 | ||
1626 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1627 | /* Load a value from memory. Use the cache and main memory as | |
1628 | specified in the Cache Coherence Algorithm (CCA) and the sort of | |
1629 | access (IorD) to find the contents of AccessLength memory bytes | |
1630 | starting at physical location pAddr. The data is returned in the | |
1631 | fixed width naturally-aligned memory element (MemElem). The | |
1632 | low-order two (or three) bits of the address and the AccessLength | |
1633 | indicate which of the bytes within MemElem needs to be given to the | |
1634 | processor. If the memory access type of the reference is uncached | |
1635 | then only the referenced bytes are read from memory and valid | |
1636 | within the memory element. If the access type is cached, and the | |
1637 | data is not present in cache, an implementation specific size and | |
1638 | alignment block of memory is read and loaded into the cache to | |
1639 | satisfy a load reference. At a minimum, the block is the entire | |
1640 | memory element. */ | |
18c64df6 AC |
1641 | void |
1642 | load_memory(sd,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) | |
1643 | SIM_DESC sd; | |
53b9417e DE |
1644 | uword64* memvalp; |
1645 | uword64* memval1p; | |
8bae0a0c JSC |
1646 | int CCA; |
1647 | int AccessLength; | |
e871dd18 JSC |
1648 | uword64 pAddr; |
1649 | uword64 vAddr; | |
8bae0a0c JSC |
1650 | int IorD; |
1651 | int raw; | |
1652 | { | |
50a2a691 AC |
1653 | uword64 value = 0; |
1654 | uword64 value1 = 0; | |
8bae0a0c JSC |
1655 | |
1656 | #ifdef DEBUG | |
50a2a691 | 1657 | if (STATE_MEMORY (sd) == NULL) |
18c64df6 | 1658 | sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(raw ? "isRAW" : "isREAL")); |
8bae0a0c JSC |
1659 | #endif /* DEBUG */ |
1660 | ||
1661 | #if defined(WARN_MEM) | |
1662 | if (CCA != uncached) | |
18c64df6 | 1663 | sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c JSC |
1664 | |
1665 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) { | |
1666 | /* In reality this should be a Bus Error */ | |
18c64df6 | 1667 | sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr)); |
8bae0a0c JSC |
1668 | } |
1669 | #endif /* WARN_MEM */ | |
1670 | ||
1671 | /* Decide which physical memory locations are being dealt with. At | |
1672 | this point we should be able to split the pAddr bits into the | |
1673 | relevant address map being simulated. If the "raw" variable is | |
1674 | set, the memory read being performed should *NOT* update any I/O | |
1675 | state or affect the CPU state. This also includes avoiding | |
1676 | affecting statistics gathering. */ | |
1677 | ||
1678 | /* If instruction fetch then we need to check that the two lo-order | |
1679 | bits are zero, otherwise raise a InstructionFetch exception: */ | |
6429b296 JW |
1680 | if ((IorD == isINSTRUCTION) |
1681 | && ((pAddr & 0x3) != 0) | |
1682 | && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0))) | |
18c64df6 | 1683 | SignalExceptionInstructionFetch (); |
8bae0a0c | 1684 | else { |
50a2a691 | 1685 | unsigned int index = 0; |
8bae0a0c JSC |
1686 | unsigned char *mem = NULL; |
1687 | ||
8bae0a0c JSC |
1688 | #if defined(TRACE) |
1689 | if (!raw) | |
0c2c5f61 | 1690 | dotrace(sd,tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); |
8bae0a0c JSC |
1691 | #endif /* TRACE */ |
1692 | ||
1693 | /* NOTE: Quicker methods of decoding the address space can be used | |
1694 | when a real memory map is being simulated (i.e. using hi-order | |
1695 | address bits to select device). */ | |
50a2a691 AC |
1696 | if ((pAddr >= STATE_MEM_BASE (sd)) && (pAddr < (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd)))) { |
1697 | index = ((unsigned int)(pAddr - STATE_MEM_BASE (sd)) & (STATE_MEM_SIZE (sd) - 1)); | |
1698 | mem = STATE_MEMORY (sd); | |
8bae0a0c JSC |
1699 | } else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) { |
1700 | index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1)); | |
1701 | mem = monitor; | |
1702 | } | |
1703 | if (mem == NULL) | |
18c64df6 | 1704 | sim_io_error(sd,"Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr)); |
8bae0a0c JSC |
1705 | else { |
1706 | /* If we obtained the endianness of the host, and it is the same | |
1707 | as the target memory system we can optimise the memory | |
1708 | accesses. However, without that information we must perform | |
1709 | slow transfer, and hope that the compiler optimisation will | |
1710 | merge successive loads. */ | |
8bae0a0c JSC |
1711 | |
1712 | /* In reality we should always be loading a doubleword value (or | |
1713 | word value in 32bit memory worlds). The external code then | |
1714 | extracts the required bytes. However, to keep performance | |
1715 | high we only load the required bytes into the relevant | |
1716 | slots. */ | |
0049ba7a | 1717 | if (BigEndianMem) |
8bae0a0c | 1718 | switch (AccessLength) { /* big-endian memory */ |
53b9417e DE |
1719 | case AccessLength_QUADWORD : |
1720 | value1 |= ((uword64)mem[index++] << 56); | |
1721 | case 14: /* AccessLength is one less than datalen */ | |
1722 | value1 |= ((uword64)mem[index++] << 48); | |
1723 | case 13: | |
1724 | value1 |= ((uword64)mem[index++] << 40); | |
1725 | case 12: | |
1726 | value1 |= ((uword64)mem[index++] << 32); | |
1727 | case 11: | |
1728 | value1 |= ((unsigned int)mem[index++] << 24); | |
1729 | case 10: | |
1730 | value1 |= ((unsigned int)mem[index++] << 16); | |
1731 | case 9: | |
1732 | value1 |= ((unsigned int)mem[index++] << 8); | |
1733 | case 8: | |
1734 | value1 |= mem[index]; | |
1735 | ||
8bae0a0c | 1736 | case AccessLength_DOUBLEWORD : |
e871dd18 | 1737 | value |= ((uword64)mem[index++] << 56); |
8bae0a0c | 1738 | case AccessLength_SEPTIBYTE : |
e871dd18 | 1739 | value |= ((uword64)mem[index++] << 48); |
8bae0a0c | 1740 | case AccessLength_SEXTIBYTE : |
e871dd18 | 1741 | value |= ((uword64)mem[index++] << 40); |
8bae0a0c | 1742 | case AccessLength_QUINTIBYTE : |
e871dd18 | 1743 | value |= ((uword64)mem[index++] << 32); |
8bae0a0c JSC |
1744 | case AccessLength_WORD : |
1745 | value |= ((unsigned int)mem[index++] << 24); | |
1746 | case AccessLength_TRIPLEBYTE : | |
1747 | value |= ((unsigned int)mem[index++] << 16); | |
1748 | case AccessLength_HALFWORD : | |
1749 | value |= ((unsigned int)mem[index++] << 8); | |
1750 | case AccessLength_BYTE : | |
1751 | value |= mem[index]; | |
1752 | break; | |
1753 | } | |
1754 | else { | |
1755 | index += (AccessLength + 1); | |
1756 | switch (AccessLength) { /* little-endian memory */ | |
53b9417e DE |
1757 | case AccessLength_QUADWORD : |
1758 | value1 |= ((uword64)mem[--index] << 56); | |
1759 | case 14: /* AccessLength is one less than datalen */ | |
1760 | value1 |= ((uword64)mem[--index] << 48); | |
1761 | case 13: | |
1762 | value1 |= ((uword64)mem[--index] << 40); | |
1763 | case 12: | |
1764 | value1 |= ((uword64)mem[--index] << 32); | |
1765 | case 11: | |
1766 | value1 |= ((uword64)mem[--index] << 24); | |
1767 | case 10: | |
1768 | value1 |= ((uword64)mem[--index] << 16); | |
1769 | case 9: | |
1770 | value1 |= ((uword64)mem[--index] << 8); | |
1771 | case 8: | |
1772 | value1 |= ((uword64)mem[--index] << 0); | |
1773 | ||
8bae0a0c | 1774 | case AccessLength_DOUBLEWORD : |
e871dd18 | 1775 | value |= ((uword64)mem[--index] << 56); |
8bae0a0c | 1776 | case AccessLength_SEPTIBYTE : |
e871dd18 | 1777 | value |= ((uword64)mem[--index] << 48); |
8bae0a0c | 1778 | case AccessLength_SEXTIBYTE : |
e871dd18 | 1779 | value |= ((uword64)mem[--index] << 40); |
8bae0a0c | 1780 | case AccessLength_QUINTIBYTE : |
e871dd18 | 1781 | value |= ((uword64)mem[--index] << 32); |
8bae0a0c | 1782 | case AccessLength_WORD : |
e871dd18 | 1783 | value |= ((uword64)mem[--index] << 24); |
8bae0a0c | 1784 | case AccessLength_TRIPLEBYTE : |
e871dd18 | 1785 | value |= ((uword64)mem[--index] << 16); |
8bae0a0c | 1786 | case AccessLength_HALFWORD : |
e871dd18 | 1787 | value |= ((uword64)mem[--index] << 8); |
8bae0a0c | 1788 | case AccessLength_BYTE : |
e871dd18 | 1789 | value |= ((uword64)mem[--index] << 0); |
8bae0a0c JSC |
1790 | break; |
1791 | } | |
1792 | } | |
1793 | ||
1794 | #ifdef DEBUG | |
53b9417e | 1795 | printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n", |
87e43259 | 1796 | (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value)); |
8bae0a0c JSC |
1797 | #endif /* DEBUG */ |
1798 | ||
1799 | /* TODO: We could try and avoid the shifts when dealing with raw | |
1800 | memory accesses. This would mean updating the LoadMemory and | |
1801 | StoreMemory routines to avoid shifting the data before | |
1802 | returning or using it. */ | |
53b9417e DE |
1803 | if (AccessLength <= AccessLength_DOUBLEWORD) { |
1804 | if (!raw) { /* do nothing for raw accessess */ | |
1805 | if (BigEndianMem) | |
1806 | value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1807 | else /* little-endian only needs to be shifted up to the correct byte offset */ | |
1808 | value <<= ((pAddr & LOADDRMASK) * 8); | |
1809 | } | |
8bae0a0c JSC |
1810 | } |
1811 | ||
1812 | #ifdef DEBUG | |
53b9417e | 1813 | printf("DBG: LoadMemory() : shifted value = 0x%s%s\n", |
87e43259 | 1814 | pr_uword64(value1),pr_uword64(value)); |
e871dd18 | 1815 | #endif /* DEBUG */ |
8bae0a0c JSC |
1816 | } |
1817 | } | |
1818 | ||
53b9417e DE |
1819 | *memvalp = value; |
1820 | if (memval1p) *memval1p = value1; | |
8bae0a0c JSC |
1821 | } |
1822 | ||
53b9417e | 1823 | |
50a2a691 AC |
1824 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual |
1825 | (revision 3.1) */ | |
8bae0a0c JSC |
1826 | /* Store a value to memory. The specified data is stored into the |
1827 | physical location pAddr using the memory hierarchy (data caches and | |
1828 | main memory) as specified by the Cache Coherence Algorithm | |
1829 | (CCA). The MemElem contains the data for an aligned, fixed-width | |
1830 | memory element (word for 32-bit processors, doubleword for 64-bit | |
1831 | processors), though only the bytes that will actually be stored to | |
1832 | memory need to be valid. The low-order two (or three) bits of pAddr | |
1833 | and the AccessLength field indicates which of the bytes within the | |
1834 | MemElem data should actually be stored; only these bytes in memory | |
1835 | will be changed. */ | |
53b9417e | 1836 | |
18c64df6 AC |
1837 | void |
1838 | store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) | |
1839 | SIM_DESC sd; | |
8bae0a0c JSC |
1840 | int CCA; |
1841 | int AccessLength; | |
e871dd18 | 1842 | uword64 MemElem; |
53b9417e | 1843 | uword64 MemElem1; /* High order 64 bits */ |
e871dd18 JSC |
1844 | uword64 pAddr; |
1845 | uword64 vAddr; | |
8bae0a0c JSC |
1846 | int raw; |
1847 | { | |
1848 | #ifdef DEBUG | |
18c64df6 | 1849 | sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s,%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr),(raw ? "isRAW" : "isREAL")); |
8bae0a0c JSC |
1850 | #endif /* DEBUG */ |
1851 | ||
1852 | #if defined(WARN_MEM) | |
1853 | if (CCA != uncached) | |
18c64df6 | 1854 | sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c JSC |
1855 | |
1856 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
18c64df6 | 1857 | sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr)); |
8bae0a0c JSC |
1858 | #endif /* WARN_MEM */ |
1859 | ||
1860 | #if defined(TRACE) | |
1861 | if (!raw) | |
0c2c5f61 | 1862 | dotrace(sd,tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); |
8bae0a0c JSC |
1863 | #endif /* TRACE */ |
1864 | ||
1865 | /* See the comments in the LoadMemory routine about optimising | |
1866 | memory accesses. Also if we wanted to make the simulator smaller, | |
1867 | we could merge a lot of this code with the LoadMemory | |
1868 | routine. However, this would slow the simulator down with | |
1869 | run-time conditionals. */ | |
1870 | { | |
50a2a691 | 1871 | unsigned int index = 0; |
8bae0a0c JSC |
1872 | unsigned char *mem = NULL; |
1873 | ||
50a2a691 AC |
1874 | if ((pAddr >= STATE_MEM_BASE (sd)) && (pAddr < (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd)))) { |
1875 | index = ((unsigned int)(pAddr - STATE_MEM_BASE (sd)) & (STATE_MEM_SIZE (sd) - 1)); | |
1876 | mem = STATE_MEMORY (sd); | |
8bae0a0c JSC |
1877 | } else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) { |
1878 | index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1)); | |
1879 | mem = monitor; | |
1880 | } | |
1881 | ||
1882 | if (mem == NULL) | |
18c64df6 | 1883 | sim_io_error(sd,"Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr)); |
8bae0a0c JSC |
1884 | else { |
1885 | int shift = 0; | |
1886 | ||
1887 | #ifdef DEBUG | |
87e43259 | 1888 | printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c JSC |
1889 | #endif /* DEBUG */ |
1890 | ||
53b9417e DE |
1891 | if (AccessLength <= AccessLength_DOUBLEWORD) { |
1892 | if (BigEndianMem) { | |
1893 | if (raw) | |
1894 | shift = ((7 - AccessLength) * 8); | |
1895 | else /* real memory access */ | |
1896 | shift = ((pAddr & LOADDRMASK) * 8); | |
1897 | MemElem <<= shift; | |
1898 | } else { | |
1899 | /* no need to shift raw little-endian data */ | |
1900 | if (!raw) | |
1901 | MemElem >>= ((pAddr & LOADDRMASK) * 8); | |
1902 | } | |
8bae0a0c JSC |
1903 | } |
1904 | ||
1905 | #ifdef DEBUG | |
87e43259 | 1906 | printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c JSC |
1907 | #endif /* DEBUG */ |
1908 | ||
0049ba7a | 1909 | if (BigEndianMem) { |
8bae0a0c | 1910 | switch (AccessLength) { /* big-endian memory */ |
53b9417e DE |
1911 | case AccessLength_QUADWORD : |
1912 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1913 | MemElem1 <<= 8; | |
1914 | case 14 : | |
1915 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1916 | MemElem1 <<= 8; | |
1917 | case 13 : | |
1918 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1919 | MemElem1 <<= 8; | |
1920 | case 12 : | |
1921 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1922 | MemElem1 <<= 8; | |
1923 | case 11 : | |
1924 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1925 | MemElem1 <<= 8; | |
1926 | case 10 : | |
1927 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1928 | MemElem1 <<= 8; | |
1929 | case 9 : | |
1930 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1931 | MemElem1 <<= 8; | |
1932 | case 8 : | |
1933 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
1934 | ||
8bae0a0c JSC |
1935 | case AccessLength_DOUBLEWORD : |
1936 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1937 | MemElem <<= 8; | |
1938 | case AccessLength_SEPTIBYTE : | |
1939 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1940 | MemElem <<= 8; | |
1941 | case AccessLength_SEXTIBYTE : | |
1942 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1943 | MemElem <<= 8; | |
1944 | case AccessLength_QUINTIBYTE : | |
1945 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1946 | MemElem <<= 8; | |
1947 | case AccessLength_WORD : | |
1948 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1949 | MemElem <<= 8; | |
1950 | case AccessLength_TRIPLEBYTE : | |
1951 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1952 | MemElem <<= 8; | |
1953 | case AccessLength_HALFWORD : | |
1954 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1955 | MemElem <<= 8; | |
1956 | case AccessLength_BYTE : | |
1957 | mem[index++] = (unsigned char)(MemElem >> 56); | |
1958 | break; | |
1959 | } | |
1960 | } else { | |
1961 | index += (AccessLength + 1); | |
1962 | switch (AccessLength) { /* little-endian memory */ | |
53b9417e DE |
1963 | case AccessLength_QUADWORD : |
1964 | mem[--index] = (unsigned char)(MemElem1 >> 56); | |
1965 | case 14 : | |
1966 | mem[--index] = (unsigned char)(MemElem1 >> 48); | |
1967 | case 13 : | |
1968 | mem[--index] = (unsigned char)(MemElem1 >> 40); | |
1969 | case 12 : | |
1970 | mem[--index] = (unsigned char)(MemElem1 >> 32); | |
1971 | case 11 : | |
1972 | mem[--index] = (unsigned char)(MemElem1 >> 24); | |
1973 | case 10 : | |
1974 | mem[--index] = (unsigned char)(MemElem1 >> 16); | |
1975 | case 9 : | |
1976 | mem[--index] = (unsigned char)(MemElem1 >> 8); | |
1977 | case 8 : | |
1978 | mem[--index] = (unsigned char)(MemElem1 >> 0); | |
1979 | ||
8bae0a0c JSC |
1980 | case AccessLength_DOUBLEWORD : |
1981 | mem[--index] = (unsigned char)(MemElem >> 56); | |
1982 | case AccessLength_SEPTIBYTE : | |
1983 | mem[--index] = (unsigned char)(MemElem >> 48); | |
1984 | case AccessLength_SEXTIBYTE : | |
1985 | mem[--index] = (unsigned char)(MemElem >> 40); | |
1986 | case AccessLength_QUINTIBYTE : | |
1987 | mem[--index] = (unsigned char)(MemElem >> 32); | |
1988 | case AccessLength_WORD : | |
1989 | mem[--index] = (unsigned char)(MemElem >> 24); | |
1990 | case AccessLength_TRIPLEBYTE : | |
1991 | mem[--index] = (unsigned char)(MemElem >> 16); | |
1992 | case AccessLength_HALFWORD : | |
1993 | mem[--index] = (unsigned char)(MemElem >> 8); | |
1994 | case AccessLength_BYTE : | |
1995 | mem[--index] = (unsigned char)(MemElem >> 0); | |
1996 | break; | |
1997 | } | |
1998 | } | |
1999 | } | |
2000 | } | |
2001 | ||
2002 | return; | |
2003 | } | |
2004 | ||
53b9417e | 2005 | |
8bae0a0c JSC |
2006 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ |
2007 | /* Order loads and stores to synchronise shared memory. Perform the | |
2008 | action necessary to make the effects of groups of synchronizable | |
2009 | loads and stores indicated by stype occur in the same order for all | |
2010 | processors. */ | |
ea985d24 AC |
2011 | void |
2012 | sync_operation(sd,stype) | |
2013 | SIM_DESC sd; | |
8bae0a0c JSC |
2014 | int stype; |
2015 | { | |
2016 | #ifdef DEBUG | |
18c64df6 | 2017 | sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype); |
8bae0a0c JSC |
2018 | #endif /* DEBUG */ |
2019 | return; | |
2020 | } | |
2021 | ||
2022 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
2023 | /* Signal an exception condition. This will result in an exception | |
2024 | that aborts the instruction. The instruction operation pseudocode | |
50a2a691 | 2025 | will never see a return from this function call. */ |
2e61a3ad | 2026 | |
18c64df6 AC |
2027 | void |
2028 | signal_exception (SIM_DESC sd, int exception,...) | |
8bae0a0c | 2029 | { |
56e7c849 | 2030 | int vector; |
6eedf3f4 MA |
2031 | |
2032 | #ifdef DEBUG | |
18c64df6 | 2033 | sim_io_printf(sd,"DBG: SignalException(%d) IPC = 0x%s\n",exception,pr_addr(IPC)); |
6eedf3f4 MA |
2034 | #endif /* DEBUG */ |
2035 | ||
8bae0a0c JSC |
2036 | /* Ensure that any active atomic read/modify/write operation will fail: */ |
2037 | LLBIT = 0; | |
2038 | ||
2039 | switch (exception) { | |
2040 | /* TODO: For testing purposes I have been ignoring TRAPs. In | |
2041 | reality we should either simulate them, or allow the user to | |
6eedf3f4 MA |
2042 | ignore them at run-time. |
2043 | Same for SYSCALL */ | |
8bae0a0c | 2044 | case Trap : |
18c64df6 | 2045 | sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(IPC)); |
8bae0a0c JSC |
2046 | break; |
2047 | ||
6eedf3f4 MA |
2048 | case SystemCall : |
2049 | { | |
2050 | va_list ap; | |
2051 | unsigned int instruction; | |
2052 | unsigned int code; | |
2053 | ||
2054 | va_start(ap,exception); | |
2055 | instruction = va_arg(ap,unsigned int); | |
2056 | va_end(ap); | |
2057 | ||
2058 | code = (instruction >> 6) & 0xFFFFF; | |
2059 | ||
18c64df6 | 2060 | sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n", |
6eedf3f4 MA |
2061 | code, pr_addr(IPC)); |
2062 | } | |
2063 | break; | |
2064 | ||
2065 | case DebugBreakPoint : | |
2066 | if (! (Debug & Debug_DM)) | |
2067 | { | |
2068 | if (INDELAYSLOT()) | |
2069 | { | |
2070 | CANCELDELAYSLOT(); | |
2071 | ||
2072 | Debug |= Debug_DBD; /* signaled from within in delay slot */ | |
2073 | DEPC = IPC - 4; /* reference the branch instruction */ | |
2074 | } | |
2075 | else | |
2076 | { | |
2077 | Debug &= ~Debug_DBD; /* not signaled from within a delay slot */ | |
2078 | DEPC = IPC; | |
2079 | } | |
2080 | ||
2081 | Debug |= Debug_DM; /* in debugging mode */ | |
2082 | Debug |= Debug_DBp; /* raising a DBp exception */ | |
2083 | PC = 0xBFC00200; | |
2084 | sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA); | |
2085 | } | |
2086 | break; | |
2087 | ||
8bae0a0c JSC |
2088 | case ReservedInstruction : |
2089 | { | |
2090 | va_list ap; | |
2091 | unsigned int instruction; | |
2092 | va_start(ap,exception); | |
2093 | instruction = va_arg(ap,unsigned int); | |
2094 | va_end(ap); | |
2095 | /* Provide simple monitor support using ReservedInstruction | |
2096 | exceptions. The following code simulates the fixed vector | |
2097 | entry points into the IDT monitor by causing a simulator | |
2098 | trap, performing the monitor operation, and returning to | |
2099 | the address held in the $ra register (standard PCS return | |
2100 | address). This means we only need to pre-load the vector | |
2101 | space with suitable instruction values. For systems were | |
2102 | actual trap instructions are used, we would not need to | |
2103 | perform this magic. */ | |
53b9417e | 2104 | if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) { |
18c64df6 | 2105 | sim_monitor(sd, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) ); |
8bae0a0c JSC |
2106 | PC = RA; /* simulate the return from the vector entry */ |
2107 | /* NOTE: This assumes that a branch-and-link style | |
2108 | instruction was used to enter the vector (which is the | |
2109 | case with the current IDT monitor). */ | |
2e61a3ad | 2110 | sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA); |
7e6c297e ILT |
2111 | } |
2112 | /* Look for the mips16 entry and exit instructions, and | |
2113 | simulate a handler for them. */ | |
2114 | else if ((IPC & 1) != 0 | |
2115 | && (instruction & 0xf81f) == 0xe809 | |
7e6c297e ILT |
2116 | && (instruction & 0x0c0) != 0x0c0) { |
2117 | mips16_entry (instruction); | |
2e61a3ad | 2118 | sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA); |
8bae0a0c | 2119 | } /* else fall through to normal exception processing */ |
18c64df6 | 2120 | sim_io_eprintf(sd,"ReservedInstruction 0x%08X at IPC = 0x%s\n",instruction,pr_addr(IPC)); |
8bae0a0c JSC |
2121 | } |
2122 | ||
05d1322f | 2123 | case BreakPoint: |
e3d12c65 | 2124 | #ifdef DEBUG |
18c64df6 | 2125 | sim_io_printf(sd,"DBG: SignalException(%d) IPC = 0x%s\n",exception,pr_addr(IPC)); |
8bae0a0c | 2126 | #endif /* DEBUG */ |
05d1322f JL |
2127 | /* Keep a copy of the current A0 in-case this is the program exit |
2128 | breakpoint: */ | |
2129 | { | |
2130 | va_list ap; | |
2131 | unsigned int instruction; | |
2132 | va_start(ap,exception); | |
2133 | instruction = va_arg(ap,unsigned int); | |
2134 | va_end(ap); | |
2135 | /* Check for our special terminating BREAK: */ | |
2136 | if ((instruction & 0x03FFFFC0) == 0x03ff0000) { | |
2137 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, | |
2138 | sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); | |
2139 | } | |
2140 | } | |
0c2c5f61 | 2141 | if (STATE & simDELAYSLOT) |
05d1322f JL |
2142 | PC = IPC - 4; /* reference the branch instruction */ |
2143 | else | |
2144 | PC = IPC; | |
2145 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, | |
2146 | sim_stopped, SIGTRAP); | |
2147 | ||
2148 | default: | |
8bae0a0c JSC |
2149 | /* Store exception code into current exception id variable (used |
2150 | by exit code): */ | |
2151 | ||
2152 | /* TODO: If not simulating exceptions then stop the simulator | |
2153 | execution. At the moment we always stop the simulation. */ | |
e3d12c65 | 2154 | |
56e7c849 AC |
2155 | /* See figure 5-17 for an outline of the code below */ |
2156 | if (! (SR & status_EXL)) | |
2157 | { | |
2158 | CAUSE = (exception << 2); | |
0c2c5f61 | 2159 | if (STATE & simDELAYSLOT) |
56e7c849 | 2160 | { |
0c2c5f61 | 2161 | STATE &= ~simDELAYSLOT; |
56e7c849 AC |
2162 | CAUSE |= cause_BD; |
2163 | EPC = (IPC - 4); /* reference the branch instruction */ | |
2164 | } | |
2165 | else | |
2166 | EPC = IPC; | |
2167 | /* FIXME: TLB et.al. */ | |
2168 | vector = 0x180; | |
2169 | } | |
2170 | else | |
2171 | { | |
05d1322f | 2172 | CAUSE = (exception << 2); |
56e7c849 AC |
2173 | vector = 0x180; |
2174 | } | |
2175 | SR |= status_EXL; | |
e3d12c65 DE |
2176 | /* Store exception code into current exception id variable (used |
2177 | by exit code): */ | |
56e7c849 AC |
2178 | if (SR & status_BEV) |
2179 | PC = (signed)0xBFC00200 + 0x180; | |
2180 | else | |
2181 | PC = (signed)0x80000000 + 0x180; | |
2182 | ||
50a2a691 AC |
2183 | switch ((CAUSE >> 2) & 0x1F) |
2184 | { | |
2185 | case Interrupt: | |
56e7c849 AC |
2186 | /* Interrupts arrive during event processing, no need to |
2187 | restart */ | |
2188 | return; | |
50a2a691 AC |
2189 | |
2190 | case TLBModification: | |
2191 | case TLBLoad: | |
2192 | case TLBStore: | |
2193 | case AddressLoad: | |
2194 | case AddressStore: | |
2195 | case InstructionFetch: | |
2196 | case DataReference: | |
56e7c849 AC |
2197 | /* The following is so that the simulator will continue from the |
2198 | exception address on breakpoint operations. */ | |
2199 | PC = EPC; | |
50a2a691 AC |
2200 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, |
2201 | sim_stopped, SIGBUS); | |
2202 | ||
2203 | case ReservedInstruction: | |
2204 | case CoProcessorUnusable: | |
56e7c849 | 2205 | PC = EPC; |
50a2a691 AC |
2206 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, |
2207 | sim_stopped, SIGILL); | |
2208 | ||
2209 | case IntegerOverflow: | |
2210 | case FPE: | |
2211 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, | |
2212 | sim_stopped, SIGFPE); | |
2213 | ||
2214 | case Trap: | |
2215 | case Watch: | |
2216 | case SystemCall: | |
56e7c849 | 2217 | PC = EPC; |
50a2a691 AC |
2218 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, |
2219 | sim_stopped, SIGTRAP); | |
2220 | ||
05d1322f JL |
2221 | case BreakPoint: |
2222 | PC = EPC; | |
2223 | sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA, | |
2224 | "FATAL: Should not encounter a breakpoint\n"); | |
2225 | ||
50a2a691 | 2226 | default : /* Unknown internal exception */ |
56e7c849 | 2227 | PC = EPC; |
50a2a691 AC |
2228 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, |
2229 | sim_stopped, SIGQUIT); | |
2230 | ||
2231 | } | |
8bae0a0c JSC |
2232 | |
2233 | case SimulatorFault: | |
2234 | { | |
2235 | va_list ap; | |
2236 | char *msg; | |
2237 | va_start(ap,exception); | |
2238 | msg = va_arg(ap,char *); | |
50a2a691 | 2239 | va_end(ap); |
2e61a3ad AC |
2240 | sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA, |
2241 | "FATAL: Simulator error \"%s\"\n",msg); | |
8bae0a0c | 2242 | } |
8bae0a0c JSC |
2243 | } |
2244 | ||
2245 | return; | |
2246 | } | |
2247 | ||
2248 | #if defined(WARN_RESULT) | |
2249 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
2250 | /* This function indicates that the result of the operation is | |
2251 | undefined. However, this should not affect the instruction | |
2252 | stream. All that is meant to happen is that the destination | |
2253 | register is set to an undefined result. To keep the simulator | |
2254 | simple, we just don't bother updating the destination register, so | |
2255 | the overall result will be undefined. If desired we can stop the | |
2256 | simulator by raising a pseudo-exception. */ | |
2257 | static void | |
2258 | UndefinedResult() | |
2259 | { | |
18c64df6 | 2260 | sim_io_eprintf(sd,"UndefinedResult: IPC = 0x%s\n",pr_addr(IPC)); |
8bae0a0c JSC |
2261 | #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */ |
2262 | state |= simSTOP; | |
2263 | #endif | |
2264 | return; | |
2265 | } | |
2266 | #endif /* WARN_RESULT */ | |
2267 | ||
18c64df6 AC |
2268 | void |
2269 | cache_op(sd,op,pAddr,vAddr,instruction) | |
2270 | SIM_DESC sd; | |
8bae0a0c | 2271 | int op; |
e871dd18 JSC |
2272 | uword64 pAddr; |
2273 | uword64 vAddr; | |
8bae0a0c JSC |
2274 | unsigned int instruction; |
2275 | { | |
f24b7b69 JSC |
2276 | #if 1 /* stop warning message being displayed (we should really just remove the code) */ |
2277 | static int icache_warning = 1; | |
2278 | static int dcache_warning = 1; | |
2279 | #else | |
a9f7253f JSC |
2280 | static int icache_warning = 0; |
2281 | static int dcache_warning = 0; | |
f24b7b69 | 2282 | #endif |
a9f7253f | 2283 | |
8bae0a0c JSC |
2284 | /* If CP0 is not useable (User or Supervisor mode) and the CP0 |
2285 | enable bit in the Status Register is clear - a coprocessor | |
2286 | unusable exception is taken. */ | |
a9f7253f | 2287 | #if 0 |
18c64df6 | 2288 | sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(IPC)); |
a9f7253f | 2289 | #endif |
8bae0a0c JSC |
2290 | |
2291 | switch (op & 0x3) { | |
2292 | case 0: /* instruction cache */ | |
2293 | switch (op >> 2) { | |
2294 | case 0: /* Index Invalidate */ | |
2295 | case 1: /* Index Load Tag */ | |
2296 | case 2: /* Index Store Tag */ | |
2297 | case 4: /* Hit Invalidate */ | |
2298 | case 5: /* Fill */ | |
2299 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
2300 | if (!icache_warning) |
2301 | { | |
18c64df6 | 2302 | sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
2303 | icache_warning = 1; |
2304 | } | |
8bae0a0c JSC |
2305 | break; |
2306 | ||
2307 | default: | |
2308 | SignalException(ReservedInstruction,instruction); | |
2309 | break; | |
2310 | } | |
2311 | break; | |
2312 | ||
2313 | case 1: /* data cache */ | |
2314 | switch (op >> 2) { | |
2315 | case 0: /* Index Writeback Invalidate */ | |
2316 | case 1: /* Index Load Tag */ | |
2317 | case 2: /* Index Store Tag */ | |
2318 | case 3: /* Create Dirty */ | |
2319 | case 4: /* Hit Invalidate */ | |
2320 | case 5: /* Hit Writeback Invalidate */ | |
2321 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
2322 | if (!dcache_warning) |
2323 | { | |
18c64df6 | 2324 | sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
2325 | dcache_warning = 1; |
2326 | } | |
8bae0a0c JSC |
2327 | break; |
2328 | ||
2329 | default: | |
2330 | SignalException(ReservedInstruction,instruction); | |
2331 | break; | |
2332 | } | |
2333 | break; | |
2334 | ||
2335 | default: /* unrecognised cache ID */ | |
2336 | SignalException(ReservedInstruction,instruction); | |
2337 | break; | |
2338 | } | |
2339 | ||
2340 | return; | |
2341 | } | |
2342 | ||
2343 | /*-- FPU support routines ---------------------------------------------------*/ | |
2344 | ||
2345 | #if defined(HASFPU) /* Only needed when building FPU aware simulators */ | |
2346 | ||
8bae0a0c JSC |
2347 | /* Numbers are held in normalized form. The SINGLE and DOUBLE binary |
2348 | formats conform to ANSI/IEEE Std 754-1985. */ | |
2349 | /* SINGLE precision floating: | |
2350 | * seeeeeeeefffffffffffffffffffffff | |
2351 | * s = 1bit = sign | |
2352 | * e = 8bits = exponent | |
2353 | * f = 23bits = fraction | |
2354 | */ | |
2355 | /* SINGLE precision fixed: | |
2356 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2357 | * s = 1bit = sign | |
2358 | * i = 31bits = integer | |
2359 | */ | |
2360 | /* DOUBLE precision floating: | |
2361 | * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff | |
2362 | * s = 1bit = sign | |
2363 | * e = 11bits = exponent | |
2364 | * f = 52bits = fraction | |
2365 | */ | |
2366 | /* DOUBLE precision fixed: | |
2367 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2368 | * s = 1bit = sign | |
2369 | * i = 63bits = integer | |
2370 | */ | |
2371 | ||
2372 | /* Extract sign-bit: */ | |
2373 | #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0) | |
e871dd18 | 2374 | #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0) |
8bae0a0c JSC |
2375 | /* Extract biased exponent: */ |
2376 | #define FP_S_be(v) (((v) >> 23) & 0xFF) | |
2377 | #define FP_D_be(v) (((v) >> 52) & 0x7FF) | |
2378 | /* Extract unbiased Exponent: */ | |
2379 | #define FP_S_e(v) (FP_S_be(v) - 0x7F) | |
2380 | #define FP_D_e(v) (FP_D_be(v) - 0x3FF) | |
2381 | /* Extract complete fraction field: */ | |
2382 | #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23)) | |
e871dd18 | 2383 | #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52)) |
8bae0a0c JSC |
2384 | /* Extract numbered fraction bit: */ |
2385 | #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0) | |
2386 | #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0) | |
2387 | ||
2388 | /* Explicit QNaN values used when value required: */ | |
2389 | #define FPQNaN_SINGLE (0x7FBFFFFF) | |
2390 | #define FPQNaN_WORD (0x7FFFFFFF) | |
e871dd18 JSC |
2391 | #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF) |
2392 | #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF) | |
8bae0a0c JSC |
2393 | |
2394 | /* Explicit Infinity values used when required: */ | |
2395 | #define FPINF_SINGLE (0x7F800000) | |
e871dd18 | 2396 | #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000) |
8bae0a0c JSC |
2397 | |
2398 | #if 1 /* def DEBUG */ | |
2399 | #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor"))) | |
2400 | #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>")))))) | |
2401 | #endif /* DEBUG */ | |
2402 | ||
18c64df6 AC |
2403 | uword64 |
2404 | value_fpr(sd,fpr,fmt) | |
2405 | SIM_DESC sd; | |
2406 | int fpr; | |
2407 | FP_formats fmt; | |
8bae0a0c | 2408 | { |
50a2a691 | 2409 | uword64 value = 0; |
8bae0a0c JSC |
2410 | int err = 0; |
2411 | ||
2412 | /* Treat unused register values, as fixed-point 64bit values: */ | |
2413 | if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown)) | |
2414 | #if 1 | |
2415 | /* If request to read data as "uninterpreted", then use the current | |
2416 | encoding: */ | |
0c2c5f61 | 2417 | fmt = FPR_STATE[fpr]; |
8bae0a0c JSC |
2418 | #else |
2419 | fmt = fmt_long; | |
2420 | #endif | |
2421 | ||
2422 | /* For values not yet accessed, set to the desired format: */ | |
0c2c5f61 AC |
2423 | if (FPR_STATE[fpr] == fmt_uninterpreted) { |
2424 | FPR_STATE[fpr] = fmt; | |
8bae0a0c JSC |
2425 | #ifdef DEBUG |
2426 | printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt)); | |
2427 | #endif /* DEBUG */ | |
2428 | } | |
0c2c5f61 AC |
2429 | if (fmt != FPR_STATE[fpr]) { |
2430 | sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(IPC)); | |
2431 | FPR_STATE[fpr] = fmt_unknown; | |
8bae0a0c JSC |
2432 | } |
2433 | ||
0c2c5f61 | 2434 | if (FPR_STATE[fpr] == fmt_unknown) { |
8bae0a0c JSC |
2435 | /* Set QNaN value: */ |
2436 | switch (fmt) { | |
2437 | case fmt_single: | |
2438 | value = FPQNaN_SINGLE; | |
2439 | break; | |
2440 | ||
2441 | case fmt_double: | |
2442 | value = FPQNaN_DOUBLE; | |
2443 | break; | |
2444 | ||
2445 | case fmt_word: | |
2446 | value = FPQNaN_WORD; | |
2447 | break; | |
2448 | ||
2449 | case fmt_long: | |
2450 | value = FPQNaN_LONG; | |
2451 | break; | |
2452 | ||
2453 | default: | |
2454 | err = -1; | |
2455 | break; | |
2456 | } | |
2457 | } else if (SizeFGR() == 64) { | |
2458 | switch (fmt) { | |
2459 | case fmt_single: | |
2460 | case fmt_word: | |
2461 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2462 | break; | |
2463 | ||
2464 | case fmt_uninterpreted: | |
2465 | case fmt_double: | |
2466 | case fmt_long: | |
2467 | value = FGR[fpr]; | |
2468 | break; | |
2469 | ||
2470 | default : | |
2471 | err = -1; | |
2472 | break; | |
2473 | } | |
da0bce9c | 2474 | } else { |
8bae0a0c JSC |
2475 | switch (fmt) { |
2476 | case fmt_single: | |
2477 | case fmt_word: | |
2478 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2479 | break; | |
2480 | ||
2481 | case fmt_uninterpreted: | |
2482 | case fmt_double: | |
2483 | case fmt_long: | |
da0bce9c ILT |
2484 | if ((fpr & 1) == 0) { /* even registers only */ |
2485 | value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF)); | |
2486 | } else { | |
18c64df6 | 2487 | SignalException(ReservedInstruction,0); |
da0bce9c | 2488 | } |
8bae0a0c JSC |
2489 | break; |
2490 | ||
2491 | default : | |
2492 | err = -1; | |
2493 | break; | |
2494 | } | |
2495 | } | |
2496 | ||
2497 | if (err) | |
18c64df6 | 2498 | SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()"); |
8bae0a0c JSC |
2499 | |
2500 | #ifdef DEBUG | |
53b9417e | 2501 | printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(IPC),SizeFGR()); |
8bae0a0c JSC |
2502 | #endif /* DEBUG */ |
2503 | ||
2504 | return(value); | |
2505 | } | |
2506 | ||
18c64df6 AC |
2507 | void |
2508 | store_fpr(sd,fpr,fmt,value) | |
2509 | SIM_DESC sd; | |
8bae0a0c JSC |
2510 | int fpr; |
2511 | FP_formats fmt; | |
e871dd18 | 2512 | uword64 value; |
8bae0a0c JSC |
2513 | { |
2514 | int err = 0; | |
2515 | ||
2516 | #ifdef DEBUG | |
53b9417e | 2517 | printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(IPC),SizeFGR()); |
8bae0a0c JSC |
2518 | #endif /* DEBUG */ |
2519 | ||
2520 | if (SizeFGR() == 64) { | |
2521 | switch (fmt) { | |
2522 | case fmt_single : | |
2523 | case fmt_word : | |
e871dd18 | 2524 | FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF)); |
0c2c5f61 | 2525 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2526 | break; |
2527 | ||
2528 | case fmt_uninterpreted: | |
2529 | case fmt_double : | |
2530 | case fmt_long : | |
2531 | FGR[fpr] = value; | |
0c2c5f61 | 2532 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2533 | break; |
2534 | ||
2535 | default : | |
0c2c5f61 | 2536 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2537 | err = -1; |
2538 | break; | |
2539 | } | |
da0bce9c | 2540 | } else { |
8bae0a0c JSC |
2541 | switch (fmt) { |
2542 | case fmt_single : | |
2543 | case fmt_word : | |
8bae0a0c | 2544 | FGR[fpr] = (value & 0xFFFFFFFF); |
0c2c5f61 | 2545 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2546 | break; |
2547 | ||
2548 | case fmt_uninterpreted: | |
2549 | case fmt_double : | |
2550 | case fmt_long : | |
da0bce9c ILT |
2551 | if ((fpr & 1) == 0) { /* even register number only */ |
2552 | FGR[fpr+1] = (value >> 32); | |
2553 | FGR[fpr] = (value & 0xFFFFFFFF); | |
0c2c5f61 AC |
2554 | FPR_STATE[fpr + 1] = fmt; |
2555 | FPR_STATE[fpr] = fmt; | |
da0bce9c | 2556 | } else { |
0c2c5f61 AC |
2557 | FPR_STATE[fpr] = fmt_unknown; |
2558 | FPR_STATE[fpr + 1] = fmt_unknown; | |
18c64df6 | 2559 | SignalException(ReservedInstruction,0); |
da0bce9c | 2560 | } |
8bae0a0c JSC |
2561 | break; |
2562 | ||
2563 | default : | |
0c2c5f61 | 2564 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2565 | err = -1; |
2566 | break; | |
2567 | } | |
e871dd18 JSC |
2568 | } |
2569 | #if defined(WARN_RESULT) | |
2570 | else | |
2571 | UndefinedResult(); | |
2572 | #endif /* WARN_RESULT */ | |
8bae0a0c JSC |
2573 | |
2574 | if (err) | |
18c64df6 | 2575 | SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()"); |
8bae0a0c JSC |
2576 | |
2577 | #ifdef DEBUG | |
53b9417e | 2578 | printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt)); |
8bae0a0c JSC |
2579 | #endif /* DEBUG */ |
2580 | ||
2581 | return; | |
2582 | } | |
2583 | ||
18c64df6 | 2584 | int |
8bae0a0c | 2585 | NaN(op,fmt) |
e871dd18 | 2586 | uword64 op; |
8bae0a0c JSC |
2587 | FP_formats fmt; |
2588 | { | |
2589 | int boolean = 0; | |
2590 | ||
2591 | /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We | |
2592 | know that the exponent field is biased... we we cheat and avoid | |
2593 | removing the bias value. */ | |
2594 | switch (fmt) { | |
2595 | case fmt_single: | |
2596 | boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) != 0)); | |
2597 | /* We could use "FP_S_fb(1,op)" to ascertain whether we are | |
2598 | dealing with a SNaN or QNaN */ | |
2599 | break; | |
2600 | case fmt_double: | |
2601 | boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) != 0)); | |
2602 | /* We could use "FP_S_fb(1,op)" to ascertain whether we are | |
2603 | dealing with a SNaN or QNaN */ | |
2604 | break; | |
2605 | case fmt_word: | |
2606 | boolean = (op == FPQNaN_WORD); | |
2607 | break; | |
2608 | case fmt_long: | |
2609 | boolean = (op == FPQNaN_LONG); | |
2610 | break; | |
50a2a691 AC |
2611 | default: |
2612 | fprintf (stderr, "Bad switch\n"); | |
2613 | abort (); | |
8bae0a0c JSC |
2614 | } |
2615 | ||
2616 | #ifdef DEBUG | |
53b9417e | 2617 | printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2618 | #endif /* DEBUG */ |
2619 | ||
2620 | return(boolean); | |
2621 | } | |
2622 | ||
18c64df6 | 2623 | int |
8bae0a0c | 2624 | Infinity(op,fmt) |
e871dd18 | 2625 | uword64 op; |
8bae0a0c JSC |
2626 | FP_formats fmt; |
2627 | { | |
2628 | int boolean = 0; | |
2629 | ||
2630 | #ifdef DEBUG | |
53b9417e | 2631 | printf("DBG: Infinity: format %s 0x%s (PC = 0x%s)\n",DOFMT(fmt),pr_addr(op),pr_addr(IPC)); |
8bae0a0c JSC |
2632 | #endif /* DEBUG */ |
2633 | ||
2634 | /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We | |
2635 | know that the exponent field is biased... we we cheat and avoid | |
2636 | removing the bias value. */ | |
2637 | switch (fmt) { | |
2638 | case fmt_single: | |
2639 | boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) == 0)); | |
2640 | break; | |
2641 | case fmt_double: | |
2642 | boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) == 0)); | |
2643 | break; | |
2644 | default: | |
2645 | printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt)); | |
2646 | break; | |
2647 | } | |
2648 | ||
2649 | #ifdef DEBUG | |
53b9417e | 2650 | printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2651 | #endif /* DEBUG */ |
2652 | ||
2653 | return(boolean); | |
2654 | } | |
2655 | ||
18c64df6 | 2656 | int |
8bae0a0c | 2657 | Less(op1,op2,fmt) |
e871dd18 JSC |
2658 | uword64 op1; |
2659 | uword64 op2; | |
8bae0a0c JSC |
2660 | FP_formats fmt; |
2661 | { | |
2662 | int boolean = 0; | |
2663 | ||
e871dd18 JSC |
2664 | /* Argument checking already performed by the FPCOMPARE code */ |
2665 | ||
8bae0a0c | 2666 | #ifdef DEBUG |
53b9417e | 2667 | printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2668 | #endif /* DEBUG */ |
2669 | ||
8bae0a0c JSC |
2670 | /* The format type should already have been checked: */ |
2671 | switch (fmt) { | |
2672 | case fmt_single: | |
2673 | { | |
2674 | unsigned int wop1 = (unsigned int)op1; | |
2675 | unsigned int wop2 = (unsigned int)op2; | |
2676 | boolean = (*(float *)&wop1 < *(float *)&wop2); | |
2677 | } | |
2678 | break; | |
2679 | case fmt_double: | |
2680 | boolean = (*(double *)&op1 < *(double *)&op2); | |
2681 | break; | |
50a2a691 AC |
2682 | default: |
2683 | fprintf (stderr, "Bad switch\n"); | |
2684 | abort (); | |
8bae0a0c JSC |
2685 | } |
2686 | ||
2687 | #ifdef DEBUG | |
2688 | printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2689 | #endif /* DEBUG */ | |
2690 | ||
2691 | return(boolean); | |
2692 | } | |
2693 | ||
18c64df6 | 2694 | int |
8bae0a0c | 2695 | Equal(op1,op2,fmt) |
e871dd18 JSC |
2696 | uword64 op1; |
2697 | uword64 op2; | |
8bae0a0c JSC |
2698 | FP_formats fmt; |
2699 | { | |
2700 | int boolean = 0; | |
2701 | ||
e871dd18 JSC |
2702 | /* Argument checking already performed by the FPCOMPARE code */ |
2703 | ||
8bae0a0c | 2704 | #ifdef DEBUG |
53b9417e | 2705 | printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2706 | #endif /* DEBUG */ |
2707 | ||
8bae0a0c JSC |
2708 | /* The format type should already have been checked: */ |
2709 | switch (fmt) { | |
2710 | case fmt_single: | |
2711 | boolean = ((op1 & 0xFFFFFFFF) == (op2 & 0xFFFFFFFF)); | |
2712 | break; | |
2713 | case fmt_double: | |
2714 | boolean = (op1 == op2); | |
2715 | break; | |
50a2a691 AC |
2716 | default: |
2717 | fprintf (stderr, "Bad switch\n"); | |
2718 | abort (); | |
8bae0a0c JSC |
2719 | } |
2720 | ||
2721 | #ifdef DEBUG | |
2722 | printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2723 | #endif /* DEBUG */ | |
2724 | ||
2725 | return(boolean); | |
2726 | } | |
2727 | ||
18c64df6 | 2728 | uword64 |
a9f7253f JSC |
2729 | AbsoluteValue(op,fmt) |
2730 | uword64 op; | |
2731 | FP_formats fmt; | |
2732 | { | |
50a2a691 | 2733 | uword64 result = 0; |
a9f7253f JSC |
2734 | |
2735 | #ifdef DEBUG | |
53b9417e | 2736 | printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
a9f7253f JSC |
2737 | #endif /* DEBUG */ |
2738 | ||
2739 | /* The format type should already have been checked: */ | |
2740 | switch (fmt) { | |
2741 | case fmt_single: | |
2742 | { | |
2743 | unsigned int wop = (unsigned int)op; | |
2744 | float tmp = ((float)fabs((double)*(float *)&wop)); | |
2745 | result = (uword64)*(unsigned int *)&tmp; | |
2746 | } | |
2747 | break; | |
2748 | case fmt_double: | |
2749 | { | |
2750 | double tmp = (fabs(*(double *)&op)); | |
2751 | result = *(uword64 *)&tmp; | |
2752 | } | |
50a2a691 AC |
2753 | default: |
2754 | fprintf (stderr, "Bad switch\n"); | |
2755 | abort (); | |
a9f7253f JSC |
2756 | } |
2757 | ||
2758 | return(result); | |
2759 | } | |
2760 | ||
18c64df6 | 2761 | uword64 |
8bae0a0c | 2762 | Negate(op,fmt) |
e871dd18 | 2763 | uword64 op; |
8bae0a0c JSC |
2764 | FP_formats fmt; |
2765 | { | |
50a2a691 | 2766 | uword64 result = 0; |
8bae0a0c JSC |
2767 | |
2768 | #ifdef DEBUG | |
53b9417e | 2769 | printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2770 | #endif /* DEBUG */ |
2771 | ||
2772 | /* The format type should already have been checked: */ | |
2773 | switch (fmt) { | |
2774 | case fmt_single: | |
2775 | { | |
2776 | unsigned int wop = (unsigned int)op; | |
2777 | float tmp = ((float)0.0 - *(float *)&wop); | |
e871dd18 | 2778 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2779 | } |
2780 | break; | |
2781 | case fmt_double: | |
2782 | { | |
2783 | double tmp = ((double)0.0 - *(double *)&op); | |
e871dd18 | 2784 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2785 | } |
2786 | break; | |
50a2a691 AC |
2787 | default: |
2788 | fprintf (stderr, "Bad switch\n"); | |
2789 | abort (); | |
8bae0a0c JSC |
2790 | } |
2791 | ||
2792 | return(result); | |
2793 | } | |
2794 | ||
18c64df6 | 2795 | uword64 |
8bae0a0c | 2796 | Add(op1,op2,fmt) |
e871dd18 JSC |
2797 | uword64 op1; |
2798 | uword64 op2; | |
8bae0a0c JSC |
2799 | FP_formats fmt; |
2800 | { | |
50a2a691 | 2801 | uword64 result = 0; |
8bae0a0c JSC |
2802 | |
2803 | #ifdef DEBUG | |
53b9417e | 2804 | printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2805 | #endif /* DEBUG */ |
2806 | ||
e871dd18 JSC |
2807 | /* The registers must specify FPRs valid for operands of type |
2808 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2809 | |
2810 | /* The format type should already have been checked: */ | |
2811 | switch (fmt) { | |
2812 | case fmt_single: | |
2813 | { | |
2814 | unsigned int wop1 = (unsigned int)op1; | |
2815 | unsigned int wop2 = (unsigned int)op2; | |
2816 | float tmp = (*(float *)&wop1 + *(float *)&wop2); | |
e871dd18 | 2817 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2818 | } |
2819 | break; | |
2820 | case fmt_double: | |
2821 | { | |
2822 | double tmp = (*(double *)&op1 + *(double *)&op2); | |
e871dd18 | 2823 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2824 | } |
2825 | break; | |
50a2a691 AC |
2826 | default: |
2827 | fprintf (stderr, "Bad switch\n"); | |
2828 | abort (); | |
8bae0a0c JSC |
2829 | } |
2830 | ||
2831 | #ifdef DEBUG | |
53b9417e | 2832 | printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2833 | #endif /* DEBUG */ |
2834 | ||
2835 | return(result); | |
2836 | } | |
2837 | ||
18c64df6 | 2838 | uword64 |
8bae0a0c | 2839 | Sub(op1,op2,fmt) |
e871dd18 JSC |
2840 | uword64 op1; |
2841 | uword64 op2; | |
8bae0a0c JSC |
2842 | FP_formats fmt; |
2843 | { | |
50a2a691 | 2844 | uword64 result = 0; |
8bae0a0c JSC |
2845 | |
2846 | #ifdef DEBUG | |
53b9417e | 2847 | printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2848 | #endif /* DEBUG */ |
2849 | ||
e871dd18 JSC |
2850 | /* The registers must specify FPRs valid for operands of type |
2851 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2852 | |
2853 | /* The format type should already have been checked: */ | |
2854 | switch (fmt) { | |
2855 | case fmt_single: | |
2856 | { | |
2857 | unsigned int wop1 = (unsigned int)op1; | |
2858 | unsigned int wop2 = (unsigned int)op2; | |
2859 | float tmp = (*(float *)&wop1 - *(float *)&wop2); | |
e871dd18 | 2860 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2861 | } |
2862 | break; | |
2863 | case fmt_double: | |
2864 | { | |
2865 | double tmp = (*(double *)&op1 - *(double *)&op2); | |
e871dd18 | 2866 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2867 | } |
2868 | break; | |
50a2a691 AC |
2869 | default: |
2870 | fprintf (stderr, "Bad switch\n"); | |
2871 | abort (); | |
8bae0a0c JSC |
2872 | } |
2873 | ||
2874 | #ifdef DEBUG | |
53b9417e | 2875 | printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2876 | #endif /* DEBUG */ |
2877 | ||
2878 | return(result); | |
2879 | } | |
2880 | ||
18c64df6 | 2881 | uword64 |
8bae0a0c | 2882 | Multiply(op1,op2,fmt) |
e871dd18 JSC |
2883 | uword64 op1; |
2884 | uword64 op2; | |
8bae0a0c JSC |
2885 | FP_formats fmt; |
2886 | { | |
50a2a691 | 2887 | uword64 result = 0; |
8bae0a0c JSC |
2888 | |
2889 | #ifdef DEBUG | |
53b9417e | 2890 | printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2891 | #endif /* DEBUG */ |
2892 | ||
e871dd18 JSC |
2893 | /* The registers must specify FPRs valid for operands of type |
2894 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2895 | |
2896 | /* The format type should already have been checked: */ | |
2897 | switch (fmt) { | |
2898 | case fmt_single: | |
2899 | { | |
2900 | unsigned int wop1 = (unsigned int)op1; | |
2901 | unsigned int wop2 = (unsigned int)op2; | |
2902 | float tmp = (*(float *)&wop1 * *(float *)&wop2); | |
e871dd18 | 2903 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2904 | } |
2905 | break; | |
2906 | case fmt_double: | |
2907 | { | |
2908 | double tmp = (*(double *)&op1 * *(double *)&op2); | |
e871dd18 | 2909 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2910 | } |
2911 | break; | |
50a2a691 AC |
2912 | default: |
2913 | fprintf (stderr, "Bad switch\n"); | |
2914 | abort (); | |
8bae0a0c JSC |
2915 | } |
2916 | ||
2917 | #ifdef DEBUG | |
53b9417e | 2918 | printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2919 | #endif /* DEBUG */ |
2920 | ||
2921 | return(result); | |
2922 | } | |
2923 | ||
18c64df6 | 2924 | uword64 |
8bae0a0c | 2925 | Divide(op1,op2,fmt) |
e871dd18 JSC |
2926 | uword64 op1; |
2927 | uword64 op2; | |
8bae0a0c JSC |
2928 | FP_formats fmt; |
2929 | { | |
50a2a691 | 2930 | uword64 result = 0; |
8bae0a0c JSC |
2931 | |
2932 | #ifdef DEBUG | |
53b9417e | 2933 | printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2934 | #endif /* DEBUG */ |
2935 | ||
e871dd18 JSC |
2936 | /* The registers must specify FPRs valid for operands of type |
2937 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2938 | |
2939 | /* The format type should already have been checked: */ | |
2940 | switch (fmt) { | |
2941 | case fmt_single: | |
2942 | { | |
2943 | unsigned int wop1 = (unsigned int)op1; | |
2944 | unsigned int wop2 = (unsigned int)op2; | |
2945 | float tmp = (*(float *)&wop1 / *(float *)&wop2); | |
e871dd18 | 2946 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2947 | } |
2948 | break; | |
2949 | case fmt_double: | |
2950 | { | |
2951 | double tmp = (*(double *)&op1 / *(double *)&op2); | |
e871dd18 | 2952 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2953 | } |
2954 | break; | |
50a2a691 AC |
2955 | default: |
2956 | fprintf (stderr, "Bad switch\n"); | |
2957 | abort (); | |
8bae0a0c JSC |
2958 | } |
2959 | ||
2960 | #ifdef DEBUG | |
53b9417e | 2961 | printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2962 | #endif /* DEBUG */ |
2963 | ||
2964 | return(result); | |
2965 | } | |
2966 | ||
18c64df6 | 2967 | uword64 UNUSED |
8bae0a0c | 2968 | Recip(op,fmt) |
e871dd18 | 2969 | uword64 op; |
8bae0a0c JSC |
2970 | FP_formats fmt; |
2971 | { | |
50a2a691 | 2972 | uword64 result = 0; |
8bae0a0c JSC |
2973 | |
2974 | #ifdef DEBUG | |
53b9417e | 2975 | printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2976 | #endif /* DEBUG */ |
2977 | ||
e871dd18 JSC |
2978 | /* The registers must specify FPRs valid for operands of type |
2979 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2980 | |
2981 | /* The format type should already have been checked: */ | |
2982 | switch (fmt) { | |
2983 | case fmt_single: | |
2984 | { | |
2985 | unsigned int wop = (unsigned int)op; | |
2986 | float tmp = ((float)1.0 / *(float *)&wop); | |
e871dd18 | 2987 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2988 | } |
2989 | break; | |
2990 | case fmt_double: | |
2991 | { | |
2992 | double tmp = ((double)1.0 / *(double *)&op); | |
e871dd18 | 2993 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2994 | } |
2995 | break; | |
50a2a691 AC |
2996 | default: |
2997 | fprintf (stderr, "Bad switch\n"); | |
2998 | abort (); | |
8bae0a0c JSC |
2999 | } |
3000 | ||
3001 | #ifdef DEBUG | |
53b9417e | 3002 | printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
3003 | #endif /* DEBUG */ |
3004 | ||
3005 | return(result); | |
3006 | } | |
3007 | ||
18c64df6 | 3008 | uword64 |
8bae0a0c | 3009 | SquareRoot(op,fmt) |
e871dd18 | 3010 | uword64 op; |
8bae0a0c JSC |
3011 | FP_formats fmt; |
3012 | { | |
50a2a691 | 3013 | uword64 result = 0; |
8bae0a0c JSC |
3014 | |
3015 | #ifdef DEBUG | |
53b9417e | 3016 | printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
3017 | #endif /* DEBUG */ |
3018 | ||
e871dd18 JSC |
3019 | /* The registers must specify FPRs valid for operands of type |
3020 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
3021 | |
3022 | /* The format type should already have been checked: */ | |
3023 | switch (fmt) { | |
3024 | case fmt_single: | |
3025 | { | |
3026 | unsigned int wop = (unsigned int)op; | |
e3d12c65 | 3027 | #ifdef HAVE_SQRT |
8bae0a0c | 3028 | float tmp = ((float)sqrt((double)*(float *)&wop)); |
e871dd18 | 3029 | result = (uword64)*(unsigned int *)&tmp; |
e3d12c65 DE |
3030 | #else |
3031 | /* TODO: Provide square-root */ | |
3032 | result = (uword64)0; | |
3033 | #endif | |
8bae0a0c JSC |
3034 | } |
3035 | break; | |
3036 | case fmt_double: | |
3037 | { | |
e3d12c65 | 3038 | #ifdef HAVE_SQRT |
8bae0a0c | 3039 | double tmp = (sqrt(*(double *)&op)); |
e871dd18 | 3040 | result = *(uword64 *)&tmp; |
e3d12c65 DE |
3041 | #else |
3042 | /* TODO: Provide square-root */ | |
3043 | result = (uword64)0; | |
3044 | #endif | |
8bae0a0c JSC |
3045 | } |
3046 | break; | |
50a2a691 AC |
3047 | default: |
3048 | fprintf (stderr, "Bad switch\n"); | |
3049 | abort (); | |
8bae0a0c JSC |
3050 | } |
3051 | ||
3052 | #ifdef DEBUG | |
53b9417e | 3053 | printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
3054 | #endif /* DEBUG */ |
3055 | ||
3056 | return(result); | |
3057 | } | |
3058 | ||
18c64df6 AC |
3059 | uword64 |
3060 | convert(sd,rm,op,from,to) | |
3061 | SIM_DESC sd; | |
8bae0a0c | 3062 | int rm; |
e871dd18 | 3063 | uword64 op; |
8bae0a0c JSC |
3064 | FP_formats from; |
3065 | FP_formats to; | |
3066 | { | |
50a2a691 | 3067 | uword64 result = 0; |
8bae0a0c JSC |
3068 | |
3069 | #ifdef DEBUG | |
53b9417e | 3070 | printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC)); |
8bae0a0c JSC |
3071 | #endif /* DEBUG */ |
3072 | ||
3073 | /* The value "op" is converted to the destination format, rounding | |
3074 | using mode "rm". When the destination is a fixed-point format, | |
3075 | then a source value of Infinity, NaN or one which would round to | |
3076 | an integer outside the fixed point range then an IEEE Invalid | |
3077 | Operation condition is raised. */ | |
3078 | switch (to) { | |
3079 | case fmt_single: | |
3080 | { | |
3081 | float tmp; | |
3082 | switch (from) { | |
3083 | case fmt_double: | |
3084 | tmp = (float)(*(double *)&op); | |
3085 | break; | |
3086 | ||
3087 | case fmt_word: | |
3088 | tmp = (float)((int)(op & 0xFFFFFFFF)); | |
3089 | break; | |
3090 | ||
3091 | case fmt_long: | |
e3d12c65 | 3092 | tmp = (float)((word64)op); |
8bae0a0c | 3093 | break; |
50a2a691 AC |
3094 | default: |
3095 | fprintf (stderr, "Bad switch\n"); | |
3096 | abort (); | |
8bae0a0c JSC |
3097 | } |
3098 | ||
458e1f58 ILT |
3099 | #if 0 |
3100 | /* FIXME: This code is incorrect. The rounding mode does not | |
3101 | round to integral values; it rounds to the nearest | |
3102 | representable value in the format. */ | |
3103 | ||
8bae0a0c JSC |
3104 | switch (rm) { |
3105 | case FP_RM_NEAREST: | |
e871dd18 JSC |
3106 | /* Round result to nearest representable value. When two |
3107 | representable values are equally near, round to the value | |
3108 | that has a least significant bit of zero (i.e. is even). */ | |
4fa134be | 3109 | #ifdef HAVE_ANINT |
e871dd18 | 3110 | tmp = (float)anint((double)tmp); |
d0757082 JSC |
3111 | #else |
3112 | /* TODO: Provide round-to-nearest */ | |
3113 | #endif | |
8bae0a0c JSC |
3114 | break; |
3115 | ||
3116 | case FP_RM_TOZERO: | |
e871dd18 JSC |
3117 | /* Round result to the value closest to, and not greater in |
3118 | magnitude than, the result. */ | |
4fa134be | 3119 | #ifdef HAVE_AINT |
e871dd18 | 3120 | tmp = (float)aint((double)tmp); |
d0757082 JSC |
3121 | #else |
3122 | /* TODO: Provide round-to-zero */ | |
3123 | #endif | |
8bae0a0c JSC |
3124 | break; |
3125 | ||
3126 | case FP_RM_TOPINF: | |
e871dd18 JSC |
3127 | /* Round result to the value closest to, and not less than, |
3128 | the result. */ | |
3129 | tmp = (float)ceil((double)tmp); | |
8bae0a0c JSC |
3130 | break; |
3131 | ||
3132 | case FP_RM_TOMINF: | |
e871dd18 JSC |
3133 | /* Round result to the value closest to, and not greater than, |
3134 | the result. */ | |
3135 | tmp = (float)floor((double)tmp); | |
8bae0a0c JSC |
3136 | break; |
3137 | } | |
458e1f58 ILT |
3138 | #endif /* 0 */ |
3139 | ||
e871dd18 | 3140 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
3141 | } |
3142 | break; | |
3143 | ||
3144 | case fmt_double: | |
3145 | { | |
3146 | double tmp; | |
f24b7b69 | 3147 | word64 xxx; |
8bae0a0c JSC |
3148 | |
3149 | switch (from) { | |
3150 | case fmt_single: | |
3151 | { | |
3152 | unsigned int wop = (unsigned int)op; | |
3153 | tmp = (double)(*(float *)&wop); | |
3154 | } | |
3155 | break; | |
3156 | ||
3157 | case fmt_word: | |
f24b7b69 | 3158 | xxx = SIGNEXTEND((op & 0xFFFFFFFF),32); |
e3d12c65 | 3159 | tmp = (double)xxx; |
8bae0a0c JSC |
3160 | break; |
3161 | ||
3162 | case fmt_long: | |
e871dd18 | 3163 | tmp = (double)((word64)op); |
8bae0a0c | 3164 | break; |
50a2a691 AC |
3165 | |
3166 | default: | |
3167 | fprintf (stderr, "Bad switch\n"); | |
3168 | abort (); | |
8bae0a0c | 3169 | } |
e871dd18 | 3170 | |
458e1f58 ILT |
3171 | #if 0 |
3172 | /* FIXME: This code is incorrect. The rounding mode does not | |
3173 | round to integral values; it rounds to the nearest | |
3174 | representable value in the format. */ | |
3175 | ||
8bae0a0c JSC |
3176 | switch (rm) { |
3177 | case FP_RM_NEAREST: | |
4fa134be | 3178 | #ifdef HAVE_ANINT |
e871dd18 | 3179 | tmp = anint(*(double *)&tmp); |
d0757082 JSC |
3180 | #else |
3181 | /* TODO: Provide round-to-nearest */ | |
3182 | #endif | |
8bae0a0c JSC |
3183 | break; |
3184 | ||
3185 | case FP_RM_TOZERO: | |
4fa134be | 3186 | #ifdef HAVE_AINT |
e871dd18 | 3187 | tmp = aint(*(double *)&tmp); |
d0757082 JSC |
3188 | #else |
3189 | /* TODO: Provide round-to-zero */ | |
3190 | #endif | |
8bae0a0c JSC |
3191 | break; |
3192 | ||
3193 | case FP_RM_TOPINF: | |
3194 | tmp = ceil(*(double *)&tmp); | |
3195 | break; | |
3196 | ||
3197 | case FP_RM_TOMINF: | |
3198 | tmp = floor(*(double *)&tmp); | |
3199 | break; | |
3200 | } | |
458e1f58 ILT |
3201 | #endif /* 0 */ |
3202 | ||
e871dd18 | 3203 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
3204 | } |
3205 | break; | |
3206 | ||
3207 | case fmt_word: | |
3208 | case fmt_long: | |
3209 | if (Infinity(op,from) || NaN(op,from) || (1 == 0/*TODO: check range */)) { | |
3210 | printf("DBG: TODO: update FCSR\n"); | |
18c64df6 | 3211 | SignalExceptionFPE (); |
8bae0a0c JSC |
3212 | } else { |
3213 | if (to == fmt_word) { | |
50a2a691 | 3214 | int tmp = 0; |
8bae0a0c JSC |
3215 | switch (from) { |
3216 | case fmt_single: | |
3217 | { | |
3218 | unsigned int wop = (unsigned int)op; | |
e3d12c65 | 3219 | tmp = (int)*((float *)&wop); |
8bae0a0c JSC |
3220 | } |
3221 | break; | |
3222 | case fmt_double: | |
e3d12c65 | 3223 | tmp = (int)*((double *)&op); |
8bae0a0c | 3224 | #ifdef DEBUG |
53b9417e | 3225 | printf("DBG: from double %.30f (0x%s) to word: 0x%08X\n",*((double *)&op),pr_addr(op),tmp); |
8bae0a0c JSC |
3226 | #endif /* DEBUG */ |
3227 | break; | |
50a2a691 AC |
3228 | default: |
3229 | fprintf (stderr, "Bad switch\n"); | |
3230 | abort (); | |
8bae0a0c | 3231 | } |
e871dd18 | 3232 | result = (uword64)tmp; |
8bae0a0c | 3233 | } else { /* fmt_long */ |
50a2a691 | 3234 | word64 tmp = 0; |
8bae0a0c JSC |
3235 | switch (from) { |
3236 | case fmt_single: | |
3237 | { | |
3238 | unsigned int wop = (unsigned int)op; | |
e3d12c65 | 3239 | tmp = (word64)*((float *)&wop); |
8bae0a0c JSC |
3240 | } |
3241 | break; | |
3242 | case fmt_double: | |
e3d12c65 | 3243 | tmp = (word64)*((double *)&op); |
8bae0a0c | 3244 | break; |
50a2a691 AC |
3245 | default: |
3246 | fprintf (stderr, "Bad switch\n"); | |
3247 | abort (); | |
8bae0a0c | 3248 | } |
e3d12c65 | 3249 | result = (uword64)tmp; |
8bae0a0c JSC |
3250 | } |
3251 | } | |
3252 | break; | |
50a2a691 AC |
3253 | default: |
3254 | fprintf (stderr, "Bad switch\n"); | |
3255 | abort (); | |
8bae0a0c JSC |
3256 | } |
3257 | ||
3258 | #ifdef DEBUG | |
53b9417e | 3259 | printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result),DOFMT(to)); |
8bae0a0c JSC |
3260 | #endif /* DEBUG */ |
3261 | ||
3262 | return(result); | |
3263 | } | |
3264 | #endif /* HASFPU */ | |
3265 | ||
3266 | /*-- co-processor support routines ------------------------------------------*/ | |
3267 | ||
2f2e6c5d | 3268 | static int UNUSED |
8bae0a0c JSC |
3269 | CoProcPresent(coproc_number) |
3270 | unsigned int coproc_number; | |
3271 | { | |
3272 | /* Return TRUE if simulator provides a model for the given co-processor number */ | |
3273 | return(0); | |
3274 | } | |
3275 | ||
18c64df6 AC |
3276 | void |
3277 | cop_lw(sd,coproc_num,coproc_reg,memword) | |
3278 | SIM_DESC sd; | |
8bae0a0c JSC |
3279 | int coproc_num, coproc_reg; |
3280 | unsigned int memword; | |
3281 | { | |
3282 | switch (coproc_num) { | |
3283 | #if defined(HASFPU) | |
3284 | case 1: | |
3285 | #ifdef DEBUG | |
53b9417e | 3286 | printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword)); |
8bae0a0c | 3287 | #endif |
da0bce9c | 3288 | StoreFPR(coproc_reg,fmt_word,(uword64)memword); |
0c2c5f61 | 3289 | FPR_STATE[coproc_reg] = fmt_uninterpreted; |
8bae0a0c JSC |
3290 | break; |
3291 | #endif /* HASFPU */ | |
3292 | ||
3293 | default: | |
f24b7b69 | 3294 | #if 0 /* this should be controlled by a configuration option */ |
18c64df6 | 3295 | sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(IPC)); |
f24b7b69 | 3296 | #endif |
8bae0a0c JSC |
3297 | break; |
3298 | } | |
3299 | ||
3300 | return; | |
3301 | } | |
3302 | ||
18c64df6 AC |
3303 | void |
3304 | cop_ld(sd,coproc_num,coproc_reg,memword) | |
3305 | SIM_DESC sd; | |
8bae0a0c | 3306 | int coproc_num, coproc_reg; |
e871dd18 | 3307 | uword64 memword; |
8bae0a0c JSC |
3308 | { |
3309 | switch (coproc_num) { | |
3310 | #if defined(HASFPU) | |
3311 | case 1: | |
3312 | StoreFPR(coproc_reg,fmt_uninterpreted,memword); | |
3313 | break; | |
3314 | #endif /* HASFPU */ | |
3315 | ||
3316 | default: | |
f24b7b69 | 3317 | #if 0 /* this message should be controlled by a configuration option */ |
18c64df6 | 3318 | sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(IPC)); |
f24b7b69 | 3319 | #endif |
8bae0a0c JSC |
3320 | break; |
3321 | } | |
3322 | ||
3323 | return; | |
3324 | } | |
3325 | ||
18c64df6 AC |
3326 | unsigned int |
3327 | cop_sw(sd,coproc_num,coproc_reg) | |
3328 | SIM_DESC sd; | |
8bae0a0c JSC |
3329 | int coproc_num, coproc_reg; |
3330 | { | |
3331 | unsigned int value = 0; | |
da0bce9c | 3332 | |
8bae0a0c JSC |
3333 | switch (coproc_num) { |
3334 | #if defined(HASFPU) | |
3335 | case 1: | |
3336 | #if 1 | |
9cb8397f GRK |
3337 | { |
3338 | FP_formats hold; | |
0c2c5f61 AC |
3339 | hold = FPR_STATE[coproc_reg]; |
3340 | FPR_STATE[coproc_reg] = fmt_word; | |
9cb8397f | 3341 | value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted); |
0c2c5f61 | 3342 | FPR_STATE[coproc_reg] = hold; |
9cb8397f | 3343 | } |
8bae0a0c JSC |
3344 | #else |
3345 | #if 1 | |
0c2c5f61 | 3346 | value = (unsigned int)ValueFPR(coproc_reg,FPR_STATE[coproc_reg]); |
8bae0a0c JSC |
3347 | #else |
3348 | #ifdef DEBUG | |
0c2c5f61 | 3349 | printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE[coproc_reg])); |
8bae0a0c JSC |
3350 | #endif /* DEBUG */ |
3351 | value = (unsigned int)ValueFPR(coproc_reg,fmt_single); | |
3352 | #endif | |
3353 | #endif | |
3354 | break; | |
3355 | #endif /* HASFPU */ | |
3356 | ||
3357 | default: | |
f24b7b69 | 3358 | #if 0 /* should be controlled by configuration option */ |
18c64df6 | 3359 | sim_io_printf(sd,"COP_SW(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(IPC)); |
f24b7b69 | 3360 | #endif |
8bae0a0c JSC |
3361 | break; |
3362 | } | |
3363 | ||
3364 | return(value); | |
3365 | } | |
3366 | ||
18c64df6 AC |
3367 | uword64 |
3368 | cop_sd(sd,coproc_num,coproc_reg) | |
3369 | SIM_DESC sd; | |
8bae0a0c JSC |
3370 | int coproc_num, coproc_reg; |
3371 | { | |
e871dd18 | 3372 | uword64 value = 0; |
8bae0a0c JSC |
3373 | switch (coproc_num) { |
3374 | #if defined(HASFPU) | |
3375 | case 1: | |
3376 | #if 1 | |
3377 | value = ValueFPR(coproc_reg,fmt_uninterpreted); | |
3378 | #else | |
3379 | #if 1 | |
0c2c5f61 | 3380 | value = ValueFPR(coproc_reg,FPR_STATE[coproc_reg]); |
8bae0a0c JSC |
3381 | #else |
3382 | #ifdef DEBUG | |
0c2c5f61 | 3383 | printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE[coproc_reg])); |
8bae0a0c JSC |
3384 | #endif /* DEBUG */ |
3385 | value = ValueFPR(coproc_reg,fmt_double); | |
3386 | #endif | |
3387 | #endif | |
3388 | break; | |
3389 | #endif /* HASFPU */ | |
3390 | ||
3391 | default: | |
f24b7b69 | 3392 | #if 0 /* should be controlled by configuration option */ |
18c64df6 | 3393 | sim_io_printf(sd,"COP_SD(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(IPC)); |
f24b7b69 | 3394 | #endif |
8bae0a0c JSC |
3395 | break; |
3396 | } | |
3397 | ||
3398 | return(value); | |
3399 | } | |
3400 | ||
ea985d24 | 3401 | void |
18c64df6 AC |
3402 | decode_coproc(sd,instruction) |
3403 | SIM_DESC sd; | |
8bae0a0c JSC |
3404 | unsigned int instruction; |
3405 | { | |
3406 | int coprocnum = ((instruction >> 26) & 3); | |
3407 | ||
56e7c849 AC |
3408 | switch (coprocnum) |
3409 | { | |
8bae0a0c JSC |
3410 | case 0: /* standard CPU control and cache registers */ |
3411 | { | |
8bae0a0c JSC |
3412 | int code = ((instruction >> 21) & 0x1F); |
3413 | /* R4000 Users Manual (second edition) lists the following CP0 | |
3414 | instructions: | |
56e7c849 AC |
3415 | DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000) |
3416 | DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000) | |
3417 | MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000) | |
3418 | MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000) | |
3419 | TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001) | |
3420 | TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010) | |
3421 | TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110) | |
3422 | TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000) | |
3423 | CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) | |
3424 | ERET Exception return (VR4100 = 01000010000000000000000000011000) | |
3425 | */ | |
3426 | if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) | |
3427 | { | |
3428 | int rt = ((instruction >> 16) & 0x1F); | |
3429 | int rd = ((instruction >> 11) & 0x1F); | |
3430 | ||
3431 | switch (rd) /* NOTEs: Standard CP0 registers */ | |
3432 | { | |
3433 | /* 0 = Index R4000 VR4100 VR4300 */ | |
3434 | /* 1 = Random R4000 VR4100 VR4300 */ | |
3435 | /* 2 = EntryLo0 R4000 VR4100 VR4300 */ | |
3436 | /* 3 = EntryLo1 R4000 VR4100 VR4300 */ | |
3437 | /* 4 = Context R4000 VR4100 VR4300 */ | |
3438 | /* 5 = PageMask R4000 VR4100 VR4300 */ | |
3439 | /* 6 = Wired R4000 VR4100 VR4300 */ | |
3440 | /* 8 = BadVAddr R4000 VR4100 VR4300 */ | |
3441 | /* 9 = Count R4000 VR4100 VR4300 */ | |
3442 | /* 10 = EntryHi R4000 VR4100 VR4300 */ | |
3443 | /* 11 = Compare R4000 VR4100 VR4300 */ | |
3444 | /* 12 = SR R4000 VR4100 VR4300 */ | |
3445 | case 12: | |
3446 | if (code == 0x00) | |
3447 | GPR[rt] = SR; | |
3448 | else | |
3449 | SR = GPR[rt]; | |
3450 | break; | |
3451 | /* 13 = Cause R4000 VR4100 VR4300 */ | |
05d1322f JL |
3452 | case 13: |
3453 | if (code == 0x00) | |
3454 | GPR[rt] = CAUSE; | |
3455 | else | |
3456 | CAUSE = GPR[rt]; | |
3457 | break; | |
56e7c849 AC |
3458 | /* 14 = EPC R4000 VR4100 VR4300 */ |
3459 | /* 15 = PRId R4000 VR4100 VR4300 */ | |
6eedf3f4 MA |
3460 | #ifdef SUBTARGET_R3900 |
3461 | /* 16 = Debug */ | |
3462 | case 16: | |
3463 | if (code == 0x00) | |
3464 | GPR[rt] = Debug; | |
3465 | else | |
3466 | Debug = GPR[rt]; | |
3467 | break; | |
3468 | #else | |
56e7c849 | 3469 | /* 16 = Config R4000 VR4100 VR4300 */ |
6eedf3f4 MA |
3470 | #endif |
3471 | #ifdef SUBTARGET_R3900 | |
3472 | /* 17 = Debug */ | |
3473 | case 17: | |
3474 | if (code == 0x00) | |
3475 | GPR[rt] = DEPC; | |
3476 | else | |
3477 | DEPC = GPR[rt]; | |
3478 | break; | |
3479 | #else | |
56e7c849 | 3480 | /* 17 = LLAddr R4000 VR4100 VR4300 */ |
6eedf3f4 | 3481 | #endif |
56e7c849 AC |
3482 | /* 18 = WatchLo R4000 VR4100 VR4300 */ |
3483 | /* 19 = WatchHi R4000 VR4100 VR4300 */ | |
3484 | /* 20 = XContext R4000 VR4100 VR4300 */ | |
3485 | /* 26 = PErr or ECC R4000 VR4100 VR4300 */ | |
3486 | /* 27 = CacheErr R4000 VR4100 */ | |
3487 | /* 28 = TagLo R4000 VR4100 VR4300 */ | |
3488 | /* 29 = TagHi R4000 VR4100 VR4300 */ | |
3489 | /* 30 = ErrorEPC R4000 VR4100 VR4300 */ | |
3490 | GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */ | |
3491 | /* CPR[0,rd] = GPR[rt]; */ | |
3492 | default: | |
3493 | if (code == 0x00) | |
18c64df6 | 3494 | sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 | 3495 | else |
18c64df6 | 3496 | sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 AC |
3497 | } |
3498 | } | |
3499 | else if (code == 0x10 && (instruction & 0x3f) == 0x18) | |
3500 | { | |
3501 | /* ERET */ | |
3502 | if (SR & status_ERL) | |
3503 | { | |
3504 | /* Oops, not yet available */ | |
18c64df6 | 3505 | sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet"); |
56e7c849 AC |
3506 | PC = EPC; |
3507 | SR &= ~status_ERL; | |
3508 | } | |
3509 | else | |
3510 | { | |
3511 | PC = EPC; | |
3512 | SR &= ~status_EXL; | |
3513 | } | |
3514 | } | |
6eedf3f4 MA |
3515 | else if (code == 0x10 && (instruction & 0x3f) == 0x10) |
3516 | { | |
3517 | /* RFE */ | |
3518 | } | |
3519 | else if (code == 0x10 && (instruction & 0x3f) == 0x1F) | |
3520 | { | |
3521 | /* DERET */ | |
3522 | Debug &= ~Debug_DM; | |
3523 | DELAYSLOT(); | |
3524 | DSPC = DEPC; | |
3525 | } | |
56e7c849 | 3526 | else |
18c64df6 | 3527 | sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction,pr_addr(IPC)); |
e871dd18 | 3528 | /* TODO: When executing an ERET or RFE instruction we should |
8bae0a0c JSC |
3529 | clear LLBIT, to ensure that any out-standing atomic |
3530 | read/modify/write sequence fails. */ | |
3531 | } | |
56e7c849 AC |
3532 | break; |
3533 | ||
8bae0a0c | 3534 | case 2: /* undefined co-processor */ |
18c64df6 | 3535 | sim_io_eprintf(sd,"COP2 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction,pr_addr(IPC)); |
8bae0a0c | 3536 | break; |
56e7c849 | 3537 | |
8bae0a0c JSC |
3538 | case 1: /* should not occur (FPU co-processor) */ |
3539 | case 3: /* should not occur (FPU co-processor) */ | |
3540 | SignalException(ReservedInstruction,instruction); | |
3541 | break; | |
56e7c849 AC |
3542 | } |
3543 | ||
8bae0a0c JSC |
3544 | return; |
3545 | } | |
3546 | ||
3547 | /*-- instruction simulation -------------------------------------------------*/ | |
3548 | ||
2e61a3ad AC |
3549 | void |
3550 | sim_engine_run (sd, next_cpu_nr, siggnal) | |
3551 | SIM_DESC sd; | |
3552 | int next_cpu_nr; /* ignore */ | |
3553 | int siggnal; /* ignore */ | |
8bae0a0c | 3554 | { |
50a2a691 | 3555 | #if !defined(FASTSIM) |
8bae0a0c | 3556 | unsigned int pipeline_count = 1; |
50a2a691 | 3557 | #endif |
8bae0a0c JSC |
3558 | |
3559 | #ifdef DEBUG | |
50a2a691 | 3560 | if (STATE_MEMORY (sd) == NULL) { |
8bae0a0c JSC |
3561 | printf("DBG: simulate() entered with no memory\n"); |
3562 | exit(1); | |
3563 | } | |
3564 | #endif /* DEBUG */ | |
3565 | ||
3566 | #if 0 /* Disabled to check that everything works OK */ | |
3567 | /* The VR4300 seems to sign-extend the PC on its first | |
3568 | access. However, this may just be because it is currently | |
3569 | configured in 32bit mode. However... */ | |
3570 | PC = SIGNEXTEND(PC,32); | |
3571 | #endif | |
3572 | ||
3573 | /* main controlling loop */ | |
2e61a3ad | 3574 | while (1) { |
8bae0a0c | 3575 | /* Fetch the next instruction from the simulator memory: */ |
e871dd18 JSC |
3576 | uword64 vaddr = (uword64)PC; |
3577 | uword64 paddr; | |
8bae0a0c | 3578 | int cca; |
53b9417e | 3579 | unsigned int instruction; /* uword64? what's this used for? FIXME! */ |
8bae0a0c JSC |
3580 | |
3581 | #ifdef DEBUG | |
3582 | { | |
3583 | printf("DBG: state = 0x%08X :",state); | |
d3d2a9f7 | 3584 | #if 0 |
8bae0a0c JSC |
3585 | if (state & simSTOP) printf(" simSTOP"); |
3586 | if (state & simSTEP) printf(" simSTEP"); | |
d3d2a9f7 | 3587 | #endif |
8bae0a0c JSC |
3588 | if (state & simHALTEX) printf(" simHALTEX"); |
3589 | if (state & simHALTIN) printf(" simHALTIN"); | |
d3d2a9f7 | 3590 | #if 0 |
8bae0a0c | 3591 | if (state & simBE) printf(" simBE"); |
d3d2a9f7 | 3592 | #endif |
53b9417e | 3593 | printf("\n"); |
8bae0a0c JSC |
3594 | } |
3595 | #endif /* DEBUG */ | |
3596 | ||
0c2c5f61 | 3597 | DSSTATE = (STATE & simDELAYSLOT); |
8bae0a0c JSC |
3598 | #ifdef DEBUG |
3599 | if (dsstate) | |
18c64df6 | 3600 | sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3601 | #endif /* DEBUG */ |
3602 | ||
6429b296 JW |
3603 | if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { |
3604 | if ((vaddr & 1) == 0) { | |
3605 | /* Copy the action of the LW instruction */ | |
3606 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
3607 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
3608 | uword64 value; | |
3609 | unsigned int byte; | |
3610 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
53b9417e | 3611 | LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL); |
6429b296 JW |
3612 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); |
3613 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
3614 | } else { | |
3615 | /* Copy the action of the LH instruction */ | |
3616 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0); | |
3617 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0); | |
3618 | uword64 value; | |
3619 | unsigned int byte; | |
3620 | paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK) | |
3621 | | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1))); | |
53b9417e | 3622 | LoadMemory(&value,NULL,cca, AccessLength_HALFWORD, |
6429b296 JW |
3623 | paddr & ~ (uword64) 1, |
3624 | vaddr, isINSTRUCTION, isREAL); | |
3625 | byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1)); | |
3626 | instruction = ((value >> (8 * byte)) & 0xFFFF); | |
3627 | } | |
8bae0a0c | 3628 | } else { |
53b9417e | 3629 | fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC)); |
8bae0a0c JSC |
3630 | exit(1); |
3631 | } | |
3632 | ||
3633 | #ifdef DEBUG | |
18c64df6 | 3634 | sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC)); |
8bae0a0c JSC |
3635 | #endif /* DEBUG */ |
3636 | ||
8bae0a0c JSC |
3637 | IPC = PC; /* copy PC for this instruction */ |
3638 | /* This is required by exception processing, to ensure that we can | |
3639 | cope with exceptions in the delay slots of branches that may | |
3640 | already have changed the PC. */ | |
6429b296 JW |
3641 | if ((vaddr & 1) == 0) |
3642 | PC += 4; /* increment ready for the next fetch */ | |
3643 | else | |
3644 | PC += 2; | |
8bae0a0c JSC |
3645 | /* NOTE: If we perform a delay slot change to the PC, this |
3646 | increment is not requuired. However, it would make the | |
3647 | simulator more complicated to try and avoid this small hit. */ | |
3648 | ||
3649 | /* Currently this code provides a simple model. For more | |
3650 | complicated models we could perform exception status checks at | |
3651 | this point, and set the simSTOP state as required. This could | |
3652 | also include processing any hardware interrupts raised by any | |
3653 | I/O model attached to the simulator context. | |
3654 | ||
3655 | Support for "asynchronous" I/O events within the simulated world | |
3656 | could be providing by managing a counter, and calling a I/O | |
3657 | specific handler when a particular threshold is reached. On most | |
3658 | architectures a decrement and check for zero operation is | |
3659 | usually quicker than an increment and compare. However, the | |
3660 | process of managing a known value decrement to zero, is higher | |
3661 | than the cost of using an explicit value UINT_MAX into the | |
3662 | future. Which system is used will depend on how complicated the | |
3663 | I/O model is, and how much it is likely to affect the simulator | |
3664 | bandwidth. | |
3665 | ||
3666 | If events need to be scheduled further in the future than | |
3667 | UINT_MAX event ticks, then the I/O model should just provide its | |
3668 | own counter, triggered from the event system. */ | |
3669 | ||
3670 | /* MIPS pipeline ticks. To allow for future support where the | |
3671 | pipeline hit of individual instructions is known, this control | |
3672 | loop manages a "pipeline_count" variable. It is initialised to | |
3673 | 1 (one), and will only be changed by the simulator engine when | |
3674 | executing an instruction. If the engine does not have access to | |
3675 | pipeline cycle count information then all instructions will be | |
3676 | treated as using a single cycle. NOTE: A standard system is not | |
3677 | provided by the default simulator because different MIPS | |
3678 | architectures have different cycle counts for the same | |
50a2a691 AC |
3679 | instructions. |
3680 | ||
3681 | [NOTE: pipeline_count has been replaced the event queue] */ | |
8bae0a0c JSC |
3682 | |
3683 | #if defined(HASFPU) | |
3684 | /* Set previous flag, depending on current: */ | |
0c2c5f61 AC |
3685 | if (STATE & simPCOC0) |
3686 | STATE |= simPCOC1; | |
8bae0a0c | 3687 | else |
0c2c5f61 | 3688 | STATE &= ~simPCOC1; |
8bae0a0c JSC |
3689 | /* and update the current value: */ |
3690 | if (GETFCC(0)) | |
0c2c5f61 | 3691 | STATE |= simPCOC0; |
8bae0a0c | 3692 | else |
0c2c5f61 | 3693 | STATE &= ~simPCOC0; |
8bae0a0c JSC |
3694 | #endif /* HASFPU */ |
3695 | ||
3696 | /* NOTE: For multi-context simulation environments the "instruction" | |
3697 | variable should be local to this routine. */ | |
3698 | ||
3699 | /* Shorthand accesses for engine. Note: If we wanted to use global | |
3700 | variables (and a single-threaded simulator engine), then we can | |
3701 | create the actual variables with these names. */ | |
3702 | ||
0c2c5f61 | 3703 | if (!(STATE & simSKIPNEXT)) { |
8bae0a0c | 3704 | /* Include the simulator engine */ |
284e759d | 3705 | #include "oengine.c" |
f24b7b69 | 3706 | #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT) |
8bae0a0c JSC |
3707 | #error "Mismatch between run-time simulator code and simulation engine" |
3708 | #endif | |
18c64df6 AC |
3709 | #if (WITH_TARGET_WORD_BITSIZE != GPRLEN) |
3710 | #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN" | |
3711 | #endif | |
3712 | #if (WITH_FLOATING_POINT == HARD_FLOATING_POINT != defined (HASFPU)) | |
3713 | #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU" | |
3714 | #endif | |
8bae0a0c JSC |
3715 | |
3716 | #if defined(WARN_LOHI) | |
3717 | /* Decrement the HI/LO validity ticks */ | |
3718 | if (HIACCESS > 0) | |
3719 | HIACCESS--; | |
3720 | if (LOACCESS > 0) | |
3721 | LOACCESS--; | |
53b9417e DE |
3722 | if (HI1ACCESS > 0) |
3723 | HI1ACCESS--; | |
3724 | if (LO1ACCESS > 0) | |
3725 | LO1ACCESS--; | |
8bae0a0c JSC |
3726 | #endif /* WARN_LOHI */ |
3727 | ||
8bae0a0c JSC |
3728 | /* For certain MIPS architectures, GPR[0] is hardwired to zero. We |
3729 | should check for it being changed. It is better doing it here, | |
3730 | than within the simulator, since it will help keep the simulator | |
3731 | small. */ | |
3732 | if (ZERO != 0) { | |
05d1322f | 3733 | #if defined(WARN_ZERO) |
18c64df6 | 3734 | sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(IPC)); |
05d1322f | 3735 | #endif /* WARN_ZERO */ |
8bae0a0c JSC |
3736 | ZERO = 0; /* reset back to zero before next instruction */ |
3737 | } | |
8bae0a0c | 3738 | } else /* simSKIPNEXT check */ |
0c2c5f61 | 3739 | STATE &= ~simSKIPNEXT; |
8bae0a0c JSC |
3740 | |
3741 | /* If the delay slot was active before the instruction is | |
3742 | executed, then update the PC to its new value: */ | |
0c2c5f61 | 3743 | if (DSSTATE) { |
8bae0a0c | 3744 | #ifdef DEBUG |
53b9417e | 3745 | printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3746 | #endif /* DEBUG */ |
3747 | PC = DSPC; | |
6eedf3f4 | 3748 | CANCELDELAYSLOT(); |
8bae0a0c JSC |
3749 | } |
3750 | ||
3751 | if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */ | |
3752 | /* Deal with pending register updates: */ | |
3753 | #ifdef DEBUG | |
3754 | printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total); | |
3755 | #endif /* DEBUG */ | |
0c2c5f61 | 3756 | if (PENDING_OUT != PENDING_IN) { |
8bae0a0c | 3757 | int loop; |
0c2c5f61 AC |
3758 | int index = PENDING_OUT; |
3759 | int total = PENDING_TOTAL; | |
3760 | if (PENDING_TOTAL == 0) { | |
8bae0a0c JSC |
3761 | fprintf(stderr,"FATAL: Mis-match on pending update pointers\n"); |
3762 | exit(1); | |
3763 | } | |
3764 | for (loop = 0; (loop < total); loop++) { | |
3765 | #ifdef DEBUG | |
3766 | printf("DBG: BEFORE index = %d, loop = %d\n",index,loop); | |
3767 | #endif /* DEBUG */ | |
0c2c5f61 | 3768 | if (PENDING_SLOT_REG[index] != (LAST_EMBED_REGNUM + 1)) { |
8bae0a0c | 3769 | #ifdef DEBUG |
0c2c5f61 | 3770 | printf("pending_slot_count[%d] = %d\n",index,PENDING_SLOT_COUNT[index]); |
8bae0a0c | 3771 | #endif /* DEBUG */ |
0c2c5f61 | 3772 | if (--(PENDING_SLOT_COUNT[index]) == 0) { |
8bae0a0c | 3773 | #ifdef DEBUG |
0c2c5f61 AC |
3774 | printf("pending_slot_reg[%d] = %d\n",index,PENDING_SLOT_REG[index]); |
3775 | printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(PENDING_SLOT_VALUE[index])); | |
8bae0a0c | 3776 | #endif /* DEBUG */ |
0c2c5f61 | 3777 | if (PENDING_SLOT_REG[index] == COCIDX) { |
9cb8397f | 3778 | #if defined(HASFPU) |
8bae0a0c | 3779 | SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0)); |
9cb8397f GRK |
3780 | #else |
3781 | ; | |
3782 | #endif | |
8bae0a0c | 3783 | } else { |
0c2c5f61 | 3784 | REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index]; |
8bae0a0c JSC |
3785 | #if defined(HASFPU) |
3786 | /* The only time we have PENDING updates to FPU | |
3787 | registers, is when performing binary transfers. This | |
3788 | means we should update the register type field. */ | |
0c2c5f61 AC |
3789 | if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32))) |
3790 | FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted; | |
8bae0a0c JSC |
3791 | #endif /* HASFPU */ |
3792 | } | |
3793 | #ifdef DEBUG | |
0c2c5f61 | 3794 | printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG[index],pr_addr(REGISTERS[PENDING_SLOT_REG[index]])); |
8bae0a0c | 3795 | #endif /* DEBUG */ |
0c2c5f61 AC |
3796 | PENDING_SLOT_REG[index] = (LAST_EMBED_REGNUM + 1); |
3797 | PENDING_OUT++; | |
3798 | if (PENDING_OUT == PSLOTS) | |
3799 | PENDING_OUT = 0; | |
3800 | PENDING_TOTAL--; | |
8bae0a0c JSC |
3801 | } |
3802 | } | |
3803 | #ifdef DEBUG | |
3804 | printf("DBG: AFTER index = %d, loop = %d\n",index,loop); | |
3805 | #endif /* DEBUG */ | |
3806 | index++; | |
3807 | if (index == PSLOTS) | |
3808 | index = 0; | |
3809 | } | |
3810 | } | |
3811 | #ifdef DEBUG | |
0c2c5f61 | 3812 | printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); |
8bae0a0c JSC |
3813 | #endif /* DEBUG */ |
3814 | } | |
3815 | ||
3816 | #if !defined(FASTSIM) | |
50a2a691 AC |
3817 | if (sim_events_tickn (sd, pipeline_count)) |
3818 | { | |
3819 | /* cpu->cia = cia; */ | |
3820 | sim_events_process (sd); | |
3821 | } | |
3822 | #else | |
2e61a3ad AC |
3823 | if (sim_events_tick (sd)) |
3824 | { | |
3825 | /* cpu->cia = cia; */ | |
3826 | sim_events_process (sd); | |
3827 | } | |
50a2a691 | 3828 | #endif /* FASTSIM */ |
8bae0a0c | 3829 | } |
8bae0a0c JSC |
3830 | } |
3831 | ||
53b9417e DE |
3832 | /* This code copied from gdb's utils.c. Would like to share this code, |
3833 | but don't know of a common place where both could get to it. */ | |
3834 | ||
3835 | /* Temporary storage using circular buffer */ | |
3836 | #define NUMCELLS 16 | |
3837 | #define CELLSIZE 32 | |
3838 | static char* | |
3839 | get_cell() | |
3840 | { | |
3841 | static char buf[NUMCELLS][CELLSIZE]; | |
3842 | static int cell=0; | |
3843 | if (++cell>=NUMCELLS) cell=0; | |
3844 | return buf[cell]; | |
3845 | } | |
3846 | ||
3847 | /* Print routines to handle variable size regs, etc */ | |
3848 | ||
3849 | /* Eliminate warning from compiler on 32-bit systems */ | |
3850 | static int thirty_two = 32; | |
3851 | ||
3852 | char* | |
3853 | pr_addr(addr) | |
3854 | SIM_ADDR addr; | |
3855 | { | |
3856 | char *paddr_str=get_cell(); | |
3857 | switch (sizeof(addr)) | |
3858 | { | |
3859 | case 8: | |
50a2a691 | 3860 | sprintf(paddr_str,"%08lx%08lx", |
53b9417e DE |
3861 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3862 | break; | |
3863 | case 4: | |
50a2a691 | 3864 | sprintf(paddr_str,"%08lx",(unsigned long)addr); |
53b9417e DE |
3865 | break; |
3866 | case 2: | |
3867 | sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff)); | |
3868 | break; | |
3869 | default: | |
3870 | sprintf(paddr_str,"%x",addr); | |
3871 | } | |
3872 | return paddr_str; | |
3873 | } | |
3874 | ||
87e43259 AC |
3875 | char* |
3876 | pr_uword64(addr) | |
3877 | uword64 addr; | |
3878 | { | |
3879 | char *paddr_str=get_cell(); | |
50a2a691 | 3880 | sprintf(paddr_str,"%08lx%08lx", |
87e43259 AC |
3881 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3882 | return paddr_str; | |
3883 | } | |
3884 | ||
3885 | ||
8bae0a0c JSC |
3886 | /*---------------------------------------------------------------------------*/ |
3887 | /*> EOF interp.c <*/ |