Commit | Line | Data |
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8bae0a0c JSC |
1 | /*> interp.c <*/ |
2 | /* Simulator for the MIPS architecture. | |
3 | ||
4 | This file is part of the MIPS sim | |
5 | ||
6 | THIS SOFTWARE IS NOT COPYRIGHTED | |
7 | ||
8 | Cygnus offers the following for use in the public domain. Cygnus | |
9 | makes no warranty with regard to the software or it's performance | |
10 | and the user accepts the software "AS IS" with all faults. | |
11 | ||
12 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
13 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
14 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
15 | ||
16 | $Revision$ | |
15232df4 | 17 | $Date$ |
8bae0a0c JSC |
18 | |
19 | NOTEs: | |
20 | ||
8bae0a0c JSC |
21 | The IDT monitor (found on the VR4300 board), seems to lie about |
22 | register contents. It seems to treat the registers as sign-extended | |
23 | 32-bit values. This cause *REAL* problems when single-stepping 64-bit | |
24 | code on the hardware. | |
25 | ||
26 | */ | |
27 | ||
e2f8ffb7 AC |
28 | /* The TRACE manifests enable the provision of extra features. If they |
29 | are not defined then a simpler (quicker) simulator is constructed | |
30 | without the required run-time checks, etc. */ | |
8bae0a0c JSC |
31 | #if 1 /* 0 to allow user build selection, 1 to force inclusion */ |
32 | #define TRACE (1) | |
8bae0a0c JSC |
33 | #endif |
34 | ||
2e61a3ad AC |
35 | #include "bfd.h" |
36 | #include "sim-main.h" | |
37 | #include "sim-utils.h" | |
38 | #include "sim-options.h" | |
50a2a691 | 39 | #include "sim-assert.h" |
2e61a3ad | 40 | |
15232df4 FCE |
41 | /* start-sanitize-sky */ |
42 | #ifdef TARGET_SKY | |
43 | #include "sky-vu.h" | |
44 | #include "sky-vpe.h" | |
45 | #include "sky-libvpe.h" | |
64ed8b6a | 46 | #include "sky-pke.h" |
ebcfd86a | 47 | #include "idecode.h" |
46399a00 FCE |
48 | #include "support.h" |
49 | #undef SD | |
15232df4 FCE |
50 | #endif |
51 | /* end-sanitize-sky */ | |
52 | ||
4fa134be ILT |
53 | #include "config.h" |
54 | ||
8bae0a0c JSC |
55 | #include <stdio.h> |
56 | #include <stdarg.h> | |
57 | #include <ansidecl.h> | |
8bae0a0c JSC |
58 | #include <ctype.h> |
59 | #include <limits.h> | |
60 | #include <math.h> | |
4fa134be ILT |
61 | #ifdef HAVE_STDLIB_H |
62 | #include <stdlib.h> | |
63 | #endif | |
64 | #ifdef HAVE_STRING_H | |
65 | #include <string.h> | |
66 | #else | |
67 | #ifdef HAVE_STRINGS_H | |
68 | #include <strings.h> | |
69 | #endif | |
70 | #endif | |
8bae0a0c JSC |
71 | |
72 | #include "getopt.h" | |
73 | #include "libiberty.h" | |
9d52bcb7 | 74 | #include "bfd.h" |
8bae0a0c | 75 | #include "callback.h" /* GDB simulator callback interface */ |
e3d12c65 | 76 | #include "remote-sim.h" /* GDB simulator interface */ |
8bae0a0c | 77 | |
f24b7b69 JSC |
78 | #include "sysdep.h" |
79 | ||
53b9417e DE |
80 | #ifndef PARAMS |
81 | #define PARAMS(x) | |
82 | #endif | |
83 | ||
84 | char* pr_addr PARAMS ((SIM_ADDR addr)); | |
87e43259 | 85 | char* pr_uword64 PARAMS ((uword64 addr)); |
53b9417e | 86 | |
f24b7b69 | 87 | |
8bae0a0c | 88 | /* Get the simulator engine description, without including the code: */ |
69d5a566 | 89 | #if !(WITH_IGEN) |
8bae0a0c | 90 | #define SIM_MANIFESTS |
284e759d | 91 | #include "oengine.c" |
8bae0a0c | 92 | #undef SIM_MANIFESTS |
192ae475 | 93 | #endif |
8bae0a0c | 94 | |
01737f42 | 95 | /* Within interp.c we refer to the sim_state and sim_cpu directly. */ |
01737f42 | 96 | #define CPU cpu |
46399a00 | 97 | #define SD sd |
01737f42 | 98 | |
f7481d45 | 99 | |
8bae0a0c JSC |
100 | /* The following reserved instruction value is used when a simulator |
101 | trap is required. NOTE: Care must be taken, since this value may be | |
102 | used in later revisions of the MIPS ISA. */ | |
53b9417e DE |
103 | #define RSVD_INSTRUCTION (0x00000005) |
104 | #define RSVD_INSTRUCTION_MASK (0xFC00003F) | |
105 | ||
106 | #define RSVD_INSTRUCTION_ARG_SHIFT 6 | |
107 | #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF | |
108 | ||
8bae0a0c | 109 | |
6eedf3f4 MA |
110 | /* Bits in the Debug register */ |
111 | #define Debug_DBD 0x80000000 /* Debug Branch Delay */ | |
112 | #define Debug_DM 0x40000000 /* Debug Mode */ | |
113 | #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */ | |
114 | ||
115 | ||
116 | ||
8bae0a0c | 117 | |
8bae0a0c | 118 | |
e3d12c65 DE |
119 | /*---------------------------------------------------------------------------*/ |
120 | /*-- GDB simulator interface ------------------------------------------------*/ | |
121 | /*---------------------------------------------------------------------------*/ | |
122 | ||
0c2c5f61 | 123 | static void ColdReset PARAMS((SIM_DESC sd)); |
e3d12c65 DE |
124 | |
125 | /*---------------------------------------------------------------------------*/ | |
126 | ||
8bae0a0c | 127 | |
8bae0a0c | 128 | |
8bae0a0c | 129 | #define DELAYSLOT() {\ |
0c2c5f61 | 130 | if (STATE & simDELAYSLOT)\ |
18c64df6 | 131 | sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\ |
0c2c5f61 | 132 | STATE |= simDELAYSLOT;\ |
8bae0a0c JSC |
133 | } |
134 | ||
aaff8437 ILT |
135 | #define JALDELAYSLOT() {\ |
136 | DELAYSLOT ();\ | |
0c2c5f61 | 137 | STATE |= simJALDELAYSLOT;\ |
aaff8437 ILT |
138 | } |
139 | ||
8bae0a0c | 140 | #define NULLIFY() {\ |
0c2c5f61 AC |
141 | STATE &= ~simDELAYSLOT;\ |
142 | STATE |= simSKIPNEXT;\ | |
8bae0a0c JSC |
143 | } |
144 | ||
6eedf3f4 | 145 | #define CANCELDELAYSLOT() {\ |
0c2c5f61 AC |
146 | DSSTATE = 0;\ |
147 | STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\ | |
6eedf3f4 MA |
148 | } |
149 | ||
0c2c5f61 AC |
150 | #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0) |
151 | #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0) | |
aaff8437 | 152 | |
a9f7253f JSC |
153 | #define K0BASE (0x80000000) |
154 | #define K0SIZE (0x20000000) | |
155 | #define K1BASE (0xA0000000) | |
156 | #define K1SIZE (0x20000000) | |
525d929e AC |
157 | #define MONITOR_BASE (0xBFC00000) |
158 | #define MONITOR_SIZE (1 << 11) | |
159 | #define MEM_SIZE (2 << 20) | |
15232df4 | 160 | |
82ea14fd AC |
161 | /* start-sanitize-sky */ |
162 | #ifdef TARGET_SKY | |
163 | #undef MEM_SIZE | |
164 | #define MEM_SIZE (16 << 20) /* 16 MB */ | |
165 | #endif | |
166 | /* end-sanitize-sky */ | |
a9f7253f | 167 | |
8bae0a0c | 168 | #if defined(TRACE) |
4fa134be | 169 | static char *tracefile = "trace.din"; /* default filename for trace log */ |
030843d7 | 170 | FILE *tracefh = NULL; |
18c64df6 | 171 | static void open_trace PARAMS((SIM_DESC sd)); |
8bae0a0c JSC |
172 | #endif /* TRACE */ |
173 | ||
7c5d88c1 DE |
174 | static DECLARE_OPTION_HANDLER (mips_option_handler); |
175 | ||
1ff39ecb JL |
176 | enum { |
177 | OPTION_DINERO_TRACE = OPTION_START, | |
178 | OPTION_DINERO_FILE | |
179 | /* start-sanitize-sky */ | |
180 | ,OPTION_FLOAT_TYPE | |
181 | /* end-sanitize-sky */ | |
182 | }; | |
22de994d | 183 | |
50a2a691 | 184 | static SIM_RC |
7c5d88c1 | 185 | mips_option_handler (sd, cpu, opt, arg, is_command) |
50a2a691 | 186 | SIM_DESC sd; |
7c5d88c1 | 187 | sim_cpu *cpu; |
50a2a691 AC |
188 | int opt; |
189 | char *arg; | |
7c5d88c1 | 190 | int is_command; |
2e61a3ad | 191 | { |
01737f42 | 192 | int cpu_nr; |
50a2a691 AC |
193 | switch (opt) |
194 | { | |
22de994d | 195 | case OPTION_DINERO_TRACE: /* ??? */ |
50a2a691 AC |
196 | #if defined(TRACE) |
197 | /* Eventually the simTRACE flag could be treated as a toggle, to | |
198 | allow external control of the program points being traced | |
199 | (i.e. only from main onwards, excluding the run-time setup, | |
200 | etc.). */ | |
82ea14fd | 201 | for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++) |
50a2a691 | 202 | { |
01737f42 AC |
203 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); |
204 | if (arg == NULL) | |
205 | STATE |= simTRACE; | |
206 | else if (strcmp (arg, "yes") == 0) | |
207 | STATE |= simTRACE; | |
208 | else if (strcmp (arg, "no") == 0) | |
209 | STATE &= ~simTRACE; | |
210 | else if (strcmp (arg, "on") == 0) | |
211 | STATE |= simTRACE; | |
212 | else if (strcmp (arg, "off") == 0) | |
213 | STATE &= ~simTRACE; | |
214 | else | |
215 | { | |
1ff39ecb | 216 | fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg); |
01737f42 AC |
217 | return SIM_RC_FAIL; |
218 | } | |
50a2a691 AC |
219 | } |
220 | return SIM_RC_OK; | |
221 | #else /* !TRACE */ | |
222 | fprintf(stderr,"\ | |
22de994d | 223 | Simulator constructed without dinero tracing support (for performance).\n\ |
50a2a691 AC |
224 | Re-compile simulator with \"-DTRACE\" to enable this option.\n"); |
225 | return SIM_RC_FAIL; | |
226 | #endif /* !TRACE */ | |
227 | ||
22de994d | 228 | case OPTION_DINERO_FILE: |
50a2a691 AC |
229 | #if defined(TRACE) |
230 | if (optarg != NULL) { | |
231 | char *tmp; | |
232 | tmp = (char *)malloc(strlen(optarg) + 1); | |
233 | if (tmp == NULL) | |
234 | { | |
18c64df6 | 235 | sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg); |
50a2a691 AC |
236 | return SIM_RC_FAIL; |
237 | } | |
238 | else { | |
239 | strcpy(tmp,optarg); | |
240 | tracefile = tmp; | |
18c64df6 | 241 | sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile); |
50a2a691 AC |
242 | } |
243 | } | |
244 | #endif /* TRACE */ | |
245 | return SIM_RC_OK; | |
246 | ||
1ff39ecb JL |
247 | /* start-sanitize-sky */ |
248 | case OPTION_FLOAT_TYPE: | |
249 | /* Use host (fast) or target (accurate) floating point implementation. */ | |
250 | if (arg && strcmp (arg, "host") == 0) | |
251 | STATE_FP_TYPE_OPT (sd) &= ~STATE_FP_TYPE_OPT_TARGET; | |
252 | else if (arg && strcmp (arg, "target") == 0) | |
253 | STATE_FP_TYPE_OPT (sd) |= STATE_FP_TYPE_OPT_TARGET; | |
254 | else | |
255 | { | |
256 | fprintf (stderr, "Unrecognized float-type option `%s'\n", arg); | |
257 | return SIM_RC_FAIL; | |
258 | } | |
259 | return SIM_RC_OK; | |
260 | /* end-sanitize-sky */ | |
50a2a691 AC |
261 | } |
262 | ||
263 | return SIM_RC_OK; | |
2e61a3ad | 264 | } |
50a2a691 AC |
265 | |
266 | static const OPTION mips_options[] = | |
2e61a3ad | 267 | { |
22de994d AC |
268 | { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE}, |
269 | '\0', "on|off", "Enable dinero tracing", | |
50a2a691 | 270 | mips_option_handler }, |
22de994d AC |
271 | { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE}, |
272 | '\0', "FILE", "Write dinero trace to FILE", | |
50a2a691 | 273 | mips_option_handler }, |
1ff39ecb JL |
274 | /* start-sanitize-sky */ |
275 | { {"float-type", required_argument, NULL, OPTION_FLOAT_TYPE}, | |
276 | '\0', "host|target", "Use host (fast) or target (accurate) floating point", | |
277 | mips_option_handler }, | |
278 | /* end-sanitize-sky */ | |
50a2a691 AC |
279 | { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } |
280 | }; | |
281 | ||
282 | ||
56e7c849 AC |
283 | int interrupt_pending; |
284 | ||
50a2a691 AC |
285 | static void |
286 | interrupt_event (SIM_DESC sd, void *data) | |
2e61a3ad | 287 | { |
01737f42 | 288 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
56e7c849 AC |
289 | if (SR & status_IE) |
290 | { | |
291 | interrupt_pending = 0; | |
18c64df6 | 292 | SignalExceptionInterrupt (); |
56e7c849 AC |
293 | } |
294 | else if (!interrupt_pending) | |
295 | sim_events_schedule (sd, 1, interrupt_event, data); | |
2e61a3ad | 296 | } |
f7481d45 | 297 | |
f7481d45 | 298 | |
2c88fae9 IC |
299 | /*---------------------------------------------------------------------------*/ |
300 | /*-- Device registration hook -----------------------------------------------*/ | |
301 | /*---------------------------------------------------------------------------*/ | |
97908603 | 302 | static void device_init(SIM_DESC sd) { |
2c88fae9 IC |
303 | #ifdef DEVICE_INIT |
304 | extern void register_devices(SIM_DESC); | |
305 | register_devices(sd); | |
306 | #endif | |
307 | } | |
50a2a691 | 308 | |
8bae0a0c JSC |
309 | /*---------------------------------------------------------------------------*/ |
310 | /*-- GDB simulator interface ------------------------------------------------*/ | |
311 | /*---------------------------------------------------------------------------*/ | |
312 | ||
53b9417e | 313 | SIM_DESC |
247fccde | 314 | sim_open (kind, cb, abfd, argv) |
87e43259 | 315 | SIM_OPEN_KIND kind; |
50a2a691 | 316 | host_callback *cb; |
247fccde | 317 | struct _bfd *abfd; |
53b9417e | 318 | char **argv; |
8bae0a0c | 319 | { |
18c64df6 | 320 | SIM_DESC sd = sim_state_alloc (kind, cb); |
01737f42 | 321 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
2e61a3ad | 322 | |
525d929e AC |
323 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
324 | ||
50a2a691 AC |
325 | /* FIXME: watchpoints code shouldn't need this */ |
326 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
327 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
328 | STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event; | |
329 | ||
0c2c5f61 | 330 | STATE = 0; |
50a2a691 | 331 | |
2e61a3ad AC |
332 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
333 | return 0; | |
7c5d88c1 | 334 | sim_add_option_table (sd, NULL, mips_options); |
2e61a3ad | 335 | |
63be8feb AC |
336 | /* Allocate core managed memory */ |
337 | ||
338 | /* the monitor */ | |
339 | sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE); | |
340 | /* For compatibility with the old code - under this (at level one) | |
341 | are the kernel spaces K0 & K1. Both of these map to a single | |
342 | smaller sub region */ | |
a48e8c8d | 343 | sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */ |
fd909089 FCE |
344 | /* start-sanitize-sky */ |
345 | #ifndef TARGET_SKY | |
346 | /* end-sanitize-sky */ | |
63be8feb AC |
347 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x", |
348 | K1BASE, K0SIZE, | |
349 | MEM_SIZE, /* actual size */ | |
350 | K0BASE); | |
fd909089 FCE |
351 | /* start-sanitize-sky */ |
352 | #else | |
353 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x", | |
354 | K1BASE, K0SIZE, | |
355 | MEM_SIZE, /* actual size */ | |
356 | K0BASE, | |
357 | 0); /* add alias at 0x0000 */ | |
9ce23bf9 | 358 | #endif |
fd909089 | 359 | /* end-sanitize-sky */ |
63be8feb | 360 | |
2c88fae9 IC |
361 | device_init(sd); |
362 | ||
2e61a3ad AC |
363 | /* getopt will print the error message so we just have to exit if this fails. |
364 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
365 | print_filtered. */ | |
366 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
367 | { | |
368 | /* Uninstall the modules to avoid memory leaks, | |
369 | file descriptor leaks, etc. */ | |
370 | sim_module_uninstall (sd); | |
371 | return 0; | |
372 | } | |
2e61a3ad | 373 | |
fafce69a AC |
374 | /* check for/establish the a reference program image */ |
375 | if (sim_analyze_program (sd, | |
376 | (STATE_PROG_ARGV (sd) != NULL | |
377 | ? *STATE_PROG_ARGV (sd) | |
378 | : NULL), | |
379 | abfd) != SIM_RC_OK) | |
380 | { | |
381 | sim_module_uninstall (sd); | |
382 | return 0; | |
383 | } | |
384 | ||
247fccde AC |
385 | /* Configure/verify the target byte order and other runtime |
386 | configuration options */ | |
fafce69a | 387 | if (sim_config (sd) != SIM_RC_OK) |
247fccde AC |
388 | { |
389 | sim_module_uninstall (sd); | |
390 | return 0; | |
391 | } | |
392 | ||
2e61a3ad AC |
393 | if (sim_post_argv_init (sd) != SIM_RC_OK) |
394 | { | |
395 | /* Uninstall the modules to avoid memory leaks, | |
396 | file descriptor leaks, etc. */ | |
397 | sim_module_uninstall (sd); | |
398 | return 0; | |
399 | } | |
400 | ||
50a2a691 AC |
401 | /* verify assumptions the simulator made about the host type system. |
402 | This macro does not return if there is a problem */ | |
7ce8b917 AC |
403 | SIM_ASSERT (sizeof(int) == (4 * sizeof(char))); |
404 | SIM_ASSERT (sizeof(word64) == (8 * sizeof(char))); | |
8bae0a0c | 405 | |
8bae0a0c JSC |
406 | /* This is NASTY, in that we are assuming the size of specific |
407 | registers: */ | |
408 | { | |
409 | int rn; | |
a97f304b AC |
410 | for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) |
411 | { | |
412 | if (rn < 32) | |
413 | cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; | |
414 | else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR))) | |
415 | cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE; | |
416 | else if ((rn >= 33) && (rn <= 37)) | |
417 | cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; | |
a48e8c8d AC |
418 | else if ((rn == SRIDX) |
419 | || (rn == FCR0IDX) | |
420 | || (rn == FCR31IDX) | |
421 | || ((rn >= 72) && (rn <= 89))) | |
a97f304b AC |
422 | cpu->register_widths[rn] = 32; |
423 | else | |
424 | cpu->register_widths[rn] = 0; | |
425 | } | |
18c64df6 AC |
426 | /* start-sanitize-r5900 */ |
427 | ||
428 | /* set the 5900 "upper" registers to 64 bits */ | |
429 | for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++) | |
0c2c5f61 | 430 | cpu->register_widths[rn] = 64; |
18c64df6 | 431 | /* end-sanitize-r5900 */ |
97908603 RU |
432 | |
433 | /* start-sanitize-sky */ | |
434 | #ifdef TARGET_SKY | |
435 | /* Now the VU registers */ | |
a859684b | 436 | for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) { |
97908603 RU |
437 | cpu->register_widths[rn + NUM_R5900_REGS] = 16; |
438 | cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16; | |
97908603 RU |
439 | } |
440 | ||
a859684b | 441 | for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) { |
97908603 RU |
442 | cpu->register_widths[rn + NUM_R5900_REGS] = 32; |
443 | cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32; | |
97908603 | 444 | } |
64ed8b6a AC |
445 | |
446 | /* Finally the VIF registers */ | |
447 | for( rn = 2*NUM_VU_REGS; rn < 2*NUM_VU_REGS + 2*NUM_VIF_REGS; rn++ ) | |
448 | cpu->register_widths[rn + NUM_R5900_REGS] = 32; | |
97908603 RU |
449 | #endif |
450 | /* end-sanitize-sky */ | |
8bae0a0c JSC |
451 | } |
452 | ||
8bae0a0c | 453 | #if defined(TRACE) |
0c2c5f61 | 454 | if (STATE & simTRACE) |
18c64df6 | 455 | open_trace(sd); |
8bae0a0c JSC |
456 | #endif /* TRACE */ |
457 | ||
fafce69a AC |
458 | /* Write the monitor trap address handlers into the monitor (eeprom) |
459 | address space. This can only be done once the target endianness | |
460 | has been determined. */ | |
461 | { | |
462 | unsigned loop; | |
463 | /* Entry into the IDT monitor is via fixed address vectors, and | |
464 | not using machine instructions. To avoid clashing with use of | |
465 | the MIPS TRAP system, we place our own (simulator specific) | |
466 | "undefined" instructions into the relevant vector slots. */ | |
525d929e AC |
467 | for (loop = 0; (loop < MONITOR_SIZE); loop += 4) |
468 | { | |
469 | address_word vaddr = (MONITOR_BASE + loop); | |
470 | unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT)); | |
471 | H2T (insn); | |
472 | sim_write (sd, vaddr, (char *)&insn, sizeof (insn)); | |
473 | } | |
fafce69a AC |
474 | /* The PMON monitor uses the same address space, but rather than |
475 | branching into it the address of a routine is loaded. We can | |
476 | cheat for the moment, and direct the PMON routine to IDT style | |
477 | instructions within the monitor space. This relies on the IDT | |
478 | monitor not using the locations from 0xBFC00500 onwards as its | |
479 | entry points.*/ | |
480 | for (loop = 0; (loop < 24); loop++) | |
481 | { | |
525d929e AC |
482 | address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4)); |
483 | unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ | |
fafce69a AC |
484 | switch (loop) |
485 | { | |
486 | case 0: /* read */ | |
487 | value = 7; | |
488 | break; | |
fafce69a AC |
489 | case 1: /* write */ |
490 | value = 8; | |
491 | break; | |
fafce69a AC |
492 | case 2: /* open */ |
493 | value = 6; | |
494 | break; | |
fafce69a AC |
495 | case 3: /* close */ |
496 | value = 10; | |
497 | break; | |
fafce69a AC |
498 | case 5: /* printf */ |
499 | value = ((0x500 - 16) / 8); /* not an IDT reason code */ | |
500 | break; | |
fafce69a AC |
501 | case 8: /* cliexit */ |
502 | value = 17; | |
503 | break; | |
fafce69a AC |
504 | case 11: /* flush_cache */ |
505 | value = 28; | |
506 | break; | |
507 | } | |
525d929e AC |
508 | /* FIXME - should monitor_base be SIM_ADDR?? */ |
509 | value = ((unsigned int)MONITOR_BASE + (value * 8)); | |
510 | H2T (value); | |
511 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); | |
fafce69a AC |
512 | |
513 | /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */ | |
514 | vaddr -= 0x300; | |
525d929e | 515 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); |
fafce69a AC |
516 | } |
517 | } | |
518 | ||
2e61a3ad | 519 | return sd; |
8bae0a0c JSC |
520 | } |
521 | ||
6429b296 JW |
522 | #if defined(TRACE) |
523 | static void | |
18c64df6 AC |
524 | open_trace(sd) |
525 | SIM_DESC sd; | |
6429b296 JW |
526 | { |
527 | tracefh = fopen(tracefile,"wb+"); | |
528 | if (tracefh == NULL) | |
529 | { | |
18c64df6 | 530 | sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile); |
6429b296 JW |
531 | tracefh = stderr; |
532 | } | |
533 | } | |
534 | #endif /* TRACE */ | |
535 | ||
8bae0a0c | 536 | void |
53b9417e DE |
537 | sim_close (sd, quitting) |
538 | SIM_DESC sd; | |
8bae0a0c JSC |
539 | int quitting; |
540 | { | |
541 | #ifdef DEBUG | |
542 | printf("DBG: sim_close: entered (quitting = %d)\n",quitting); | |
543 | #endif | |
544 | ||
8bae0a0c JSC |
545 | /* "quitting" is non-zero if we cannot hang on errors */ |
546 | ||
547 | /* Ensure that any resources allocated through the callback | |
548 | mechanism are released: */ | |
18c64df6 | 549 | sim_io_shutdown (sd); |
8bae0a0c | 550 | |
8bae0a0c | 551 | #if defined(TRACE) |
e3d12c65 | 552 | if (tracefh != NULL && tracefh != stderr) |
8bae0a0c | 553 | fclose(tracefh); |
e3d12c65 | 554 | tracefh = NULL; |
8bae0a0c JSC |
555 | #endif /* TRACE */ |
556 | ||
01737f42 AC |
557 | /* FIXME - free SD */ |
558 | ||
8bae0a0c JSC |
559 | return; |
560 | } | |
561 | ||
8bae0a0c JSC |
562 | |
563 | int | |
53b9417e DE |
564 | sim_write (sd,addr,buffer,size) |
565 | SIM_DESC sd; | |
8bae0a0c JSC |
566 | SIM_ADDR addr; |
567 | unsigned char *buffer; | |
568 | int size; | |
569 | { | |
525d929e | 570 | int index; |
01737f42 | 571 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
8bae0a0c JSC |
572 | |
573 | /* Return the number of bytes written, or zero if error. */ | |
574 | #ifdef DEBUG | |
18c64df6 | 575 | sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
576 | #endif |
577 | ||
525d929e AC |
578 | /* We use raw read and write routines, since we do not want to count |
579 | the GDB memory accesses in our statistics gathering. */ | |
580 | ||
581 | for (index = 0; index < size; index++) | |
582 | { | |
583 | address_word vaddr = (address_word)addr + index; | |
584 | address_word paddr; | |
585 | int cca; | |
01737f42 | 586 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW)) |
525d929e | 587 | break; |
82ea14fd | 588 | if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1) |
63be8feb | 589 | break; |
8bae0a0c | 590 | } |
8bae0a0c | 591 | |
525d929e | 592 | return(index); |
8bae0a0c JSC |
593 | } |
594 | ||
595 | int | |
53b9417e DE |
596 | sim_read (sd,addr,buffer,size) |
597 | SIM_DESC sd; | |
8bae0a0c JSC |
598 | SIM_ADDR addr; |
599 | unsigned char *buffer; | |
600 | int size; | |
601 | { | |
602 | int index; | |
01737f42 | 603 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
8bae0a0c JSC |
604 | |
605 | /* Return the number of bytes read, or zero if error. */ | |
606 | #ifdef DEBUG | |
18c64df6 | 607 | sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
608 | #endif /* DEBUG */ |
609 | ||
525d929e AC |
610 | for (index = 0; (index < size); index++) |
611 | { | |
612 | address_word vaddr = (address_word)addr + index; | |
613 | address_word paddr; | |
525d929e | 614 | int cca; |
01737f42 | 615 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW)) |
525d929e | 616 | break; |
82ea14fd | 617 | if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1) |
63be8feb | 618 | break; |
525d929e | 619 | } |
8bae0a0c JSC |
620 | |
621 | return(index); | |
622 | } | |
623 | ||
f319bab2 GRK |
624 | int |
625 | sim_store_register (sd,rn,memory,length) | |
53b9417e | 626 | SIM_DESC sd; |
8bae0a0c JSC |
627 | int rn; |
628 | unsigned char *memory; | |
f319bab2 | 629 | int length; |
8bae0a0c | 630 | { |
01737f42 | 631 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
50a2a691 AC |
632 | /* NOTE: gdb (the client) stores registers in target byte order |
633 | while the simulator uses host byte order */ | |
8bae0a0c | 634 | #ifdef DEBUG |
18c64df6 | 635 | sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory))); |
8bae0a0c JSC |
636 | #endif /* DEBUG */ |
637 | ||
638 | /* Unfortunately this suffers from the same problem as the register | |
639 | numbering one. We need to know what the width of each logical | |
640 | register number is for the architecture being simulated. */ | |
50a2a691 | 641 | |
0c2c5f61 | 642 | if (cpu->register_widths[rn] == 0) |
a48e8c8d AC |
643 | { |
644 | sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn); | |
645 | return 0; | |
646 | } | |
647 | ||
648 | /* start-sanitize-r5900 */ | |
649 | if (rn >= 90 && rn < 90 + 32) | |
650 | { | |
651 | GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory); | |
652 | return 8; | |
653 | } | |
654 | switch (rn) | |
655 | { | |
656 | case REGISTER_SA: | |
657 | SA = T2H_8(*(unsigned64*)memory); | |
658 | return 8; | |
659 | case 122: /* FIXME */ | |
660 | LO1 = T2H_8(*(unsigned64*)memory); | |
661 | return 8; | |
662 | case 123: /* FIXME */ | |
663 | HI1 = T2H_8(*(unsigned64*)memory); | |
664 | return 8; | |
665 | } | |
a48e8c8d | 666 | /* end-sanitize-r5900 */ |
ce4713dc | 667 | |
97908603 RU |
668 | /* start-sanitize-sky */ |
669 | #ifdef TARGET_SKY | |
a859684b | 670 | if (rn >= NUM_R5900_REGS) |
ce4713dc RU |
671 | { |
672 | rn = rn - NUM_R5900_REGS; | |
97908603 | 673 | |
64ed8b6a | 674 | if( rn < NUM_VU_REGS ) |
2151467d | 675 | { |
64ed8b6a | 676 | if (rn < NUM_VU_INTEGER_REGS) |
ebcfd86a | 677 | return write_vu_int_reg (&(vu0_device.regs), rn, memory); |
64ed8b6a | 678 | else if (rn >= FIRST_VEC_REG) |
2151467d RU |
679 | { |
680 | rn -= FIRST_VEC_REG; | |
ebcfd86a | 681 | return write_vu_vec_reg (&(vu0_device.regs), rn>>2, rn&3, |
64ed8b6a | 682 | memory); |
2151467d RU |
683 | } |
684 | else switch (rn - NUM_VU_INTEGER_REGS) | |
685 | { | |
686 | case 0: | |
ebcfd86a | 687 | return write_vu_special_reg (&vu0_device, VU_REG_CIA, |
64ed8b6a | 688 | memory); |
2151467d | 689 | case 1: |
ebcfd86a | 690 | return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MR, |
64ed8b6a | 691 | memory); |
2151467d | 692 | case 2: /* VU0 has no P register */ |
64ed8b6a | 693 | return 4; |
2151467d | 694 | case 3: |
ebcfd86a | 695 | return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MI, |
64ed8b6a | 696 | memory); |
2151467d | 697 | case 4: |
ebcfd86a | 698 | return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ, |
64ed8b6a | 699 | memory); |
2151467d | 700 | default: |
ebcfd86a | 701 | return write_vu_acc_reg (&(vu0_device.regs), |
2151467d RU |
702 | rn - (NUM_VU_INTEGER_REGS + 5), |
703 | memory); | |
2151467d RU |
704 | } |
705 | } | |
ce4713dc | 706 | |
64ed8b6a AC |
707 | rn = rn - NUM_VU_REGS; |
708 | ||
709 | if (rn < NUM_VU_REGS) | |
710 | { | |
711 | if (rn < NUM_VU_INTEGER_REGS) | |
ebcfd86a | 712 | return write_vu_int_reg (&(vu1_device.regs), rn, memory); |
64ed8b6a AC |
713 | else if (rn >= FIRST_VEC_REG) |
714 | { | |
715 | rn -= FIRST_VEC_REG; | |
ebcfd86a | 716 | return write_vu_vec_reg (&(vu1_device.regs), |
64ed8b6a AC |
717 | rn >> 2, rn & 3, memory); |
718 | } | |
719 | else switch (rn - NUM_VU_INTEGER_REGS) | |
720 | { | |
721 | case 0: | |
ebcfd86a | 722 | return write_vu_special_reg (&vu1_device, VU_REG_CIA, |
64ed8b6a AC |
723 | memory); |
724 | case 1: | |
ebcfd86a | 725 | return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MR, |
2151467d | 726 | memory); |
64ed8b6a | 727 | case 2: |
ebcfd86a | 728 | return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MP, |
64ed8b6a AC |
729 | memory); |
730 | case 3: | |
ebcfd86a | 731 | return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MI, |
64ed8b6a AC |
732 | memory); |
733 | case 4: | |
ebcfd86a | 734 | return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MQ, |
64ed8b6a AC |
735 | memory); |
736 | default: | |
ebcfd86a | 737 | return write_vu_acc_reg (&(vu1_device.regs), |
64ed8b6a AC |
738 | rn - (NUM_VU_INTEGER_REGS + 5), |
739 | memory); | |
740 | } | |
741 | } | |
a859684b | 742 | |
64ed8b6a AC |
743 | rn -= NUM_VU_REGS; /* VIF0 registers are next */ |
744 | ||
745 | if (rn < NUM_VIF_REGS) | |
746 | { | |
747 | if (rn < NUM_VIF_REGS-1) | |
748 | return write_pke_reg (&pke0_device, rn, memory); | |
749 | else | |
750 | { | |
751 | sim_io_eprintf( sd, "Can't write vif0_pc (store ignored)\n" ); | |
752 | return 0; | |
753 | } | |
754 | } | |
755 | ||
756 | rn -= NUM_VIF_REGS; /* VIF1 registers are last */ | |
757 | ||
758 | if (rn < NUM_VIF_REGS) | |
759 | { | |
760 | if (rn < NUM_VIF_REGS-1) | |
761 | return write_pke_reg (&pke1_device, rn, memory); | |
762 | else | |
763 | { | |
764 | sim_io_eprintf( sd, "Can't write vif1_pc (store ignored)\n" ); | |
765 | return 0; | |
766 | } | |
767 | } | |
768 | ||
769 | sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" ); | |
770 | return 0; | |
97908603 | 771 | } |
97908603 RU |
772 | #endif |
773 | /* end-sanitize-sky */ | |
a48e8c8d AC |
774 | |
775 | if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) | |
a97f304b AC |
776 | { |
777 | if (cpu->register_widths[rn] == 32) | |
a48e8c8d AC |
778 | { |
779 | cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory); | |
780 | return 4; | |
781 | } | |
a97f304b | 782 | else |
a48e8c8d AC |
783 | { |
784 | cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory); | |
785 | return 8; | |
786 | } | |
a97f304b | 787 | } |
8bae0a0c | 788 | |
a48e8c8d AC |
789 | if (cpu->register_widths[rn] == 32) |
790 | { | |
791 | cpu->registers[rn] = T2H_4 (*(unsigned32*)memory); | |
792 | return 4; | |
793 | } | |
794 | else | |
795 | { | |
796 | cpu->registers[rn] = T2H_8 (*(unsigned64*)memory); | |
797 | return 8; | |
798 | } | |
64ed8b6a AC |
799 | |
800 | return 0; | |
8bae0a0c JSC |
801 | } |
802 | ||
f319bab2 GRK |
803 | int |
804 | sim_fetch_register (sd,rn,memory,length) | |
53b9417e | 805 | SIM_DESC sd; |
8bae0a0c JSC |
806 | int rn; |
807 | unsigned char *memory; | |
f319bab2 | 808 | int length; |
8bae0a0c | 809 | { |
01737f42 | 810 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
50a2a691 AC |
811 | /* NOTE: gdb (the client) stores registers in target byte order |
812 | while the simulator uses host byte order */ | |
8bae0a0c | 813 | #ifdef DEBUG |
18c64df6 | 814 | sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn])); |
8bae0a0c JSC |
815 | #endif /* DEBUG */ |
816 | ||
0c2c5f61 | 817 | if (cpu->register_widths[rn] == 0) |
a48e8c8d AC |
818 | { |
819 | sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn); | |
820 | return 0; | |
821 | } | |
822 | ||
823 | /* start-sanitize-r5900 */ | |
824 | if (rn >= 90 && rn < 90 + 32) | |
825 | { | |
826 | *(unsigned64*)memory = GPR1[rn - 90]; | |
827 | return 8; | |
828 | } | |
829 | switch (rn) | |
830 | { | |
831 | case REGISTER_SA: | |
832 | *((unsigned64*)memory) = H2T_8(SA); | |
833 | return 8; | |
834 | case 122: /* FIXME */ | |
835 | *((unsigned64*)memory) = H2T_8(LO1); | |
836 | return 8; | |
837 | case 123: /* FIXME */ | |
838 | *((unsigned64*)memory) = H2T_8(HI1); | |
839 | return 8; | |
840 | } | |
a48e8c8d | 841 | /* end-sanitize-r5900 */ |
ce4713dc | 842 | |
97908603 RU |
843 | /* start-sanitize-sky */ |
844 | #ifdef TARGET_SKY | |
a859684b | 845 | if (rn >= NUM_R5900_REGS) |
ce4713dc RU |
846 | { |
847 | rn = rn - NUM_R5900_REGS; | |
97908603 | 848 | |
64ed8b6a | 849 | if (rn < NUM_VU_REGS) |
2151467d | 850 | { |
64ed8b6a | 851 | if (rn < NUM_VU_INTEGER_REGS) |
ebcfd86a | 852 | return read_vu_int_reg (&(vu0_device.regs), rn, memory); |
64ed8b6a | 853 | else if (rn >= FIRST_VEC_REG) |
2151467d RU |
854 | { |
855 | rn -= FIRST_VEC_REG; | |
ebcfd86a | 856 | return read_vu_vec_reg (&(vu0_device.regs), rn>>2, rn & 3, |
2151467d RU |
857 | memory); |
858 | } | |
859 | else switch (rn - NUM_VU_INTEGER_REGS) | |
860 | { | |
861 | case 0: | |
ebcfd86a | 862 | return read_vu_special_reg(&vu0_device, VU_REG_CIA, memory); |
2151467d | 863 | case 1: |
ebcfd86a | 864 | return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MR, |
2151467d | 865 | memory); |
2151467d | 866 | case 2: /* VU0 has no P register */ |
64ed8b6a AC |
867 | *((int *) memory) = 0; |
868 | return 4; | |
2151467d | 869 | case 3: |
ebcfd86a | 870 | return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MI, |
2151467d | 871 | memory); |
2151467d | 872 | case 4: |
ebcfd86a | 873 | return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ, |
2151467d | 874 | memory); |
2151467d | 875 | default: |
ebcfd86a | 876 | return read_vu_acc_reg (&(vu0_device.regs), |
2151467d RU |
877 | rn - (NUM_VU_INTEGER_REGS + 5), |
878 | memory); | |
2151467d RU |
879 | } |
880 | } | |
64ed8b6a AC |
881 | |
882 | rn -= NUM_VU_REGS; /* VU1 registers are next */ | |
883 | ||
884 | if (rn < NUM_VU_REGS) | |
a859684b | 885 | { |
a859684b | 886 | if (rn < NUM_VU_INTEGER_REGS) |
ebcfd86a | 887 | return read_vu_int_reg (&(vu1_device.regs), rn, memory); |
64ed8b6a | 888 | else if (rn >= FIRST_VEC_REG) |
2151467d | 889 | { |
64ed8b6a | 890 | rn -= FIRST_VEC_REG; |
ebcfd86a | 891 | return read_vu_vec_reg (&(vu1_device.regs), |
64ed8b6a | 892 | rn >> 2, rn & 3, memory); |
2151467d | 893 | } |
64ed8b6a AC |
894 | else switch (rn - NUM_VU_INTEGER_REGS) |
895 | { | |
896 | case 0: | |
ebcfd86a | 897 | return read_vu_special_reg(&vu1_device, VU_REG_CIA, memory); |
64ed8b6a | 898 | case 1: |
ebcfd86a | 899 | return read_vu_misc_reg (&(vu1_device.regs), |
64ed8b6a AC |
900 | VU_REG_MR, memory); |
901 | case 2: | |
ebcfd86a | 902 | return read_vu_misc_reg (&(vu1_device.regs), |
64ed8b6a AC |
903 | VU_REG_MP, memory); |
904 | case 3: | |
ebcfd86a | 905 | return read_vu_misc_reg (&(vu1_device.regs), |
64ed8b6a AC |
906 | VU_REG_MI, memory); |
907 | case 4: | |
ebcfd86a | 908 | return read_vu_misc_reg (&(vu1_device.regs), |
64ed8b6a AC |
909 | VU_REG_MQ, memory); |
910 | default: | |
ebcfd86a | 911 | return read_vu_acc_reg (&(vu1_device.regs), |
64ed8b6a AC |
912 | rn - (NUM_VU_INTEGER_REGS + 5), |
913 | memory); | |
914 | } | |
915 | } | |
916 | ||
917 | rn -= NUM_VU_REGS; /* VIF0 registers are next */ | |
918 | ||
919 | if (rn < NUM_VIF_REGS) | |
920 | { | |
921 | if (rn < NUM_VIF_REGS-1) | |
922 | return read_pke_reg (&pke0_device, rn, memory); | |
a859684b | 923 | else |
64ed8b6a | 924 | return read_pke_pc (&pke0_device, memory); |
a859684b RU |
925 | } |
926 | ||
64ed8b6a AC |
927 | rn -= NUM_VIF_REGS; /* VIF1 registers are last */ |
928 | ||
929 | if (rn < NUM_VIF_REGS) | |
930 | { | |
931 | if (rn < NUM_VIF_REGS-1) | |
932 | return read_pke_reg (&pke1_device, rn, memory); | |
933 | else | |
934 | return read_pke_pc (&pke1_device, memory); | |
935 | } | |
936 | ||
937 | sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" ); | |
97908603 | 938 | } |
97908603 RU |
939 | #endif |
940 | /* end-sanitize-sky */ | |
a48e8c8d AC |
941 | |
942 | /* Any floating point register */ | |
943 | if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) | |
a97f304b AC |
944 | { |
945 | if (cpu->register_widths[rn] == 32) | |
a48e8c8d AC |
946 | { |
947 | *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]); | |
948 | return 4; | |
949 | } | |
a97f304b | 950 | else |
a48e8c8d AC |
951 | { |
952 | *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]); | |
953 | return 8; | |
954 | } | |
a97f304b | 955 | } |
50a2a691 | 956 | |
a48e8c8d AC |
957 | if (cpu->register_widths[rn] == 32) |
958 | { | |
959 | *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn])); | |
960 | return 4; | |
961 | } | |
962 | else | |
963 | { | |
964 | *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn])); | |
965 | return 8; | |
966 | } | |
64ed8b6a AC |
967 | |
968 | return 0; | |
8bae0a0c | 969 | } |
50a2a691 | 970 | |
8bae0a0c | 971 | |
9d52bcb7 | 972 | SIM_RC |
fafce69a | 973 | sim_create_inferior (sd, abfd, argv,env) |
53b9417e | 974 | SIM_DESC sd; |
fafce69a | 975 | struct _bfd *abfd; |
8bae0a0c JSC |
976 | char **argv; |
977 | char **env; | |
978 | { | |
50a2a691 | 979 | |
8bae0a0c | 980 | #ifdef DEBUG |
9d52bcb7 DE |
981 | printf("DBG: sim_create_inferior entered: start_address = 0x%s\n", |
982 | pr_addr(PC)); | |
8bae0a0c JSC |
983 | #endif /* DEBUG */ |
984 | ||
0c2c5f61 | 985 | ColdReset(sd); |
50a2a691 | 986 | |
fafce69a | 987 | if (abfd != NULL) |
01737f42 AC |
988 | { |
989 | /* override PC value set by ColdReset () */ | |
990 | int cpu_nr; | |
991 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
992 | { | |
993 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); | |
994 | CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd)); | |
995 | } | |
996 | } | |
2e61a3ad | 997 | |
f24b7b69 | 998 | #if 0 /* def DEBUG */ |
dad6f1f3 | 999 | if (argv || env) |
8bae0a0c | 1000 | { |
dad6f1f3 AC |
1001 | /* We should really place the argv slot values into the argument |
1002 | registers, and onto the stack as required. However, this | |
1003 | assumes that we have a stack defined, which is not | |
1004 | necessarily true at the moment. */ | |
1005 | char **cptr; | |
1006 | sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n"); | |
1007 | for (cptr = argv; (cptr && *cptr); cptr++) | |
1008 | printf("DBG: arg \"%s\"\n",*cptr); | |
8bae0a0c JSC |
1009 | } |
1010 | #endif /* DEBUG */ | |
8bae0a0c | 1011 | |
9d52bcb7 | 1012 | return SIM_RC_OK; |
8bae0a0c JSC |
1013 | } |
1014 | ||
8bae0a0c | 1015 | void |
53b9417e DE |
1016 | sim_do_command (sd,cmd) |
1017 | SIM_DESC sd; | |
8bae0a0c JSC |
1018 | char *cmd; |
1019 | { | |
63be8feb AC |
1020 | if (sim_args_command (sd, cmd) != SIM_RC_OK) |
1021 | sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n", | |
1022 | cmd); | |
8bae0a0c JSC |
1023 | } |
1024 | ||
8bae0a0c JSC |
1025 | /*---------------------------------------------------------------------------*/ |
1026 | /*-- Private simulator support interface ------------------------------------*/ | |
1027 | /*---------------------------------------------------------------------------*/ | |
1028 | ||
525d929e AC |
1029 | /* Read a null terminated string from memory, return in a buffer */ |
1030 | static char * | |
1031 | fetch_str (sd, addr) | |
1032 | SIM_DESC sd; | |
1033 | address_word addr; | |
1034 | { | |
1035 | char *buf; | |
1036 | int nr = 0; | |
1037 | char null; | |
1038 | while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0) | |
1039 | nr++; | |
1040 | buf = NZALLOC (char, nr + 1); | |
1041 | sim_read (sd, addr, buf, nr); | |
1042 | return buf; | |
1043 | } | |
1044 | ||
a9f7253f | 1045 | /* Simple monitor interface (currently setup for the IDT and PMON monitors) */ |
8bae0a0c | 1046 | static void |
01737f42 AC |
1047 | sim_monitor (SIM_DESC sd, |
1048 | sim_cpu *cpu, | |
1049 | address_word cia, | |
1050 | unsigned int reason) | |
8bae0a0c | 1051 | { |
53b9417e DE |
1052 | #ifdef DEBUG |
1053 | printf("DBG: sim_monitor: entered (reason = %d)\n",reason); | |
1054 | #endif /* DEBUG */ | |
1055 | ||
8bae0a0c JSC |
1056 | /* The IDT monitor actually allows two instructions per vector |
1057 | slot. However, the simulator currently causes a trap on each | |
1058 | individual instruction. We cheat, and lose the bottom bit. */ | |
1059 | reason >>= 1; | |
1060 | ||
1061 | /* The following callback functions are available, however the | |
1062 | monitor we are simulating does not make use of them: get_errno, | |
1063 | isatty, lseek, rename, system, time and unlink */ | |
525d929e AC |
1064 | switch (reason) |
1065 | { | |
1066 | ||
8bae0a0c JSC |
1067 | case 6: /* int open(char *path,int flags) */ |
1068 | { | |
525d929e AC |
1069 | char *path = fetch_str (sd, A0); |
1070 | V0 = sim_io_open (sd, path, (int)A1); | |
1071 | zfree (path); | |
1072 | break; | |
8bae0a0c | 1073 | } |
8bae0a0c JSC |
1074 | |
1075 | case 7: /* int read(int file,char *ptr,int len) */ | |
1076 | { | |
525d929e AC |
1077 | int fd = A0; |
1078 | int nr = A2; | |
1079 | char *buf = zalloc (nr); | |
1080 | V0 = sim_io_read (sd, fd, buf, nr); | |
1081 | sim_write (sd, A1, buf, nr); | |
1082 | zfree (buf); | |
8bae0a0c JSC |
1083 | } |
1084 | break; | |
1085 | ||
1086 | case 8: /* int write(int file,char *ptr,int len) */ | |
1087 | { | |
525d929e AC |
1088 | int fd = A0; |
1089 | int nr = A2; | |
1090 | char *buf = zalloc (nr); | |
1091 | sim_read (sd, A1, buf, nr); | |
1092 | V0 = sim_io_write (sd, fd, buf, nr); | |
1093 | zfree (buf); | |
1094 | break; | |
8bae0a0c | 1095 | } |
8bae0a0c JSC |
1096 | |
1097 | case 10: /* int close(int file) */ | |
525d929e AC |
1098 | { |
1099 | V0 = sim_io_close (sd, (int)A0); | |
1100 | break; | |
1101 | } | |
8bae0a0c | 1102 | |
e0e0fc76 MA |
1103 | case 2: /* Densan monitor: char inbyte(int waitflag) */ |
1104 | { | |
1105 | if (A0 == 0) /* waitflag == NOWAIT */ | |
192ae475 | 1106 | V0 = (unsigned_word)-1; |
e0e0fc76 MA |
1107 | } |
1108 | /* Drop through to case 11 */ | |
1109 | ||
8bae0a0c JSC |
1110 | case 11: /* char inbyte(void) */ |
1111 | { | |
1112 | char tmp; | |
525d929e AC |
1113 | if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char)) |
1114 | { | |
1115 | sim_io_error(sd,"Invalid return from character read"); | |
192ae475 | 1116 | V0 = (unsigned_word)-1; |
525d929e | 1117 | } |
8bae0a0c | 1118 | else |
192ae475 | 1119 | V0 = (unsigned_word)tmp; |
525d929e | 1120 | break; |
8bae0a0c | 1121 | } |
8bae0a0c | 1122 | |
e0e0fc76 | 1123 | case 3: /* Densan monitor: void co(char chr) */ |
8bae0a0c JSC |
1124 | case 12: /* void outbyte(char chr) : write a byte to "stdout" */ |
1125 | { | |
1126 | char tmp = (char)(A0 & 0xFF); | |
525d929e AC |
1127 | sim_io_write_stdout (sd, &tmp, sizeof(char)); |
1128 | break; | |
8bae0a0c | 1129 | } |
8bae0a0c JSC |
1130 | |
1131 | case 17: /* void _exit() */ | |
525d929e AC |
1132 | { |
1133 | sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n"); | |
01737f42 | 1134 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited, |
525d929e AC |
1135 | (unsigned int)(A0 & 0xFFFFFFFF)); |
1136 | break; | |
1137 | } | |
8bae0a0c | 1138 | |
280f90e1 AMT |
1139 | case 28 : /* PMON flush_cache */ |
1140 | break; | |
1141 | ||
8bae0a0c JSC |
1142 | case 55: /* void get_mem_info(unsigned int *ptr) */ |
1143 | /* in: A0 = pointer to three word memory location */ | |
1144 | /* out: [A0 + 0] = size */ | |
1145 | /* [A0 + 4] = instruction cache size */ | |
1146 | /* [A0 + 8] = data cache size */ | |
1147 | { | |
725fc5d9 AC |
1148 | unsigned_4 value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */; |
1149 | unsigned_4 zero = 0; | |
525d929e | 1150 | H2T (value); |
725fc5d9 AC |
1151 | sim_write (sd, A0 + 0, (char *)&value, 4); |
1152 | sim_write (sd, A0 + 4, (char *)&zero, 4); | |
1153 | sim_write (sd, A0 + 8, (char *)&zero, 4); | |
030843d7 | 1154 | /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */ |
525d929e | 1155 | break; |
8bae0a0c | 1156 | } |
525d929e | 1157 | |
a9f7253f JSC |
1158 | case 158 : /* PMON printf */ |
1159 | /* in: A0 = pointer to format string */ | |
1160 | /* A1 = optional argument 1 */ | |
1161 | /* A2 = optional argument 2 */ | |
1162 | /* A3 = optional argument 3 */ | |
1163 | /* out: void */ | |
f24b7b69 | 1164 | /* The following is based on the PMON printf source */ |
a9f7253f | 1165 | { |
525d929e AC |
1166 | address_word s = A0; |
1167 | char c; | |
1168 | signed_word *ap = &A1; /* 1st argument */ | |
f24b7b69 JSC |
1169 | /* This isn't the quickest way, since we call the host print |
1170 | routine for every character almost. But it does avoid | |
1171 | having to allocate and manage a temporary string buffer. */ | |
525d929e AC |
1172 | /* TODO: Include check that we only use three arguments (A1, |
1173 | A2 and A3) */ | |
1174 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
1175 | { | |
1176 | if (c == '%') | |
1177 | { | |
1178 | char tmp[40]; | |
1179 | enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST; | |
1180 | int width = 0, trunc = 0, haddot = 0, longlong = 0; | |
1181 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
1182 | { | |
1183 | if (strchr ("dobxXulscefg%", s)) | |
1184 | break; | |
1185 | else if (c == '-') | |
1186 | fmt = FMT_LJUST; | |
1187 | else if (c == '0') | |
1188 | fmt = FMT_RJUST0; | |
1189 | else if (c == '~') | |
1190 | fmt = FMT_CENTER; | |
1191 | else if (c == '*') | |
1192 | { | |
1193 | if (haddot) | |
1194 | trunc = (int)*ap++; | |
1195 | else | |
1196 | width = (int)*ap++; | |
1197 | } | |
1198 | else if (c >= '1' && c <= '9') | |
1199 | { | |
1200 | address_word t = s; | |
1201 | unsigned int n; | |
1202 | while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c)) | |
1203 | tmp[s - t] = c; | |
1204 | tmp[s - t] = '\0'; | |
1205 | n = (unsigned int)strtol(tmp,NULL,10); | |
1206 | if (haddot) | |
1207 | trunc = n; | |
1208 | else | |
1209 | width = n; | |
1210 | s--; | |
1211 | } | |
1212 | else if (c == '.') | |
1213 | haddot = 1; | |
1214 | } | |
1215 | switch (c) | |
1216 | { | |
1217 | case '%': | |
1218 | sim_io_printf (sd, "%%"); | |
1219 | break; | |
1220 | case 's': | |
1221 | if ((int)*ap != 0) | |
1222 | { | |
1223 | address_word p = *ap++; | |
1224 | char ch; | |
1225 | while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0') | |
1226 | sim_io_printf(sd, "%c", ch); | |
1227 | } | |
1228 | else | |
1229 | sim_io_printf(sd,"(null)"); | |
1230 | break; | |
1231 | case 'c': | |
1232 | sim_io_printf (sd, "%c", (int)*ap++); | |
1233 | break; | |
1234 | default: | |
1235 | if (c == 'l') | |
1236 | { | |
1237 | sim_read (sd, s++, &c, 1); | |
1238 | if (c == 'l') | |
1239 | { | |
1240 | longlong = 1; | |
1241 | sim_read (sd, s++, &c, 1); | |
1242 | } | |
1243 | } | |
1244 | if (strchr ("dobxXu", c)) | |
1245 | { | |
1246 | word64 lv = (word64) *ap++; | |
1247 | if (c == 'b') | |
1248 | sim_io_printf(sd,"<binary not supported>"); | |
1249 | else | |
1250 | { | |
1251 | sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c); | |
1252 | if (longlong) | |
1253 | sim_io_printf(sd, tmp, lv); | |
1254 | else | |
1255 | sim_io_printf(sd, tmp, (int)lv); | |
1256 | } | |
1257 | } | |
1258 | else if (strchr ("eEfgG", c)) | |
1259 | { | |
1260 | double dbl = *(double*)(ap++); | |
1261 | sprintf (tmp, "%%%d.%d%c", width, trunc, c); | |
1262 | sim_io_printf (sd, tmp, dbl); | |
1263 | trunc = 0; | |
1264 | } | |
1265 | } | |
1266 | } | |
1267 | else | |
1268 | sim_io_printf(sd, "%c", c); | |
1269 | } | |
1270 | break; | |
a9f7253f | 1271 | } |
a9f7253f | 1272 | |
8bae0a0c | 1273 | default: |
525d929e | 1274 | sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n", |
95469ceb | 1275 | reason, pr_addr(cia)); |
8bae0a0c JSC |
1276 | break; |
1277 | } | |
1278 | return; | |
1279 | } | |
1280 | ||
7e6c297e ILT |
1281 | /* Store a word into memory. */ |
1282 | ||
1283 | static void | |
01737f42 AC |
1284 | store_word (SIM_DESC sd, |
1285 | sim_cpu *cpu, | |
1286 | address_word cia, | |
1287 | uword64 vaddr, | |
192ae475 | 1288 | signed_word val) |
7e6c297e | 1289 | { |
dad6f1f3 | 1290 | address_word paddr; |
7e6c297e ILT |
1291 | int uncached; |
1292 | ||
1293 | if ((vaddr & 3) != 0) | |
18c64df6 | 1294 | SignalExceptionAddressStore (); |
7e6c297e ILT |
1295 | else |
1296 | { | |
1297 | if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, | |
1298 | isTARGET, isREAL)) | |
1299 | { | |
1300 | const uword64 mask = 7; | |
1301 | uword64 memval; | |
1302 | unsigned int byte; | |
1303 | ||
1304 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)); | |
1305 | byte = (vaddr & mask) ^ (BigEndianCPU << 2); | |
1306 | memval = ((uword64) val) << (8 * byte); | |
53b9417e | 1307 | StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, |
7e6c297e ILT |
1308 | isREAL); |
1309 | } | |
1310 | } | |
1311 | } | |
1312 | ||
1313 | /* Load a word from memory. */ | |
1314 | ||
192ae475 | 1315 | static signed_word |
01737f42 AC |
1316 | load_word (SIM_DESC sd, |
1317 | sim_cpu *cpu, | |
1318 | address_word cia, | |
1319 | uword64 vaddr) | |
7e6c297e ILT |
1320 | { |
1321 | if ((vaddr & 3) != 0) | |
18c64df6 | 1322 | SignalExceptionAddressLoad (); |
7e6c297e ILT |
1323 | else |
1324 | { | |
dad6f1f3 | 1325 | address_word paddr; |
7e6c297e ILT |
1326 | int uncached; |
1327 | ||
1328 | if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, | |
1329 | isTARGET, isREAL)) | |
1330 | { | |
1331 | const uword64 mask = 0x7; | |
1332 | const unsigned int reverse = ReverseEndian ? 1 : 0; | |
1333 | const unsigned int bigend = BigEndianCPU ? 1 : 0; | |
1334 | uword64 memval; | |
1335 | unsigned int byte; | |
1336 | ||
1337 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2)); | |
53b9417e | 1338 | LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr, |
7e6c297e ILT |
1339 | isDATA, isREAL); |
1340 | byte = (vaddr & mask) ^ (bigend << 2); | |
1341 | return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32); | |
1342 | } | |
1343 | } | |
1344 | ||
1345 | return 0; | |
1346 | } | |
1347 | ||
1348 | /* Simulate the mips16 entry and exit pseudo-instructions. These | |
1349 | would normally be handled by the reserved instruction exception | |
1350 | code, but for ease of simulation we just handle them directly. */ | |
1351 | ||
1352 | static void | |
01737f42 AC |
1353 | mips16_entry (SIM_DESC sd, |
1354 | sim_cpu *cpu, | |
1355 | address_word cia, | |
1356 | unsigned int insn) | |
7e6c297e ILT |
1357 | { |
1358 | int aregs, sregs, rreg; | |
1359 | ||
53b9417e DE |
1360 | #ifdef DEBUG |
1361 | printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn); | |
1362 | #endif /* DEBUG */ | |
1363 | ||
7e6c297e ILT |
1364 | aregs = (insn & 0x700) >> 8; |
1365 | sregs = (insn & 0x0c0) >> 6; | |
1366 | rreg = (insn & 0x020) >> 5; | |
1367 | ||
da0bce9c ILT |
1368 | /* This should be checked by the caller. */ |
1369 | if (sregs == 3) | |
7e6c297e ILT |
1370 | abort (); |
1371 | ||
da0bce9c | 1372 | if (aregs < 5) |
7e6c297e ILT |
1373 | { |
1374 | int i; | |
192ae475 | 1375 | signed_word tsp; |
7e6c297e ILT |
1376 | |
1377 | /* This is the entry pseudo-instruction. */ | |
1378 | ||
1379 | for (i = 0; i < aregs; i++) | |
01737f42 | 1380 | store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]); |
7e6c297e ILT |
1381 | |
1382 | tsp = SP; | |
1383 | SP -= 32; | |
1384 | ||
1385 | if (rreg) | |
1386 | { | |
1387 | tsp -= 4; | |
01737f42 | 1388 | store_word (SD, CPU, cia, (uword64) tsp, RA); |
7e6c297e ILT |
1389 | } |
1390 | ||
1391 | for (i = 0; i < sregs; i++) | |
1392 | { | |
1393 | tsp -= 4; | |
01737f42 | 1394 | store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]); |
7e6c297e ILT |
1395 | } |
1396 | } | |
1397 | else | |
1398 | { | |
1399 | int i; | |
192ae475 | 1400 | signed_word tsp; |
7e6c297e ILT |
1401 | |
1402 | /* This is the exit pseudo-instruction. */ | |
1403 | ||
1404 | tsp = SP + 32; | |
1405 | ||
1406 | if (rreg) | |
1407 | { | |
1408 | tsp -= 4; | |
01737f42 | 1409 | RA = load_word (SD, CPU, cia, (uword64) tsp); |
7e6c297e ILT |
1410 | } |
1411 | ||
1412 | for (i = 0; i < sregs; i++) | |
1413 | { | |
1414 | tsp -= 4; | |
01737f42 | 1415 | GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp); |
7e6c297e ILT |
1416 | } |
1417 | ||
1418 | SP += 32; | |
1419 | ||
192ae475 | 1420 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
da0bce9c | 1421 | { |
192ae475 AC |
1422 | if (aregs == 5) |
1423 | { | |
1424 | FGR[0] = WORD64LO (GPR[4]); | |
1425 | FPR_STATE[0] = fmt_uninterpreted; | |
1426 | } | |
1427 | else if (aregs == 6) | |
1428 | { | |
1429 | FGR[0] = WORD64LO (GPR[5]); | |
1430 | FGR[1] = WORD64LO (GPR[4]); | |
1431 | FPR_STATE[0] = fmt_uninterpreted; | |
1432 | FPR_STATE[1] = fmt_uninterpreted; | |
1433 | } | |
1434 | } | |
da0bce9c | 1435 | |
7e6c297e ILT |
1436 | PC = RA; |
1437 | } | |
192ae475 | 1438 | |
7e6c297e ILT |
1439 | } |
1440 | ||
8bae0a0c JSC |
1441 | /*-- trace support ----------------------------------------------------------*/ |
1442 | ||
1443 | /* The TRACE support is provided (if required) in the memory accessing | |
1444 | routines. Since we are also providing the architecture specific | |
1445 | features, the architecture simulation code can also deal with | |
1446 | notifying the TRACE world of cache flushes, etc. Similarly we do | |
1447 | not need to provide profiling support in the simulator engine, | |
1448 | since we can sample in the instruction fetch control loop. By | |
1449 | defining the TRACE manifest, we add tracing as a run-time | |
1450 | option. */ | |
1451 | ||
1452 | #if defined(TRACE) | |
1453 | /* Tracing by default produces "din" format (as required by | |
1454 | dineroIII). Each line of such a trace file *MUST* have a din label | |
1455 | and address field. The rest of the line is ignored, so comments can | |
1456 | be included if desired. The first field is the label which must be | |
1457 | one of the following values: | |
1458 | ||
1459 | 0 read data | |
1460 | 1 write data | |
1461 | 2 instruction fetch | |
1462 | 3 escape record (treated as unknown access type) | |
1463 | 4 escape record (causes cache flush) | |
1464 | ||
1465 | The address field is a 32bit (lower-case) hexadecimal address | |
1466 | value. The address should *NOT* be preceded by "0x". | |
1467 | ||
1468 | The size of the memory transfer is not important when dealing with | |
1469 | cache lines (as long as no more than a cache line can be | |
1470 | transferred in a single operation :-), however more information | |
1471 | could be given following the dineroIII requirement to allow more | |
1472 | complete memory and cache simulators to provide better | |
1473 | results. i.e. the University of Pisa has a cache simulator that can | |
1474 | also take bus size and speed as (variable) inputs to calculate | |
1475 | complete system performance (a much more useful ability when trying | |
1476 | to construct an end product, rather than a processor). They | |
1477 | currently have an ARM version of their tool called ChARM. */ | |
1478 | ||
e3d12c65 | 1479 | |
030843d7 | 1480 | void |
01737f42 AC |
1481 | dotrace (SIM_DESC sd, |
1482 | sim_cpu *cpu, | |
1483 | FILE *tracefh, | |
1484 | int type, | |
1485 | SIM_ADDR address, | |
1486 | int width, | |
1487 | char *comment,...) | |
8bae0a0c | 1488 | { |
0c2c5f61 | 1489 | if (STATE & simTRACE) { |
8bae0a0c | 1490 | va_list ap; |
53b9417e | 1491 | fprintf(tracefh,"%d %s ; width %d ; ", |
6429b296 | 1492 | type, |
53b9417e DE |
1493 | pr_addr(address), |
1494 | width); | |
8bae0a0c | 1495 | va_start(ap,comment); |
6429b296 | 1496 | vfprintf(tracefh,comment,ap); |
8bae0a0c JSC |
1497 | va_end(ap); |
1498 | fprintf(tracefh,"\n"); | |
1499 | } | |
1500 | /* NOTE: Since the "din" format will only accept 32bit addresses, and | |
1501 | we may be generating 64bit ones, we should put the hi-32bits of the | |
1502 | address into the comment field. */ | |
1503 | ||
1504 | /* TODO: Provide a buffer for the trace lines. We can then avoid | |
1505 | performing writes until the buffer is filled, or the file is | |
1506 | being closed. */ | |
1507 | ||
1508 | /* NOTE: We could consider adding a comment field to the "din" file | |
1509 | produced using type 3 markers (unknown access). This would then | |
1510 | allow information about the program that the "din" is for, and | |
1511 | the MIPs world that was being simulated, to be placed into the | |
1512 | trace file. */ | |
1513 | ||
1514 | return; | |
1515 | } | |
1516 | #endif /* TRACE */ | |
1517 | ||
1518 | /*---------------------------------------------------------------------------*/ | |
1519 | /*-- simulator engine -------------------------------------------------------*/ | |
1520 | /*---------------------------------------------------------------------------*/ | |
1521 | ||
1522 | static void | |
01737f42 | 1523 | ColdReset (SIM_DESC sd) |
8bae0a0c | 1524 | { |
01737f42 AC |
1525 | int cpu_nr; |
1526 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
dad6f1f3 | 1527 | { |
01737f42 AC |
1528 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); |
1529 | /* RESET: Fixed PC address: */ | |
1530 | PC = UNSIGNED64 (0xFFFFFFFFBFC00000); | |
1531 | /* The reset vector address is in the unmapped, uncached memory space. */ | |
1532 | ||
1533 | SR &= ~(status_SR | status_TS | status_RP); | |
1534 | SR |= (status_ERL | status_BEV); | |
1535 | ||
1536 | /* Cheat and allow access to the complete register set immediately */ | |
1537 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT | |
1538 | && WITH_TARGET_WORD_BITSIZE == 64) | |
1539 | SR |= status_FR; /* 64bit registers */ | |
1540 | ||
1541 | /* Ensure that any instructions with pending register updates are | |
1542 | cleared: */ | |
2acd126a | 1543 | PENDING_INVALIDATE(); |
01737f42 AC |
1544 | |
1545 | /* Initialise the FPU registers to the unknown state */ | |
1546 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) | |
1547 | { | |
1548 | int rn; | |
1549 | for (rn = 0; (rn < 32); rn++) | |
1550 | FPR_STATE[rn] = fmt_uninterpreted; | |
1551 | } | |
1552 | ||
dad6f1f3 | 1553 | } |
8bae0a0c JSC |
1554 | } |
1555 | ||
8bae0a0c JSC |
1556 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ |
1557 | /* Signal an exception condition. This will result in an exception | |
1558 | that aborts the instruction. The instruction operation pseudocode | |
50a2a691 | 1559 | will never see a return from this function call. */ |
2e61a3ad | 1560 | |
18c64df6 | 1561 | void |
7ce8b917 | 1562 | signal_exception (SIM_DESC sd, |
01737f42 | 1563 | sim_cpu *cpu, |
7ce8b917 AC |
1564 | address_word cia, |
1565 | int exception,...) | |
8bae0a0c | 1566 | { |
56e7c849 | 1567 | int vector; |
6eedf3f4 MA |
1568 | |
1569 | #ifdef DEBUG | |
95469ceb | 1570 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); |
6eedf3f4 MA |
1571 | #endif /* DEBUG */ |
1572 | ||
8bae0a0c JSC |
1573 | /* Ensure that any active atomic read/modify/write operation will fail: */ |
1574 | LLBIT = 0; | |
1575 | ||
1576 | switch (exception) { | |
1577 | /* TODO: For testing purposes I have been ignoring TRAPs. In | |
1578 | reality we should either simulate them, or allow the user to | |
6eedf3f4 MA |
1579 | ignore them at run-time. |
1580 | Same for SYSCALL */ | |
8bae0a0c | 1581 | case Trap : |
95469ceb | 1582 | sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia)); |
8bae0a0c JSC |
1583 | break; |
1584 | ||
6eedf3f4 MA |
1585 | case SystemCall : |
1586 | { | |
1587 | va_list ap; | |
1588 | unsigned int instruction; | |
1589 | unsigned int code; | |
1590 | ||
1591 | va_start(ap,exception); | |
1592 | instruction = va_arg(ap,unsigned int); | |
1593 | va_end(ap); | |
1594 | ||
1595 | code = (instruction >> 6) & 0xFFFFF; | |
1596 | ||
18c64df6 | 1597 | sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n", |
69d5a566 | 1598 | code, pr_addr(cia)); |
6eedf3f4 MA |
1599 | } |
1600 | break; | |
1601 | ||
1602 | case DebugBreakPoint : | |
1603 | if (! (Debug & Debug_DM)) | |
1604 | { | |
1605 | if (INDELAYSLOT()) | |
1606 | { | |
1607 | CANCELDELAYSLOT(); | |
1608 | ||
1609 | Debug |= Debug_DBD; /* signaled from within in delay slot */ | |
95469ceb | 1610 | DEPC = cia - 4; /* reference the branch instruction */ |
6eedf3f4 MA |
1611 | } |
1612 | else | |
1613 | { | |
1614 | Debug &= ~Debug_DBD; /* not signaled from within a delay slot */ | |
95469ceb | 1615 | DEPC = cia; |
6eedf3f4 MA |
1616 | } |
1617 | ||
1618 | Debug |= Debug_DM; /* in debugging mode */ | |
1619 | Debug |= Debug_DBp; /* raising a DBp exception */ | |
1620 | PC = 0xBFC00200; | |
01737f42 | 1621 | sim_engine_restart (SD, CPU, NULL, NULL_CIA); |
6eedf3f4 MA |
1622 | } |
1623 | break; | |
1624 | ||
8bae0a0c JSC |
1625 | case ReservedInstruction : |
1626 | { | |
1627 | va_list ap; | |
1628 | unsigned int instruction; | |
1629 | va_start(ap,exception); | |
1630 | instruction = va_arg(ap,unsigned int); | |
1631 | va_end(ap); | |
1632 | /* Provide simple monitor support using ReservedInstruction | |
1633 | exceptions. The following code simulates the fixed vector | |
1634 | entry points into the IDT monitor by causing a simulator | |
1635 | trap, performing the monitor operation, and returning to | |
1636 | the address held in the $ra register (standard PCS return | |
1637 | address). This means we only need to pre-load the vector | |
1638 | space with suitable instruction values. For systems were | |
1639 | actual trap instructions are used, we would not need to | |
1640 | perform this magic. */ | |
7ce8b917 AC |
1641 | if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) |
1642 | { | |
01737f42 | 1643 | sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) ); |
7ce8b917 AC |
1644 | /* NOTE: This assumes that a branch-and-link style |
1645 | instruction was used to enter the vector (which is the | |
1646 | case with the current IDT monitor). */ | |
01737f42 | 1647 | sim_engine_restart (SD, CPU, NULL, RA); |
7ce8b917 | 1648 | } |
7e6c297e ILT |
1649 | /* Look for the mips16 entry and exit instructions, and |
1650 | simulate a handler for them. */ | |
95469ceb | 1651 | else if ((cia & 1) != 0 |
7e6c297e | 1652 | && (instruction & 0xf81f) == 0xe809 |
7ce8b917 AC |
1653 | && (instruction & 0x0c0) != 0x0c0) |
1654 | { | |
01737f42 | 1655 | mips16_entry (SD, CPU, cia, instruction); |
7ce8b917 AC |
1656 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); |
1657 | } | |
1658 | /* else fall through to normal exception processing */ | |
f3bdd368 | 1659 | sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia)); |
8bae0a0c JSC |
1660 | } |
1661 | ||
05d1322f | 1662 | case BreakPoint: |
e3d12c65 | 1663 | #ifdef DEBUG |
95469ceb | 1664 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); |
8bae0a0c | 1665 | #endif /* DEBUG */ |
05d1322f JL |
1666 | /* Keep a copy of the current A0 in-case this is the program exit |
1667 | breakpoint: */ | |
1668 | { | |
1669 | va_list ap; | |
1670 | unsigned int instruction; | |
1671 | va_start(ap,exception); | |
1672 | instruction = va_arg(ap,unsigned int); | |
1673 | va_end(ap); | |
1674 | /* Check for our special terminating BREAK: */ | |
1675 | if ((instruction & 0x03FFFFC0) == 0x03ff0000) { | |
01737f42 | 1676 | sim_engine_halt (SD, CPU, NULL, cia, |
05d1322f JL |
1677 | sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); |
1678 | } | |
1679 | } | |
0c2c5f61 | 1680 | if (STATE & simDELAYSLOT) |
95469ceb | 1681 | PC = cia - 4; /* reference the branch instruction */ |
05d1322f | 1682 | else |
95469ceb | 1683 | PC = cia; |
01737f42 | 1684 | sim_engine_halt (SD, CPU, NULL, cia, |
232156de | 1685 | sim_stopped, SIM_SIGTRAP); |
05d1322f JL |
1686 | |
1687 | default: | |
8bae0a0c JSC |
1688 | /* Store exception code into current exception id variable (used |
1689 | by exit code): */ | |
1690 | ||
1691 | /* TODO: If not simulating exceptions then stop the simulator | |
1692 | execution. At the moment we always stop the simulation. */ | |
e3d12c65 | 1693 | |
56e7c849 AC |
1694 | /* See figure 5-17 for an outline of the code below */ |
1695 | if (! (SR & status_EXL)) | |
1696 | { | |
1697 | CAUSE = (exception << 2); | |
0c2c5f61 | 1698 | if (STATE & simDELAYSLOT) |
56e7c849 | 1699 | { |
0c2c5f61 | 1700 | STATE &= ~simDELAYSLOT; |
56e7c849 | 1701 | CAUSE |= cause_BD; |
95469ceb | 1702 | EPC = (cia - 4); /* reference the branch instruction */ |
56e7c849 AC |
1703 | } |
1704 | else | |
95469ceb | 1705 | EPC = cia; |
56e7c849 AC |
1706 | /* FIXME: TLB et.al. */ |
1707 | vector = 0x180; | |
1708 | } | |
1709 | else | |
1710 | { | |
05d1322f | 1711 | CAUSE = (exception << 2); |
56e7c849 AC |
1712 | vector = 0x180; |
1713 | } | |
1714 | SR |= status_EXL; | |
e3d12c65 DE |
1715 | /* Store exception code into current exception id variable (used |
1716 | by exit code): */ | |
56e7c849 AC |
1717 | if (SR & status_BEV) |
1718 | PC = (signed)0xBFC00200 + 0x180; | |
1719 | else | |
1720 | PC = (signed)0x80000000 + 0x180; | |
1721 | ||
50a2a691 AC |
1722 | switch ((CAUSE >> 2) & 0x1F) |
1723 | { | |
1724 | case Interrupt: | |
56e7c849 AC |
1725 | /* Interrupts arrive during event processing, no need to |
1726 | restart */ | |
1727 | return; | |
50a2a691 AC |
1728 | |
1729 | case TLBModification: | |
1730 | case TLBLoad: | |
1731 | case TLBStore: | |
1732 | case AddressLoad: | |
1733 | case AddressStore: | |
1734 | case InstructionFetch: | |
1735 | case DataReference: | |
56e7c849 AC |
1736 | /* The following is so that the simulator will continue from the |
1737 | exception address on breakpoint operations. */ | |
1738 | PC = EPC; | |
01737f42 | 1739 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1740 | sim_stopped, SIM_SIGBUS); |
50a2a691 AC |
1741 | |
1742 | case ReservedInstruction: | |
1743 | case CoProcessorUnusable: | |
56e7c849 | 1744 | PC = EPC; |
01737f42 | 1745 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1746 | sim_stopped, SIM_SIGILL); |
50a2a691 AC |
1747 | |
1748 | case IntegerOverflow: | |
1749 | case FPE: | |
01737f42 | 1750 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1751 | sim_stopped, SIM_SIGFPE); |
50a2a691 AC |
1752 | |
1753 | case Trap: | |
1754 | case Watch: | |
1755 | case SystemCall: | |
56e7c849 | 1756 | PC = EPC; |
01737f42 | 1757 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1758 | sim_stopped, SIM_SIGTRAP); |
50a2a691 | 1759 | |
05d1322f JL |
1760 | case BreakPoint: |
1761 | PC = EPC; | |
01737f42 | 1762 | sim_engine_abort (SD, CPU, NULL_CIA, |
05d1322f JL |
1763 | "FATAL: Should not encounter a breakpoint\n"); |
1764 | ||
50a2a691 | 1765 | default : /* Unknown internal exception */ |
56e7c849 | 1766 | PC = EPC; |
01737f42 | 1767 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1768 | sim_stopped, SIM_SIGABRT); |
50a2a691 AC |
1769 | |
1770 | } | |
8bae0a0c JSC |
1771 | |
1772 | case SimulatorFault: | |
1773 | { | |
1774 | va_list ap; | |
1775 | char *msg; | |
1776 | va_start(ap,exception); | |
1777 | msg = va_arg(ap,char *); | |
50a2a691 | 1778 | va_end(ap); |
01737f42 | 1779 | sim_engine_abort (SD, CPU, NULL_CIA, |
2e61a3ad | 1780 | "FATAL: Simulator error \"%s\"\n",msg); |
8bae0a0c | 1781 | } |
8bae0a0c JSC |
1782 | } |
1783 | ||
1784 | return; | |
1785 | } | |
1786 | ||
1787 | #if defined(WARN_RESULT) | |
1788 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1789 | /* This function indicates that the result of the operation is | |
1790 | undefined. However, this should not affect the instruction | |
1791 | stream. All that is meant to happen is that the destination | |
1792 | register is set to an undefined result. To keep the simulator | |
1793 | simple, we just don't bother updating the destination register, so | |
1794 | the overall result will be undefined. If desired we can stop the | |
1795 | simulator by raising a pseudo-exception. */ | |
95469ceb | 1796 | #define UndefinedResult() undefined_result (sd,cia) |
8bae0a0c | 1797 | static void |
95469ceb AC |
1798 | undefined_result(sd,cia) |
1799 | SIM_DESC sd; | |
1800 | address_word cia; | |
8bae0a0c | 1801 | { |
95469ceb | 1802 | sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia)); |
8bae0a0c JSC |
1803 | #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */ |
1804 | state |= simSTOP; | |
1805 | #endif | |
1806 | return; | |
1807 | } | |
1808 | #endif /* WARN_RESULT */ | |
1809 | ||
8bae0a0c JSC |
1810 | /*-- FPU support routines ---------------------------------------------------*/ |
1811 | ||
8bae0a0c JSC |
1812 | /* Numbers are held in normalized form. The SINGLE and DOUBLE binary |
1813 | formats conform to ANSI/IEEE Std 754-1985. */ | |
1814 | /* SINGLE precision floating: | |
1815 | * seeeeeeeefffffffffffffffffffffff | |
1816 | * s = 1bit = sign | |
1817 | * e = 8bits = exponent | |
1818 | * f = 23bits = fraction | |
1819 | */ | |
1820 | /* SINGLE precision fixed: | |
1821 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
1822 | * s = 1bit = sign | |
1823 | * i = 31bits = integer | |
1824 | */ | |
1825 | /* DOUBLE precision floating: | |
1826 | * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff | |
1827 | * s = 1bit = sign | |
1828 | * e = 11bits = exponent | |
1829 | * f = 52bits = fraction | |
1830 | */ | |
1831 | /* DOUBLE precision fixed: | |
1832 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
1833 | * s = 1bit = sign | |
1834 | * i = 63bits = integer | |
1835 | */ | |
1836 | ||
1837 | /* Extract sign-bit: */ | |
1838 | #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0) | |
e871dd18 | 1839 | #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0) |
8bae0a0c JSC |
1840 | /* Extract biased exponent: */ |
1841 | #define FP_S_be(v) (((v) >> 23) & 0xFF) | |
1842 | #define FP_D_be(v) (((v) >> 52) & 0x7FF) | |
1843 | /* Extract unbiased Exponent: */ | |
1844 | #define FP_S_e(v) (FP_S_be(v) - 0x7F) | |
1845 | #define FP_D_e(v) (FP_D_be(v) - 0x3FF) | |
1846 | /* Extract complete fraction field: */ | |
1847 | #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23)) | |
e871dd18 | 1848 | #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52)) |
8bae0a0c JSC |
1849 | /* Extract numbered fraction bit: */ |
1850 | #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0) | |
1851 | #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0) | |
1852 | ||
1853 | /* Explicit QNaN values used when value required: */ | |
1854 | #define FPQNaN_SINGLE (0x7FBFFFFF) | |
1855 | #define FPQNaN_WORD (0x7FFFFFFF) | |
e871dd18 JSC |
1856 | #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF) |
1857 | #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF) | |
8bae0a0c JSC |
1858 | |
1859 | /* Explicit Infinity values used when required: */ | |
1860 | #define FPINF_SINGLE (0x7F800000) | |
e871dd18 | 1861 | #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000) |
8bae0a0c JSC |
1862 | |
1863 | #if 1 /* def DEBUG */ | |
1864 | #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor"))) | |
1865 | #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>")))))) | |
1866 | #endif /* DEBUG */ | |
1867 | ||
18c64df6 | 1868 | uword64 |
01737f42 AC |
1869 | value_fpr (SIM_DESC sd, |
1870 | sim_cpu *cpu, | |
1871 | address_word cia, | |
1872 | int fpr, | |
1873 | FP_formats fmt) | |
8bae0a0c | 1874 | { |
50a2a691 | 1875 | uword64 value = 0; |
8bae0a0c JSC |
1876 | int err = 0; |
1877 | ||
1878 | /* Treat unused register values, as fixed-point 64bit values: */ | |
1879 | if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown)) | |
1880 | #if 1 | |
1881 | /* If request to read data as "uninterpreted", then use the current | |
1882 | encoding: */ | |
0c2c5f61 | 1883 | fmt = FPR_STATE[fpr]; |
8bae0a0c JSC |
1884 | #else |
1885 | fmt = fmt_long; | |
1886 | #endif | |
1887 | ||
1888 | /* For values not yet accessed, set to the desired format: */ | |
0c2c5f61 AC |
1889 | if (FPR_STATE[fpr] == fmt_uninterpreted) { |
1890 | FPR_STATE[fpr] = fmt; | |
8bae0a0c JSC |
1891 | #ifdef DEBUG |
1892 | printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt)); | |
1893 | #endif /* DEBUG */ | |
1894 | } | |
0c2c5f61 | 1895 | if (fmt != FPR_STATE[fpr]) { |
95469ceb | 1896 | sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia)); |
0c2c5f61 | 1897 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
1898 | } |
1899 | ||
0c2c5f61 | 1900 | if (FPR_STATE[fpr] == fmt_unknown) { |
8bae0a0c JSC |
1901 | /* Set QNaN value: */ |
1902 | switch (fmt) { | |
1903 | case fmt_single: | |
1904 | value = FPQNaN_SINGLE; | |
1905 | break; | |
1906 | ||
1907 | case fmt_double: | |
1908 | value = FPQNaN_DOUBLE; | |
1909 | break; | |
1910 | ||
1911 | case fmt_word: | |
1912 | value = FPQNaN_WORD; | |
1913 | break; | |
1914 | ||
1915 | case fmt_long: | |
1916 | value = FPQNaN_LONG; | |
1917 | break; | |
1918 | ||
1919 | default: | |
1920 | err = -1; | |
1921 | break; | |
1922 | } | |
1923 | } else if (SizeFGR() == 64) { | |
1924 | switch (fmt) { | |
1925 | case fmt_single: | |
1926 | case fmt_word: | |
1927 | value = (FGR[fpr] & 0xFFFFFFFF); | |
1928 | break; | |
1929 | ||
1930 | case fmt_uninterpreted: | |
1931 | case fmt_double: | |
1932 | case fmt_long: | |
1933 | value = FGR[fpr]; | |
1934 | break; | |
1935 | ||
1936 | default : | |
1937 | err = -1; | |
1938 | break; | |
1939 | } | |
da0bce9c | 1940 | } else { |
8bae0a0c JSC |
1941 | switch (fmt) { |
1942 | case fmt_single: | |
1943 | case fmt_word: | |
1944 | value = (FGR[fpr] & 0xFFFFFFFF); | |
1945 | break; | |
1946 | ||
1947 | case fmt_uninterpreted: | |
1948 | case fmt_double: | |
1949 | case fmt_long: | |
da0bce9c ILT |
1950 | if ((fpr & 1) == 0) { /* even registers only */ |
1951 | value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF)); | |
1952 | } else { | |
18c64df6 | 1953 | SignalException(ReservedInstruction,0); |
da0bce9c | 1954 | } |
8bae0a0c JSC |
1955 | break; |
1956 | ||
1957 | default : | |
1958 | err = -1; | |
1959 | break; | |
1960 | } | |
1961 | } | |
1962 | ||
1963 | if (err) | |
18c64df6 | 1964 | SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()"); |
8bae0a0c JSC |
1965 | |
1966 | #ifdef DEBUG | |
95469ceb | 1967 | printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); |
8bae0a0c JSC |
1968 | #endif /* DEBUG */ |
1969 | ||
1970 | return(value); | |
1971 | } | |
1972 | ||
18c64df6 | 1973 | void |
01737f42 AC |
1974 | store_fpr (SIM_DESC sd, |
1975 | sim_cpu *cpu, | |
1976 | address_word cia, | |
1977 | int fpr, | |
1978 | FP_formats fmt, | |
1979 | uword64 value) | |
8bae0a0c JSC |
1980 | { |
1981 | int err = 0; | |
1982 | ||
1983 | #ifdef DEBUG | |
95469ceb | 1984 | printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); |
8bae0a0c JSC |
1985 | #endif /* DEBUG */ |
1986 | ||
1987 | if (SizeFGR() == 64) { | |
1988 | switch (fmt) { | |
a09a30d2 AC |
1989 | case fmt_uninterpreted_32: |
1990 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
1991 | case fmt_single : |
1992 | case fmt_word : | |
e871dd18 | 1993 | FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF)); |
0c2c5f61 | 1994 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
1995 | break; |
1996 | ||
a09a30d2 AC |
1997 | case fmt_uninterpreted_64: |
1998 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
1999 | case fmt_uninterpreted: |
2000 | case fmt_double : | |
2001 | case fmt_long : | |
2002 | FGR[fpr] = value; | |
0c2c5f61 | 2003 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2004 | break; |
2005 | ||
2006 | default : | |
0c2c5f61 | 2007 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2008 | err = -1; |
2009 | break; | |
2010 | } | |
da0bce9c | 2011 | } else { |
8bae0a0c | 2012 | switch (fmt) { |
a09a30d2 AC |
2013 | case fmt_uninterpreted_32: |
2014 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2015 | case fmt_single : |
2016 | case fmt_word : | |
8bae0a0c | 2017 | FGR[fpr] = (value & 0xFFFFFFFF); |
0c2c5f61 | 2018 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2019 | break; |
2020 | ||
a09a30d2 AC |
2021 | case fmt_uninterpreted_64: |
2022 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2023 | case fmt_uninterpreted: |
2024 | case fmt_double : | |
2025 | case fmt_long : | |
da0bce9c ILT |
2026 | if ((fpr & 1) == 0) { /* even register number only */ |
2027 | FGR[fpr+1] = (value >> 32); | |
2028 | FGR[fpr] = (value & 0xFFFFFFFF); | |
0c2c5f61 AC |
2029 | FPR_STATE[fpr + 1] = fmt; |
2030 | FPR_STATE[fpr] = fmt; | |
da0bce9c | 2031 | } else { |
0c2c5f61 AC |
2032 | FPR_STATE[fpr] = fmt_unknown; |
2033 | FPR_STATE[fpr + 1] = fmt_unknown; | |
18c64df6 | 2034 | SignalException(ReservedInstruction,0); |
da0bce9c | 2035 | } |
8bae0a0c JSC |
2036 | break; |
2037 | ||
2038 | default : | |
0c2c5f61 | 2039 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2040 | err = -1; |
2041 | break; | |
2042 | } | |
e871dd18 JSC |
2043 | } |
2044 | #if defined(WARN_RESULT) | |
2045 | else | |
2046 | UndefinedResult(); | |
2047 | #endif /* WARN_RESULT */ | |
8bae0a0c JSC |
2048 | |
2049 | if (err) | |
18c64df6 | 2050 | SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()"); |
8bae0a0c JSC |
2051 | |
2052 | #ifdef DEBUG | |
53b9417e | 2053 | printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt)); |
8bae0a0c JSC |
2054 | #endif /* DEBUG */ |
2055 | ||
2056 | return; | |
2057 | } | |
2058 | ||
18c64df6 | 2059 | int |
8bae0a0c | 2060 | NaN(op,fmt) |
e871dd18 | 2061 | uword64 op; |
8bae0a0c JSC |
2062 | FP_formats fmt; |
2063 | { | |
2064 | int boolean = 0; | |
8bae0a0c JSC |
2065 | switch (fmt) { |
2066 | case fmt_single: | |
8bae0a0c | 2067 | case fmt_word: |
76ef4165 FL |
2068 | { |
2069 | sim_fpu wop; | |
2070 | sim_fpu_32to (&wop, op); | |
2071 | boolean = sim_fpu_is_nan (&wop); | |
2072 | break; | |
2073 | } | |
2074 | case fmt_double: | |
8bae0a0c | 2075 | case fmt_long: |
76ef4165 FL |
2076 | { |
2077 | sim_fpu wop; | |
2078 | sim_fpu_64to (&wop, op); | |
2079 | boolean = sim_fpu_is_nan (&wop); | |
2080 | break; | |
2081 | } | |
50a2a691 AC |
2082 | default: |
2083 | fprintf (stderr, "Bad switch\n"); | |
2084 | abort (); | |
8bae0a0c JSC |
2085 | } |
2086 | ||
2087 | #ifdef DEBUG | |
53b9417e | 2088 | printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2089 | #endif /* DEBUG */ |
2090 | ||
2091 | return(boolean); | |
2092 | } | |
2093 | ||
18c64df6 | 2094 | int |
8bae0a0c | 2095 | Infinity(op,fmt) |
e871dd18 | 2096 | uword64 op; |
8bae0a0c JSC |
2097 | FP_formats fmt; |
2098 | { | |
2099 | int boolean = 0; | |
2100 | ||
2101 | #ifdef DEBUG | |
95469ceb | 2102 | printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2103 | #endif /* DEBUG */ |
2104 | ||
8bae0a0c JSC |
2105 | switch (fmt) { |
2106 | case fmt_single: | |
76ef4165 FL |
2107 | { |
2108 | sim_fpu wop; | |
2109 | sim_fpu_32to (&wop, op); | |
2110 | boolean = sim_fpu_is_infinity (&wop); | |
2111 | break; | |
2112 | } | |
8bae0a0c | 2113 | case fmt_double: |
76ef4165 FL |
2114 | { |
2115 | sim_fpu wop; | |
2116 | sim_fpu_64to (&wop, op); | |
2117 | boolean = sim_fpu_is_infinity (&wop); | |
2118 | break; | |
2119 | } | |
8bae0a0c JSC |
2120 | default: |
2121 | printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt)); | |
2122 | break; | |
2123 | } | |
2124 | ||
2125 | #ifdef DEBUG | |
53b9417e | 2126 | printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2127 | #endif /* DEBUG */ |
2128 | ||
2129 | return(boolean); | |
2130 | } | |
2131 | ||
18c64df6 | 2132 | int |
8bae0a0c | 2133 | Less(op1,op2,fmt) |
e871dd18 JSC |
2134 | uword64 op1; |
2135 | uword64 op2; | |
8bae0a0c JSC |
2136 | FP_formats fmt; |
2137 | { | |
2138 | int boolean = 0; | |
2139 | ||
e871dd18 JSC |
2140 | /* Argument checking already performed by the FPCOMPARE code */ |
2141 | ||
8bae0a0c | 2142 | #ifdef DEBUG |
53b9417e | 2143 | printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2144 | #endif /* DEBUG */ |
2145 | ||
8bae0a0c JSC |
2146 | /* The format type should already have been checked: */ |
2147 | switch (fmt) { | |
2148 | case fmt_single: | |
2149 | { | |
76ef4165 FL |
2150 | sim_fpu wop1; |
2151 | sim_fpu wop2; | |
2152 | sim_fpu_32to (&wop1, op1); | |
2153 | sim_fpu_32to (&wop2, op2); | |
2154 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2155 | break; | |
8bae0a0c | 2156 | } |
8bae0a0c | 2157 | case fmt_double: |
76ef4165 FL |
2158 | { |
2159 | sim_fpu wop1; | |
2160 | sim_fpu wop2; | |
2161 | sim_fpu_64to (&wop1, op1); | |
2162 | sim_fpu_64to (&wop2, op2); | |
2163 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2164 | break; | |
2165 | } | |
50a2a691 AC |
2166 | default: |
2167 | fprintf (stderr, "Bad switch\n"); | |
2168 | abort (); | |
8bae0a0c JSC |
2169 | } |
2170 | ||
2171 | #ifdef DEBUG | |
2172 | printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2173 | #endif /* DEBUG */ | |
2174 | ||
2175 | return(boolean); | |
2176 | } | |
2177 | ||
18c64df6 | 2178 | int |
8bae0a0c | 2179 | Equal(op1,op2,fmt) |
e871dd18 JSC |
2180 | uword64 op1; |
2181 | uword64 op2; | |
8bae0a0c JSC |
2182 | FP_formats fmt; |
2183 | { | |
2184 | int boolean = 0; | |
2185 | ||
e871dd18 JSC |
2186 | /* Argument checking already performed by the FPCOMPARE code */ |
2187 | ||
8bae0a0c | 2188 | #ifdef DEBUG |
53b9417e | 2189 | printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2190 | #endif /* DEBUG */ |
2191 | ||
8bae0a0c JSC |
2192 | /* The format type should already have been checked: */ |
2193 | switch (fmt) { | |
2194 | case fmt_single: | |
76ef4165 FL |
2195 | { |
2196 | sim_fpu wop1; | |
2197 | sim_fpu wop2; | |
2198 | sim_fpu_32to (&wop1, op1); | |
2199 | sim_fpu_32to (&wop2, op2); | |
2200 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2201 | break; | |
2202 | } | |
8bae0a0c | 2203 | case fmt_double: |
76ef4165 FL |
2204 | { |
2205 | sim_fpu wop1; | |
2206 | sim_fpu wop2; | |
2207 | sim_fpu_64to (&wop1, op1); | |
2208 | sim_fpu_64to (&wop2, op2); | |
2209 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2210 | break; | |
2211 | } | |
50a2a691 AC |
2212 | default: |
2213 | fprintf (stderr, "Bad switch\n"); | |
2214 | abort (); | |
8bae0a0c JSC |
2215 | } |
2216 | ||
2217 | #ifdef DEBUG | |
2218 | printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2219 | #endif /* DEBUG */ | |
2220 | ||
2221 | return(boolean); | |
2222 | } | |
2223 | ||
18c64df6 | 2224 | uword64 |
a9f7253f JSC |
2225 | AbsoluteValue(op,fmt) |
2226 | uword64 op; | |
2227 | FP_formats fmt; | |
2228 | { | |
50a2a691 | 2229 | uword64 result = 0; |
a9f7253f JSC |
2230 | |
2231 | #ifdef DEBUG | |
53b9417e | 2232 | printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
a9f7253f JSC |
2233 | #endif /* DEBUG */ |
2234 | ||
2235 | /* The format type should already have been checked: */ | |
2236 | switch (fmt) { | |
2237 | case fmt_single: | |
2238 | { | |
76ef4165 FL |
2239 | sim_fpu wop; |
2240 | unsigned32 ans; | |
2241 | sim_fpu_32to (&wop, op); | |
2242 | sim_fpu_abs (&wop, &wop); | |
2243 | sim_fpu_to32 (&ans, &wop); | |
2244 | result = ans; | |
2245 | break; | |
a9f7253f | 2246 | } |
a9f7253f JSC |
2247 | case fmt_double: |
2248 | { | |
76ef4165 FL |
2249 | sim_fpu wop; |
2250 | unsigned64 ans; | |
2251 | sim_fpu_64to (&wop, op); | |
2252 | sim_fpu_abs (&wop, &wop); | |
2253 | sim_fpu_to64 (&ans, &wop); | |
2254 | result = ans; | |
2255 | break; | |
a9f7253f | 2256 | } |
50a2a691 AC |
2257 | default: |
2258 | fprintf (stderr, "Bad switch\n"); | |
2259 | abort (); | |
a9f7253f JSC |
2260 | } |
2261 | ||
2262 | return(result); | |
2263 | } | |
2264 | ||
18c64df6 | 2265 | uword64 |
8bae0a0c | 2266 | Negate(op,fmt) |
e871dd18 | 2267 | uword64 op; |
8bae0a0c JSC |
2268 | FP_formats fmt; |
2269 | { | |
50a2a691 | 2270 | uword64 result = 0; |
8bae0a0c JSC |
2271 | |
2272 | #ifdef DEBUG | |
53b9417e | 2273 | printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2274 | #endif /* DEBUG */ |
2275 | ||
2276 | /* The format type should already have been checked: */ | |
2277 | switch (fmt) { | |
2278 | case fmt_single: | |
2279 | { | |
76ef4165 FL |
2280 | sim_fpu wop; |
2281 | unsigned32 ans; | |
2282 | sim_fpu_32to (&wop, op); | |
2283 | sim_fpu_neg (&wop, &wop); | |
2284 | sim_fpu_to32 (&ans, &wop); | |
2285 | result = ans; | |
2286 | break; | |
8bae0a0c | 2287 | } |
8bae0a0c JSC |
2288 | case fmt_double: |
2289 | { | |
76ef4165 FL |
2290 | sim_fpu wop; |
2291 | unsigned64 ans; | |
2292 | sim_fpu_64to (&wop, op); | |
2293 | sim_fpu_neg (&wop, &wop); | |
2294 | sim_fpu_to64 (&ans, &wop); | |
2295 | result = ans; | |
2296 | break; | |
8bae0a0c | 2297 | } |
50a2a691 AC |
2298 | default: |
2299 | fprintf (stderr, "Bad switch\n"); | |
2300 | abort (); | |
8bae0a0c JSC |
2301 | } |
2302 | ||
2303 | return(result); | |
2304 | } | |
2305 | ||
18c64df6 | 2306 | uword64 |
8bae0a0c | 2307 | Add(op1,op2,fmt) |
e871dd18 JSC |
2308 | uword64 op1; |
2309 | uword64 op2; | |
8bae0a0c JSC |
2310 | FP_formats fmt; |
2311 | { | |
50a2a691 | 2312 | uword64 result = 0; |
8bae0a0c JSC |
2313 | |
2314 | #ifdef DEBUG | |
53b9417e | 2315 | printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2316 | #endif /* DEBUG */ |
2317 | ||
e871dd18 JSC |
2318 | /* The registers must specify FPRs valid for operands of type |
2319 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2320 | |
2321 | /* The format type should already have been checked: */ | |
2322 | switch (fmt) { | |
2323 | case fmt_single: | |
2324 | { | |
76ef4165 FL |
2325 | sim_fpu wop1; |
2326 | sim_fpu wop2; | |
2327 | sim_fpu ans; | |
2328 | unsigned32 res; | |
2329 | sim_fpu_32to (&wop1, op1); | |
2330 | sim_fpu_32to (&wop2, op2); | |
2331 | sim_fpu_add (&ans, &wop1, &wop2); | |
2332 | sim_fpu_to32 (&res, &ans); | |
2333 | result = res; | |
2334 | break; | |
8bae0a0c | 2335 | } |
8bae0a0c JSC |
2336 | case fmt_double: |
2337 | { | |
76ef4165 FL |
2338 | sim_fpu wop1; |
2339 | sim_fpu wop2; | |
2340 | sim_fpu ans; | |
2341 | unsigned64 res; | |
2342 | sim_fpu_64to (&wop1, op1); | |
2343 | sim_fpu_64to (&wop2, op2); | |
2344 | sim_fpu_add (&ans, &wop1, &wop2); | |
2345 | sim_fpu_to64 (&res, &ans); | |
2346 | result = res; | |
2347 | break; | |
8bae0a0c | 2348 | } |
50a2a691 AC |
2349 | default: |
2350 | fprintf (stderr, "Bad switch\n"); | |
2351 | abort (); | |
8bae0a0c JSC |
2352 | } |
2353 | ||
2354 | #ifdef DEBUG | |
53b9417e | 2355 | printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2356 | #endif /* DEBUG */ |
2357 | ||
2358 | return(result); | |
2359 | } | |
2360 | ||
18c64df6 | 2361 | uword64 |
8bae0a0c | 2362 | Sub(op1,op2,fmt) |
e871dd18 JSC |
2363 | uword64 op1; |
2364 | uword64 op2; | |
8bae0a0c JSC |
2365 | FP_formats fmt; |
2366 | { | |
50a2a691 | 2367 | uword64 result = 0; |
8bae0a0c JSC |
2368 | |
2369 | #ifdef DEBUG | |
53b9417e | 2370 | printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2371 | #endif /* DEBUG */ |
2372 | ||
e871dd18 JSC |
2373 | /* The registers must specify FPRs valid for operands of type |
2374 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2375 | |
2376 | /* The format type should already have been checked: */ | |
2377 | switch (fmt) { | |
2378 | case fmt_single: | |
2379 | { | |
76ef4165 FL |
2380 | sim_fpu wop1; |
2381 | sim_fpu wop2; | |
2382 | sim_fpu ans; | |
2383 | unsigned32 res; | |
2384 | sim_fpu_32to (&wop1, op1); | |
2385 | sim_fpu_32to (&wop2, op2); | |
2386 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2387 | sim_fpu_to32 (&res, &ans); | |
2388 | result = res; | |
8bae0a0c JSC |
2389 | } |
2390 | break; | |
2391 | case fmt_double: | |
2392 | { | |
76ef4165 FL |
2393 | sim_fpu wop1; |
2394 | sim_fpu wop2; | |
2395 | sim_fpu ans; | |
2396 | unsigned64 res; | |
2397 | sim_fpu_64to (&wop1, op1); | |
2398 | sim_fpu_64to (&wop2, op2); | |
2399 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2400 | sim_fpu_to64 (&res, &ans); | |
2401 | result = res; | |
8bae0a0c JSC |
2402 | } |
2403 | break; | |
50a2a691 AC |
2404 | default: |
2405 | fprintf (stderr, "Bad switch\n"); | |
2406 | abort (); | |
8bae0a0c JSC |
2407 | } |
2408 | ||
2409 | #ifdef DEBUG | |
53b9417e | 2410 | printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2411 | #endif /* DEBUG */ |
2412 | ||
2413 | return(result); | |
2414 | } | |
2415 | ||
18c64df6 | 2416 | uword64 |
8bae0a0c | 2417 | Multiply(op1,op2,fmt) |
e871dd18 JSC |
2418 | uword64 op1; |
2419 | uword64 op2; | |
8bae0a0c JSC |
2420 | FP_formats fmt; |
2421 | { | |
50a2a691 | 2422 | uword64 result = 0; |
8bae0a0c JSC |
2423 | |
2424 | #ifdef DEBUG | |
53b9417e | 2425 | printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2426 | #endif /* DEBUG */ |
2427 | ||
e871dd18 JSC |
2428 | /* The registers must specify FPRs valid for operands of type |
2429 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2430 | |
2431 | /* The format type should already have been checked: */ | |
2432 | switch (fmt) { | |
2433 | case fmt_single: | |
2434 | { | |
76ef4165 FL |
2435 | sim_fpu wop1; |
2436 | sim_fpu wop2; | |
2437 | sim_fpu ans; | |
2438 | unsigned32 res; | |
2439 | sim_fpu_32to (&wop1, op1); | |
2440 | sim_fpu_32to (&wop2, op2); | |
2441 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2442 | sim_fpu_to32 (&res, &ans); | |
2443 | result = res; | |
2444 | break; | |
8bae0a0c | 2445 | } |
8bae0a0c JSC |
2446 | case fmt_double: |
2447 | { | |
76ef4165 FL |
2448 | sim_fpu wop1; |
2449 | sim_fpu wop2; | |
2450 | sim_fpu ans; | |
2451 | unsigned64 res; | |
2452 | sim_fpu_64to (&wop1, op1); | |
2453 | sim_fpu_64to (&wop2, op2); | |
2454 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2455 | sim_fpu_to64 (&res, &ans); | |
2456 | result = res; | |
2457 | break; | |
8bae0a0c | 2458 | } |
50a2a691 AC |
2459 | default: |
2460 | fprintf (stderr, "Bad switch\n"); | |
2461 | abort (); | |
8bae0a0c JSC |
2462 | } |
2463 | ||
2464 | #ifdef DEBUG | |
53b9417e | 2465 | printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2466 | #endif /* DEBUG */ |
2467 | ||
2468 | return(result); | |
2469 | } | |
2470 | ||
18c64df6 | 2471 | uword64 |
8bae0a0c | 2472 | Divide(op1,op2,fmt) |
e871dd18 JSC |
2473 | uword64 op1; |
2474 | uword64 op2; | |
8bae0a0c JSC |
2475 | FP_formats fmt; |
2476 | { | |
50a2a691 | 2477 | uword64 result = 0; |
8bae0a0c JSC |
2478 | |
2479 | #ifdef DEBUG | |
53b9417e | 2480 | printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2481 | #endif /* DEBUG */ |
2482 | ||
e871dd18 JSC |
2483 | /* The registers must specify FPRs valid for operands of type |
2484 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2485 | |
2486 | /* The format type should already have been checked: */ | |
2487 | switch (fmt) { | |
2488 | case fmt_single: | |
2489 | { | |
76ef4165 FL |
2490 | sim_fpu wop1; |
2491 | sim_fpu wop2; | |
2492 | sim_fpu ans; | |
2493 | unsigned32 res; | |
2494 | sim_fpu_32to (&wop1, op1); | |
2495 | sim_fpu_32to (&wop2, op2); | |
2496 | sim_fpu_div (&ans, &wop1, &wop2); | |
2497 | sim_fpu_to32 (&res, &ans); | |
2498 | result = res; | |
2499 | break; | |
8bae0a0c | 2500 | } |
8bae0a0c JSC |
2501 | case fmt_double: |
2502 | { | |
76ef4165 FL |
2503 | sim_fpu wop1; |
2504 | sim_fpu wop2; | |
2505 | sim_fpu ans; | |
2506 | unsigned64 res; | |
2507 | sim_fpu_64to (&wop1, op1); | |
2508 | sim_fpu_64to (&wop2, op2); | |
2509 | sim_fpu_div (&ans, &wop1, &wop2); | |
2510 | sim_fpu_to64 (&res, &ans); | |
2511 | result = res; | |
2512 | break; | |
8bae0a0c | 2513 | } |
50a2a691 AC |
2514 | default: |
2515 | fprintf (stderr, "Bad switch\n"); | |
2516 | abort (); | |
8bae0a0c JSC |
2517 | } |
2518 | ||
2519 | #ifdef DEBUG | |
53b9417e | 2520 | printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2521 | #endif /* DEBUG */ |
2522 | ||
2523 | return(result); | |
2524 | } | |
2525 | ||
18c64df6 | 2526 | uword64 UNUSED |
8bae0a0c | 2527 | Recip(op,fmt) |
e871dd18 | 2528 | uword64 op; |
8bae0a0c JSC |
2529 | FP_formats fmt; |
2530 | { | |
50a2a691 | 2531 | uword64 result = 0; |
8bae0a0c JSC |
2532 | |
2533 | #ifdef DEBUG | |
53b9417e | 2534 | printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2535 | #endif /* DEBUG */ |
2536 | ||
e871dd18 JSC |
2537 | /* The registers must specify FPRs valid for operands of type |
2538 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2539 | |
2540 | /* The format type should already have been checked: */ | |
2541 | switch (fmt) { | |
2542 | case fmt_single: | |
2543 | { | |
76ef4165 FL |
2544 | sim_fpu wop; |
2545 | sim_fpu ans; | |
2546 | unsigned32 res; | |
2547 | sim_fpu_32to (&wop, op); | |
2548 | sim_fpu_inv (&ans, &wop); | |
2549 | sim_fpu_to32 (&res, &ans); | |
2550 | result = res; | |
2551 | break; | |
8bae0a0c | 2552 | } |
8bae0a0c JSC |
2553 | case fmt_double: |
2554 | { | |
76ef4165 FL |
2555 | sim_fpu wop; |
2556 | sim_fpu ans; | |
2557 | unsigned64 res; | |
2558 | sim_fpu_64to (&wop, op); | |
2559 | sim_fpu_inv (&ans, &wop); | |
2560 | sim_fpu_to64 (&res, &ans); | |
2561 | result = res; | |
2562 | break; | |
8bae0a0c | 2563 | } |
50a2a691 AC |
2564 | default: |
2565 | fprintf (stderr, "Bad switch\n"); | |
2566 | abort (); | |
8bae0a0c JSC |
2567 | } |
2568 | ||
2569 | #ifdef DEBUG | |
53b9417e | 2570 | printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2571 | #endif /* DEBUG */ |
2572 | ||
2573 | return(result); | |
2574 | } | |
2575 | ||
18c64df6 | 2576 | uword64 |
8bae0a0c | 2577 | SquareRoot(op,fmt) |
e871dd18 | 2578 | uword64 op; |
8bae0a0c JSC |
2579 | FP_formats fmt; |
2580 | { | |
50a2a691 | 2581 | uword64 result = 0; |
8bae0a0c JSC |
2582 | |
2583 | #ifdef DEBUG | |
53b9417e | 2584 | printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2585 | #endif /* DEBUG */ |
2586 | ||
e871dd18 JSC |
2587 | /* The registers must specify FPRs valid for operands of type |
2588 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2589 | |
2590 | /* The format type should already have been checked: */ | |
2591 | switch (fmt) { | |
2592 | case fmt_single: | |
2593 | { | |
76ef4165 FL |
2594 | sim_fpu wop; |
2595 | sim_fpu ans; | |
2596 | unsigned32 res; | |
2597 | sim_fpu_32to (&wop, op); | |
2598 | sim_fpu_sqrt (&ans, &wop); | |
2599 | sim_fpu_to32 (&res, &ans); | |
2600 | result = res; | |
2601 | break; | |
8bae0a0c | 2602 | } |
8bae0a0c JSC |
2603 | case fmt_double: |
2604 | { | |
76ef4165 FL |
2605 | sim_fpu wop; |
2606 | sim_fpu ans; | |
2607 | unsigned64 res; | |
2608 | sim_fpu_64to (&wop, op); | |
2609 | sim_fpu_sqrt (&ans, &wop); | |
2610 | sim_fpu_to64 (&res, &ans); | |
2611 | result = res; | |
2612 | break; | |
8bae0a0c | 2613 | } |
50a2a691 AC |
2614 | default: |
2615 | fprintf (stderr, "Bad switch\n"); | |
2616 | abort (); | |
8bae0a0c JSC |
2617 | } |
2618 | ||
2619 | #ifdef DEBUG | |
53b9417e | 2620 | printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2621 | #endif /* DEBUG */ |
2622 | ||
2623 | return(result); | |
2624 | } | |
2625 | ||
82ea14fd | 2626 | #if 0 |
a48e8c8d AC |
2627 | uword64 |
2628 | Max (uword64 op1, | |
2629 | uword64 op2, | |
2630 | FP_formats fmt) | |
2631 | { | |
2632 | int cmp; | |
2633 | unsigned64 result; | |
2634 | ||
2635 | #ifdef DEBUG | |
2636 | printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
2637 | #endif /* DEBUG */ | |
2638 | ||
2639 | /* The registers must specify FPRs valid for operands of type | |
2640 | "fmt". If they are not valid, the result is undefined. */ | |
2641 | ||
2642 | /* The format type should already have been checked: */ | |
2643 | switch (fmt) | |
2644 | { | |
2645 | case fmt_single: | |
2646 | { | |
2647 | sim_fpu wop1; | |
2648 | sim_fpu wop2; | |
2649 | sim_fpu_32to (&wop1, op1); | |
2650 | sim_fpu_32to (&wop2, op2); | |
2651 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
2652 | break; | |
2653 | } | |
2654 | case fmt_double: | |
2655 | { | |
2656 | sim_fpu wop1; | |
2657 | sim_fpu wop2; | |
2658 | sim_fpu_64to (&wop1, op1); | |
2659 | sim_fpu_64to (&wop2, op2); | |
2660 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
2661 | break; | |
2662 | } | |
2663 | default: | |
2664 | fprintf (stderr, "Bad switch\n"); | |
2665 | abort (); | |
2666 | } | |
2667 | ||
2668 | switch (cmp) | |
2669 | { | |
2670 | case SIM_FPU_IS_SNAN: | |
2671 | case SIM_FPU_IS_QNAN: | |
2672 | result = op1; | |
2673 | case SIM_FPU_IS_NINF: | |
2674 | case SIM_FPU_IS_NNUMBER: | |
2675 | case SIM_FPU_IS_NDENORM: | |
2676 | case SIM_FPU_IS_NZERO: | |
2677 | result = op2; /* op1 - op2 < 0 */ | |
2678 | case SIM_FPU_IS_PINF: | |
2679 | case SIM_FPU_IS_PNUMBER: | |
2680 | case SIM_FPU_IS_PDENORM: | |
2681 | case SIM_FPU_IS_PZERO: | |
2682 | result = op1; /* op1 - op2 > 0 */ | |
2683 | default: | |
2684 | fprintf (stderr, "Bad switch\n"); | |
2685 | abort (); | |
2686 | } | |
2687 | ||
2688 | #ifdef DEBUG | |
2689 | printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
2690 | #endif /* DEBUG */ | |
2691 | ||
2692 | return(result); | |
2693 | } | |
82ea14fd | 2694 | #endif |
a48e8c8d | 2695 | |
82ea14fd | 2696 | #if 0 |
a48e8c8d AC |
2697 | uword64 |
2698 | Min (uword64 op1, | |
2699 | uword64 op2, | |
2700 | FP_formats fmt) | |
2701 | { | |
2702 | int cmp; | |
2703 | unsigned64 result; | |
2704 | ||
2705 | #ifdef DEBUG | |
2706 | printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
2707 | #endif /* DEBUG */ | |
2708 | ||
2709 | /* The registers must specify FPRs valid for operands of type | |
2710 | "fmt". If they are not valid, the result is undefined. */ | |
2711 | ||
2712 | /* The format type should already have been checked: */ | |
2713 | switch (fmt) | |
2714 | { | |
2715 | case fmt_single: | |
2716 | { | |
2717 | sim_fpu wop1; | |
2718 | sim_fpu wop2; | |
2719 | sim_fpu_32to (&wop1, op1); | |
2720 | sim_fpu_32to (&wop2, op2); | |
2721 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
2722 | break; | |
2723 | } | |
2724 | case fmt_double: | |
2725 | { | |
2726 | sim_fpu wop1; | |
2727 | sim_fpu wop2; | |
2728 | sim_fpu_64to (&wop1, op1); | |
2729 | sim_fpu_64to (&wop2, op2); | |
2730 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
2731 | break; | |
2732 | } | |
2733 | default: | |
2734 | fprintf (stderr, "Bad switch\n"); | |
2735 | abort (); | |
2736 | } | |
2737 | ||
2738 | switch (cmp) | |
2739 | { | |
2740 | case SIM_FPU_IS_SNAN: | |
2741 | case SIM_FPU_IS_QNAN: | |
2742 | result = op1; | |
2743 | case SIM_FPU_IS_NINF: | |
2744 | case SIM_FPU_IS_NNUMBER: | |
2745 | case SIM_FPU_IS_NDENORM: | |
2746 | case SIM_FPU_IS_NZERO: | |
2747 | result = op1; /* op1 - op2 < 0 */ | |
2748 | case SIM_FPU_IS_PINF: | |
2749 | case SIM_FPU_IS_PNUMBER: | |
2750 | case SIM_FPU_IS_PDENORM: | |
2751 | case SIM_FPU_IS_PZERO: | |
2752 | result = op2; /* op1 - op2 > 0 */ | |
2753 | default: | |
2754 | fprintf (stderr, "Bad switch\n"); | |
2755 | abort (); | |
2756 | } | |
2757 | ||
2758 | #ifdef DEBUG | |
2759 | printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
2760 | #endif /* DEBUG */ | |
2761 | ||
2762 | return(result); | |
2763 | } | |
82ea14fd | 2764 | #endif |
a48e8c8d | 2765 | |
18c64df6 | 2766 | uword64 |
01737f42 AC |
2767 | convert (SIM_DESC sd, |
2768 | sim_cpu *cpu, | |
2769 | address_word cia, | |
2770 | int rm, | |
2771 | uword64 op, | |
2772 | FP_formats from, | |
2773 | FP_formats to) | |
8bae0a0c | 2774 | { |
76ef4165 FL |
2775 | sim_fpu wop; |
2776 | sim_fpu_round round; | |
2777 | unsigned32 result32; | |
2778 | unsigned64 result64; | |
8bae0a0c JSC |
2779 | |
2780 | #ifdef DEBUG | |
53b9417e | 2781 | printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC)); |
8bae0a0c JSC |
2782 | #endif /* DEBUG */ |
2783 | ||
76ef4165 | 2784 | switch (rm) |
8bae0a0c | 2785 | { |
76ef4165 FL |
2786 | case FP_RM_NEAREST: |
2787 | /* Round result to nearest representable value. When two | |
2788 | representable values are equally near, round to the value | |
2789 | that has a least significant bit of zero (i.e. is even). */ | |
2790 | round = sim_fpu_round_near; | |
2791 | break; | |
2792 | case FP_RM_TOZERO: | |
2793 | /* Round result to the value closest to, and not greater in | |
2794 | magnitude than, the result. */ | |
2795 | round = sim_fpu_round_zero; | |
2796 | break; | |
2797 | case FP_RM_TOPINF: | |
2798 | /* Round result to the value closest to, and not less than, | |
2799 | the result. */ | |
2800 | round = sim_fpu_round_up; | |
2801 | break; | |
2802 | ||
2803 | case FP_RM_TOMINF: | |
2804 | /* Round result to the value closest to, and not greater than, | |
2805 | the result. */ | |
2806 | round = sim_fpu_round_down; | |
2807 | break; | |
2808 | default: | |
2809 | round = 0; | |
2810 | fprintf (stderr, "Bad switch\n"); | |
2811 | abort (); | |
8bae0a0c | 2812 | } |
76ef4165 FL |
2813 | |
2814 | /* Convert the input to sim_fpu internal format */ | |
2815 | switch (from) | |
8bae0a0c | 2816 | { |
76ef4165 FL |
2817 | case fmt_double: |
2818 | sim_fpu_64to (&wop, op); | |
2819 | break; | |
2820 | case fmt_single: | |
2821 | sim_fpu_32to (&wop, op); | |
2822 | break; | |
2823 | case fmt_word: | |
2824 | sim_fpu_i32to (&wop, op, round); | |
2825 | break; | |
2826 | case fmt_long: | |
2827 | sim_fpu_i64to (&wop, op, round); | |
2828 | break; | |
2829 | default: | |
2830 | fprintf (stderr, "Bad switch\n"); | |
2831 | abort (); | |
8bae0a0c | 2832 | } |
8bae0a0c | 2833 | |
76ef4165 FL |
2834 | /* Convert sim_fpu format into the output */ |
2835 | /* The value WOP is converted to the destination format, rounding | |
2836 | using mode RM. When the destination is a fixed-point format, then | |
2837 | a source value of Infinity, NaN or one which would round to an | |
2838 | integer outside the fixed point range then an IEEE Invalid | |
2839 | Operation condition is raised. */ | |
2840 | switch (to) | |
2841 | { | |
2842 | case fmt_single: | |
2843 | sim_fpu_round_32 (&wop, round, 0); | |
2844 | sim_fpu_to32 (&result32, &wop); | |
2845 | result64 = result32; | |
2846 | break; | |
2847 | case fmt_double: | |
2848 | sim_fpu_round_64 (&wop, round, 0); | |
2849 | sim_fpu_to64 (&result64, &wop); | |
2850 | break; | |
2851 | case fmt_word: | |
2852 | sim_fpu_to32i (&result32, &wop, round); | |
2853 | result64 = result32; | |
2854 | break; | |
2855 | case fmt_long: | |
2856 | sim_fpu_to64i (&result64, &wop, round); | |
2857 | break; | |
2858 | default: | |
2859 | result64 = 0; | |
2860 | fprintf (stderr, "Bad switch\n"); | |
2861 | abort (); | |
8bae0a0c | 2862 | } |
76ef4165 | 2863 | |
8bae0a0c | 2864 | #ifdef DEBUG |
76ef4165 | 2865 | printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to)); |
8bae0a0c JSC |
2866 | #endif /* DEBUG */ |
2867 | ||
76ef4165 | 2868 | return(result64); |
8bae0a0c | 2869 | } |
8bae0a0c | 2870 | |
76ef4165 | 2871 | |
8bae0a0c JSC |
2872 | /*-- co-processor support routines ------------------------------------------*/ |
2873 | ||
2f2e6c5d | 2874 | static int UNUSED |
8bae0a0c JSC |
2875 | CoProcPresent(coproc_number) |
2876 | unsigned int coproc_number; | |
2877 | { | |
2878 | /* Return TRUE if simulator provides a model for the given co-processor number */ | |
2879 | return(0); | |
2880 | } | |
2881 | ||
18c64df6 | 2882 | void |
01737f42 AC |
2883 | cop_lw (SIM_DESC sd, |
2884 | sim_cpu *cpu, | |
2885 | address_word cia, | |
2886 | int coproc_num, | |
2887 | int coproc_reg, | |
2888 | unsigned int memword) | |
8bae0a0c | 2889 | { |
192ae475 AC |
2890 | switch (coproc_num) |
2891 | { | |
8bae0a0c | 2892 | case 1: |
192ae475 AC |
2893 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
2894 | { | |
8bae0a0c | 2895 | #ifdef DEBUG |
192ae475 | 2896 | printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword)); |
8bae0a0c | 2897 | #endif |
192ae475 AC |
2898 | StoreFPR(coproc_reg,fmt_word,(uword64)memword); |
2899 | FPR_STATE[coproc_reg] = fmt_uninterpreted; | |
2900 | break; | |
2901 | } | |
8bae0a0c JSC |
2902 | |
2903 | default: | |
f24b7b69 | 2904 | #if 0 /* this should be controlled by a configuration option */ |
192ae475 | 2905 | sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia)); |
f24b7b69 | 2906 | #endif |
192ae475 AC |
2907 | break; |
2908 | } | |
8bae0a0c JSC |
2909 | |
2910 | return; | |
2911 | } | |
2912 | ||
18c64df6 | 2913 | void |
01737f42 AC |
2914 | cop_ld (SIM_DESC sd, |
2915 | sim_cpu *cpu, | |
2916 | address_word cia, | |
2917 | int coproc_num, | |
2918 | int coproc_reg, | |
2919 | uword64 memword) | |
8bae0a0c JSC |
2920 | { |
2921 | switch (coproc_num) { | |
8bae0a0c | 2922 | case 1: |
192ae475 AC |
2923 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
2924 | { | |
2925 | StoreFPR(coproc_reg,fmt_uninterpreted,memword); | |
2926 | break; | |
2927 | } | |
8bae0a0c JSC |
2928 | |
2929 | default: | |
f24b7b69 | 2930 | #if 0 /* this message should be controlled by a configuration option */ |
95469ceb | 2931 | sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia)); |
f24b7b69 | 2932 | #endif |
8bae0a0c JSC |
2933 | break; |
2934 | } | |
2935 | ||
2936 | return; | |
2937 | } | |
2938 | ||
15232df4 | 2939 | |
6ed00b06 FCE |
2940 | /* start-sanitize-sky */ |
2941 | #ifdef TARGET_SKY | |
15232df4 FCE |
2942 | void |
2943 | cop_lq (SIM_DESC sd, | |
2944 | sim_cpu *cpu, | |
2945 | address_word cia, | |
2946 | int coproc_num, | |
2947 | int coproc_reg, | |
2948 | unsigned128 memword) | |
2949 | { | |
2950 | switch (coproc_num) | |
2951 | { | |
15232df4 | 2952 | case 2: |
2ebb2a68 FCE |
2953 | { |
2954 | unsigned_16 xyzw; | |
2955 | ||
2956 | while(vu0_busy()) | |
2957 | vu0_issue(sd); | |
2958 | ||
2959 | memcpy(& xyzw, & memword, sizeof(xyzw)); | |
2960 | xyzw = H2T_16(xyzw); | |
2961 | /* one word at a time, argh! */ | |
2962 | write_vu_vec_reg(&(vu0_device.regs), coproc_reg, 0, A4_16(& xyzw, 3)); | |
2963 | write_vu_vec_reg(&(vu0_device.regs), coproc_reg, 1, A4_16(& xyzw, 2)); | |
2964 | write_vu_vec_reg(&(vu0_device.regs), coproc_reg, 2, A4_16(& xyzw, 1)); | |
2965 | write_vu_vec_reg(&(vu0_device.regs), coproc_reg, 3, A4_16(& xyzw, 0)); | |
2966 | } | |
2967 | break; | |
2968 | ||
15232df4 FCE |
2969 | default: |
2970 | sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n", | |
2971 | coproc_num,coproc_reg,pr_addr(cia)); | |
2972 | break; | |
2973 | } | |
2974 | ||
2975 | return; | |
2976 | } | |
6ed00b06 FCE |
2977 | #endif /* TARGET_SKY */ |
2978 | /* end-sanitize-sky */ | |
15232df4 FCE |
2979 | |
2980 | ||
18c64df6 | 2981 | unsigned int |
01737f42 AC |
2982 | cop_sw (SIM_DESC sd, |
2983 | sim_cpu *cpu, | |
2984 | address_word cia, | |
2985 | int coproc_num, | |
2986 | int coproc_reg) | |
8bae0a0c JSC |
2987 | { |
2988 | unsigned int value = 0; | |
da0bce9c | 2989 | |
192ae475 AC |
2990 | switch (coproc_num) |
2991 | { | |
8bae0a0c | 2992 | case 1: |
192ae475 AC |
2993 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
2994 | { | |
2995 | FP_formats hold; | |
2996 | hold = FPR_STATE[coproc_reg]; | |
2997 | FPR_STATE[coproc_reg] = fmt_word; | |
2998 | value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted); | |
2999 | FPR_STATE[coproc_reg] = hold; | |
3000 | break; | |
3001 | } | |
8bae0a0c JSC |
3002 | |
3003 | default: | |
f24b7b69 | 3004 | #if 0 /* should be controlled by configuration option */ |
192ae475 | 3005 | sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); |
f24b7b69 | 3006 | #endif |
192ae475 AC |
3007 | break; |
3008 | } | |
8bae0a0c JSC |
3009 | |
3010 | return(value); | |
3011 | } | |
3012 | ||
18c64df6 | 3013 | uword64 |
01737f42 AC |
3014 | cop_sd (SIM_DESC sd, |
3015 | sim_cpu *cpu, | |
3016 | address_word cia, | |
3017 | int coproc_num, | |
3018 | int coproc_reg) | |
8bae0a0c | 3019 | { |
e871dd18 | 3020 | uword64 value = 0; |
192ae475 AC |
3021 | switch (coproc_num) |
3022 | { | |
8bae0a0c | 3023 | case 1: |
192ae475 AC |
3024 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3025 | { | |
3026 | value = ValueFPR(coproc_reg,fmt_uninterpreted); | |
3027 | break; | |
3028 | } | |
8bae0a0c JSC |
3029 | |
3030 | default: | |
f24b7b69 | 3031 | #if 0 /* should be controlled by configuration option */ |
192ae475 | 3032 | sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); |
f24b7b69 | 3033 | #endif |
192ae475 AC |
3034 | break; |
3035 | } | |
8bae0a0c JSC |
3036 | |
3037 | return(value); | |
3038 | } | |
3039 | ||
15232df4 | 3040 | |
6ed00b06 FCE |
3041 | /* start-sanitize-sky */ |
3042 | #ifdef TARGET_SKY | |
15232df4 FCE |
3043 | unsigned128 |
3044 | cop_sq (SIM_DESC sd, | |
3045 | sim_cpu *cpu, | |
3046 | address_word cia, | |
3047 | int coproc_num, | |
3048 | int coproc_reg) | |
3049 | { | |
6ed00b06 | 3050 | unsigned128 value = U16_8(0, 0); |
15232df4 FCE |
3051 | switch (coproc_num) |
3052 | { | |
15232df4 | 3053 | case 2: |
2ebb2a68 FCE |
3054 | { |
3055 | unsigned_16 xyzw; | |
3056 | ||
3057 | while(vu0_busy()) | |
3058 | vu0_issue(sd); | |
3059 | ||
3060 | /* one word at a time, argh! */ | |
3061 | read_vu_vec_reg(&(vu0_device.regs), coproc_reg, 0, A4_16(& xyzw, 3)); | |
3062 | read_vu_vec_reg(&(vu0_device.regs), coproc_reg, 1, A4_16(& xyzw, 2)); | |
3063 | read_vu_vec_reg(&(vu0_device.regs), coproc_reg, 2, A4_16(& xyzw, 1)); | |
3064 | read_vu_vec_reg(&(vu0_device.regs), coproc_reg, 3, A4_16(& xyzw, 0)); | |
3065 | xyzw = T2H_16(xyzw); | |
3066 | return xyzw; | |
3067 | } | |
3068 | break; | |
3069 | ||
15232df4 FCE |
3070 | default: |
3071 | sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n", | |
3072 | coproc_num,coproc_reg,pr_addr(cia)); | |
3073 | break; | |
3074 | } | |
3075 | ||
3076 | return(value); | |
3077 | } | |
6ed00b06 FCE |
3078 | #endif /* TARGET_SKY */ |
3079 | /* end-sanitize-sky */ | |
15232df4 FCE |
3080 | |
3081 | ||
ea985d24 | 3082 | void |
01737f42 AC |
3083 | decode_coproc (SIM_DESC sd, |
3084 | sim_cpu *cpu, | |
3085 | address_word cia, | |
3086 | unsigned int instruction) | |
8bae0a0c JSC |
3087 | { |
3088 | int coprocnum = ((instruction >> 26) & 3); | |
3089 | ||
56e7c849 AC |
3090 | switch (coprocnum) |
3091 | { | |
8bae0a0c JSC |
3092 | case 0: /* standard CPU control and cache registers */ |
3093 | { | |
8bae0a0c JSC |
3094 | int code = ((instruction >> 21) & 0x1F); |
3095 | /* R4000 Users Manual (second edition) lists the following CP0 | |
3096 | instructions: | |
56e7c849 AC |
3097 | DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000) |
3098 | DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000) | |
3099 | MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000) | |
3100 | MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000) | |
3101 | TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001) | |
3102 | TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010) | |
3103 | TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110) | |
3104 | TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000) | |
3105 | CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) | |
3106 | ERET Exception return (VR4100 = 01000010000000000000000000011000) | |
3107 | */ | |
3108 | if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) | |
3109 | { | |
3110 | int rt = ((instruction >> 16) & 0x1F); | |
3111 | int rd = ((instruction >> 11) & 0x1F); | |
3112 | ||
3113 | switch (rd) /* NOTEs: Standard CP0 registers */ | |
3114 | { | |
3115 | /* 0 = Index R4000 VR4100 VR4300 */ | |
3116 | /* 1 = Random R4000 VR4100 VR4300 */ | |
3117 | /* 2 = EntryLo0 R4000 VR4100 VR4300 */ | |
3118 | /* 3 = EntryLo1 R4000 VR4100 VR4300 */ | |
3119 | /* 4 = Context R4000 VR4100 VR4300 */ | |
3120 | /* 5 = PageMask R4000 VR4100 VR4300 */ | |
3121 | /* 6 = Wired R4000 VR4100 VR4300 */ | |
3122 | /* 8 = BadVAddr R4000 VR4100 VR4300 */ | |
3123 | /* 9 = Count R4000 VR4100 VR4300 */ | |
3124 | /* 10 = EntryHi R4000 VR4100 VR4300 */ | |
3125 | /* 11 = Compare R4000 VR4100 VR4300 */ | |
3126 | /* 12 = SR R4000 VR4100 VR4300 */ | |
3127 | case 12: | |
3128 | if (code == 0x00) | |
3129 | GPR[rt] = SR; | |
3130 | else | |
3131 | SR = GPR[rt]; | |
3132 | break; | |
3133 | /* 13 = Cause R4000 VR4100 VR4300 */ | |
05d1322f JL |
3134 | case 13: |
3135 | if (code == 0x00) | |
3136 | GPR[rt] = CAUSE; | |
3137 | else | |
3138 | CAUSE = GPR[rt]; | |
3139 | break; | |
56e7c849 AC |
3140 | /* 14 = EPC R4000 VR4100 VR4300 */ |
3141 | /* 15 = PRId R4000 VR4100 VR4300 */ | |
6eedf3f4 MA |
3142 | #ifdef SUBTARGET_R3900 |
3143 | /* 16 = Debug */ | |
3144 | case 16: | |
3145 | if (code == 0x00) | |
3146 | GPR[rt] = Debug; | |
3147 | else | |
3148 | Debug = GPR[rt]; | |
3149 | break; | |
3150 | #else | |
56e7c849 | 3151 | /* 16 = Config R4000 VR4100 VR4300 */ |
a09a30d2 AC |
3152 | case 16: |
3153 | if (code == 0x00) | |
3154 | GPR[rt] = C0_CONFIG; | |
3155 | else | |
3156 | C0_CONFIG = GPR[rt]; | |
3157 | break; | |
6eedf3f4 MA |
3158 | #endif |
3159 | #ifdef SUBTARGET_R3900 | |
3160 | /* 17 = Debug */ | |
3161 | case 17: | |
3162 | if (code == 0x00) | |
3163 | GPR[rt] = DEPC; | |
3164 | else | |
3165 | DEPC = GPR[rt]; | |
3166 | break; | |
3167 | #else | |
56e7c849 | 3168 | /* 17 = LLAddr R4000 VR4100 VR4300 */ |
6eedf3f4 | 3169 | #endif |
56e7c849 AC |
3170 | /* 18 = WatchLo R4000 VR4100 VR4300 */ |
3171 | /* 19 = WatchHi R4000 VR4100 VR4300 */ | |
3172 | /* 20 = XContext R4000 VR4100 VR4300 */ | |
3173 | /* 26 = PErr or ECC R4000 VR4100 VR4300 */ | |
3174 | /* 27 = CacheErr R4000 VR4100 */ | |
3175 | /* 28 = TagLo R4000 VR4100 VR4300 */ | |
3176 | /* 29 = TagHi R4000 VR4100 VR4300 */ | |
3177 | /* 30 = ErrorEPC R4000 VR4100 VR4300 */ | |
3178 | GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */ | |
3179 | /* CPR[0,rd] = GPR[rt]; */ | |
3180 | default: | |
3181 | if (code == 0x00) | |
18c64df6 | 3182 | sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 | 3183 | else |
18c64df6 | 3184 | sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 AC |
3185 | } |
3186 | } | |
3187 | else if (code == 0x10 && (instruction & 0x3f) == 0x18) | |
3188 | { | |
3189 | /* ERET */ | |
3190 | if (SR & status_ERL) | |
3191 | { | |
3192 | /* Oops, not yet available */ | |
18c64df6 | 3193 | sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet"); |
56e7c849 AC |
3194 | PC = EPC; |
3195 | SR &= ~status_ERL; | |
3196 | } | |
3197 | else | |
3198 | { | |
3199 | PC = EPC; | |
3200 | SR &= ~status_EXL; | |
3201 | } | |
3202 | } | |
6eedf3f4 MA |
3203 | else if (code == 0x10 && (instruction & 0x3f) == 0x10) |
3204 | { | |
3205 | /* RFE */ | |
3206 | } | |
3207 | else if (code == 0x10 && (instruction & 0x3f) == 0x1F) | |
3208 | { | |
3209 | /* DERET */ | |
3210 | Debug &= ~Debug_DM; | |
3211 | DELAYSLOT(); | |
3212 | DSPC = DEPC; | |
3213 | } | |
56e7c849 | 3214 | else |
95469ceb | 3215 | sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia)); |
e871dd18 | 3216 | /* TODO: When executing an ERET or RFE instruction we should |
8bae0a0c JSC |
3217 | clear LLBIT, to ensure that any out-standing atomic |
3218 | read/modify/write sequence fails. */ | |
3219 | } | |
56e7c849 AC |
3220 | break; |
3221 | ||
ebcfd86a | 3222 | case 2: /* co-processor 2 */ |
15232df4 FCE |
3223 | { |
3224 | int handle = 0; | |
3225 | ||
3226 | /* start-sanitize-sky */ | |
7dd4a466 | 3227 | #ifdef TARGET_SKY |
15232df4 FCE |
3228 | /* On the R5900, this refers to a "VU" vector co-processor. */ |
3229 | ||
3230 | int i_25_21 = (instruction >> 21) & 0x1f; | |
3231 | int i_20_16 = (instruction >> 16) & 0x1f; | |
ebcfd86a | 3232 | int i_20_6 = (instruction >> 6) & 0x7fff; |
15232df4 FCE |
3233 | int i_15_11 = (instruction >> 11) & 0x1f; |
3234 | int i_15_0 = instruction & 0xffff; | |
3235 | int i_10_1 = (instruction >> 1) & 0x3ff; | |
ebcfd86a FCE |
3236 | int i_10_0 = instruction & 0x7ff; |
3237 | int i_10_6 = (instruction >> 6) & 0x1f; | |
6ed00b06 | 3238 | int i_5_0 = instruction & 0x03f; |
15232df4 | 3239 | int interlock = instruction & 0x01; |
15232df4 FCE |
3240 | /* setup for semantic.c-like actions below */ |
3241 | typedef unsigned_4 instruction_word; | |
3242 | int CIA = cia; | |
3243 | int NIA = cia + 4; | |
15232df4 FCE |
3244 | |
3245 | handle = 1; | |
3246 | ||
3247 | /* test COP2 usability */ | |
3248 | if(! (SR & status_CU2)) | |
3249 | { | |
3250 | SignalException(CoProcessorUnusable,instruction); | |
3251 | /* NOTREACHED */ | |
3252 | } | |
3253 | ||
46399a00 FCE |
3254 | #define MY_INDEX itable_COPz_NORMAL |
3255 | #define MY_PREFIX COPz_NORMAL | |
3256 | #define MY_NAME "COPz_NORMAL" | |
3257 | ||
15232df4 FCE |
3258 | /* classify & execute basic COP2 instructions */ |
3259 | if(i_25_21 == 0x08 && i_20_16 == 0x00) /* BC2F */ | |
3260 | { | |
3261 | address_word offset = EXTEND16(i_15_0) << 2; | |
6ed00b06 | 3262 | if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset); |
15232df4 FCE |
3263 | } |
3264 | else if(i_25_21 == 0x08 && i_20_16==0x02) /* BC2FL */ | |
3265 | { | |
3266 | address_word offset = EXTEND16(i_15_0) << 2; | |
6ed00b06 | 3267 | if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset); |
15232df4 FCE |
3268 | else NULLIFY_NEXT_INSTRUCTION(); |
3269 | } | |
3270 | else if(i_25_21 == 0x08 && i_20_16 == 0x01) /* BC2T */ | |
3271 | { | |
3272 | address_word offset = EXTEND16(i_15_0) << 2; | |
6ed00b06 | 3273 | if(vu0_busy()) DELAY_SLOT(cia + 4 + offset); |
15232df4 FCE |
3274 | } |
3275 | else if(i_25_21 == 0x08 && i_20_16 == 0x03) /* BC2TL */ | |
3276 | { | |
3277 | address_word offset = EXTEND16(i_15_0) << 2; | |
6ed00b06 | 3278 | if(vu0_busy()) DELAY_SLOT(cia + 4 + offset); |
15232df4 FCE |
3279 | else NULLIFY_NEXT_INSTRUCTION(); |
3280 | } | |
3281 | else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */ | |
6ed00b06 | 3282 | (i_25_21 == 0x01)) /* QMFC2 */ |
15232df4 FCE |
3283 | { |
3284 | int rt = i_20_16; | |
3285 | int id = i_15_11; | |
15232df4 | 3286 | |
6ed00b06 | 3287 | /* interlock checking */ |
ebcfd86a FCE |
3288 | /* POLICY: never busy in macro mode */ |
3289 | while(vu0_busy() && interlock) | |
3290 | vu0_issue(sd); | |
6ed00b06 | 3291 | |
ebcfd86a FCE |
3292 | /* perform VU register address */ |
3293 | if(i_25_21 == 0x01) /* QMFC2 */ | |
15232df4 | 3294 | { |
ebcfd86a FCE |
3295 | unsigned_16 xyzw; |
3296 | /* one word at a time, argh! */ | |
3297 | read_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3)); | |
3298 | read_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2)); | |
3299 | read_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1)); | |
3300 | read_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0)); | |
3301 | xyzw = T2H_16(xyzw); | |
3302 | memcpy(& GPR[rt], & xyzw, sizeof(xyzw)); | |
15232df4 | 3303 | } |
6ed00b06 | 3304 | else /* CFC2 */ |
ebcfd86a FCE |
3305 | { |
3306 | unsigned_4 data; | |
3307 | /* enum + int calculation, argh! */ | |
3308 | id = VU_REG_MST + 16 * id; | |
3309 | read_vu_misc_reg(&(vu0_device.regs), id, & data); | |
3310 | GPR[rt] = EXTEND32(T2H_4(data)); | |
3311 | } | |
15232df4 | 3312 | } |
6ed00b06 FCE |
3313 | else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */ |
3314 | (i_25_21 == 0x05)) /* QMTC2 */ | |
15232df4 FCE |
3315 | { |
3316 | int rt = i_20_16; | |
3317 | int id = i_15_11; | |
15232df4 | 3318 | |
fc4e5b84 | 3319 | /* interlock checking: wait until M or E bits set */ |
ebcfd86a | 3320 | /* POLICY: never busy in macro mode */ |
fc4e5b84 | 3321 | while(vu0_busy() && interlock) |
15232df4 | 3322 | { |
fc4e5b84 FCE |
3323 | if(vu0_micro_interlock_released()) |
3324 | { | |
3325 | vu0_micro_interlock_clear(); | |
3326 | break; | |
3327 | } | |
3328 | ||
3329 | vu0_issue(sd); | |
15232df4 | 3330 | } |
ebcfd86a FCE |
3331 | |
3332 | /* perform VU register address */ | |
3333 | if(i_25_21 == 0x05) /* QMTC2 */ | |
15232df4 | 3334 | { |
ebcfd86a FCE |
3335 | unsigned_16 xyzw; |
3336 | memcpy(& xyzw, & GPR[rt], sizeof(xyzw)); | |
3337 | xyzw = H2T_16(xyzw); | |
3338 | /* one word at a time, argh! */ | |
3339 | write_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3)); | |
3340 | write_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2)); | |
3341 | write_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1)); | |
3342 | write_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0)); | |
15232df4 | 3343 | } |
6ed00b06 | 3344 | else /* CTC2 */ |
ebcfd86a FCE |
3345 | { |
3346 | unsigned_4 data = H2T_4(GPR[rt]); | |
3347 | /* enum + int calculation, argh! */ | |
3348 | id = VU_REG_MST + 16 * id; | |
3349 | write_vu_misc_reg(&(vu0_device.regs), id, & data); | |
3350 | } | |
3351 | } | |
3352 | else if(i_10_0 == 0x3bf) /* VWAITQ */ | |
3353 | { | |
3354 | while(vu0_q_busy()) | |
3355 | vu0_issue(sd); | |
3356 | } | |
3357 | else if(i_5_0 == 0x38) /* VCALLMS */ | |
3358 | { | |
3359 | unsigned_4 data = H2T_2(i_20_6); | |
3360 | ||
3361 | while(vu0_busy()) | |
3362 | vu0_issue(sd); | |
3363 | ||
3364 | /* write to reserved CIA register to get VU0 moving */ | |
11c47f31 FCE |
3365 | write_vu_special_reg(& vu0_device, VU_REG_CIA, & data); |
3366 | ||
3367 | ASSERT(vu0_busy()); | |
ebcfd86a FCE |
3368 | } |
3369 | else if(i_5_0 == 0x39) /* VCALLMSR */ | |
3370 | { | |
3371 | unsigned_4 data; | |
3372 | ||
3373 | while(vu0_busy()) | |
3374 | vu0_issue(sd); | |
6ed00b06 | 3375 | |
11c47f31 | 3376 | read_vu_special_reg(& vu0_device, VU_REG_CMSAR0, & data); |
ebcfd86a | 3377 | /* write to reserved CIA register to get VU0 moving */ |
11c47f31 FCE |
3378 | write_vu_special_reg(& vu0_device, VU_REG_CIA, & data); |
3379 | ||
3380 | ASSERT(vu0_busy()); | |
6ed00b06 | 3381 | } |
ebcfd86a FCE |
3382 | /* handle all remaining UPPER VU instructions in one block */ |
3383 | else if((i_5_0 < 0x30) || /* VADDx .. VMINI */ | |
3384 | (i_5_0 >= 0x3c && i_10_6 < 0x0c)) /* VADDAx .. VNOP */ | |
6ed00b06 FCE |
3385 | { |
3386 | unsigned_4 vu_upper, vu_lower; | |
3387 | vu_upper = | |
174ff224 | 3388 | 0x00000000 | /* bits 31 .. 25 */ |
ebcfd86a | 3389 | (instruction & 0x01ffffff); /* bits 24 .. 0 */ |
6ed00b06 FCE |
3390 | vu_lower = 0x8000033c; /* NOP */ |
3391 | ||
ebcfd86a FCE |
3392 | /* POLICY: never busy in macro mode */ |
3393 | while(vu0_busy()) | |
6ed00b06 FCE |
3394 | vu0_issue(sd); |
3395 | ||
3396 | vu0_macro_issue(vu_upper, vu_lower); | |
ebcfd86a FCE |
3397 | |
3398 | /* POLICY: wait for completion of macro-instruction */ | |
3399 | while(vu0_busy()) | |
3400 | vu0_issue(sd); | |
6ed00b06 | 3401 | } |
ebcfd86a FCE |
3402 | /* handle all remaining LOWER VU instructions in one block */ |
3403 | else if((i_5_0 >= 0x30 && i_5_0 <= 0x35) || /* VIADD .. VIOR */ | |
3404 | (i_5_0 >= 0x3c && i_10_6 >= 0x0c)) /* VMOVE .. VRXOR */ | |
3405 | { /* N.B.: VWAITQ already covered by prior case */ | |
6ed00b06 | 3406 | unsigned_4 vu_upper, vu_lower; |
174ff224 | 3407 | vu_upper = 0x000002ff; /* NOP/NOP */ |
6ed00b06 | 3408 | vu_lower = |
96a4eb30 | 3409 | 0x80000000 | /* bits 31 .. 25 */ |
ebcfd86a | 3410 | (instruction & 0x01ffffff); /* bits 24 .. 0 */ |
6ed00b06 | 3411 | |
ebcfd86a FCE |
3412 | /* POLICY: never busy in macro mode */ |
3413 | while(vu0_busy()) | |
6ed00b06 FCE |
3414 | vu0_issue(sd); |
3415 | ||
3416 | vu0_macro_issue(vu_upper, vu_lower); | |
ebcfd86a FCE |
3417 | |
3418 | /* POLICY: wait for completion of macro-instruction */ | |
3419 | while(vu0_busy()) | |
3420 | vu0_issue(sd); | |
15232df4 | 3421 | } |
ebcfd86a | 3422 | /* ... no other COP2 instructions ... */ |
15232df4 FCE |
3423 | else |
3424 | { | |
6ed00b06 | 3425 | SignalException(ReservedInstruction, instruction); |
15232df4 FCE |
3426 | /* NOTREACHED */ |
3427 | } | |
3428 | ||
3429 | /* cleanup for semantic.c-like actions above */ | |
3430 | PC = NIA; | |
3431 | ||
46399a00 FCE |
3432 | #undef MY_INDEX |
3433 | #undef MY_PREFIX | |
3434 | #undef MY_NAME | |
3435 | ||
7dd4a466 | 3436 | #endif /* TARGET_SKY */ |
15232df4 FCE |
3437 | /* end-sanitize-sky */ |
3438 | ||
3439 | if(! handle) | |
3440 | { | |
ebcfd86a | 3441 | sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n", |
15232df4 FCE |
3442 | instruction,pr_addr(cia)); |
3443 | } | |
3444 | } | |
3445 | break; | |
3446 | ||
8bae0a0c JSC |
3447 | case 1: /* should not occur (FPU co-processor) */ |
3448 | case 3: /* should not occur (FPU co-processor) */ | |
3449 | SignalException(ReservedInstruction,instruction); | |
3450 | break; | |
56e7c849 AC |
3451 | } |
3452 | ||
8bae0a0c JSC |
3453 | return; |
3454 | } | |
3455 | ||
15232df4 | 3456 | |
8bae0a0c JSC |
3457 | /*-- instruction simulation -------------------------------------------------*/ |
3458 | ||
16bd5d6e AC |
3459 | /* When the IGEN simulator is being built, the function below is be |
3460 | replaced by a generated version. However, WITH_IGEN == 2 indicates | |
3461 | that the fubction below should be compiled but under a different | |
3462 | name (to allow backward compatibility) */ | |
3463 | ||
3464 | #if (WITH_IGEN != 1) | |
3465 | #if (WITH_IGEN > 1) | |
dad6f1f3 AC |
3466 | void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal)); |
3467 | void | |
9ec6741b | 3468 | old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) |
dad6f1f3 | 3469 | #else |
2e61a3ad | 3470 | void |
9ec6741b | 3471 | sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) |
dad6f1f3 | 3472 | #endif |
2e61a3ad AC |
3473 | SIM_DESC sd; |
3474 | int next_cpu_nr; /* ignore */ | |
9ec6741b | 3475 | int nr_cpus; /* ignore */ |
2e61a3ad | 3476 | int siggnal; /* ignore */ |
8bae0a0c | 3477 | { |
01737f42 | 3478 | sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */ |
50a2a691 | 3479 | #if !defined(FASTSIM) |
8bae0a0c | 3480 | unsigned int pipeline_count = 1; |
50a2a691 | 3481 | #endif |
8bae0a0c JSC |
3482 | |
3483 | #ifdef DEBUG | |
50a2a691 | 3484 | if (STATE_MEMORY (sd) == NULL) { |
8bae0a0c JSC |
3485 | printf("DBG: simulate() entered with no memory\n"); |
3486 | exit(1); | |
3487 | } | |
3488 | #endif /* DEBUG */ | |
3489 | ||
3490 | #if 0 /* Disabled to check that everything works OK */ | |
3491 | /* The VR4300 seems to sign-extend the PC on its first | |
3492 | access. However, this may just be because it is currently | |
3493 | configured in 32bit mode. However... */ | |
3494 | PC = SIGNEXTEND(PC,32); | |
3495 | #endif | |
3496 | ||
3497 | /* main controlling loop */ | |
2e61a3ad | 3498 | while (1) { |
7ce8b917 AC |
3499 | /* vaddr is slowly being replaced with cia - current instruction |
3500 | address */ | |
3501 | address_word cia = (uword64)PC; | |
3502 | address_word vaddr = cia; | |
dad6f1f3 | 3503 | address_word paddr; |
8bae0a0c | 3504 | int cca; |
53b9417e | 3505 | unsigned int instruction; /* uword64? what's this used for? FIXME! */ |
8bae0a0c JSC |
3506 | |
3507 | #ifdef DEBUG | |
3508 | { | |
3509 | printf("DBG: state = 0x%08X :",state); | |
8bae0a0c JSC |
3510 | if (state & simHALTEX) printf(" simHALTEX"); |
3511 | if (state & simHALTIN) printf(" simHALTIN"); | |
53b9417e | 3512 | printf("\n"); |
8bae0a0c JSC |
3513 | } |
3514 | #endif /* DEBUG */ | |
3515 | ||
0c2c5f61 | 3516 | DSSTATE = (STATE & simDELAYSLOT); |
8bae0a0c JSC |
3517 | #ifdef DEBUG |
3518 | if (dsstate) | |
18c64df6 | 3519 | sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3520 | #endif /* DEBUG */ |
3521 | ||
7ce8b917 AC |
3522 | /* Fetch the next instruction from the simulator memory: */ |
3523 | if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { | |
6429b296 JW |
3524 | if ((vaddr & 1) == 0) { |
3525 | /* Copy the action of the LW instruction */ | |
3526 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
3527 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
3528 | uword64 value; | |
3529 | unsigned int byte; | |
3530 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
53b9417e | 3531 | LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL); |
6429b296 JW |
3532 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); |
3533 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
3534 | } else { | |
3535 | /* Copy the action of the LH instruction */ | |
3536 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0); | |
3537 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0); | |
3538 | uword64 value; | |
3539 | unsigned int byte; | |
3540 | paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK) | |
3541 | | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1))); | |
53b9417e | 3542 | LoadMemory(&value,NULL,cca, AccessLength_HALFWORD, |
6429b296 JW |
3543 | paddr & ~ (uword64) 1, |
3544 | vaddr, isINSTRUCTION, isREAL); | |
3545 | byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1)); | |
3546 | instruction = ((value >> (8 * byte)) & 0xFFFF); | |
3547 | } | |
8bae0a0c | 3548 | } else { |
53b9417e | 3549 | fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC)); |
8bae0a0c JSC |
3550 | exit(1); |
3551 | } | |
3552 | ||
3553 | #ifdef DEBUG | |
18c64df6 | 3554 | sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC)); |
8bae0a0c JSC |
3555 | #endif /* DEBUG */ |
3556 | ||
8bae0a0c JSC |
3557 | /* This is required by exception processing, to ensure that we can |
3558 | cope with exceptions in the delay slots of branches that may | |
3559 | already have changed the PC. */ | |
6429b296 JW |
3560 | if ((vaddr & 1) == 0) |
3561 | PC += 4; /* increment ready for the next fetch */ | |
3562 | else | |
3563 | PC += 2; | |
8bae0a0c JSC |
3564 | /* NOTE: If we perform a delay slot change to the PC, this |
3565 | increment is not requuired. However, it would make the | |
3566 | simulator more complicated to try and avoid this small hit. */ | |
3567 | ||
3568 | /* Currently this code provides a simple model. For more | |
3569 | complicated models we could perform exception status checks at | |
3570 | this point, and set the simSTOP state as required. This could | |
3571 | also include processing any hardware interrupts raised by any | |
3572 | I/O model attached to the simulator context. | |
3573 | ||
3574 | Support for "asynchronous" I/O events within the simulated world | |
3575 | could be providing by managing a counter, and calling a I/O | |
3576 | specific handler when a particular threshold is reached. On most | |
3577 | architectures a decrement and check for zero operation is | |
3578 | usually quicker than an increment and compare. However, the | |
3579 | process of managing a known value decrement to zero, is higher | |
3580 | than the cost of using an explicit value UINT_MAX into the | |
3581 | future. Which system is used will depend on how complicated the | |
3582 | I/O model is, and how much it is likely to affect the simulator | |
3583 | bandwidth. | |
3584 | ||
3585 | If events need to be scheduled further in the future than | |
3586 | UINT_MAX event ticks, then the I/O model should just provide its | |
3587 | own counter, triggered from the event system. */ | |
3588 | ||
3589 | /* MIPS pipeline ticks. To allow for future support where the | |
3590 | pipeline hit of individual instructions is known, this control | |
3591 | loop manages a "pipeline_count" variable. It is initialised to | |
3592 | 1 (one), and will only be changed by the simulator engine when | |
3593 | executing an instruction. If the engine does not have access to | |
3594 | pipeline cycle count information then all instructions will be | |
3595 | treated as using a single cycle. NOTE: A standard system is not | |
3596 | provided by the default simulator because different MIPS | |
3597 | architectures have different cycle counts for the same | |
50a2a691 AC |
3598 | instructions. |
3599 | ||
3600 | [NOTE: pipeline_count has been replaced the event queue] */ | |
8bae0a0c | 3601 | |
a09a30d2 AC |
3602 | /* shuffle the floating point status pipeline state */ |
3603 | ENGINE_ISSUE_PREFIX_HOOK(); | |
8bae0a0c JSC |
3604 | |
3605 | /* NOTE: For multi-context simulation environments the "instruction" | |
3606 | variable should be local to this routine. */ | |
3607 | ||
3608 | /* Shorthand accesses for engine. Note: If we wanted to use global | |
3609 | variables (and a single-threaded simulator engine), then we can | |
3610 | create the actual variables with these names. */ | |
3611 | ||
0c2c5f61 | 3612 | if (!(STATE & simSKIPNEXT)) { |
8bae0a0c | 3613 | /* Include the simulator engine */ |
284e759d | 3614 | #include "oengine.c" |
f24b7b69 | 3615 | #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT) |
8bae0a0c JSC |
3616 | #error "Mismatch between run-time simulator code and simulation engine" |
3617 | #endif | |
18c64df6 AC |
3618 | #if (WITH_TARGET_WORD_BITSIZE != GPRLEN) |
3619 | #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN" | |
3620 | #endif | |
76ef4165 | 3621 | #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU)) |
18c64df6 AC |
3622 | #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU" |
3623 | #endif | |
8bae0a0c JSC |
3624 | |
3625 | #if defined(WARN_LOHI) | |
3626 | /* Decrement the HI/LO validity ticks */ | |
3627 | if (HIACCESS > 0) | |
3628 | HIACCESS--; | |
3629 | if (LOACCESS > 0) | |
3630 | LOACCESS--; | |
0425cfb3 | 3631 | /* start-sanitize-r5900 */ |
53b9417e DE |
3632 | if (HI1ACCESS > 0) |
3633 | HI1ACCESS--; | |
3634 | if (LO1ACCESS > 0) | |
3635 | LO1ACCESS--; | |
0425cfb3 | 3636 | /* end-sanitize-r5900 */ |
8bae0a0c JSC |
3637 | #endif /* WARN_LOHI */ |
3638 | ||
8bae0a0c JSC |
3639 | /* For certain MIPS architectures, GPR[0] is hardwired to zero. We |
3640 | should check for it being changed. It is better doing it here, | |
3641 | than within the simulator, since it will help keep the simulator | |
3642 | small. */ | |
3643 | if (ZERO != 0) { | |
05d1322f | 3644 | #if defined(WARN_ZERO) |
95469ceb | 3645 | sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia)); |
05d1322f | 3646 | #endif /* WARN_ZERO */ |
8bae0a0c JSC |
3647 | ZERO = 0; /* reset back to zero before next instruction */ |
3648 | } | |
8bae0a0c | 3649 | } else /* simSKIPNEXT check */ |
0c2c5f61 | 3650 | STATE &= ~simSKIPNEXT; |
8bae0a0c JSC |
3651 | |
3652 | /* If the delay slot was active before the instruction is | |
3653 | executed, then update the PC to its new value: */ | |
0c2c5f61 | 3654 | if (DSSTATE) { |
8bae0a0c | 3655 | #ifdef DEBUG |
53b9417e | 3656 | printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3657 | #endif /* DEBUG */ |
3658 | PC = DSPC; | |
6eedf3f4 | 3659 | CANCELDELAYSLOT(); |
8bae0a0c JSC |
3660 | } |
3661 | ||
2acd126a AC |
3662 | if (MIPSISA < 4) |
3663 | PENDING_TICK(); | |
8bae0a0c JSC |
3664 | |
3665 | #if !defined(FASTSIM) | |
50a2a691 AC |
3666 | if (sim_events_tickn (sd, pipeline_count)) |
3667 | { | |
3668 | /* cpu->cia = cia; */ | |
3669 | sim_events_process (sd); | |
3670 | } | |
3671 | #else | |
2e61a3ad AC |
3672 | if (sim_events_tick (sd)) |
3673 | { | |
3674 | /* cpu->cia = cia; */ | |
3675 | sim_events_process (sd); | |
3676 | } | |
50a2a691 | 3677 | #endif /* FASTSIM */ |
8bae0a0c | 3678 | } |
8bae0a0c | 3679 | } |
16bd5d6e AC |
3680 | #endif |
3681 | ||
8bae0a0c | 3682 | |
53b9417e DE |
3683 | /* This code copied from gdb's utils.c. Would like to share this code, |
3684 | but don't know of a common place where both could get to it. */ | |
3685 | ||
3686 | /* Temporary storage using circular buffer */ | |
3687 | #define NUMCELLS 16 | |
3688 | #define CELLSIZE 32 | |
3689 | static char* | |
3690 | get_cell() | |
3691 | { | |
3692 | static char buf[NUMCELLS][CELLSIZE]; | |
3693 | static int cell=0; | |
3694 | if (++cell>=NUMCELLS) cell=0; | |
3695 | return buf[cell]; | |
3696 | } | |
3697 | ||
3698 | /* Print routines to handle variable size regs, etc */ | |
3699 | ||
3700 | /* Eliminate warning from compiler on 32-bit systems */ | |
3701 | static int thirty_two = 32; | |
3702 | ||
3703 | char* | |
3704 | pr_addr(addr) | |
3705 | SIM_ADDR addr; | |
3706 | { | |
3707 | char *paddr_str=get_cell(); | |
3708 | switch (sizeof(addr)) | |
3709 | { | |
3710 | case 8: | |
50a2a691 | 3711 | sprintf(paddr_str,"%08lx%08lx", |
53b9417e DE |
3712 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3713 | break; | |
3714 | case 4: | |
50a2a691 | 3715 | sprintf(paddr_str,"%08lx",(unsigned long)addr); |
53b9417e DE |
3716 | break; |
3717 | case 2: | |
3718 | sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff)); | |
3719 | break; | |
3720 | default: | |
3721 | sprintf(paddr_str,"%x",addr); | |
3722 | } | |
3723 | return paddr_str; | |
3724 | } | |
3725 | ||
87e43259 AC |
3726 | char* |
3727 | pr_uword64(addr) | |
3728 | uword64 addr; | |
3729 | { | |
3730 | char *paddr_str=get_cell(); | |
50a2a691 | 3731 | sprintf(paddr_str,"%08lx%08lx", |
87e43259 AC |
3732 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3733 | return paddr_str; | |
3734 | } | |
3735 | ||
3736 | ||
2acd126a | 3737 | |
8bae0a0c JSC |
3738 | /*---------------------------------------------------------------------------*/ |
3739 | /*> EOF interp.c <*/ |