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[deliverable/binutils-gdb.git] / sim / mips / micromips.igen
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8e394ffc 1// Simulator definition for the micromips ASE.
618f726f 2// Copyright (C) 2005-2016 Free Software Foundation, Inc.
8e394ffc
AB		 3// Contributed by Imagination Technologies, Ltd.
4// Written by Andrew Bennett <andrew.bennett@imgtec.com>
5//
6// This file is part of the MIPS sim.
7//
8// This program is free software; you can redistribute it and/or modify
9// it under the terms of the GNU General Public License as published by
10// the Free Software Foundation; either version 3 of the License, or
11// (at your option) any later version.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program. If not, see <http://www.gnu.org/licenses/>.
20
21:compute:::int:TBASE:BASE:((BASE < 2) ? (16 + BASE) \: BASE)
22:compute:::int:TRD:RD:((RD < 2) ? (16 + RD) \: RD)
23:compute:::int:TRS:RS:((RS < 2) ? (16 + RS) \: RS)
24:compute:::int:TRT:RT:((RT < 2) ? (16 + RT) \: RT)
25:compute:::int:TRT_S:RT_S:((RT_S == 1 ) ? 17 \: RT_S)
26:compute:::int:ERT:RT:(compute_movep_src_reg (SD_, RT))
27:compute:::int:ERS:RS:(compute_movep_src_reg (SD_, RS))
28
29:compute:::int:IMM_DEC1:IMMEDIATE:((IMMEDIATE == 7) ? -1 \: ((IMMEDIATE == 0) ? 1 \: IMMEDIATE << 2))
30:compute:::int:IMM_DEC2:IMMEDIATE:((IMMEDIATE < 8) ? IMMEDIATE \: (IMMEDIATE - 16))
31:compute:::int:IMM_DEC3:IMMEDIATE:((IMMEDIATE < 2) ? IMMEDIATE + 256 \: ((IMMEDIATE < 256) ? IMMEDIATE \: ((IMMEDIATE < 510) ? IMMEDIATE - 512 \: IMMEDIATE - 768)))
32:compute:::int:IMM_DEC4:IMMEDIATE:(compute_andi16_imm (SD_, IMMEDIATE))
33:compute:::int:IMM_DEC5:IMMEDIATE:((IMMEDIATE < 15) ? IMMEDIATE \: -1)
34:compute:::int:IMM_DEC6:IMMEDIATE:((IMMEDIATE < 127) ? IMMEDIATE \: -1)
35
36:compute:::int:SHIFT_DEC:SHIFT:((SHIFT == 0) ? 8 \: SHIFT)
37
38:compute:::int:IMM_SHIFT_1BIT:IMMEDIATE:(IMMEDIATE << 1)
39:compute:::int:IMM_SHIFT_2BIT:IMMEDIATE:(IMMEDIATE << 2)
40
41:function:::address_word:delayslot_micromips:address_word target, address_word nia, int delayslot_instruction_size
42{
43 instruction_word delay_insn;
44 sim_events_slip (SD, 1);
45 DSPC = CIA;
46 CIA = nia;
47 STATE |= simDELAYSLOT;
48 ENGINE_ISSUE_PREFIX_HOOK();
49 micromips_instruction_decode (SD, CPU, CIA, delayslot_instruction_size);
50 STATE &= ~simDELAYSLOT;
51 return target;
52}
53
54:function:::address_word:process_isa_mode:address_word target
55{
56 SD->isa_mode = target & 0x1;
1d19cae7 57 return (target & (-(1 << 1)));
8e394ffc
AB		 58}
59
60:function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size
61{
62 GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
63 return (process_isa_mode (SD_,
64 delayslot_micromips (SD_, GPR[rs], nia, delayslot_instruction_size)));
65}
66
67:function:::address_word:do_micromips_jal:address_word target, address_word nia, int delayslot_instruction_size
68{
69 RA = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
70 return delayslot_micromips (SD_, target, nia, delayslot_instruction_size);
71}
72
73
74:function:::unsigned32:compute_movep_src_reg:int reg
75{
76 switch(reg)
77 {
78 case 0: return 0;
79 case 1: return 17;
80 case 2: return 2;
81 case 3: return 3;
82 case 4: return 16;
83 case 5: return 18;
84 case 6: return 19;
85 case 7: return 20;
86 default: return 0;
87 }
88}
89
90:function:::unsigned32:compute_andi16_imm:int encoded_imm
91{
92 switch (encoded_imm)
93 {
94 case 0: return 128;
95 case 1: return 1;
96 case 2: return 2;
97 case 3: return 3;
98 case 4: return 4;
99 case 5: return 7;
100 case 6: return 8;
101 case 7: return 15;
102 case 8: return 16;
103 case 9: return 31;
104 case 10: return 32;
105 case 11: return 63;
106 case 12: return 64;
107 case 13: return 255;
108 case 14: return 32768;
109 case 15: return 65535;
110 default: return 0;
111 }
112}
113
114:function:::FP_formats:convert_fmt_micromips:int fmt
115{
116 switch (fmt)
117 {
118 case 0: return fmt_single;
119 case 1: return fmt_double;
120 case 2: return fmt_ps;
121 default: return fmt_unknown;
122 }
123}
124
125:function:::FP_formats:convert_fmt_micromips_cvt_d:int fmt
126{
127 switch (fmt)
128 {
129 case 0: return fmt_single;
130 case 1: return fmt_word;
131 case 2: return fmt_long;
132 default: return fmt_unknown;
133 }
134}
135
136
137:function:::FP_formats:convert_fmt_micromips_cvt_s:int fmt
138{
139 switch (fmt)
140 {
141 case 0: return fmt_double;
142 case 1: return fmt_word;
143 case 2: return fmt_long;
144 default: return fmt_unknown;
145 }
146}
147
148
149011011,3.RD,6.IMMEDIATE,1:POOL16E:16::ADDIUR1SP
150"addiur1sp r<TRD>, <IMMEDIATE>"
151*micromips32:
152*micromips64:
153{
154 do_addiu (SD_, SPIDX, TRD, IMMEDIATE << 2);
155}
156
157
158011011,3.RD,3.RS,3.IMMEDIATE,0:POOL16E:16::ADDIUR2
159"addiur2 r<TRD>, r<TRS>, <IMM_DEC1>"
160*micromips32:
161*micromips64:
162{
163 do_addiu (SD_, TRS, TRD, IMM_DEC1);
164}
165
166
167010011,5.RD,4.IMMEDIATE,0:POOL16D:16::ADDIUS5
168"addius5 r<RD>, <IMM_DEC2>"
169*micromips32:
170*micromips64:
171{
172 do_addiu (SD_, RD, RD, IMM_DEC2);
173}
174
175
176010011,9.IMMEDIATE,1:POOL16D:16::ADDIUSP
177"addiusp <IMM_DEC3>"
178*micromips32:
179*micromips64:
180{
181 do_addiu (SD_, SPIDX, SPIDX, IMM_DEC3 << 2);
182}
183
184
185000001,3.RD,3.RT,3.RS,0:POOL16A:16::ADDU16
186"addu16 r<TRD>, r<TRS>, r<TRT>"
187*micromips32:
188*micromips64:
189{
190 do_addu (SD_, TRS, TRT, TRD);
191}
192
193
194001011,3.RD,3.RS,4.IMMEDIATE:MICROMIPS:16::ANDI16
195"andi16 r<TRD>, r<TRS>, <IMM_DEC4>"
196*micromips32:
197*micromips64:
198{
199 do_andi (SD_, TRS, TRD, IMM_DEC4);
200}
201
202
203010001,0010,3.RT,3.RS:POOL16C:16::AND16
204"and16 r<TRT>, r<TRS>"
205*micromips32:
206*micromips64:
207{
208 do_and (SD_, TRS, TRT, TRT);
209}
210
211
212110011,10.IMMEDIATE:MICROMIPS:16::B16
213"b16 <IMMEDIATE>"
214*micromips32:
215*micromips64:
216{
217 NIA = delayslot_micromips (SD_, NIA + (EXTEND11 (IMMEDIATE << 1)),
218 NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
219}
220
221
222100011,3.RS,7.IMMEDIATE:MICROMIPS:16::BEQZ16
223"beqz16 r<TRS>, <IMMEDIATE>"
224*micromips32:
225*micromips64:
226{
227 if (GPR[TRS] == 0)
228 NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)),
229 NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
230}
231
232
233101011,3.RS,7.IMMEDIATE:MICROMIPS:16::BNEZ16
234"bnez16 r<TRS>, <IMMEDIATE>"
235*micromips32:
236*micromips64:
237{
238 if (GPR[TRS] != 0)
239 NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)),
240 NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
241}
242
243
244010001,101000,4.CODE:POOL16C:16::BREAK16
245"break16 %#lx<CODE>"
246*micromips32:
247*micromips64:
248{
249 do_break16 (SD_, instruction_0);
250}
251
252
253010001,01110,5.RS:POOL16C:16::JALR16
254"jalr16 r<RS>"
255*micromips32:
256*micromips64:
257{
258 NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
259}
260
261
262010001,01111,5.RS:POOL16C:16::JALRS16
263"jalrs16 r<RS>"
264*micromips32:
265*micromips64:
266{
267 NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
268}
269
270
271010001,01100,5.RS:POOL16C:16::JR16
272"jr16 r<RS>"
273*micromips32:
274*micromips64:
275{
276 NIA = process_isa_mode (SD_,
277 delayslot_micromips (SD_, GPR[RS], NIA, MICROMIPS_DELAYSLOT_SIZE_ANY));
278}
279
280
281010001,11000,5.IMMEDIATE:POOL16C:16::JRADDIUSP
282"jraddiusp <IMMEDIATE>"
283*micromips32:
284*micromips64:
285{
286 address_word temp = RA;
287 do_addiu (SD_, SPIDX, SPIDX, IMMEDIATE << 2);
288 NIA = process_isa_mode (SD_, temp);
289}
290
291
292010001,01101,5.RS:POOL16C:16::JRC
293"jrc r<RS>"
294*micromips32:
295*micromips64:
296{
297 NIA = process_isa_mode (SD_, GPR[RS]);
298}
299
300
301000010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LBU16
302"lbu16 r<TRT>, <IMM_DEC5>(r<TBASE>)"
303*micromips32:
304*micromips64:
305{
306 /* LBU can have a negative offset. As the offset argument to do_load is
307 unsigned we need to do the address calcuation before the function call so
308 that the load address has been correctly calculated */
309
310 GPR[TRT] = do_load (SD_, AccessLength_BYTE, GPR[TBASE] + IMM_DEC5, 0);
311}
312
313
314001010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LHU16
315"lhu16 r<TRT>, <IMM_SHIFT_1BIT>(r<TBASE>)"
316*micromips32:
317*micromips64:
318{
319 GPR[TRT] = do_load (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT);
320}
321
322
323111011,3.RD,7.IMMEDIATE:MICROMIPS:16::LI16
324"li16 r<TRD>, <IMM_DEC6>"
325*micromips32:
326*micromips64:
327{
328 GPR[TRD] = IMM_DEC6;
329}
330
331
332011010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LW16
333"lw16 r<TRT>, <IMM_SHIFT_2BIT>(r<TBASE>)"
334*micromips32:
335*micromips64:
336{
337 GPR[TRT] = EXTEND32 (
338 do_load (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT));
339}
340
341:%s::::LWMREGS:int lwmregs
342*micromips32:
343*micromips64:
344{
345 if (lwmregs == 3)
346 return "s0, s1, s2, s3, ra";
347 else if (lwmregs == 2)
348 return "s0, s1, s2, ra";
349 else if (lwmregs == 1)
350 return "s0, s1, ra";
351 else if (lwmregs == 0)
352 return "s0, ra";
353 else
354 return "";
355}
356
357010001,0100,2.LWMREGS,4.IMMEDIATE:POOL16C:16::LWM16
358"lwm16 %s<LWMREGS>, <IMM_SHIFT_2BIT>(sp)"
359*micromips32:
360*micromips64:
361{
362 int address = GPR[SPIDX] + IMM_SHIFT_2BIT;
363 int reg_offset;
364
365 for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++)
366 GPR[16 + reg_offset] = EXTEND32 (
367 do_load (SD_, AccessLength_WORD, address, reg_offset * 4));
368
369 RA = EXTEND32 (do_load (SD_, AccessLength_WORD, address, reg_offset * 4));
370}
371
372
373011001,3.RT,7.IMMEDIATE:MICROMIPS:16::LWGP
374"lwgp r<TRT>, <IMM_SHIFT_2BIT>(gp)"
375*micromips32:
376*micromips64:
377{
378 GPR[TRT] = EXTEND32 (
379 do_load (SD_, AccessLength_WORD, GPR[28], IMM_SHIFT_2BIT));
380}
381
382
383010010,5.RT,5.IMMEDIATE:MICROMIPS:16::LWSP
384"lwsp r<RT>, <IMM_SHIFT_2BIT>(sp)"
385*micromips32:
386*micromips64:
387{
388 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT));
389}
390
391
392010001,10000,5.RD:POOL16C:16::MFHI16
393"mfhi16 r<RD>"
394*micromips32:
395*micromips64:
396{
397 do_mfhi (SD_, RD);
398}
399
400
401010001,10010,5.RD:POOL16C:16::MFLO16
402"mflo16 r<RD>"
403*micromips32:
404*micromips64:
405{
406 do_mflo (SD_, RD);
407}
408
409
410000011,5.RD,5.RS:MICROMIPS:16::MOVE16
411"nop":RD==0&&RS==0
412"move16 r<RD>, r<RS>"
413*micromips32:
414*micromips64:
415{
416 GPR[RD] = GPR[RS];
417}
418
419
420:%s::::DESTREGS:int regs
421*micromips32:
422*micromips64:
423{
424 switch (regs)
425 {
426 case 0: return "a1, a2,";
427 case 1: return "a1, a3,";
428 case 2: return "a2, a3,";
429 case 3: return "a0, s5,";
430 case 4: return "a0, s6,";
431 case 5: return "a0, a1,";
432 case 6: return "a0, a2,";
433 case 7: return "a0, a3,";
434 default: return "";
435 }
436}
437
438100001,3.DESTREGS,3.RT,3.RS,0:MICROMIPS:16::MOVEP
439"movep %s<DESTREGS> r<ERS>, r<ERT>"
440*micromips32:
441*micromips64:
442{
443 int rd;
444 int re;
445 int dest = DESTREGS;
446
447 if (dest == 0 || dest == 1)
448 rd = 5;
449 else if (dest == 2)
450 rd = 6;
451 else
452 rd = 4;
453
454 if (dest == 0 || dest == 6)
455 re = 6;
456 else if (dest == 1 || dest == 2 || dest == 7)
457 re = 7;
458 else if (dest == 3)
459 re = 21;
460 else if (dest == 4)
461 re = 22;
462 /* assume dest is 5 */
463 else
464 re = 5;
465
466 GPR[rd] = GPR[ERS];
467 GPR[re] = GPR[ERT];
468}
469
470
471010001,0000,3.RT,3.RS:POOL16C:16::NOT16
472"not16 r<TRT>, r<TRS>"
473*micromips32:
474*micromips64:
475{
476 do_nor (SD_, 0, TRS, TRT);
477}
478
479
480010001,0011,3.RT,3.RS:POOL16C:16::OR16
481"or16 r<TRT>, r<TRS>"
482*micromips32:
483*micromips64:
484{
485 do_or (SD_, TRS, TRT, TRT);
486}
487
488
489100010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SB16
490"sb16 r<TRT_S>, <IMMEDIATE>(r<TBASE>)"
491*micromips32:
492*micromips64:
493{
494 do_store (SD_, AccessLength_BYTE, GPR[TBASE], IMMEDIATE, GPR[TRT_S]);
495}
496
497
498010001,101100,4.CODE:POOL16C:16::SDBBP16
499"sdbbp16 %#lx<CODE>"
500*micromips32:
501*micromips64:
502{
503 SignalException (DebugBreakPoint, instruction_0);
504}
505
506
507101010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SH16
508"sh16 r<TRT_S>, <IMM_SHIFT_1BIT>(r<TBASE>)"
509*micromips32:
510*micromips64:
511{
512 do_store (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT, GPR[TRT_S]);
513}
514
515
516001001,3.RD,3.RT,3.SHIFT,0:POOL16B:16::SLL16
517"sll16 r<TRD>, r<TRT>, <SHIFT_DEC>"
518*micromips32:
519*micromips64:
520{
521 do_sll (SD_, TRT, TRD, SHIFT_DEC);
522}
523
524
525001001,3.RD,3.RT,3.SHIFT,1:POOL16B:16::SRL16
526"srl16 r<TRD>, r<TRT>, <SHIFT_DEC>"
527*micromips32:
528*micromips64:
529{
530 do_srl (SD_, TRT, TRD, SHIFT_DEC);
531}
532
533
534000001,3.RD,3.RT,3.RS,1:POOL16A:16::SUBU16
535"subu16 r<TRD>, r<TRS>, r<TRT>"
536*micromips32:
537*micromips64:
538{
539 do_subu (SD_, TRS, TRT, TRD);
540}
541
542
543111010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SW16
544"sw16 r<TRT_S>, <IMM_SHIFT_2BIT>(r<TBASE>)"
545*micromips32:
546*micromips64:
547{
548 do_store (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT, GPR[TRT_S]);
549}
550
551
552110010,5.RT,5.IMMEDIATE:MICROMIPS:16::SWSP
553"swsp r<RT>, <IMM_SHIFT_2BIT>(sp)"
554*micromips32:
555*micromips64:
556{
557 do_store (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT, GPR[RT]);
558}
559
560
561010001,0101,2.LWMREGS,4.IMMEDIATE:POOL16C:16::SWM16
562"swm16 %s<LWMREGS>, <IMM_SHIFT_2BIT>(sp)"
563*micromips32:
564*micromips64:
565{
566 int address = GPR[SPIDX] + IMM_SHIFT_2BIT;
567 int reg_offset;
568
569 for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++)
570 do_store (SD_, AccessLength_WORD, address, reg_offset * 4,
571 GPR[16 + reg_offset]);
572
573 do_store (SD_, AccessLength_WORD, address, reg_offset * 4, RA);
574}
575
576
577010001,0001,3.RT,3.RS:POOL16C:16::XOR16
578"xor16 r<TRT>, r<TRS>"
579*micromips32:
580*micromips64:
581{
582 do_xor (SD_, TRS, TRT, TRT);
583}
584
585
586000000,5.RT,5.RS,5.RD,00100,010000:POOL32A:32::ADD
587"add r<RD>, r<RS>, r<RT>"
588*micromips32:
589*micromips64:
590{
591 do_add (SD_, RS, RT, RD);
592}
593
594
595000100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDI
596"addi r<RT>, r<RS>, <IMMEDIATE>"
597*micromips32:
598*micromips64:
599{
600 do_addi (SD_, RS, RT, IMMEDIATE);
601}
602
603
604001100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDIU
605"li r<RT>, <IMMEDIATE>":RS==0
606"addiu r<RT>, r<RS>, <IMMEDIATE>"
607*micromips32:
608*micromips64:
609{
610 do_addiu (SD_, RS, RT, IMMEDIATE);
611}
612
613
614011110,3.RS,23.IMMEDIATE:MICROMIPS:32::ADDIUPC
615"addiupc r<TRS>, <IMM_SHIFT_2BIT>"
616*micromips32:
617*micromips64:
618{
619 GPR[TRS] = EXTEND32 ((CIA & ~3) + EXTEND25 (IMM_SHIFT_2BIT));
620}
621
622
623000000,5.RT,5.RS,5.RD,00101,010000:POOL32A:32::ADDU
624"addu r<RD>, r<RS>, r<RT>"
625*micromips32:
626*micromips64:
627{
628 do_addu (SD_, RS, RT, RD);
629}
630
631
632000000,5.RT,5.RS,5.RD,01001,010000:POOL32A:32::AND
633"and r<RD>, r<RS>, r<RT>"
634*micromips32:
635*micromips64:
636{
637 do_and (SD_, RS, RT, RD);
638}
639
640
641110100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ANDI
642"andi r<RT>, r<RS>, <IMMEDIATE>"
643*micromips32:
644*micromips64:
645{
646 do_andi (SD_, RS, RT, IMMEDIATE);
647}
648
649
650010000,1110,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32,f::BC1a
651"bc1%s<TF> <IMMEDIATE>":CC == 0
652"bc1%s<TF> <CC>, <IMMEDIATE>"
653*micromips32:
654*micromips64:
655{
656 check_fpu (SD_);
657 if (GETFCC(CC) == TF)
658 {
659 address_word dest = NIA + (EXTEND16 (IMMEDIATE) << 1);
660 NIA = delayslot_micromips (SD_, dest, NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
661 }
662}
663
664
665010000,1010,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32::BC2a
666"bc2%s<TF> <CC>, <IMMEDIATE>":CC == 0
667"bc2%s<TF> <CC>, <IMMEDIATE>"
668*micromips32:
669*micromips64:
670
671
672100101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BEQ
673"b <IMMEDIATE>":RT == 0 && RS == 0
674"beq r<RS>, r<RT>, <IMMEDIATE>"
675*micromips32:
676*micromips64:
677{
678 address_word offset = EXTEND16 (IMMEDIATE) << 1;
679 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
680 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
681 MICROMIPS_DELAYSLOT_SIZE_ANY);
682}
683
684010000,00010,5.RS,16.IMMEDIATE:POOL32I:32::BGEZ
685"bgez r<RS>, <IMMEDIATE>"
686*micromips32:
687*micromips64:
688{
689 address_word offset = EXTEND16 (IMMEDIATE) << 1;
690 if ((signed_word) GPR[RS] >= 0)
691 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
692 MICROMIPS_DELAYSLOT_SIZE_ANY);
693}
694
695
696010000,00111,5.RS,16.IMMEDIATE:POOL32I:32::BEQZC
697"beqzc r<RS>, <IMMEDIATE>"
698*micromips32:
699*micromips64:
700{
701 address_word offset = EXTEND16 (IMMEDIATE) << 1;
702 if (GPR[RS] == 0)
703 NIA = NIA + offset;
704}
705
706
707010000,00011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZAL
708"bal <IMMEDIATE>":RS == 0
709"bgezal r<RS>, <IMMEDIATE>"
710*micromips32:
711*micromips64:
712{
713 address_word offset = EXTEND16 (IMMEDIATE) << 1;
714 if (RS == 31)
715 Unpredictable ();
716 RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS;
717 if ((signed_word) GPR[RS] >= 0)
718 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
719 MICROMIPS_DELAYSLOT_SIZE_32);
720}
721
722
723010000,00110,5.RS,16.IMMEDIATE:POOL32I:32::BGTZ
724"bgtz r<RS>, <IMMEDIATE>"
725*micromips32:
726*micromips64:
727{
728 address_word offset = EXTEND16 (IMMEDIATE) << 1;
729 if ((signed_word) GPR[RS] > 0)
730 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
731 MICROMIPS_DELAYSLOT_SIZE_ANY);
732}
733
734
735010000,10011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZALS
736"bal <IMMEDIATE>":RS == 0
737"bgezals r<RS>, <IMMEDIATE>"
738*micromips32:
739*micromips64:
740{
741 address_word offset = EXTEND16 (IMMEDIATE) << 1;
742 if (RS == 31)
743 Unpredictable ();
744 RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS;
745 if ((signed_word) GPR[RS] >= 0)
746 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
747 MICROMIPS_DELAYSLOT_SIZE_16);
748}
749
750
751010000,00100,5.RS,16.IMMEDIATE:POOL32I:32::BLEZ
752"blez r<RS>, <IMMEDIATE>"
753*micromips32:
754*micromips64:
755{
756 address_word offset = EXTEND16 (IMMEDIATE) << 1;
757 /* NOTE: The branch occurs AFTER the next instruction has been
758 executed */
759 if ((signed_word) GPR[RS] <= 0)
760 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
761 MICROMIPS_DELAYSLOT_SIZE_ANY);
762}
763
764
765010000,00000,5.RS,16.IMMEDIATE:POOL32I:32::BLTZ
766"bltz r<RS>, <IMMEDIATE>"
767*micromips32:
768*micromips64:
769{
770 address_word offset = EXTEND16 (IMMEDIATE) << 1;
771 if ((signed_word) GPR[RS] < 0)
772 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
773 MICROMIPS_DELAYSLOT_SIZE_ANY);
774}
775
776
777010000,00001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZAL
778"bltzal r<RS>, <IMMEDIATE>"
779*micromips32:
780*micromips64:
781{
782 address_word offset = EXTEND16 (IMMEDIATE) << 1;
783 if (RS == 31)
784 Unpredictable ();
785 RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS;
786 /* NOTE: The branch occurs AFTER the next instruction has been
787 executed */
788 if ((signed_word) GPR[RS] < 0)
789 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
790 MICROMIPS_DELAYSLOT_SIZE_32);
791}
792
793010000,10001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZALS
794"bltzals r<RS>, <IMMEDIATE>"
795*micromips32:
796*micromips64:
797{
798 address_word offset = EXTEND16 (IMMEDIATE) << 1;
799 if (RS == 31)
800 Unpredictable ();
801 RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS;
802 if ((signed_word) GPR[RS] < 0)
803 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
804 MICROMIPS_DELAYSLOT_SIZE_16);
805}
806
807
808101101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BNE
809"bne r<RS>, r<RT>, <IMMEDIATE>"
810*micromips32:
811*micromips64:
812{
813 address_word offset = EXTEND16 (IMMEDIATE) << 1;
814 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
815 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
816 MICROMIPS_DELAYSLOT_SIZE_ANY);
817}
818
819
820010000,00101,5.RS,16.IMMEDIATE:POOL32I:32::BNEZC
821"bnezc r<RS>, <IMMEDIATE>"
822*micromips32:
823*micromips64:
824{
825 address_word offset = EXTEND16 (IMMEDIATE) << 1;
826 if ((signed_word) GPR[RS] != 0)
827 NIA = NIA + offset;
828}
829
830
831000000,20.CODE,000111:POOL32A:32::BREAK
832"break %#lx<CODE>"
833*micromips32:
834*micromips64:
835{
836 do_break (SD_, instruction_0);
837}
838
839
840001000,5.OP,5.BASE,0110,12.IMMEDIATE:POOL32B:32::CACHE
841"cache <OP>, <IMMEDIATE>(r<BASE>)"
842*micromips32:
843*micromips64:
844{
845 address_word base = GPR[BASE];
846 address_word offset = EXTEND12 (IMMEDIATE);
847 address_word vaddr = loadstore_ea (SD_, base, offset);
26f8bf63
MF		 848 address_word paddr = vaddr;
849 CacheOp (OP, vaddr, paddr, instruction_0);
8e394ffc
AB		 850}
851
852
853011000,5.OP,5.BASE,1010011,9.IMMEDIATE:POOL32C:32::CACHEE
854"cachee <OP>, <IMMEDIATE>(r<BASE>)"
855*micromips32:
856*micromips64:
857
858
859010101,5.RT,5.FS,0001000000,111011:POOL32F:32,f::CFC1
860"cfc1 r<RT>, f<FS>"
861*micromips32:
862*micromips64:
863{
864 do_cfc1 (SD_, RT, FS);
865}
866
867
868000000,5.RT,5.IMPL,1100110100,111100:POOL32A:32::CFC2
869"cfc2 r<RT>, <IMPL>"
870*micromips32:
871*micromips64:
872
873
874000000,5.RT,5.RS,0100101100,111100:POOL32A:32::CLO
875"clo r<RT>, r<RS>"
876*micromips32:
877*micromips64:
878{
879 do_clo (SD_, RT, RS);
880}
881
882
883000000,5.RT,5.RS,0101101100,111100:POOL32A:32::CLZ
884"clz r<RT>, r<RS>"
885*micromips32:
886*micromips64:
887{
888 do_clz (SD_, RT, RS);
889}
890
891
892000000,23.COFUN,010:POOL32A:32::COP2
893"cop2 <COFUN>"
894*micromips32:
895*micromips64:
896
897
898010101,5.RT,5.FS,0001100000,111011:POOL32F:32,f::CTC1
899"ctc1 r<RT>, f<FS>"
900*micromips32:
901*micromips64:
902{
903 do_ctc1 (SD_, RT, FS);
904}
905
906
907000000,5.RT,5.IMPL,1101110100,111100:POOL32A:32::CTC2
908"ctc2 r<RT>, <IMPL>"
909*micromips32:
910*micromips64:
911
912
913000000,00000000001110001101,111100:POOL32A:32::DERET
914"deret"
915*micromips32:
916*micromips64:
917
918
919000000,00000,5.RS,0100011101,111100:POOL32A:32::DI
920"di":RS == 0
921"di r<RS>"
922*micromips32:
923*micromips64:
924{
925 do_di (SD_, RS);
926}
927
928000000,5.RT,5.RS,1010101100,111100:POOL32A:32::DIV
929"div r<RS>, r<RT>"
930*micromips32:
931*micromips64:
932{
933 do_div (SD_, RS, RT);
934}
935
936
937000000,5.RT,5.RS,1011101100,111100:POOL32A:32::DIVU
938"divu r<RS>, r<RT>"
939*micromips32:
940*micromips64:
941{
942 do_divu (SD_, RS, RT);
943}
944
945
946000000,00000000000001100000,000000:POOL32A:32::EHB
947"ehb"
948*micromips32:
949*micromips64:
950
951
952000000,00000,5.RS,0101011101,111100:POOL32A:32::EI
953"ei":RS == 0
954"ei r<RS>"
955*micromips32:
956*micromips64:
957{
958 do_ei (SD_, RS);
959}
960
961000000,00000000001111001101,111100:POOL32A:32::ERET
962"eret"
963*micromips32:
964*micromips64:
965{
966 if (SR & status_ERL)
967 {
968 /* Oops, not yet available */
969 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
970 NIA = EPC;
971 SR &= ~status_ERL;
972 }
973 else
974 {
975 NIA = EPC;
976 SR &= ~status_EXL;
977 }
978}
979
980
981000000,5.RT,5.RS,5.MSBD,5.LSB,101100:POOL32A:32::EXT
982"ext r<RT>, r<RS>, <LSB>, <MSBD+1>"
983*micromips32:
984*micromips64:
985{
986 do_ext (SD_, RT, RS, LSB, MSBD);
987}
988
989
990000000,5.RT,5.RS,5.MSBD,5.LSB,001100:POOL32A:32::INS
991"ins r<RT>, r<RS>, <LSB>, <MSBD-LSB+1>"
992*micromips32:
993*micromips64:
994{
995 do_ins (SD_, RT, RS, LSB, MSBD);
996}
997
998
999110101,26.IMMEDIATE:MICROMIPS:32::J
1000"j <IMM_SHIFT_1BIT>"
1001*micromips32:
1002*micromips64:
1003{
1004 address_word region = (NIA & MASK (63, 27));
1005 NIA = delayslot_micromips (SD_, region | (IMM_SHIFT_1BIT), NIA,
1006 MICROMIPS_DELAYSLOT_SIZE_ANY);
1007}
1008
1009
1010111101,26.IMMEDIATE:MICROMIPS:32::JAL
1011"jal <IMM_SHIFT_1BIT>"
1012*micromips32:
1013*micromips64:
1014{
1015 /* NOTE: The region used is that of the delay slot and NOT the
1016 current instruction */
1017 address_word region = (NIA & MASK (63, 27));
1018 NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_1BIT)), NIA,
1019 MICROMIPS_DELAYSLOT_SIZE_32);
1020}
1021
1022
1023011101,26.IMMEDIATE:MICROMIPS:32::JALS
1024"jals <IMM_SHIFT_1BIT>"
1025*micromips32:
1026*micromips64:
1027{
1028 address_word region = (NIA & MASK (63, 27));
1029 NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_1BIT)), NIA,
1030 MICROMIPS_DELAYSLOT_SIZE_16);
1031}
1032
1033000000,5.RT!0,5.RS,0000111100,111100:POOL32A:32::JALR
1034"jalr r<RS>":RT == 31
1035"jalr r<RT>, r<RS>"
1036*micromips32:
1037*micromips64:
1038{
1039 if (RS == RT)
1040 Unpredictable ();
1041 NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1042}
1043
1044000000,5.RT,5.RS,0100111100,111100:POOL32A:32::JALRS
1045"jalrs r<RT>, r<RS>"
1046*micromips32:
1047*micromips64:
1048{
1049 if (RS == RT)
1050 Unpredictable ();
1051 NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
1052}
1053
1054
1055111100,26.IMMEDIATE:MICROMIPS:32::JALX
1056"jalx <IMM_SHIFT_2BIT>"
1057*micromips32:
1058*micromips64:
1059{
1060 address_word region = (NIA & MASK (63, 26));
1061 NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_2BIT)) | ISA_MODE_MIPS32,
1062 NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1063 SD->isa_mode = ISA_MODE_MIPS32;
1064}
1065
1066000000,00000,5.RS,0000111100,111100:POOL32A:32::JR
1067"jr r<RS>"
1068*micromips32:
1069*micromips64:
1070{
1071 NIA = process_isa_mode (SD_,
1072 delayslot_micromips (SD_, GPR[RS], NIA,
1073 MICROMIPS_DELAYSLOT_SIZE_32));
1074}
1075
1076
1077000000,5.RT,5.RS,0001111100,111100:POOL32A:32::JALR.HB
1078"jalr.hb r<RT>, r<RS>"
1079*micromips32:
1080*micromips64:
1081{
1082 if (RS == RT)
1083 Unpredictable ();
1084 NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1085}
1086
1087
1088000000,5.RT,5.RS,0101111100,111100:POOL32A:32::JALRS.HB
1089"jalrs.hb r<RT>, r<RS>"
1090*micromips32:
1091*micromips64:
1092{
1093 if (RS == RT)
1094 Unpredictable ();
1095 NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
1096}
1097
1098
1099000000,00000,5.RS,0111111100,111100:POOL32A:32::JR.HB
1100"jr.hb r<RS>"
1101*micromips32:
1102*micromips64:
1103{
1104 NIA = process_isa_mode (SD_,
1105 delayslot_micromips (SD_, GPR[RS], NIA,
1106 MICROMIPS_DELAYSLOT_SIZE_32));
1107}
1108
1109
1110000111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LB
1111"lb r<RT>, <IMMEDIATE>(r<BASE>)"
1112*micromips32:
1113*micromips64:
1114{
1115 do_lb (SD_, RT, IMMEDIATE, BASE);
1116}
1117
1118
1119011000,5.RT,5.BASE,0110100,9.IMMEDIATE:POOL32C:32::LBE
1120"lbe r<RT>, <IMMEDIATE>(r<BASE>)"
1121*micromips32:
1122*micromips64:
1123
1124
1125000101,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LBU
1126"lbu r<RT>, <IMMEDIATE>(r<BASE>)"
1127*micromips32:
1128*micromips64:
1129{
1130 do_lbu (SD_, RT, IMMEDIATE, BASE);
1131}
1132
1133
1134011000,5.RT,5.BASE,0110000,9.IMMEDIATE:POOL32C:32::LBUE
1135"lbue r<RT>, <IMMEDIATE>(r<BASE>)"
1136*micromips32:
1137*micromips64:
1138
1139
1140101111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LDC1a
1141"ldc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1142*micromips32:
1143{
1144 check_fpu (SD_);
1145 COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (IMMEDIATE)));
1146}
1147
1148
1149101111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LDC1b
1150"ldc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1151*micromips64:
1152{
1153 check_fpu (SD_);
1154 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
1155 EXTEND16 (IMMEDIATE)));
1156}
1157
1158
1159001000,5.RT,5.BASE,0010,12.IMMEDIATE:POOL32B:32::LDC2
1160"ldc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1161*micromips32:
1162*micromips64:
1163
1164
1165001111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LH
1166"lh r<RT>, <IMMEDIATE>(r<BASE>)"
1167*micromips32:
1168*micromips64:
1169{
1170 do_lh (SD_, RT, IMMEDIATE, BASE);
1171}
1172
1173
1174011000,5.RT,5.BASE,0110101,9.IMMEDIATE:POOL32C:32::LHE
1175"lhe r<RT>, <IMMEDIATE>(r<BASE>)"
1176*micromips32:
1177*micromips64:
1178
1179
1180001101,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LHU
1181"lhu r<RT>, <IMMEDIATE>(r<BASE>)"
1182*micromips32:
1183*micromips64:
1184{
1185 do_lhu (SD_, RT, IMMEDIATE, BASE);
1186}
1187
1188
1189011000,5.RT,5.BASE,0110001,9.IMMEDIATE:POOL32C:32::LHUE
1190"lhue r<RT>, <IMMEDIATE>(r<BASE>)"
1191*micromips32:
1192*micromips64:
1193
1194
1195011000,5.RT,5.BASE,0011,12.IMMEDIATE:POOL32C:32::LL
1196"ll r<RT>, <IMMEDIATE>(r<BASE>)"
1197*micromips32:
1198*micromips64:
1199{
1200 do_ll (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1201}
1202
1203
1204011000,5.RT,5.BASE,0110110,9.IMMEDIATE:POOL32C:32::LLE
1205"lle r<RT>, <IMMEDIATE>(r<BASE>)"
1206*micromips32:
1207*micromips64:
1208
1209
1210010000,01101,5.RS,16.IMMEDIATE:POOL32I:32::LUI
1211"lui r<RS>, <IMMEDIATE>"
1212*micromips32:
1213*micromips64:
1214{
1215 do_lui (SD_, RS, IMMEDIATE);
1216}
1217
1218
1219010101,5.INDEX,5.BASE,5.FD,00101,001000:POOL32F:32,f::LUXC1
1220"luxc1 f<FD>, r<INDEX>(r<BASE>)"
1221*micromips32:
1222{
1223 do_luxc1_32 (SD_, FD, INDEX, BASE);
1224}
1225
1226
1227010101,5.INDEX,5.BASE,5.FD,00101,001000:POOL32F:64,f::LUXC1
1228"luxc1 f<FD>, r<INDEX>(r<BASE>)"
1229*micromips64:
1230{
1231 check_fpu (SD_);
1232 check_u64 (SD_, instruction_0);
1233 do_luxc1_64 (SD_, FD, INDEX, BASE);
1234}
1235
1236
1237111111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LW
1238"lw r<RT>, <IMMEDIATE>(r<BASE>)"
1239*micromips32:
1240*micromips64:
1241{
1242 do_lw (SD_, RT, IMMEDIATE, BASE);
1243}
1244
1245
1246100111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LWC1
1247"lwc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1248*micromips32:
1249*micromips64:
1250{
1251 do_lwc1 (SD_, FT, IMMEDIATE, BASE);
1252}
1253
1254
1255001000,5.RT,5.BASE,0000,12.IMMEDIATE:POOL32B:32::LWC2
1256"lwc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1257*micromips32:
1258*micromips64:
1259
1260
1261011000,5.RT,5.BASE,0110111,9.IMMEDIATE:POOL32C:32::LWE
1262"lwe r<RT>, <IMMEDIATE>(r<BASE>)"
1263*micromips32:
1264*micromips64:
1265
1266
1267011000,5.RT,5.BASE,0110011,9.IMMEDIATE:POOL32C:32::LWEE
1268"lwee r<RT>, <IMMEDIATE>(r<BASE>)"
1269*micromips32:
1270*micromips64:
1271
1272
1273011000,5.RT,5.BASE,0000,12.IMMEDIATE:POOL32C:32::LWL
1274"lwl r<RT>, <IMMEDIATE>(r<BASE>)"
1275*micromips32:
1276*micromips64:
1277{
1278 do_lwl (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1279}
1280
1281
1282011000,5.RT,5.BASE,0110010,9.IMMEDIATE:POOL32C:32::LWLE
1283"lwle r<RT>, <IMMEDIATE>(r<BASE>)"
1284*micromips32:
1285*micromips64:
1286
1287:%s::::LWM32REGS:int lwmregs
1288*micromips32:
1289*micromips64:
1290{
1291 if (lwmregs & 0x10)
1292 {
1293 switch(lwmregs & 0xf)
1294 {
1295 case 0:
1296 return "ra";
1297 case 1:
1298 return "s0, ra";
1299 case 2:
1300 return "s0, s1, ra";
1301 case 3:
1302 return "s0, s1, s2, ra";
1303 case 4:
1304 return "s0, s1, s2, s3, ra";
1305 case 5:
1306 return "s0, s1, s2, s3, s4, ra";
1307 case 6:
1308 return "s0, s1, s2, s3, s4, s5, ra";
1309 case 7:
1310 return "s0, s1, s2, s3, s4, s5, s6, ra";
1311 case 8:
1312 return "s0, s1, s2, s3, s4, s5, s6, s7, ra";
1313 case 9:
1314 return "s0, s1, s2, s3, s4, s5, s6, s7, s8, ra";
1315 default:
1316 return "";
1317 }
1318 }
1319 else
1320 {
1321 switch(lwmregs & 0xf)
1322 {
1323 case 1:
1324 return "s0";
1325 case 2:
1326 return "s0, s1";
1327 case 3:
1328 return "s0, s1, s2";
1329 case 4:
1330 return "s0, s1, s2, s3";
1331 case 5:
1332 return "s0, s1, s2, s3, s4";
1333 case 6:
1334 return "s0, s1, s2, s3, s4, s5";
1335 case 7:
1336 return "s0, s1, s2, s3, s4, s5, s6";
1337 case 8:
1338 return "s0, s1, s2, s3, s4, s5, s6, s7";
1339 case 9:
1340 return "s0, s1, s2, s3, s4, s5, s6, s7, s8";
1341 default:
1342 return "";
1343 }
1344 }
1345}
1346
1347001000,5.LWM32REGS,5.BASE,0101,12.IMMEDIATE:POOL32B:32::LWM32
1348"lwm32 %s<LWM32REGS>, <IMMEDIATE>(r<BASE>)"
1349*micromips32:
1350*micromips64:
1351{
1352 int address_base = GPR[BASE] + EXTEND12 (IMMEDIATE);
1353 int reg_offset;
1354 for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
1355 {
1356 int dst = (reg_offset == 8) ? 30 : 16 + reg_offset;
1357 GPR[dst] = EXTEND32 (do_load (SD_, AccessLength_WORD, address_base,
1358 4 * reg_offset));
1359 }
1360
1361 if (LWM32REGS & 0x10)
1362 RA = EXTEND32 (do_load (SD_, AccessLength_WORD, address_base,
1363 4 * reg_offset));
1364}
1365
1366
1367001000,5.RD,5.BASE,0001,12.IMMEDIATE:POOL32B:32::LWP
1368"lwp r<RD>, <IMMEDIATE>(r<BASE>)"
1369*micromips32:
1370*micromips64:
1371{
1372 if (BASE == RD || RD == 31)
1373 Unpredictable ();
1374 else
1375 {
1376 do_lw (SD_, RD, EXTEND12 (IMMEDIATE), BASE);
1377 do_lw (SD_, RD + 1, EXTEND12 (IMMEDIATE) + 4, BASE);
1378 }
1379}
1380
1381
1382011000,5.RT,5.BASE,0001,12.IMMEDIATE:POOL32C:32::LWR
1383"lwr r<RT>, <IMMEDIATE>(r<BASE>)"
1384*micromips32:
1385*micromips64:
1386{
1387 do_lwr (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1388}
1389
1390
1391011000,5.RT,5.BASE,1110,12.IMMEDIATE:POOL32C:32::LWU
1392"lwu r<RT>, <IMMEDIATE>(r<BASE>)"
1393*micromips32:
1394*micromips64:
1395{
1396 do_lwu (SD_, RT, IMMEDIATE, BASE, instruction_0);
1397}
1398
1399
1400010101,5.INDEX,5.BASE,5.FD,00001,001000:POOL32F:32,f::LWXC1
1401"lwxc1 f<FD>, <INDEX>(r<BASE>)"
1402*micromips32:
1403*micromips64:
1404{
1405 do_lwxc1 (SD_, FD, INDEX, BASE, instruction_0);
1406}
1407
1408
1409000000,5.INDEX,5.BASE,5.RD,00100,011000:POOL32A:32::LWXS
1410"lwxs r<RD>, r<INDEX>(r<BASE>)"
1411*micromips32:
1412*micromips64:
1413{
1414 GPR[RD] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE],
1415 GPR[INDEX] * 4));
1416}
1417
1418
1419000000,5.RT,5.RS,1100101100,111100:POOL32A:32::MADD
1420"madd r<RS>, r<RT>"
1421*micromips32:
1422*micromips64:
1423{
1424 do_madd (SD_, RS, RT);
1425}
1426
1427
1428000000,5.RT,5.RS,1101101100,111100:POOL32A:32::MADDU
1429"maddu r<RS>, r<RT>"
1430*micromips32:
1431*micromips64:
1432{
1433 do_maddu (SD_, RS, RT);
1434}
1435
1436
1437000000,5.RT,5.RS,00,3.SEL,00011,111100:POOL32A:32::MFC0
1438"mfc0 r<RS>, r<RT>": SEL == 0
1439"mfc0 r<RS>, r<RT>, <SEL>"
1440*micromips32:
1441*micromips64:
1442{
1443 DecodeCoproc (instruction_0, 0, cp0_mfc0, RT, RS, SEL);
1444}
1445
1446
1447010101,5.RT,5.FS,0010000000,111011:POOL32F:32,f::MFC1
1448"mfc1 r<RT>, f<FS>"
1449*micromips32:
1450*micromips64:
1451{
1452 do_mfc1b (SD_, RT, FS);
1453}
1454
1455
1456000000,5.RT,5.IMPL,0100110100,111100:POOL32A:32::MFC2
1457"mfc2 r<RT>, <IMPL>"
1458*micromips32:
1459*micromips64:
1460
1461
1462010101,5.RT,5.FS,0011000000,111011:POOL32F:32,f::MFHC1
1463"mfhc1 r<RT>, f<FS>"
1464*micromips32:
1465*micromips64:
1466{
1467 do_mfhc1 (SD_, RT, FS);
1468}
1469
1470
1471000000,5.RT,5.IMPL,1000110100,111100:POOL32A:32::MFHC2
1472"mfhc2 r<RT>, <IMPL>"
1473*micromips32:
1474*micromips64:
1475
1476
1477000000,00000,5.RS,0000110101,111100:POOL32A:32::MFHI
1478"mfhi r<RS>"
1479*micromips32:
1480*micromips64:
1481{
1482 do_mfhi (SD_, RS);
1483}
1484
1485
1486000000,00000,5.RS,0001110101,111100:POOL32A:32::MFLO
1487"mflo r<RS>"
1488*micromips32:
1489*micromips64:
1490{
1491 do_mflo (SD_, RS);
1492}
1493
1494
1495// MOVF
1496// MOVT
1497010101,5.RT,5.RS,3.CC,0,1.TF,00101,111011:POOL32F:32::MOVtf
1498"mov%s<TF> r<RT>, r<RS>, CC"
1499*micromips32:
1500*micromips64:
1501{
1502 do_movtf (SD_, TF, RT, RS, CC);
1503}
1504
1505
1506000000,5.RT,5.RS,5.RD,00000,011000:POOL32A:32::MOVN
1507"movn r<RD>, r<RS>, r<RT>"
1508*micromips32:
1509*micromips64:
1510{
1511 do_movn (SD_, RD, RS, RT);
1512}
1513
1514
1515000000,5.RT,5.RS,5.RD,00001,011000:POOL32A:32::MOVZ
1516"movz r<RD>, r<RS>, r<RT>"
1517*micromips32:
1518*micromips64:
1519{
1520 do_movz (SD_, RD, RS, RT);
1521}
1522
1523
1524000000,5.RT,5.RS,1110101100,111100:POOL32A:32::MSUB
1525"msub r<RS>, r<RT>"
1526*micromips32:
1527*micromips64:
1528{
1529 do_msub (SD_, RS, RT);
1530}
1531
1532
1533000000,5.RT,5.RS,1111101100,111100:POOL32A:32::MSUBU
1534"msubu r<RS>, r<RT>"
1535*micromips32:
1536*micromips64:
1537{
1538 do_msubu (SD_, RS, RT);
1539}
1540
1541
1542000000,5.RT,5.RS,00,3.SEL,01011,111100:POOL32A:32::MTC0
1543"mtc0 r<RS>, r<RT>": SEL == 0
1544"mtc0 r<RS>, r<RT>, <SEL>"
1545*micromips32:
1546*micromips64:
1547{
1548 DecodeCoproc (instruction_0, 0, cp0_mtc0, RT, RS, SEL);
1549}
1550
1551
1552010101,5.RT,5.FS,0010100000,111011:POOL32F:32,f::MTC1
1553"mtc1 r<RT>, f<FS>"
1554*micromips32:
1555*micromips64:
1556{
1557 do_mtc1b (SD_, RT, FS);
1558}
1559
1560
1561000000,5.RT,5.IMPL,0101110100,111100:POOL32A:32::MTC2
1562"mtc2 r<RT>, <IMPL>"
1563*micromips32:
1564*micromips64:
1565
1566
1567010101,5.RT,5.FS,0011100000,111011:POOL32F:32,f::MTHC1
1568"mthc1 r<RT>, f<FS>"
1569*micromips32:
1570*micromips64:
1571{
1572 do_mthc1 (SD_, RT, FS);
1573}
1574
1575
1576000000,5.RT,5.IMPL,1001110100,111100:POOL32A:32::MTHC2
1577"mthc2 r<RT>, <IMPL>"
1578*micromips32:
1579*micromips64:
1580
1581
1582000000,00000,5.RS,0010110101,111100:POOL32A:32::MTHI
1583"mthi r<RS>"
1584*micromips32:
1585*micromips64:
1586{
1587 do_mthi (SD_, RS);
1588}
1589
1590
1591000000,00000,5.RS,0011110101,111100:POOL32A:32::MTLO
1592"mtlo r<RS>"
1593*micromips32:
1594*micromips64:
1595{
1596 do_mtlo (SD_, RS);
1597}
1598
1599
1600000000,5.RT,5.RS,5.RD,01000,010000:POOL32A:32::MUL
1601"mul r<RD>, r<RS>, r<RT>"
1602*micromips32:
1603*micromips64:
1604{
1605 do_mul (SD_, RD, RS, RT);
1606}
1607
1608
1609000000,5.RT,5.RS,1000101100,111100:POOL32A:32::MULT
1610"mult r<RS>, r<RT>"
1611*micromips32:
1612*micromips64:
1613{
1614 do_mult (SD_, RS, RT, 0);
1615}
1616
1617
1618000000,5.RT,5.RS,1001101100,111100:POOL32A:32::MULTU
1619"multu r<RS> r<RT>"
1620*micromips32:
1621*micromips64:
1622{
1623 do_multu (SD_, RS, RT, 0);
1624}
1625
1626
1627000000,00000000000000000000,000000:POOL32A:32::NOP
1628"nop"
1629*micromips32:
1630*micromips64:
1631{
1632}
1633
1634
1635000000,5.RT,5.RS,5.RD,01011,010000:POOL32A:32::NOR
1636"nor r<RD>, r<RS>, r<RT>"
1637*micromips32:
1638*micromips64:
1639{
1640 do_nor (SD_, RS, RT, RD);
1641}
1642
1643
1644000000,5.RT,5.RS,5.RD,01010,010000:POOL32A:32::OR
1645"or r<RD>, r<RS>, r<RT>"
1646*micromips32:
1647*micromips64:
1648{
1649 do_or (SD_, RS, RT, RD);
1650}
1651
1652
1653010100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ORI
1654"ori r<RT>, r<RS>, <IMMEDIATE>"
1655*micromips32:
1656*micromips64:
1657{
1658 do_ori (SD_, RS, RT, IMMEDIATE);
1659}
1660
1661
1662000000,00000000000010100000,000000:POOL32A:32::PAUSE
1663"pause"
1664*micromips32:
1665*micromips64:
1666
1667
1668011000,5.HINT,5.BASE,0010,12.IMMEDIATE:POOL32C:32::PREF
1669"pref <HINT>, <IMMEDIATE>(r<BASE>)"
1670*micromips32:
1671*micromips64:
1672{
1673 do_pref (SD_, HINT, EXTEND12 (IMMEDIATE), BASE);
1674}
1675
1676
1677011000,5.HINT,5.BASE,1010010,9.IMMEDIATE:POOL32C:32::PREFE
1678"prefe <HINT>, <IMMEDIATE>(r<BASE>)"
1679*micromips32:
1680*micromips64:
1681
1682
1683010101,5.INDEX,5.BASE,5.HINT,00110,100000:POOL32F:32::PREFX
1684"prefx <HINT>, r<INDEX>(r<BASE>)"
1685*micromips32:
1686*micromips64:
1687{
1688 do_prefx (SD_, HINT, INDEX, BASE);
1689}
1690
1691000000,5.RT,5.RS,0110101100,111100:POOL32A:32::RDHWR
1692"rdhwr r<RS>, r<RT>"
1693*micromips32:
1694*micromips64:
1695{
1696 do_rdhwr (SD_, RT, RS);
1697}
1698
1699000000,5.RT,5.RS,1110000101,111100:POOL32A:32::RDPGPR
1700"rdpgpr r<RS>, r<RT>"
1701*micromips32:
1702*micromips64:
1703
1704
1705000000,5.RT,5.RS,5.SHIFT,00011,000000:POOL32A:32::ROTR
1706"rotr r<RT>, r<RS>, <SHIFT>"
1707*micromips32:
1708*micromips64:
1709{
1710 GPR[RT] = do_ror (SD_, GPR[RS], SHIFT);
1711}
1712
1713
1714000000,5.RT,5.RS,5.RD,00011,010000:POOL32A:32::ROTRV
1715"rotrv r<RD>, r<RT>, r<RS>"
1716*micromips32:
1717*micromips64:
1718{
1719 GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
1720}
1721
1722
1723000110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SB
1724"sb r<RT>, <IMMEDIATE>(r<BASE>)"
1725*micromips32:
1726*micromips64:
1727{
1728 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (IMMEDIATE), GPR[RT]);
1729}
1730
1731
1732011000,5.RT,5.BASE,1010101,9.IMMEDIATE:POOL32C:32::SBE
1733"sbe r<RT>, <IMMEDIATE>(r<BASE>)"
1734*micromips32:
1735*micromips64:
1736
1737
1738011000,5.RT,5.BASE,1011,12.IMMEDIATE:POOL32C:32::SC
1739"sc r<RT>, <IMMEDIATE>(r<BASE>)"
1740*micromips32:
1741*micromips64:
1742{
1743 do_sc (SD_, RT, EXTEND12 (IMMEDIATE), BASE, instruction_0);
1744}
1745
1746
1747011000,5.RT,5.BASE,1010110,9.IMMEDIATE:POOL32C:32::SCE
1748"sce r<RT>, <IMMEDIATE>(r<BASE>)"
1749*micromips32:
1750*micromips64:
1751
1752
1753000000,10.CODE,1101101101,111100:POOL32A:32::SDBBP
1754"sdbbp %#lx<CODE>"
1755*micromips32:
1756*micromips64:
1757{
1758 SignalException (DebugBreakPoint, instruction_0);
1759}
1760
1761
1762101110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SDC1a
1763"sdc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1764*micromips32:
1765{
1766 do_sdc1 (SD_, FT, IMMEDIATE, BASE);
1767}
1768
1769
1770101110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SDC1b
1771"sdc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1772*micromips64:
1773{
1774 check_fpu (SD_);
1775 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (IMMEDIATE),
1776 COP_SD (1, FT));
1777}
1778
1779
1780001000,5.RT,5.BASE,1010,12.IMMEDIATE:MICROMIPS:32::SDC2
1781"sdc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1782*micromips32:
1783*micromips64:
1784
1785
1786000000,5.RT,5.RS,0010101100,111100:POOL32A:32::SEB
1787"seb r<RT>, r<RS>"
1788*micromips32:
1789*micromips64:
1790{
1791 do_seb (SD_, RT, RS);
1792}
1793
1794
1795000000,5.RT,5.RS,0011101100,111100:POOL32A:32::SEH
1796"seh r<RT>, r<RS>"
1797*micromips32:
1798*micromips64:
1799{
1800 do_seh (SD_, RT, RS);
1801}
1802
1803
1804001110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SH
1805"sh r<RT>, <IMMEDIATE>(r<BASE>)"
1806*micromips32:
1807*micromips64:
1808{
1809 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (IMMEDIATE),
1810 GPR[RT]);
1811}
1812
1813
1814011000,5.RT,5.BASE,1010100,9.IMMEDIATE:POOL32C:32::SHE
1815"she r<RT>, <IMMEDIATE>(r<BASE>)"
1816*micromips32:
1817*micromips64:
1818
1819
1820000000,5.RT!0,5.RS!0,5.SHIFT,00000,000000:POOL32A:32::SLL
1821"sll r<RT>, r<RS>, <SHIFT>"
1822*micromips32:
1823*micromips64:
1824{
1825 do_sll (SD_, RS, RT, SHIFT);
1826}
1827
1828
1829000000,5.RT,5.RS,5.RD,00000,010000:POOL32A:32::SLLV
1830"sllv r<RD>, r<RT>, r<RS>"
1831*micromips32:
1832*micromips64:
1833{
1834 do_sllv (SD_, RS, RT, RD);
1835}
1836
1837
1838000000,5.RT,5.RS,5.RD,01101,010000:POOL32A:32::SLT
1839"slt r<RD>, r<RS>, r<RT>"
1840*micromips32:
1841*micromips64:
1842{
1843 do_slt (SD_, RS, RT, RD);
1844}
1845
1846
1847100100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::SLTI
1848"slti r<RT>, r<RS>, <IMMEDIATE>"
1849*micromips32:
1850*micromips64:
1851{
1852 do_slti (SD_, RS, RT, IMMEDIATE);
1853}
1854
1855
1856101100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::SLTIU
1857"sltiu r<RT>, r<RS>, <IMMEDIATE>"
1858*micromips32:
1859*micromips64:
1860{
1861 do_sltiu (SD_, RS, RT, IMMEDIATE);
1862}
1863
1864
1865000000,5.RT,5.RS,5.RD,01110,010000:POOL32A:32::SLTU
1866"sltu r<RD>, r<RS>, r<RT>"
1867*micromips32:
1868*micromips64:
1869{
1870 do_sltu (SD_, RS, RT, RD);
1871}
1872
1873
1874000000,5.RT,5.RS,5.SHIFT,00010,000000:POOL32A:32::SRA
1875"sra r<RT>, r<RS>, <SHIFT>"
1876*micromips32:
1877*micromips64:
1878{
1879 do_sra (SD_, RS, RT, SHIFT);
1880}
1881
1882
1883000000,5.RT,5.RS,5.RD,00010,010000:POOL32A:32::SRAV
1884"srav r<RD>, r<RT>, r<RS>"
1885*micromips32:
1886*micromips64:
1887{
1888 do_srav (SD_, RS, RT, RD);
1889}
1890
1891
1892000000,5.RT,5.RS,5.SHIFT,00001,000000:POOL32A:32::SRL
1893"srl r<RT>, r<RS>, <SHIFT>"
1894*micromips32:
1895*micromips64:
1896{
1897 do_srl (SD_, RS, RT, SHIFT);
1898}
1899
1900
1901000000,5.RT,5.RS,5.RD,00001,010000:POOL32A:32::SRLV
1902"srlv r<RD>, r<RT>, r<RS>"
1903*micromips32:
1904*micromips64:
1905{
1906 do_srlv (SD_, RS, RT, RD);
1907}
1908
1909
1910000000,00000000000000100000,000000:POOL32A:32::SSNOP
1911"ssnop"
1912*micromips32:
1913*micromips64:
1914{
1915}
1916
1917
1918000000,5.RT,5.RS,5.RD,00110,010000:POOL32A:32::SUB
1919"sub r<RD>, r<RS>, r<RT>"
1920*micromips32:
1921*micromips64:
1922{
1923 do_sub (SD_, RD, RS, RT);
1924}
1925
1926
1927000000,5.RT,5.RS,5.RD,00111,010000:POOL32A:32::SUBU
1928"subu r<RD>, r<RS>, r<RT>"
1929*micromips32:
1930*micromips64:
1931{
1932 do_subu (SD_, RS, RT, RD);
1933}
1934
1935
1936010101,5.INDEX,5.BASE,5.FD,00110,001000:POOL32F:32,f::SUXC1
1937"suxc1 f<FD>, r<INDEX>(r<BASE>)"
1938*micromips32:
1939{
1940 do_suxc1_32 (SD_, FD, INDEX, BASE);
1941}
1942
1943
1944010101,5.INDEX,5.BASE,5.FD,00110,001000:POOL32F:64,f::SUXC1
1945"suxc1 f<FD>, r<INDEX>(r<BASE>)"
1946*micromips64:
1947{
1948 check_fpu (SD_);
1949 check_u64 (SD_, instruction_0);
1950 do_suxc1_64 (SD_, FD, INDEX, BASE);
1951}
1952
1953111110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SW
1954"sw r<RT>, <IMMEDIATE>(r<BASE>)"
1955*micromips32:
1956*micromips64:
1957{
1958 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (IMMEDIATE), GPR[RT]);
1959}
1960
1961
1962100110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SWC1
1963"swc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1964*micromips32:
1965*micromips64:
1966{
1967 do_swc1 (SD_, FT, IMMEDIATE, BASE, instruction_0);
1968}
1969
1970
1971001000,5.RT,5.BASE,1000,12.IMMEDIATE:POOL32B:32::SWC2
1972"swc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1973*micromips32:
1974*micromips64:
1975
1976
1977011000,5.RT,5.BASE,1010111,9.IMMEDIATE:POOL32C:32::SWE
1978"swe r<RT>, <IMMEDIATE>(r<BASE>)"
1979*micromips32:
1980*micromips64:
1981
1982
1983011000,5.RT,5.BASE,1000,12.IMMEDIATE:POOL32C:32::SWL
1984"swl r<RT>, <IMMEDIATE>(r<BASE>)"
1985*micromips32:
1986*micromips64:
1987{
1988 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND12 (IMMEDIATE),
1989 GPR[RT]);
1990}
1991
1992
1993011000,5.RT,5.BASE,1010000,9.IMMEDIATE:POOL32C:32::SWLE
1994"swle r<RT>, <IMMEDIATE>(r<BASE>)"
1995*micromips32:
1996*micromips64:
1997
1998
1999001000,5.LWM32REGS,5.BASE,1101,12.IMMEDIATE:POOL32B:32::SWM32
2000"swm32 %s<LWM32REGS>, <IMMEDIATE>(r<BASE>)"
2001*micromips32:
2002*micromips64:
2003{
2004 int address_base = GPR[BASE] + EXTEND12 (IMMEDIATE);
2005 int reg_offset;
2006 for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2007 {
2008 int src = (reg_offset == 8) ? 30 : 16 + reg_offset;
2009 do_store (SD_, AccessLength_WORD, address_base, 4 * reg_offset,
2010 GPR[src]);
2011 }
2012
2013 if (LWM32REGS & 0x10)
2014 do_store (SD_, AccessLength_WORD, address_base, 4 * reg_offset, RA);
2015}
2016
2017
2018001000,5.RS1,5.BASE,1001,12.IMMEDIATE:POOL32B:32::SWP
2019"swp r<RS1>, <IMMEDIATE>(r<BASE>)"
2020*micromips32:
2021*micromips64:
2022{
2023 if (RS1 == 31)
2024 Unpredictable ();
2025 else
2026 {
2027 do_sw (SD_, RS1, EXTEND12 (IMMEDIATE), BASE);
2028 do_sw (SD_, RS1 + 1, EXTEND12 (IMMEDIATE) + 4, BASE);
2029 }
2030}
2031
2032
2033011000,5.RT,5.BASE,1001,12.IMMEDIATE:POOL32C:32::SWR
2034"swr r<RT>, <IMMEDIATE>(r<BASE>)"
2035*micromips32:
2036*micromips64:
2037{
2038 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND12 (IMMEDIATE),
2039 GPR[RT]);
2040}
2041
2042
2043011000,5.RT,5.BASE,1010001,9.IMMEDIATE:POOL32C:32::SWRE
2044"swre r<RT>, <IMMEDIATE>(r<BASE>)"
2045*micromips32:
2046*micromips64:
2047
2048
2049010101,5.INDEX,5.BASE,5.FD,00010,001000:POOL32F:32,f::SWXC1
2050"swxc1 f<FD>, r<INDEX>(r<BASE>)"
2051*micromips32:
2052*micromips64:
2053{
2054 do_swxc1 (SD_, FD, INDEX, BASE, instruction_0);
2055}
2056
2057
2058000000,00000,5.STYPE,0110101101,111100:POOL32A:32::SYNC
2059"sync <STYPE>"
2060*micromips32:
2061*micromips64:
2062{
2063 SyncOperation (STYPE);
2064}
2065
2066
2067010000,10000,5.BASE,16.IMMEDIATE:POOL32I:32::SYNCI
2068"synci <IMMEDIATE>(r<BASE>)"
2069*micromips32:
2070*micromips64:
2071{
2072}
2073
2074000000,10.CODE,1000101101,111100:POOL32A:32::SYSCALL
2075"syscall %#lx<CODE>"
2076*micromips32:
2077*micromips64:
2078{
2079 SignalException (SystemCall, instruction_0);
2080}
2081
2082
2083000000,5.RT,5.RS,4.CODE,000000,111100:POOL32A:32::TEQ
2084"teq r<RS>, r<RT>"
2085*micromips32:
2086*micromips64:
2087{
2088 do_teq (SD_, RS, RT, instruction_0);
2089}
2090
2091
2092010000,01110,5.RS,16.IMMEDIATE:POOL32I:32::TEQI
2093"teqi r<RS>, <IMMEDIATE>"
2094*micromips32:
2095*micromips64:
2096{
2097 do_teqi (SD_, RS, IMMEDIATE, instruction_0);
2098}
2099
2100
2101000000,5.RT,5.RS,4.CODE,001000,111100:POOL32A:32::TGE
2102"tge r<RS>, r<RT>"
2103*micromips32:
2104*micromips64:
2105{
2106 do_tge (SD_, RS, RT, instruction_0);
2107}
2108
2109
2110010000,01001,5.RS,16.IMMEDIATE:POOL32I:32::TGEI
2111"tgei r<RS>, <IMMEDIATE>"
2112*micromips32:
2113*micromips64:
2114{
2115 do_tgei (SD_, RS, IMMEDIATE, instruction_0);
2116}
2117
2118
2119010000,01011,5.RS,16.IMMEDIATE:POOL32I:32::TGEIU
2120"tgeiu r<RS>, <IMMEDIATE>"
2121*micromips32:
2122*micromips64:
2123{
2124 do_tgeiu (SD_, RS, IMMEDIATE, instruction_0);
2125}
2126
2127
2128000000,5.RT,5.RS,4.CODE,010000,111100:POOL32A:32::TGEU
2129"tgeu r<RS>, r<RT>"
2130*micromips32:
2131*micromips64:
2132{
2133 do_tgeu (SD_, RS, RT, instruction_0);
2134}
2135
2136
2137000000,00000000000000001101,111100:POOL32A:32::TLBP
2138"tlbp"
2139*micromips32:
2140*micromips64:
2141
2142
2143000000,00000000000001001101,111100:POOL32A:32::TLBR
2144"tlbr"
2145*micromips32:
2146*micromips64:
2147
2148
2149000000,00000000000010001101,111100:POOL32A:32::TLBWI
2150"tlbwi"
2151*micromips32:
2152*micromips64:
2153
2154
2155000000,00000000000011001101,111100:POOL32A:32::TLBWR
2156"tlbwr"
2157*micromips32:
2158*micromips64:
2159
2160
2161000000,5.RT,5.RS,4.CODE,100000,111100:POOL32A:32::TLT
2162"tlt r<RS>, r<RT>, %#lx<CODE>"
2163*micromips32:
2164*micromips64:
2165{
2166 do_tlt (SD_, RS, RT, instruction_0);
2167}
2168
2169
2170010000,01000,5.RS,16.IMMEDIATE:POOL32I:32::TLTI
2171"tlti r<RS>, <IMMEDIATE>"
2172*micromips32:
2173*micromips64:
2174{
2175 do_tlti (SD_, RS, IMMEDIATE, instruction_0);
2176}
2177
2178
2179010000,01010,5.RS,16.IMMEDIATE:POOL32I:32::TLTIU
2180"tltiu r<RS>, <IMMEDIATE>"
2181*micromips32:
2182*micromips64:
2183{
2184 do_tltiu (SD_, RS, IMMEDIATE, instruction_0);
2185}
2186
2187
2188000000,5.RT,5.RS,4.CODE,101000,111100:POOL32A:32::TLTU
2189"tltu r<RS>, r<RT>"
2190*micromips32:
2191*micromips64:
2192{
2193 do_tltu (SD_, RS, RT, instruction_0);
2194}
2195
2196
2197000000,5.RT,5.RS,4.CODE,110000,111100:POOL32A:32::TNE
2198"tne r<RS>, r<RT>"
2199*micromips32:
2200*micromips64:
2201{
2202 do_tne (SD_, RS, RT, instruction_0);
2203}
2204
2205
2206010000,01100,5.RS,16.IMMEDIATE:POOL32I:32::TNEI
2207"tnei r<RS>, <IMMEDIATE>"
2208*micromips32:
2209*micromips64:
2210{
2211 do_tnei (SD_, RS, IMMEDIATE, instruction_0);
2212}
2213
2214
2215000000,10.CODE,1001001101,111100:POOL32A:32::WAIT
2216"wait"
2217*micromips32:
2218*micromips64:
2219
2220
2221000000,5.RT,5.RS,1111000101,111100:POOL32A:32::WRPGPR
2222"wrpgpr r<RS>, r<RT>"
2223*micromips32:
2224*micromips64:
2225
2226
2227000000,5.RT,5.RS,0111101100,111100:POOL32A:32::WSBH
2228"wsbh r<RT>, r<RS>"
2229*micromips32:
2230*micromips64:
2231{
2232 do_wsbh (SD_, RT, RS);
2233}
2234
2235
2236000000,5.RT,5.RS,5.RD,01100,010000:POOL32A:32::XOR
2237"xor r<RD>, r<RS>, r<RT>"
2238*micromips32:
2239*micromips64:
2240{
2241 do_xor (SD_, RS, RT, RD);
2242}
2243
2244
2245011100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::XORI
2246"xori r<RT>, r<RS>, <IMMEDIATE>"
2247*micromips32:
2248*micromips64:
2249{
2250 do_xori (SD_, RS, RT, IMMEDIATE);
2251}
2252
2253
2254:%s::::FMT_MICROMIPS:int fmt
2255{
2256 switch (fmt)
2257 {
2258 case 0: return "s";
2259 case 1: return "d";
2260 case 2: return "ps";
2261 default: return "?";
2262 }
2263}
2264
2265
2266:%s::::FMT_MICROMIPS_CVT_D:int fmt
2267{
2268 switch (fmt)
2269 {
2270 case 0: return "s";
2271 case 1: return "w";
2272 case 2: return "l";
2273 default: return "?";
2274 }
2275}
2276
2277
2278:%s::::FMT_MICROMIPS_CVT_S:int fmt
2279{
2280 switch (fmt)
2281 {
2282 case 0: return "d";
2283 case 1: return "w";
2284 case 2: return "l";
2285 default: return "?";
2286 }
2287}
2288
2289
2290010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0001101,111011:POOL32F:32,f::ABS.fmt
2291"abs.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2292*micromips32:
2293*micromips64:
2294{
2295 do_abs_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2296 instruction_0);
2297}
2298
2299
2300010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,00,110000:POOL32F:32,f::ADD.fmt
2301"add.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2302*micromips32:
2303*micromips64:
2304{
2305 do_add_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2306 instruction_0);
2307}
2308
2309
2310010101,5.FT,5.FS,5.FD,5.RS,011001:POOL32F:32,f::ALNV.PS
2311"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
2312*micromips32:
2313*micromips64:
2314{
2315 do_alnv_ps (SD_, FD, FS, FT, RS, instruction_0);
2316}
2317
2318
2319010101,5.FT,5.FS,3.CC,0,2.FMT_MICROMIPS!3,4.COND,111100:POOL32F:32,f::C.cond.fmt
2320"c.%s<COND>.%s<FMT_MICROMIPS> f<FS>, f<FT>":CC == 0
2321"c.%s<COND>.%s<FMT_MICROMIPS> <CC>, f<FS>, f<FT>"
2322*micromips32:
2323*micromips64:
2324{
2325 do_c_cond_fmt (SD_, COND, convert_fmt_micromips (SD_, FMT_MICROMIPS), CC,
2326 FS, FT, instruction_0);
2327}
2328
2329
2330010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01001100,111011:POOL32F:32,f::CEIL.L.fmt
2331"ceil.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2332*micromips32:
2333*micromips64:
2334{
2335 do_ceil_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS, instruction_0);
2336}
2337
2338
2339010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01101100,111011:POOL32F:32,f::CEIL.W.fmt
2340"ceil.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2341*micromips32:
2342*micromips64:
2343{
2344 do_ceil_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS, instruction_0);
2345}
2346
2347
2348010101,5.FT,5.FS,0,2.FMT_MICROMIPS_CVT_D!3,1001101,111011:POOL32F:32,f::CVT.D.fmt
2349"cvt.d.%s<FMT_MICROMIPS_CVT_D> f<FT>, f<FS>"
2350*micromips32:
2351*micromips64:
2352{
2353 do_cvt_d_fmt (SD_, convert_fmt_micromips_cvt_d (SD_, FMT_MICROMIPS_CVT_D),
2354 FT, FS, instruction_0);
2355}
2356
2357
2358010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00000100,111011:POOL32F:32,f::CVT.L.fmt
2359"cvt.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2360*micromips32:
2361*micromips64:
2362{
2363 do_cvt_l_fmt (SD_, FMT_MICROMIPS, FT, FS, instruction_0);
2364}
2365
2366
2367010101,5.FT,5.FS,5.FD,00110,000000:POOL32F:32,f::CVT.PS.S
2368"cvt.ps.s f<FD>, f<FS>, f<FT>"
2369*micromips32:
2370*micromips64:
2371{
2372 do_cvt_ps_s (SD_, FD, FS, FT, instruction_0);
2373}
2374
2375
2376010101,5.FT,5.FS,0,2.FMT_MICROMIPS_CVT_S!3,1101101,111011:POOL32F:32,f::CVT.S.fmt
2377"cvt.s.%s<FMT_MICROMIPS_CVT_S> f<FT>, f<FS>"
2378*micromips32:
2379*micromips64:
2380{
2381 do_cvt_s_fmt (SD_, convert_fmt_micromips_cvt_s (SD_, FMT_MICROMIPS_CVT_S),
2382 FT, FS, instruction_0);
2383}
2384
2385
2386010101,5.FT,5.FS,00,10000100,111011:POOL32F:32,f::CVT.S.PL
2387"cvt.s.pl f<FT>, f<FS>"
2388*micromips32:
2389*micromips64:
2390{
2391 do_cvt_s_pl (SD_, FT, FS, instruction_0);
2392}
2393
2394
2395010101,5.FT,5.FS,00,10100100,111011:POOL32F:32,f::CVT.S.PU
2396"cvt.s.pu f<FT>, f<FS>"
2397*micromips32:
2398*micromips64:
2399{
2400 do_cvt_s_pu (SD_, FT, FS, instruction_0);
2401}
2402
2403
2404010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00100100,111011:POOL32F:32,f::CVT.W.fmt
2405"cvt.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2406*micromips32:
2407*micromips64:
2408{
2409 do_cvt_w_fmt (SD_, FMT_MICROMIPS, FT, FS, instruction_0);
2410}
2411
2412
2413010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!2!3,11,110000:POOL32F:32,f::DIV.fmt
2414"div.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2415*micromips32:
2416*micromips64:
2417{
2418 do_div_fmt (SD_, FMT_MICROMIPS, FD, FS, FT, instruction_0);
2419}
2420
2421
2422010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00001100,111011:POOL32F:32,f::FLOOR.L.fmt
2423"floor.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2424*micromips32:
2425*micromips64:
2426{
2427 do_floor_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2428}
2429
2430
2431010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00101100,111011:POOL32F:32,f::FLOOR.W.fmt
2432"floor.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2433*micromips32:
2434*micromips64:
2435{
2436 do_floor_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2437}
2438
2439
2440010101,5.FT,5.FS,5.FD,5.FR,0,2.FMT_MICROMIPS!3,001:POOL32F:32,f::MADD.fmt
2441"madd.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2442*micromips32:
2443*micromips64:
2444{
2445 do_madd_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2446 FT, instruction_0);
2447}
2448
2449010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0000001,111011:POOL32F:32,f::MOV.fmt
2450"mov.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2451*micromips32:
2452*micromips64:
2453{
2454 do_mov_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2455 instruction_0);
2456}
2457
2458
2459010101,5.FT,5.FS,3.CC,00,2.FMT_MICROMIPS!3,00,1.TF,100000:POOL32F:32,f::MOVtf.fmt
2460"mov%s<TF>.%s<FMT_MICROMIPS> f<FT>, f<FS>, <CC>"
2461*micromips32:
2462*micromips64:
2463{
2464 do_movtf_fmt (SD_, TF, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT,
2465 FS, CC);
2466}
2467
2468
2469010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,00,111000:POOL32F:32,f::MOVN.fmt
2470"movn.%s<FMT_MICROMIPS> f<FD>, f<FS>, r<FT>"
2471*micromips32:
2472*micromips64:
2473{
2474 do_movn_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT);
2475}
2476
2477010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,01,111000:POOL32F:32,f::MOVZ.fmt
2478"movz.%s<FMT_MICROMIPS> f<FD>, f<FS>, r<FT>"
2479*micromips32:
2480*micromips64:
2481{
2482 do_movz_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT);
2483}
2484
2485
2486010101,5.FT,5.FS,5.FD,5.FR,1,2.FMT_MICROMIPS!3,001:POOL32F:32,f::MSUB.fmt
2487"msub.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2488*micromips32:
2489*micromips64:
2490{
2491 do_msub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2492 FT, instruction_0);
2493}
2494
2495010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,10,110000:POOL32F:32,f::MUL.fmt
2496"mul.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2497*micromips32:
2498*micromips64:
2499{
2500 do_mul_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2501 instruction_0);
2502}
2503
2504
2505010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0101101,111011:POOL32F:32,f::NEG.fmt
2506"neg.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2507*micromips32:
2508*micromips64:
2509{
2510 do_neg_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2511 instruction_0);
2512}
2513
2514
2515010101,5.FT,5.FS,5.FD,5.FR,0,2.FMT_MICROMIPS!3,010:POOL32F:32,f::NMADD.fmt
2516"nmadd.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2517*micromips32:
2518*micromips64:
2519{
2520 do_nmadd_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2521 FT, instruction_0);
2522}
2523
2524010101,5.FT,5.FS,5.FD,5.FR,1,2.FMT_MICROMIPS!3,010:POOL32F:32,f::NMSUB.fmt
2525"nmsub.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2526*micromips32:
2527*micromips64:
2528{
2529 do_nmsub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2530 FT, instruction_0);
2531}
2532
2533
2534010101,5.FT,5.FS,5.FD,00010,000000:POOL32F:32,f::PLL.PS
2535"pll.ps f<FD>, f<FS>, f<FT>"
2536*micromips32:
2537*micromips64:
2538{
2539 do_pll_ps (SD_, FD, FS, FT, instruction_0);
2540}
2541
2542
2543010101,5.FT,5.FS,5.FD,00011,000000:POOL32F:32,f::PLU.PS
2544"plu.ps f<FD>, f<FS>, f<FT>"
2545*micromips32:
2546*micromips64:
2547{
2548 do_plu_ps (SD_, FD, FS, FT, instruction_0);
2549}
2550
2551
2552010101,5.FT,5.FS,5.FD,00100,000000:POOL32F:32,f::PUL.PS
2553"pul.ps f<FD>, f<FS>, f<FT>"
2554*micromips32:
2555*micromips64:
2556{
2557 do_pul_ps (SD_, FD, FS, FT, instruction_0);
2558}
2559
2560
2561010101,5.FT,5.FS,5.FD,00101,000000:POOL32F:32,f::PUU.PS
2562"puu.ps f<FD>, f<FS>, f<FT>"
2563*micromips32:
2564*micromips64:
2565{
2566 do_puu_ps (SD_, FD, FS, FT, instruction_0);
2567}
2568
2569
2570010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01001000,111011:POOL32F:32,f::RECIP.fmt
2571"recip.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2572*micromips32:
2573*micromips64:
2574{
2575 do_recip_fmt (SD_, FMT_MICROMIPS, FT, FS);
2576}
2577
2578
2579010101,5.FT,5.FS,0,1.FMT_MICROMIPS,11001100,111011:POOL32F:32,f::ROUND.L.fmt
2580"round.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2581*micromips32:
2582*micromips64:
2583{
2584 do_round_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2585}
2586
2587
2588010101,5.FT,5.FS,0,1.FMT_MICROMIPS,11101100,111011:POOL32F:32,f::ROUND.W.fmt
2589"round.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2590*micromips32:
2591*micromips64:
2592{
2593 do_round_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2594}
2595
2596
2597010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00001000,111011:POOL32F:32,f::RSQRT.fmt
2598"rsqrt.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2599*micromips32:
2600*micromips64:
2601{
2602 do_rsqrt_fmt (SD_, FMT_MICROMIPS, FT, FS);
2603}
2604
2605
2606010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00101000,111011:POOL32F:32,f::SQRT.fmt
2607"sqrt.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2608*micromips32:
2609*micromips64:
2610{
2611 do_sqrt_fmt (SD_, FMT_MICROMIPS, FT, FS);
2612}
2613
2614
2615010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,01,110000:POOL32F:32,f::SUB.fmt
2616"sub.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2617*micromips32:
2618*micromips64:
2619{
2620 do_sub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2621 instruction_0);
2622}
2623
2624
2625010101,5.FT,5.FS,0,1.FMT_MICROMIPS,10001100,111011:POOL32F:32,f::TRUNC.L.fmt
2626"trunc.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2627*micromips32:
2628*micromips64:
2629{
2630 do_trunc_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2631}
2632
2633
2634010101,5.FT,5.FS,0,1.FMT_MICROMIPS,10101100,111011:POOL32F:32,f::TRUNC.W.fmt
2635"trunc.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2636*micromips32:
2637*micromips64:
2638{
2639 do_trunc_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2640}
2641
2642001000,5.LWM32REGS,5.BASE,0111,12.OFFSET:POOL32B:64::LDM
2643"ldm %s<LWM32REGS>, <OFFSET>(r<BASE>)"
2644*micromips64:
2645{
2646 int address_base = GPR[BASE] + EXTEND12 (OFFSET);
2647 int reg_offset;
2648 for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2649 {
2650 int dst = (reg_offset == 8) ? 30 : 16 + reg_offset;
2651 GPR[dst] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, address_base,
2652 8 * reg_offset));
2653 }
2654
2655 if (LWM32REGS & 0x10)
2656 RA = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, address_base,
2657 8 * reg_offset));
2658}
2659
2660001000,5.RD,5.BASE,0100,12.OFFSET:POOL32B:64::LDP
2661"ldp r<RD>, <OFFSET>(r<BASE>)"
2662*micromips64:
2663{
2664 if (BASE == RD || RD == 31)
2665 Unpredictable ();
2666 else
2667 {
2668 check_u64 (SD_, instruction_0);
2669 GPR[RD] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
2670 EXTEND12 (OFFSET)));
2671 GPR[RD + 1] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
2672 EXTEND12 (OFFSET) + 8));
2673 }
2674}
2675
2676001000,5.LWM32REGS,5.BASE,1111,12.OFFSET:POOL32B:64::SDM
2677"sdm %s<LWM32REGS>, <OFFSET>(r<BASE>)"
2678*micromips64:
2679{
2680 int address_base = GPR[BASE] + EXTEND12 (OFFSET);
2681 int reg_offset;
2682 for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2683 {
2684 int src = (reg_offset == 8) ? 30 : 16 + reg_offset;
2685 do_store (SD_, AccessLength_DOUBLEWORD, address_base, 8 * reg_offset,
2686 GPR[src]);
2687 }
2688
2689 if (LWM32REGS & 0x10)
2690 do_store (SD_, AccessLength_DOUBLEWORD, address_base, 8 * reg_offset, RA);
2691}
2692
2693001000,5.RD,5.BASE,1100,12.OFFSET:POOL32B:64::SDP
2694"sdp r<RD>, <OFFSET>(r<BASE>)"
2695*micromips64:
2696{
2697 if (RD == 31)
2698 Unpredictable ();
2699 else
2700 {
2701 check_u64 (SD_, instruction_0);
2702 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
2703 GPR[RD]);
2704 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET) + 8,
2705 GPR[RD + 1]);
2706 }
2707}
2708
2709010110,5.RT,5.RS,5.RD,00,100010000:POOL32S:64::DADD
2710"dadd r<RD>, r<RS>, r<RT>"
2711*micromips64:
2712{
2713 check_u64 (SD_, instruction_0);
2714 do_dadd (SD_, RD, RS, RT);
2715}
2716
2717010110,5.RT,5.RS,10.IMMEDIATE,011100:POOL32S:64::DADDI
2718"daddi r<RT>, r<RS>, <IMMEDIATE>"
2719*micromips64:
2720{
2721 check_u64 (SD_, instruction_0);
2722 do_daddi (SD_, RT, RS, IMMEDIATE);
2723}
2724
2725010111,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:64::DADDIU
2726"daddiu r<RT>, r<RS>, <IMMEDIATE>"
2727*micromips64:
2728{
2729 check_u64 (SD_, instruction_0);
2730 do_daddiu (SD_, RS, RT, IMMEDIATE);
2731}
2732
2733010110,5.RT,5.RS,5.RD,00,101010000:POOL32S:64::DADDU
2734"daddu r<RD>, r<RS>, r<RT>"
2735*micromips64:
2736{
2737 check_u64 (SD_, instruction_0);
2738 do_daddu (SD_, RS, RT, RD);
2739}
2740
2741010110,5.RT,5.RS,0100101100,111100:POOL32S:64::DCLO
2742"dclo r<RT>, r<RS>"
2743*micromips64:
2744{
2745 check_u64 (SD_, instruction_0);
2746 do_dclo (SD_, RT, RS);
2747}
2748
2749010110,5.RT,5.RS,0101101100,111100:POOL32S:64::DCLZ
2750"dclz r<RT>, r<RS>"
2751*micromips64:
2752{
2753 check_u64 (SD_, instruction_0);
2754 do_dclz (SD_, RT, RS);
2755}
2756
2757010110,5.RT,5.RS,1010101100,111100:POOL32S:64::DDIV
2758"ddiv r<RS>, r<RT>"
2759*micromips64:
2760{
2761 check_u64 (SD_, instruction_0);
2762 do_ddiv (SD_, RS, RT);
2763}
2764
2765010110,5.RT,5.RS,1011101100,111100:POOL32S:64::DDIVU
2766"ddivu r<RS>, r<RT>"
2767*micromips64:
2768{
2769 check_u64 (SD_, instruction_0);
2770 do_ddivu (SD_, RS, RT);
2771}
2772
2773010110,5.RT,5.RS,5.SIZE,5.LSB,101100:POOL32S:64::DEXT
2774"dext r<RT>, r<RS>, <LSB>, <SIZE+1>"
2775*micromips64:
2776{
2777 check_u64 (SD_, instruction_0);
2778 do_dext (SD_, RT, RS, LSB, SIZE);
2779}
2780
2781010110,5.RT,5.RS,5.SIZE,5.LSB,100100:POOL32S:64::DEXTM
2782"dextm r<RT>, r<RS>, <LSB>, <SIZE+33>"
2783*micromips64:
2784{
2785 check_u64 (SD_, instruction_0);
2786 do_dextm (SD_, RT, RS, LSB, SIZE);
2787}
2788
2789010110,5.RT,5.RS,5.SIZE,5.LSB,010100:POOL32S:64::DEXTU
2790"dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>"
2791*micromips64:
2792{
2793 check_u64 (SD_, instruction_0);
2794 do_dextu (SD_, RT, RS, LSB, SIZE);
2795}
2796
2797010110,5.RT,5.RS,5.MSB,5.LSB,001100:POOL32S:64::DINS
2798"dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
2799*micromips64:
2800{
2801 check_u64 (SD_, instruction_0);
2802 do_dins (SD_, RT, RS, LSB, MSB);
2803}
2804
2805010110,5.RT,5.RS,5.MSB,5.LSB,000100:POOL32S:64::DINSM
2806"dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>"
2807*micromips64:
2808{
2809 check_u64 (SD_, instruction_0);
2810 do_dinsm (SD_, RT, RS, LSB, MSB);
2811}
2812
2813010110,5.RT,5.RS,5.MSB,5.LSB,110100:POOL32S:64::DINSU
2814"dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>"
2815*micromips64:
2816{
2817 check_u64 (SD_, instruction_0);
2818 do_dinsu (SD_, RT, RS, LSB, MSB);
2819}
2820
2821010110,5.RT,5.RS,00,3.SEL,00011,111100:POOL32S:64::DMFC0
2822"dmfc0 r<RT>, r<RS>": SEL == 0
2823"dmfc0 r<RT>, r<RS>, <SEL>"
2824*micromips64:
2825{
2826 check_u64 (SD_, instruction_0);
2827 DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RS, SEL);
2828}
2829
2830010101,5.RT,5.FS,00,10010000,111011:POOL32F:64::DMFC1
2831"dmfc1 r<RT>, f<FS>"
2832*micromips64:
2833{
2834 check_fpu (SD_);
2835 check_u64 (SD_, instruction_0);
2836 do_dmfc1b (SD_, RT, FS);
2837}
2838
2839010110,5.RT,5.RS,00,3.SEL,01011,111100:POOL32S:64::DMTC0
2840"dmtc0 r<RT>, r<RS>": SEL == 0
2841"dmtc0 r<RT>, r<RS>, <SEL>"
2842*micromips64:
2843{
2844 check_u64 (SD_, instruction_0);
2845 DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RS, SEL);
2846}
2847
2848010101,5.RT,5.FS,00,10110000,111011:POOL32F:64::DMTC1
2849"dmtc1 r<RT>, f<FS>"
2850*micromips64:
2851{
2852 check_fpu (SD_);
2853 check_u64 (SD_, instruction_0);
2854 do_dmtc1b (SD_, RT, FS);
2855}
2856
2857010110,5.RT,5.RS,1000101100,111100:POOL32S:64::DMULT
2858"dmult r<RS>, r<RT>"
2859*micromips64:
2860{
2861 check_u64 (SD_, instruction_0);
2862 do_dmult (SD_, RS, RT, 0);
2863}
2864
2865010110,5.RT,5.RS,1001101100,111100:POOL32S:64::DMULTU
2866"dmultu r<RS>, r<RT>"
2867*micromips64:
2868{
2869 check_u64 (SD_, instruction_0);
2870 do_dmultu (SD_, RS, RT, 0);
2871}
2872
2873010110,5.RT,5.RS,5.SA,00,011000000:POOL32S:64::DROTR
2874"drotr r<RT>, r<RS>, <SA>"
2875*micromips64:
2876{
2877 check_u64 (SD_, instruction_0);
2878 GPR[RT] = do_dror (SD_, GPR[RS], SA);
2879}
2880
2881010110,5.RT,5.RS,5.SA,00,011001000:POOL32S:64::DROTR32
2882"drotr32 r<RT>, r<RS>, <SA+32>"
2883*micromips64:
2884{
2885 check_u64 (SD_, instruction_0);
2886 GPR[RT] = do_dror (SD_, GPR[RS], SA + 32);
2887}
2888
2889010110,5.RT,5.RS,5.RD,00,011010000:POOL32S:64::DROTRV
2890"drotrv r<RD>, r<RT>, r<RS>"
2891*micromips64:
2892{
2893 check_u64 (SD_, instruction_0);
2894 GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
2895}
2896
2897010110,5.RT,5.RS,0111101100,111100:POOL32S:64::DSBH
2898"dsbh r<RT>, r<RS>"
2899*micromips64:
2900{
2901 check_u64 (SD_, instruction_0);
2902 do_dsbh (SD_, RT, RS);
2903}
2904
2905010110,5.RT,5.RS,1111101100,111100:POOL32S:64::DSHD
2906"dshd r<RT>, r<RS>"
2907*micromips64:
2908{
2909 check_u64 (SD_, instruction_0);
2910 do_dshd (SD_, RS, RT);
2911}
2912
2913010110,5.RT,5.RS,5.SA,00,000000000:POOL32S:64::DSLL
2914"dsll r<RT>, r<RS>, <SA>"
2915*micromips64:
2916{
2917 check_u64 (SD_, instruction_0);
2918 do_dsll (SD_, RS, RT, SA);
2919}
2920
2921010110,5.RT,5.RS,5.SA,00,000001000:POOL32S:64::DSLL32
2922"dsll32 r<RT>, r<RS>, <SA>"
2923*micromips64:
2924{
2925 check_u64 (SD_, instruction_0);
2926 do_dsll32 (SD_, RT, RS, SA);
2927}
2928
2929010110,5.RT,5.RS,5.RD,00,000010000:POOL32S:64::DSLLV
2930"dsllv r<RD>, r<RT>, r<RS>"
2931*micromips64:
2932{
2933 check_u64 (SD_, instruction_0);
2934 do_dsllv (SD_, RS, RT, RD);
2935}
2936
2937010110,5.RT,5.RS,5.SA,00,010000000:POOL32S:64::DSRA
2938"dsra r<RT>, r<RS>, <SA>"
2939*micromips64:
2940{
2941 check_u64 (SD_, instruction_0);
2942 do_dsra (SD_, RS, RT, SA);
2943}
2944
2945010110,5.RT,5.RS,5.SA,00,010001000:POOL32S:64::DSRA32
2946"dsra32 r<RT>, r<RS>, <SA>"
2947*micromips64:
2948{
2949 check_u64 (SD_, instruction_0);
2950 do_dsra32 (SD_, RT, RS, SA);
2951}
2952
2953010110,5.RT,5.RS,5.RD,00,010010000:POOL32S:64::DSRAV
2954"dsrav r<RD>, r<RS>, r<RT>"
2955*micromips64:
2956{
2957 check_u64 (SD_, instruction_0);
2958 do_dsrav (SD_, RS, RT, RD);
2959}
2960
2961010110,5.RT,5.RS,5.SA,00,001000000:POOL32S:64::DSRL
2962"dsrl r<RT>, r<RS>, <SA>"
2963*micromips64:
2964{
2965 check_u64 (SD_, instruction_0);
2966 do_dsrl (SD_, RS, RT, SA);
2967}
2968
2969010110,5.RT,5.RS,5.SA,00,001001000:POOL32S:64::DSRL32
2970"dsrl32 r<RT>, r<RS>, <SA>"
2971*micromips64:
2972{
2973 check_u64 (SD_, instruction_0);
2974 do_dsrl32 (SD_, RT, RS, SA);
2975}
2976
2977010110,5.RT,5.RS,5.RD,00,001010000:POOL32S:64::DSRLV
2978"dsrlv r<RD>, r<RT>, r<RS>"
2979*micromips64:
2980{
2981 check_u64 (SD_, instruction_0);
2982 do_dsrlv (SD_, RS, RT, RD);
2983}
2984
2985010110,5.RT,5.RS,5.RD,00,110001000:POOL32S:64::DSUB
2986"dsub r<RD>, r<RS>, r<RT>"
2987*micromips64:
2988{
2989 check_u64 (SD_, instruction_0);
2990 do_dsub (SD_, RD, RS, RT);
2991}
2992
2993010110,5.RT,5.RS,5.RD,00,111001000:POOL32S:64::DSUBU
2994"dsubu r<RD>, r<RS>, r<RT>"
2995*micromips64:
2996{
2997 check_u64 (SD_, instruction_0);
2998 do_dsubu (SD_, RS, RT, RD);
2999}
3000
3001110111,5.RT,5.BASE,16.OFFSET:MICROMIPS64:64::LD
3002"ld r<RT>, <OFFSET>(r<BASE>)"
3003*micromips64:
3004{
3005 check_u64 (SD_, instruction_0);
3006 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3007 EXTEND16 (OFFSET)));
3008}
3009
3010011000,5.RT,5.BASE,0100,12.OFFSET:POOL32C:64::LDL
3011"ldl r<RT>, <OFFSET>(r<BASE>)"
3012*micromips64:
3013{
3014 check_u64 (SD_, instruction_0);
3015 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3016 EXTEND12 (OFFSET), GPR[RT]);
3017}
3018
3019011000,5.RT,5.BASE,0101,12.OFFSET:POOL32C:64::LDR
3020"ldr r<RT>, <OFFSET>(r<BASE>)"
3021*micromips64:
3022{
3023 check_u64 (SD_, instruction_0);
3024 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3025 EXTEND12 (OFFSET), GPR[RT]);
3026}
3027
3028010101,5.INDEX,5.BASE,5.FD,00,011001000:POOL32F:64,f::LDXC1
3029"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3030*micromips64:
3031{
3032 check_fpu (SD_);
3033 check_u64 (SD_, instruction_0);
3034 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3035}
3036
3037011000,5.RT,5.BASE,0111,12.OFFSET:POOL32C:64::LLD
3038"lld r<RT>, <OFFSET>(r<BASE>)"
3039*micromips64:
3040{
3041 check_u64 (SD_, instruction_0);
3042 do_lld (SD_, RT, OFFSET, BASE);
3043}
3044
3045011000,5.RT,5.BASE,1111,12.OFFSET:POOL32C:64::SCD
3046"scd r<RT>, <OFFSET>(r<BASE>)"
3047*micromips64:
3048{
3049 check_u64 (SD_, instruction_0);
3050 do_scd (SD_, RT, OFFSET, BASE);
3051}
3052
3053110110,5.RT,5.BASE,16.OFFSET:MICROMIPS64:64::SD
3054"sd r<RT>, <OFFSET>(r<BASE>)"
3055*micromips64:
3056{
3057 check_u64 (SD_, instruction_0);
3058 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET),
3059 GPR[RT]);
3060}
3061
3062011000,5.RT,5.BASE,1100,12.OFFSET:POOL32C:64::SDL
3063"sdl r<RT>, <OFFSET>(r<BASE>)"
3064*micromips64:
3065{
3066 check_u64 (SD_, instruction_0);
3067 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
3068 GPR[RT]);
3069}
3070
3071011000,5.RT,5.BASE,1101,12.OFFSET:POOL32C:64::SDR
3072"sdr r<RT>, <OFFSET>(r<BASE>)"
3073*micromips64:
3074{
3075 check_u64 (SD_, instruction_0);
3076 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
3077 GPR[RT]);
3078}
3079
3080010101,5.INDEX,5.BASE,5.FD,00,100001000:POOL32F:64,f::SDXC1
3081"sdxc1 f<FD>, r<INDEX>(r<BASE>)"
3082*micromips64:
3083{
3084 check_fpu (SD_);
3085 check_u64 (SD_, instruction_0);
3086 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX],
3087 COP_SD (1, FD));
3088}
GDB Binutils - Deliverables
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