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[deliverable/binutils-gdb.git] / sim / mips / mips.igen
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c906108c
SS		 1// -*- C -*-
2//
3// In mips.igen, the semantics for many of the instructions were created
4// using code generated by gencode. Those semantic segments could be
5// greatly simplified.
6//
7// <insn> ::=
8// <insn-word> { "+" <insn-word> }
9// ":" <format-name>
10// ":" <filter-flags>
11// ":" <options>
12// ":" <name>
13// <nl>
14// { <insn-model> }
15// { <insn-mnemonic> }
16// <code-block>
17//
18
19
20// IGEN config - mips16
21// :option:16::insn-bit-size:16
22// :option:16::hi-bit-nr:15
23:option:16::insn-specifying-widths:true
24:option:16::gen-delayed-branch:false
25
26// IGEN config - mips32/64..
27// :option:32::insn-bit-size:32
28// :option:32::hi-bit-nr:31
29:option:32::insn-specifying-widths:true
30:option:32::gen-delayed-branch:false
31
32
33// Generate separate simulators for each target
34// :option:::multi-sim:true
35
36
37// Models known by this simulator
38:model:::mipsI:mips3000:
39:model:::mipsII:mips6000:
40:model:::mipsIII:mips4000:
41:model:::mipsIV:mips8000:
42:model:::mips16:mips16:
43:model:::r3900:mips3900:
44:model:::vr4100:mips4100:
45:model:::vr5000:mips5000:
46
47
48
49// Pseudo instructions known by IGEN
50:internal::::illegal:
51{
52 SignalException (ReservedInstruction, 0);
53}
54
55
56// Pseudo instructions known by interp.c
57// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
58000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
59"rsvd <OP>"
60{
61 SignalException (ReservedInstruction, instruction_0);
62}
63
64
65
66// Helper:
67//
68// Simulate a 32 bit delayslot instruction
69//
70
71:function:::address_word:delayslot32:address_word target
72{
73 instruction_word delay_insn;
74 sim_events_slip (SD, 1);
75 DSPC = CIA;
76 CIA = CIA + 4; /* NOTE not mips16 */
77 STATE |= simDELAYSLOT;
78 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
d4f3574e 79 ENGINE_ISSUE_PREFIX_HOOK();
c906108c
SS		 80 idecode_issue (CPU_, delay_insn, (CIA));
81 STATE &= ~simDELAYSLOT;
82 return target;
83}
84
85:function:::address_word:nullify_next_insn32:
86{
87 sim_events_slip (SD, 1);
88 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
89 return CIA + 8;
90}
91
92// Helper:
93//
94// Check that an access to a HI/LO register meets timing requirements
95//
96// The following requirements exist:
97//
98// - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
99// - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
100// - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
101// corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
102//
103
104:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
105{
106 if (history->mf.timestamp + 3 > time)
107 {
108 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
109 itable[MY_INDEX].name,
110 new, (long) CIA,
111 (long) history->mf.cia);
112 return 0;
113 }
114 return 1;
115}
116
117:function:::int:check_mt_hilo:hilo_history *history
118*mipsI,mipsII,mipsIII,mipsIV:
119*vr4100:
120*vr5000:
121{
122 signed64 time = sim_events_time (SD);
123 int ok = check_mf_cycles (SD_, history, time, "MT");
124 history->mt.timestamp = time;
125 history->mt.cia = CIA;
126 return ok;
127}
128
129:function:::int:check_mt_hilo:hilo_history *history
130*r3900:
131{
132 signed64 time = sim_events_time (SD);
133 history->mt.timestamp = time;
134 history->mt.cia = CIA;
135 return 1;
136}
137
138
139:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
140*mipsI,mipsII,mipsIII,mipsIV:
141*vr4100:
142*vr5000:
143*r3900:
144{
145 signed64 time = sim_events_time (SD);
146 int ok = 1;
147 if (peer != NULL
148 && peer->mt.timestamp > history->op.timestamp
149 && history->mt.timestamp < history->op.timestamp
150 && ! (history->mf.timestamp > history->op.timestamp
151 && history->mf.timestamp < peer->mt.timestamp)
152 && ! (peer->mf.timestamp > history->op.timestamp
153 && peer->mf.timestamp < peer->mt.timestamp))
154 {
155 /* The peer has been written to since the last OP yet we have
156 not */
157 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
158 itable[MY_INDEX].name,
159 (long) CIA,
160 (long) history->op.cia,
161 (long) peer->mt.cia);
162 ok = 0;
163 }
164 history->mf.timestamp = time;
165 history->mf.cia = CIA;
166 return ok;
167}
168
169
170
171:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
172*mipsI,mipsII,mipsIII,mipsIV:
173*vr4100:
174*vr5000:
175{
176 signed64 time = sim_events_time (SD);
177 int ok = (check_mf_cycles (SD_, hi, time, "OP")
178 && check_mf_cycles (SD_, lo, time, "OP"));
179 hi->op.timestamp = time;
180 lo->op.timestamp = time;
181 hi->op.cia = CIA;
182 lo->op.cia = CIA;
183 return ok;
184}
185
186// The r3900 mult and multu insns _can_ be exectuted immediatly after
187// a mf{hi,lo}
188:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
189*r3900:
190{
191 /* FIXME: could record the fact that a stall occured if we want */
192 signed64 time = sim_events_time (SD);
193 hi->op.timestamp = time;
194 lo->op.timestamp = time;
195 hi->op.cia = CIA;
196 lo->op.cia = CIA;
197 return 1;
198}
199
200
201:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
202*mipsI,mipsII,mipsIII,mipsIV:
203*vr4100:
204*vr5000:
205*r3900:
206{
207 signed64 time = sim_events_time (SD);
208 int ok = (check_mf_cycles (SD_, hi, time, "OP")
209 && check_mf_cycles (SD_, lo, time, "OP"));
210 hi->op.timestamp = time;
211 lo->op.timestamp = time;
212 hi->op.cia = CIA;
213 lo->op.cia = CIA;
214 return ok;
215}
216
217
218
219
220
221//
222// Mips Architecture:
223//
224// CPU Instruction Set (mipsI - mipsIV)
225//
226
227
228
229000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
230"add r<RD>, r<RS>, r<RT>"
231*mipsI,mipsII,mipsIII,mipsIV:
232*vr4100:
233*vr5000:
234*r3900:
235{
236 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
237 {
238 ALU32_BEGIN (GPR[RS]);
239 ALU32_ADD (GPR[RT]);
9805e229 240 ALU32_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 241 }
242 TRACE_ALU_RESULT (GPR[RD]);
243}
244
245
246
247001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
20ae0098 248"addi r<RT>, r<RS>, <IMMEDIATE>"
c906108c
SS		 249*mipsI,mipsII,mipsIII,mipsIV:
250*vr4100:
251*vr5000:
252*r3900:
253{
254 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
255 {
256 ALU32_BEGIN (GPR[RS]);
257 ALU32_ADD (EXTEND16 (IMMEDIATE));
9805e229 258 ALU32_END (GPR[RT]); /* This checks for overflow. */
c906108c
SS		 259 }
260 TRACE_ALU_RESULT (GPR[RT]);
261}
262
263
264
265:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
266{
267 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
268 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
269 TRACE_ALU_RESULT (GPR[rt]);
270}
271
272001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
273"addiu r<RT>, r<RS>, <IMMEDIATE>"
274*mipsI,mipsII,mipsIII,mipsIV:
275*vr4100:
276*vr5000:
277*r3900:
278{
279 do_addiu (SD_, RS, RT, IMMEDIATE);
280}
281
282
283
284:function:::void:do_addu:int rs, int rt, int rd
285{
286 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
287 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
288 TRACE_ALU_RESULT (GPR[rd]);
289}
290
291000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
292"addu r<RD>, r<RS>, r<RT>"
293*mipsI,mipsII,mipsIII,mipsIV:
294*vr4100:
295*vr5000:
296*r3900:
297{
298 do_addu (SD_, RS, RT, RD);
299}
300
301
302
303:function:::void:do_and:int rs, int rt, int rd
304{
305 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
306 GPR[rd] = GPR[rs] & GPR[rt];
307 TRACE_ALU_RESULT (GPR[rd]);
308}
309
310000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
311"and r<RD>, r<RS>, r<RT>"
312*mipsI,mipsII,mipsIII,mipsIV:
313*vr4100:
314*vr5000:
315*r3900:
316{
317 do_and (SD_, RS, RT, RD);
318}
319
320
321
322001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
323"and r<RT>, r<RS>, <IMMEDIATE>"
324*mipsI,mipsII,mipsIII,mipsIV:
325*vr4100:
326*vr5000:
327*r3900:
328{
329 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
330 GPR[RT] = GPR[RS] & IMMEDIATE;
331 TRACE_ALU_RESULT (GPR[RT]);
332}
333
334
335
336000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
337"beq r<RS>, r<RT>, <OFFSET>"
338*mipsI,mipsII,mipsIII,mipsIV:
339*vr4100:
340*vr5000:
341*r3900:
342{
343 address_word offset = EXTEND16 (OFFSET) << 2;
344 check_branch_bug ();
345 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
346 {
347 mark_branch_bug (NIA+offset);
348 DELAY_SLOT (NIA + offset);
349 }
350}
351
352
353
354010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
355"beql r<RS>, r<RT>, <OFFSET>"
356*mipsII:
357*mipsIII:
358*mipsIV:
359*vr4100:
360*vr5000:
361*r3900:
362{
363 address_word offset = EXTEND16 (OFFSET) << 2;
364 check_branch_bug ();
365 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
366 {
367 mark_branch_bug (NIA+offset);
368 DELAY_SLOT (NIA + offset);
369 }
370 else
371 NULLIFY_NEXT_INSTRUCTION ();
372}
373
374
375
376000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
377"bgez r<RS>, <OFFSET>"
378*mipsI,mipsII,mipsIII,mipsIV:
379*vr4100:
380*vr5000:
381*r3900:
382{
383 address_word offset = EXTEND16 (OFFSET) << 2;
384 check_branch_bug ();
385 if ((signed_word) GPR[RS] >= 0)
386 {
387 mark_branch_bug (NIA+offset);
388 DELAY_SLOT (NIA + offset);
389 }
390}
391
392
393
394000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
395"bgezal r<RS>, <OFFSET>"
396*mipsI,mipsII,mipsIII,mipsIV:
397*vr4100:
398*vr5000:
399*r3900:
400{
401 address_word offset = EXTEND16 (OFFSET) << 2;
402 check_branch_bug ();
403 RA = (CIA + 8);
404 if ((signed_word) GPR[RS] >= 0)
405 {
406 mark_branch_bug (NIA+offset);
407 DELAY_SLOT (NIA + offset);
408 }
409}
410
411
412
413000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
414"bgezall r<RS>, <OFFSET>"
415*mipsII:
416*mipsIII:
417*mipsIV:
418*vr4100:
419*vr5000:
420*r3900:
421{
422 address_word offset = EXTEND16 (OFFSET) << 2;
423 check_branch_bug ();
424 RA = (CIA + 8);
425 /* NOTE: The branch occurs AFTER the next instruction has been
426 executed */
427 if ((signed_word) GPR[RS] >= 0)
428 {
429 mark_branch_bug (NIA+offset);
430 DELAY_SLOT (NIA + offset);
431 }
432 else
433 NULLIFY_NEXT_INSTRUCTION ();
434}
435
436
437
438000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
439"bgezl r<RS>, <OFFSET>"
440*mipsII:
441*mipsIII:
442*mipsIV:
443*vr4100:
444*vr5000:
445*r3900:
446{
447 address_word offset = EXTEND16 (OFFSET) << 2;
448 check_branch_bug ();
449 if ((signed_word) GPR[RS] >= 0)
450 {
451 mark_branch_bug (NIA+offset);
452 DELAY_SLOT (NIA + offset);
453 }
454 else
455 NULLIFY_NEXT_INSTRUCTION ();
456}
457
458
459
460000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
461"bgtz r<RS>, <OFFSET>"
462*mipsI,mipsII,mipsIII,mipsIV:
463*vr4100:
464*vr5000:
465*r3900:
466{
467 address_word offset = EXTEND16 (OFFSET) << 2;
468 check_branch_bug ();
469 if ((signed_word) GPR[RS] > 0)
470 {
471 mark_branch_bug (NIA+offset);
472 DELAY_SLOT (NIA + offset);
473 }
474}
475
476
477
478010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
479"bgtzl r<RS>, <OFFSET>"
480*mipsII:
481*mipsIII:
482*mipsIV:
483*vr4100:
484*vr5000:
485*r3900:
486{
487 address_word offset = EXTEND16 (OFFSET) << 2;
488 check_branch_bug ();
489 /* NOTE: The branch occurs AFTER the next instruction has been
490 executed */
491 if ((signed_word) GPR[RS] > 0)
492 {
493 mark_branch_bug (NIA+offset);
494 DELAY_SLOT (NIA + offset);
495 }
496 else
497 NULLIFY_NEXT_INSTRUCTION ();
498}
499
500
501
502000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
503"blez r<RS>, <OFFSET>"
504*mipsI,mipsII,mipsIII,mipsIV:
505*vr4100:
506*vr5000:
507*r3900:
508{
509 address_word offset = EXTEND16 (OFFSET) << 2;
510 check_branch_bug ();
511 /* NOTE: The branch occurs AFTER the next instruction has been
512 executed */
513 if ((signed_word) GPR[RS] <= 0)
514 {
515 mark_branch_bug (NIA+offset);
516 DELAY_SLOT (NIA + offset);
517 }
518}
519
520
521
522010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
523"bgezl r<RS>, <OFFSET>"
524*mipsII:
525*mipsIII:
526*mipsIV:
527*vr4100:
528*vr5000:
529*r3900:
530{
531 address_word offset = EXTEND16 (OFFSET) << 2;
532 check_branch_bug ();
533 if ((signed_word) GPR[RS] <= 0)
534 {
535 mark_branch_bug (NIA+offset);
536 DELAY_SLOT (NIA + offset);
537 }
538 else
539 NULLIFY_NEXT_INSTRUCTION ();
540}
541
542
543
544000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
545"bltz r<RS>, <OFFSET>"
546*mipsI,mipsII,mipsIII,mipsIV:
547*vr4100:
548*vr5000:
549*r3900:
550{
551 address_word offset = EXTEND16 (OFFSET) << 2;
552 check_branch_bug ();
553 if ((signed_word) GPR[RS] < 0)
554 {
555 mark_branch_bug (NIA+offset);
556 DELAY_SLOT (NIA + offset);
557 }
558}
559
560
561
562000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
563"bltzal r<RS>, <OFFSET>"
564*mipsI,mipsII,mipsIII,mipsIV:
565*vr4100:
566*vr5000:
567*r3900:
568{
569 address_word offset = EXTEND16 (OFFSET) << 2;
570 check_branch_bug ();
571 RA = (CIA + 8);
572 /* NOTE: The branch occurs AFTER the next instruction has been
573 executed */
574 if ((signed_word) GPR[RS] < 0)
575 {
576 mark_branch_bug (NIA+offset);
577 DELAY_SLOT (NIA + offset);
578 }
579}
580
581
582
583000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
584"bltzall r<RS>, <OFFSET>"
585*mipsII:
586*mipsIII:
587*mipsIV:
588*vr4100:
589*vr5000:
590*r3900:
591{
592 address_word offset = EXTEND16 (OFFSET) << 2;
593 check_branch_bug ();
594 RA = (CIA + 8);
595 if ((signed_word) GPR[RS] < 0)
596 {
597 mark_branch_bug (NIA+offset);
598 DELAY_SLOT (NIA + offset);
599 }
600 else
601 NULLIFY_NEXT_INSTRUCTION ();
602}
603
604
605
606000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
607"bltzl r<RS>, <OFFSET>"
608*mipsII:
609*mipsIII:
610*mipsIV:
611*vr4100:
612*vr5000:
613*r3900:
614{
615 address_word offset = EXTEND16 (OFFSET) << 2;
616 check_branch_bug ();
617 /* NOTE: The branch occurs AFTER the next instruction has been
618 executed */
619 if ((signed_word) GPR[RS] < 0)
620 {
621 mark_branch_bug (NIA+offset);
622 DELAY_SLOT (NIA + offset);
623 }
624 else
625 NULLIFY_NEXT_INSTRUCTION ();
626}
627
628
629
630000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
631"bne r<RS>, r<RT>, <OFFSET>"
632*mipsI,mipsII,mipsIII,mipsIV:
633*vr4100:
634*vr5000:
635*r3900:
636{
637 address_word offset = EXTEND16 (OFFSET) << 2;
638 check_branch_bug ();
639 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
640 {
641 mark_branch_bug (NIA+offset);
642 DELAY_SLOT (NIA + offset);
643 }
644}
645
646
647
648010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
649"bnel r<RS>, r<RT>, <OFFSET>"
650*mipsII:
651*mipsIII:
652*mipsIV:
653*vr4100:
654*vr5000:
655*r3900:
656{
657 address_word offset = EXTEND16 (OFFSET) << 2;
658 check_branch_bug ();
659 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
660 {
661 mark_branch_bug (NIA+offset);
662 DELAY_SLOT (NIA + offset);
663 }
664 else
665 NULLIFY_NEXT_INSTRUCTION ();
666}
667
668
669
670000000,20.CODE,001101:SPECIAL:32::BREAK
20ae0098 671"break <CODE>"
c906108c
SS		 672*mipsI,mipsII,mipsIII,mipsIV:
673*vr4100:
674*vr5000:
675*r3900:
676{
677 /* Check for some break instruction which are reserved for use by the simulator. */
678 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
679 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
680 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
681 {
682 sim_engine_halt (SD, CPU, NULL, cia,
683 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
684 }
685 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
686 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
687 {
688 if (STATE & simDELAYSLOT)
689 PC = cia - 4; /* reference the branch instruction */
690 else
691 PC = cia;
692 SignalException(BreakPoint, instruction_0);
693 }
694
695 else
696 {
697 /* If we get this far, we're not an instruction reserved by the sim. Raise
698 the exception. */
699 SignalException(BreakPoint, instruction_0);
700 }
701}
702
703
704
c906108c
SS		 705000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
706"dadd r<RD>, r<RS>, r<RT>"
707*mipsIII:
708*mipsIV:
709*vr4100:
710*vr5000:
711{
c906108c
SS		 712 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
713 {
714 ALU64_BEGIN (GPR[RS]);
715 ALU64_ADD (GPR[RT]);
9805e229 716 ALU64_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 717 }
718 TRACE_ALU_RESULT (GPR[RD]);
719}
720
721
722
723011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
724"daddi r<RT>, r<RS>, <IMMEDIATE>"
725*mipsIII:
726*mipsIV:
727*vr4100:
728*vr5000:
729{
730 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
731 {
732 ALU64_BEGIN (GPR[RS]);
733 ALU64_ADD (EXTEND16 (IMMEDIATE));
9805e229 734 ALU64_END (GPR[RT]); /* This checks for overflow. */
c906108c
SS		 735 }
736 TRACE_ALU_RESULT (GPR[RT]);
737}
738
739
740
741:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
742{
743 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
744 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
745 TRACE_ALU_RESULT (GPR[rt]);
746}
747
748011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
20ae0098 749"daddiu r<RT>, r<RS>, <IMMEDIATE>"
c906108c
SS		 750*mipsIII:
751*mipsIV:
752*vr4100:
753*vr5000:
754{
755 do_daddiu (SD_, RS, RT, IMMEDIATE);
756}
757
758
759
760:function:::void:do_daddu:int rs, int rt, int rd
761{
762 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
763 GPR[rd] = GPR[rs] + GPR[rt];
764 TRACE_ALU_RESULT (GPR[rd]);
765}
766
767000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
768"daddu r<RD>, r<RS>, r<RT>"
769*mipsIII:
770*mipsIV:
771*vr4100:
772*vr5000:
773{
774 do_daddu (SD_, RS, RT, RD);
775}
776
777
778
779:function:::void:do_ddiv:int rs, int rt
780{
781 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
782 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
783 {
784 signed64 n = GPR[rs];
785 signed64 d = GPR[rt];
786 signed64 hi;
787 signed64 lo;
788 if (d == 0)
789 {
790 lo = SIGNED64 (0x8000000000000000);
791 hi = 0;
792 }
793 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
794 {
795 lo = SIGNED64 (0x8000000000000000);
796 hi = 0;
797 }
798 else
799 {
800 lo = (n / d);
801 hi = (n % d);
802 }
803 HI = hi;
804 LO = lo;
805 }
806 TRACE_ALU_RESULT2 (HI, LO);
807}
808
f701dad2 809000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
c906108c
SS		 810"ddiv r<RS>, r<RT>"
811*mipsIII:
812*mipsIV:
813*vr4100:
814*vr5000:
815{
816 do_ddiv (SD_, RS, RT);
817}
818
819
820
821:function:::void:do_ddivu:int rs, int rt
822{
823 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
824 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
825 {
826 unsigned64 n = GPR[rs];
827 unsigned64 d = GPR[rt];
828 unsigned64 hi;
829 unsigned64 lo;
830 if (d == 0)
831 {
832 lo = SIGNED64 (0x8000000000000000);
833 hi = 0;
834 }
835 else
836 {
837 lo = (n / d);
838 hi = (n % d);
839 }
840 HI = hi;
841 LO = lo;
842 }
843 TRACE_ALU_RESULT2 (HI, LO);
844}
845
846000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
847"ddivu r<RS>, r<RT>"
848*mipsIII:
849*mipsIV:
850*vr4100:
851*vr5000:
852{
853 do_ddivu (SD_, RS, RT);
854}
855
856
857
858:function:::void:do_div:int rs, int rt
859{
860 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
861 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
862 {
863 signed32 n = GPR[rs];
864 signed32 d = GPR[rt];
865 if (d == 0)
866 {
867 LO = EXTEND32 (0x80000000);
868 HI = EXTEND32 (0);
869 }
870 else if (n == SIGNED32 (0x80000000) && d == -1)
871 {
872 LO = EXTEND32 (0x80000000);
873 HI = EXTEND32 (0);
874 }
875 else
876 {
877 LO = EXTEND32 (n / d);
878 HI = EXTEND32 (n % d);
879 }
880 }
881 TRACE_ALU_RESULT2 (HI, LO);
882}
883
f701dad2 884000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
c906108c
SS		 885"div r<RS>, r<RT>"
886*mipsI,mipsII,mipsIII,mipsIV:
887*vr4100:
888*vr5000:
889*r3900:
890{
891 do_div (SD_, RS, RT);
892}
893
894
895
896:function:::void:do_divu:int rs, int rt
897{
898 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
899 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
900 {
901 unsigned32 n = GPR[rs];
902 unsigned32 d = GPR[rt];
903 if (d == 0)
904 {
905 LO = EXTEND32 (0x80000000);
906 HI = EXTEND32 (0);
907 }
908 else
909 {
910 LO = EXTEND32 (n / d);
911 HI = EXTEND32 (n % d);
912 }
913 }
914 TRACE_ALU_RESULT2 (HI, LO);
915}
916
f701dad2 917000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
c906108c
SS		 918"divu r<RS>, r<RT>"
919*mipsI,mipsII,mipsIII,mipsIV:
920*vr4100:
921*vr5000:
922*r3900:
923{
924 do_divu (SD_, RS, RT);
925}
926
927
928
929:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
930{
931 unsigned64 lo;
932 unsigned64 hi;
933 unsigned64 m00;
934 unsigned64 m01;
935 unsigned64 m10;
936 unsigned64 m11;
937 unsigned64 mid;
938 int sign;
939 unsigned64 op1 = GPR[rs];
940 unsigned64 op2 = GPR[rt];
941 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
942 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
943 /* make signed multiply unsigned */
944 sign = 0;
945 if (signed_p)
946 {
947 if (op1 < 0)
948 {
949 op1 = - op1;
950 ++sign;
951 }
952 if (op2 < 0)
953 {
954 op2 = - op2;
955 ++sign;
956 }
957 }
67f5c7ef 958 /* multiply out the 4 sub products */
c906108c
SS		 959 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
960 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
961 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
962 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
963 /* add the products */
964 mid = ((unsigned64) VH4_8 (m00)
965 + (unsigned64) VL4_8 (m10)
966 + (unsigned64) VL4_8 (m01));
967 lo = U8_4 (mid, m00);
968 hi = (m11
969 + (unsigned64) VH4_8 (mid)
970 + (unsigned64) VH4_8 (m01)
971 + (unsigned64) VH4_8 (m10));
972 /* fix the sign */
973 if (sign & 1)
974 {
975 lo = -lo;
976 if (lo == 0)
977 hi = -hi;
978 else
979 hi = -hi - 1;
980 }
981 /* save the result HI/LO (and a gpr) */
982 LO = lo;
983 HI = hi;
984 if (rd != 0)
985 GPR[rd] = lo;
986 TRACE_ALU_RESULT2 (HI, LO);
987}
988
989:function:::void:do_dmult:int rs, int rt, int rd
990{
991 do_dmultx (SD_, rs, rt, rd, 1);
992}
993
f701dad2 994000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
c906108c
SS		 995"dmult r<RS>, r<RT>"
996*mipsIII,mipsIV:
997*vr4100:
998{
999 do_dmult (SD_, RS, RT, 0);
1000}
1001
f701dad2 1002000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
c906108c
SS		 1003"dmult r<RS>, r<RT>":RD == 0
1004"dmult r<RD>, r<RS>, r<RT>"
1005*vr5000:
1006{
1007 do_dmult (SD_, RS, RT, RD);
1008}
1009
1010
1011
1012:function:::void:do_dmultu:int rs, int rt, int rd
1013{
1014 do_dmultx (SD_, rs, rt, rd, 0);
1015}
1016
f701dad2 1017000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
c906108c
SS		 1018"dmultu r<RS>, r<RT>"
1019*mipsIII,mipsIV:
1020*vr4100:
1021{
1022 do_dmultu (SD_, RS, RT, 0);
1023}
1024
f701dad2 1025000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
c906108c
SS		 1026"dmultu r<RD>, r<RS>, r<RT>":RD == 0
1027"dmultu r<RS>, r<RT>"
1028*vr5000:
1029{
1030 do_dmultu (SD_, RS, RT, RD);
1031}
1032
1033:function:::void:do_dsll:int rt, int rd, int shift
1034{
1035 GPR[rd] = GPR[rt] << shift;
1036}
1037
1038:function:::void:do_dsllv:int rs, int rt, int rd
1039{
1040 int s = MASKED64 (GPR[rs], 5, 0);
1041 GPR[rd] = GPR[rt] << s;
1042}
1043
1044
f701dad2 1045000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
c906108c
SS		 1046"dsll r<RD>, r<RT>, <SHIFT>"
1047*mipsIII:
1048*mipsIV:
1049*vr4100:
1050*vr5000:
1051{
1052 do_dsll (SD_, RT, RD, SHIFT);
1053}
1054
1055
f701dad2 1056000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
c906108c
SS		 1057"dsll32 r<RD>, r<RT>, <SHIFT>"
1058*mipsIII:
1059*mipsIV:
1060*vr4100:
1061*vr5000:
1062{
1063 int s = 32 + SHIFT;
1064 GPR[RD] = GPR[RT] << s;
1065}
1066
f701dad2 1067000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
c906108c
SS		 1068"dsllv r<RD>, r<RT>, r<RS>"
1069*mipsIII:
1070*mipsIV:
1071*vr4100:
1072*vr5000:
1073{
1074 do_dsllv (SD_, RS, RT, RD);
1075}
1076
1077:function:::void:do_dsra:int rt, int rd, int shift
1078{
1079 GPR[rd] = ((signed64) GPR[rt]) >> shift;
1080}
1081
1082
f701dad2 1083000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
c906108c
SS		 1084"dsra r<RD>, r<RT>, <SHIFT>"
1085*mipsIII:
1086*mipsIV:
1087*vr4100:
1088*vr5000:
1089{
1090 do_dsra (SD_, RT, RD, SHIFT);
1091}
1092
1093
f701dad2 1094000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
c906108c
SS		 1095"dsra32 r<RT>, r<RD>, <SHIFT>"
1096*mipsIII:
1097*mipsIV:
1098*vr4100:
1099*vr5000:
1100{
1101 int s = 32 + SHIFT;
1102 GPR[RD] = ((signed64) GPR[RT]) >> s;
1103}
1104
1105
1106:function:::void:do_dsrav:int rs, int rt, int rd
1107{
1108 int s = MASKED64 (GPR[rs], 5, 0);
1109 TRACE_ALU_INPUT2 (GPR[rt], s);
1110 GPR[rd] = ((signed64) GPR[rt]) >> s;
1111 TRACE_ALU_RESULT (GPR[rd]);
1112}
1113
f701dad2 1114000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
20ae0098 1115"dsrav r<RT>, r<RD>, r<RS>"
c906108c
SS		 1116*mipsIII:
1117*mipsIV:
1118*vr4100:
1119*vr5000:
1120{
1121 do_dsrav (SD_, RS, RT, RD);
1122}
1123
1124:function:::void:do_dsrl:int rt, int rd, int shift
1125{
1126 GPR[rd] = (unsigned64) GPR[rt] >> shift;
1127}
1128
1129
f701dad2 1130000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
c906108c
SS		 1131"dsrl r<RD>, r<RT>, <SHIFT>"
1132*mipsIII:
1133*mipsIV:
1134*vr4100:
1135*vr5000:
1136{
1137 do_dsrl (SD_, RT, RD, SHIFT);
1138}
1139
1140
f701dad2 1141000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
c906108c
SS		 1142"dsrl32 r<RD>, r<RT>, <SHIFT>"
1143*mipsIII:
1144*mipsIV:
1145*vr4100:
1146*vr5000:
1147{
1148 int s = 32 + SHIFT;
1149 GPR[RD] = (unsigned64) GPR[RT] >> s;
1150}
1151
1152
1153:function:::void:do_dsrlv:int rs, int rt, int rd
1154{
1155 int s = MASKED64 (GPR[rs], 5, 0);
1156 GPR[rd] = (unsigned64) GPR[rt] >> s;
1157}
1158
1159
1160
f701dad2 1161000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
20ae0098 1162"dsrlv r<RD>, r<RT>, r<RS>"
c906108c
SS		 1163*mipsIII:
1164*mipsIV:
1165*vr4100:
1166*vr5000:
1167{
1168 do_dsrlv (SD_, RS, RT, RD);
1169}
1170
1171
f701dad2 1172000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
c906108c
SS		 1173"dsub r<RD>, r<RS>, r<RT>"
1174*mipsIII:
1175*mipsIV:
1176*vr4100:
1177*vr5000:
1178{
1179 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1180 {
1181 ALU64_BEGIN (GPR[RS]);
1182 ALU64_SUB (GPR[RT]);
9805e229 1183 ALU64_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 1184 }
1185 TRACE_ALU_RESULT (GPR[RD]);
1186}
1187
1188
1189:function:::void:do_dsubu:int rs, int rt, int rd
1190{
1191 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1192 GPR[rd] = GPR[rs] - GPR[rt];
1193 TRACE_ALU_RESULT (GPR[rd]);
1194}
1195
f701dad2 1196000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
c906108c
SS		 1197"dsubu r<RD>, r<RS>, r<RT>"
1198*mipsIII:
1199*mipsIV:
1200*vr4100:
1201*vr5000:
1202{
1203 do_dsubu (SD_, RS, RT, RD);
1204}
1205
1206
1207000010,26.INSTR_INDEX:NORMAL:32::J
1208"j <INSTR_INDEX>"
1209*mipsI,mipsII,mipsIII,mipsIV:
1210*vr4100:
1211*vr5000:
1212*r3900:
1213{
1214 /* NOTE: The region used is that of the delay slot NIA and NOT the
1215 current instruction */
1216 address_word region = (NIA & MASK (63, 28));
1217 DELAY_SLOT (region | (INSTR_INDEX << 2));
1218}
1219
1220
1221000011,26.INSTR_INDEX:NORMAL:32::JAL
1222"jal <INSTR_INDEX>"
1223*mipsI,mipsII,mipsIII,mipsIV:
1224*vr4100:
1225*vr5000:
1226*r3900:
1227{
1228 /* NOTE: The region used is that of the delay slot and NOT the
1229 current instruction */
1230 address_word region = (NIA & MASK (63, 28));
1231 GPR[31] = CIA + 8;
1232 DELAY_SLOT (region | (INSTR_INDEX << 2));
1233}
1234
f701dad2 1235000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
c906108c
SS		 1236"jalr r<RS>":RD == 31
1237"jalr r<RD>, r<RS>"
1238*mipsI,mipsII,mipsIII,mipsIV:
1239*vr4100:
1240*vr5000:
1241*r3900:
1242{
1243 address_word temp = GPR[RS];
1244 GPR[RD] = CIA + 8;
1245 DELAY_SLOT (temp);
1246}
1247
1248
f701dad2 1249000000,5.RS,000000000000000,001000:SPECIAL:32::JR
c906108c
SS		 1250"jr r<RS>"
1251*mipsI,mipsII,mipsIII,mipsIV:
1252*vr4100:
1253*vr5000:
1254*r3900:
1255{
1256 DELAY_SLOT (GPR[RS]);
1257}
1258
1259
1260:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1261{
1262 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1263 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1264 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1265 unsigned int byte;
1266 address_word paddr;
1267 int uncached;
1268 unsigned64 memval;
1269 address_word vaddr;
1270
1271 vaddr = base + offset;
1272 if ((vaddr & access) != 0)
1273 {
1274 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1275 }
1276 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1277 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1278 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1279 byte = ((vaddr & mask) ^ bigendiancpu);
1280 return (memval >> (8 * byte));
1281}
1282
1283
1284100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1285"lb r<RT>, <OFFSET>(r<BASE>)"
1286*mipsI,mipsII,mipsIII,mipsIV:
1287*vr4100:
1288*vr5000:
1289*r3900:
1290{
1291 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1292}
1293
1294
1295100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1296"lbu r<RT>, <OFFSET>(r<BASE>)"
1297*mipsI,mipsII,mipsIII,mipsIV:
1298*vr4100:
1299*vr5000:
1300*r3900:
1301{
1302 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1303}
1304
1305
1306110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1307"ld r<RT>, <OFFSET>(r<BASE>)"
1308*mipsIII:
1309*mipsIV:
1310*vr4100:
1311*vr5000:
1312{
1313 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1314}
1315
1316
13171101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1318"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1319*mipsII:
1320*mipsIII:
1321*mipsIV:
1322*vr4100:
1323*vr5000:
1324*r3900:
1325{
1326 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1327}
1328
1329
1330
1331
1332011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1333"ldl r<RT>, <OFFSET>(r<BASE>)"
1334*mipsIII:
1335*mipsIV:
1336*vr4100:
1337*vr5000:
1338{
1339 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1340}
1341
1342
1343011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1344"ldr r<RT>, <OFFSET>(r<BASE>)"
1345*mipsIII:
1346*mipsIV:
1347*vr4100:
1348*vr5000:
1349{
1350 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1351}
1352
1353
1354100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1355"lh r<RT>, <OFFSET>(r<BASE>)"
1356*mipsI,mipsII,mipsIII,mipsIV:
1357*vr4100:
1358*vr5000:
1359*r3900:
1360{
1361 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1362}
1363
1364
1365100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1366"lhu r<RT>, <OFFSET>(r<BASE>)"
1367*mipsI,mipsII,mipsIII,mipsIV:
1368*vr4100:
1369*vr5000:
1370*r3900:
1371{
1372 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1373}
1374
1375
1376110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1377"ll r<RT>, <OFFSET>(r<BASE>)"
1378*mipsII:
1379*mipsIII:
1380*mipsIV:
1381*vr4100:
1382*vr5000:
1383{
1384 unsigned32 instruction = instruction_0;
1385 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1386 int destreg = ((instruction >> 16) & 0x0000001F);
1387 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1388 {
1389 address_word vaddr = ((unsigned64)op1 + offset);
1390 address_word paddr;
1391 int uncached;
1392 if ((vaddr & 3) != 0)
1393 {
1394 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
1395 }
1396 else
1397 {
1398 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1399 {
1400 unsigned64 memval = 0;
1401 unsigned64 memval1 = 0;
1402 unsigned64 mask = 0x7;
1403 unsigned int shift = 2;
1404 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1405 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1406 unsigned int byte;
1407 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1408 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1409 byte = ((vaddr & mask) ^ (bigend << shift));
1410 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1411 LLBIT = 1;
1412 }
1413 }
1414 }
1415}
1416
1417
1418110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1419"lld r<RT>, <OFFSET>(r<BASE>)"
1420*mipsIII:
1421*mipsIV:
1422*vr4100:
1423*vr5000:
1424{
1425 unsigned32 instruction = instruction_0;
1426 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1427 int destreg = ((instruction >> 16) & 0x0000001F);
1428 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1429 {
1430 address_word vaddr = ((unsigned64)op1 + offset);
1431 address_word paddr;
1432 int uncached;
1433 if ((vaddr & 7) != 0)
1434 {
1435 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
1436 }
1437 else
1438 {
1439 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1440 {
1441 unsigned64 memval = 0;
1442 unsigned64 memval1 = 0;
1443 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1444 GPR[destreg] = memval;
1445 LLBIT = 1;
1446 }
1447 }
1448 }
1449}
1450
1451
1452001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1453"lui r<RT>, <IMMEDIATE>"
1454*mipsI,mipsII,mipsIII,mipsIV:
1455*vr4100:
1456*vr5000:
1457*r3900:
1458{
1459 TRACE_ALU_INPUT1 (IMMEDIATE);
1460 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1461 TRACE_ALU_RESULT (GPR[RT]);
1462}
1463
1464
1465100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1466"lw r<RT>, <OFFSET>(r<BASE>)"
1467*mipsI,mipsII,mipsIII,mipsIV:
1468*vr4100:
1469*vr5000:
1470*r3900:
1471{
1472 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1473}
1474
1475
14761100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1477"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1478*mipsI,mipsII,mipsIII,mipsIV:
1479*vr4100:
1480*vr5000:
1481*r3900:
1482{
1483 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1484}
1485
1486
1487:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1488{
1489 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1490 address_word reverseendian = (ReverseEndian ? -1 : 0);
1491 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1492 unsigned int byte;
1493 unsigned int word;
1494 address_word paddr;
1495 int uncached;
1496 unsigned64 memval;
1497 address_word vaddr;
1498 int nr_lhs_bits;
1499 int nr_rhs_bits;
1500 unsigned_word lhs_mask;
1501 unsigned_word temp;
1502
1503 vaddr = base + offset;
1504 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1505 paddr = (paddr ^ (reverseendian & mask));
1506 if (BigEndianMem == 0)
1507 paddr = paddr & ~access;
1508
1509 /* compute where within the word/mem we are */
1510 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1511 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1512 nr_lhs_bits = 8 * byte + 8;
1513 nr_rhs_bits = 8 * access - 8 * byte;
1514 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1515
1516 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1517 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1518 (long) ((unsigned64) paddr >> 32), (long) paddr,
1519 word, byte, nr_lhs_bits, nr_rhs_bits); */
1520
1521 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1522 if (word == 0)
1523 {
1524 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1525 temp = (memval << nr_rhs_bits);
1526 }
1527 else
1528 {
1529 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1530 temp = (memval >> nr_lhs_bits);
1531 }
1532 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1533 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1534
1535 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1536 (long) ((unsigned64) memval >> 32), (long) memval,
1537 (long) ((unsigned64) temp >> 32), (long) temp,
1538 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1539 (long) (rt >> 32), (long) rt); */
1540 return rt;
1541}
1542
1543
1544100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1545"lwl r<RT>, <OFFSET>(r<BASE>)"
1546*mipsI,mipsII,mipsIII,mipsIV:
1547*vr4100:
1548*vr5000:
1549*r3900:
1550{
7a292a7a 1551 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
c906108c
SS		 1552}
1553
1554
1555:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1556{
1557 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1558 address_word reverseendian = (ReverseEndian ? -1 : 0);
1559 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1560 unsigned int byte;
1561 address_word paddr;
1562 int uncached;
1563 unsigned64 memval;
1564 address_word vaddr;
1565
1566 vaddr = base + offset;
1567 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1568 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1569 paddr = (paddr ^ (reverseendian & mask));
1570 if (BigEndianMem != 0)
1571 paddr = paddr & ~access;
1572 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1573 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
1574 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1575 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1576 (long) paddr, byte, (long) paddr, (long) memval); */
1577 {
1578 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1579 rt &= ~screen;
1580 rt |= (memval >> (8 * byte)) & screen;
1581 }
1582 return rt;
1583}
1584
1585
1586100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1587"lwr r<RT>, <OFFSET>(r<BASE>)"
1588*mipsI,mipsII,mipsIII,mipsIV:
1589*vr4100:
1590*vr5000:
1591*r3900:
1592{
1593 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1594}
1595
1596
1597100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1598"lwu r<RT>, <OFFSET>(r<BASE>)"
1599*mipsIII:
1600*mipsIV:
1601*vr4100:
1602*vr5000:
1603{
1604 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
1605}
1606
1607
1608:function:::void:do_mfhi:int rd
1609{
1610 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
1611 TRACE_ALU_INPUT1 (HI);
1612 GPR[rd] = HI;
1613 TRACE_ALU_RESULT (GPR[rd]);
1614}
1615
1616000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1617"mfhi r<RD>"
1618*mipsI,mipsII,mipsIII,mipsIV:
1619*vr4100:
1620*vr5000:
1621*r3900:
1622{
1623 do_mfhi (SD_, RD);
1624}
1625
1626
1627
1628:function:::void:do_mflo:int rd
1629{
1630 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
1631 TRACE_ALU_INPUT1 (LO);
1632 GPR[rd] = LO;
1633 TRACE_ALU_RESULT (GPR[rd]);
1634}
1635
1636000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1637"mflo r<RD>"
1638*mipsI,mipsII,mipsIII,mipsIV:
1639*vr4100:
1640*vr5000:
1641*r3900:
1642{
1643 do_mflo (SD_, RD);
1644}
1645
1646
1647
f701dad2 1648000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
c906108c
SS		 1649"movn r<RD>, r<RS>, r<RT>"
1650*mipsIV:
1651*vr5000:
1652{
1653 if (GPR[RT] != 0)
1654 GPR[RD] = GPR[RS];
1655}
1656
1657
1658
f701dad2 1659000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
c906108c
SS		 1660"movz r<RD>, r<RS>, r<RT>"
1661*mipsIV:
1662*vr5000:
1663{
1664 if (GPR[RT] == 0)
1665 GPR[RD] = GPR[RS];
1666}
1667
1668
1669
1670000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1671"mthi r<RS>"
1672*mipsI,mipsII,mipsIII,mipsIV:
1673*vr4100:
1674*vr5000:
1675*r3900:
1676{
1677 check_mt_hilo (SD_, HIHISTORY);
1678 HI = GPR[RS];
1679}
1680
1681
1682
f701dad2 1683000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
c906108c
SS		 1684"mtlo r<RS>"
1685*mipsI,mipsII,mipsIII,mipsIV:
1686*vr4100:
1687*vr5000:
1688*r3900:
1689{
1690 check_mt_hilo (SD_, LOHISTORY);
1691 LO = GPR[RS];
1692}
1693
1694
1695
1696:function:::void:do_mult:int rs, int rt, int rd
1697{
1698 signed64 prod;
1699 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1700 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1701 prod = (((signed64)(signed32) GPR[rs])
1702 * ((signed64)(signed32) GPR[rt]));
1703 LO = EXTEND32 (VL4_8 (prod));
1704 HI = EXTEND32 (VH4_8 (prod));
1705 if (rd != 0)
1706 GPR[rd] = LO;
1707 TRACE_ALU_RESULT2 (HI, LO);
1708}
1709
f701dad2 1710000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
c906108c
SS		 1711"mult r<RS>, r<RT>"
1712*mipsI,mipsII,mipsIII,mipsIV:
1713*vr4100:
1714{
1715 do_mult (SD_, RS, RT, 0);
1716}
1717
1718
f701dad2 1719000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
9846de1b 1720"mult r<RS>, r<RT>":RD == 0
c906108c
SS		 1721"mult r<RD>, r<RS>, r<RT>"
1722*vr5000:
1723*r3900:
1724{
1725 do_mult (SD_, RS, RT, RD);
1726}
1727
1728
1729:function:::void:do_multu:int rs, int rt, int rd
1730{
1731 unsigned64 prod;
1732 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1733 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1734 prod = (((unsigned64)(unsigned32) GPR[rs])
1735 * ((unsigned64)(unsigned32) GPR[rt]));
1736 LO = EXTEND32 (VL4_8 (prod));
1737 HI = EXTEND32 (VH4_8 (prod));
1738 if (rd != 0)
1739 GPR[rd] = LO;
1740 TRACE_ALU_RESULT2 (HI, LO);
1741}
1742
f701dad2 1743000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
c906108c
SS		 1744"multu r<RS>, r<RT>"
1745*mipsI,mipsII,mipsIII,mipsIV:
1746*vr4100:
1747{
cff3e48b 1748 do_multu (SD_, RS, RT, 0);
c906108c
SS		 1749}
1750
f701dad2 1751000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
9846de1b 1752"multu r<RS>, r<RT>":RD == 0
c906108c
SS		 1753"multu r<RD>, r<RS>, r<RT>"
1754*vr5000:
1755*r3900:
1756{
cff3e48b 1757 do_multu (SD_, RS, RT, RD);
c906108c
SS		 1758}
1759
1760
1761:function:::void:do_nor:int rs, int rt, int rd
1762{
1763 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1764 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
1765 TRACE_ALU_RESULT (GPR[rd]);
1766}
1767
1768000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
1769"nor r<RD>, r<RS>, r<RT>"
1770*mipsI,mipsII,mipsIII,mipsIV:
1771*vr4100:
1772*vr5000:
1773*r3900:
1774{
1775 do_nor (SD_, RS, RT, RD);
1776}
1777
1778
1779:function:::void:do_or:int rs, int rt, int rd
1780{
1781 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1782 GPR[rd] = (GPR[rs] | GPR[rt]);
1783 TRACE_ALU_RESULT (GPR[rd]);
1784}
1785
1786000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
1787"or r<RD>, r<RS>, r<RT>"
1788*mipsI,mipsII,mipsIII,mipsIV:
1789*vr4100:
1790*vr5000:
1791*r3900:
1792{
1793 do_or (SD_, RS, RT, RD);
1794}
1795
1796
1797
1798:function:::void:do_ori:int rs, int rt, unsigned immediate
1799{
1800 TRACE_ALU_INPUT2 (GPR[rs], immediate);
1801 GPR[rt] = (GPR[rs] | immediate);
1802 TRACE_ALU_RESULT (GPR[rt]);
1803}
1804
1805001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
1806"ori r<RT>, r<RS>, <IMMEDIATE>"
1807*mipsI,mipsII,mipsIII,mipsIV:
1808*vr4100:
1809*vr5000:
1810*r3900:
1811{
1812 do_ori (SD_, RS, RT, IMMEDIATE);
1813}
1814
1815
1816110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
1817*mipsIV:
1818*vr5000:
1819{
1820 unsigned32 instruction = instruction_0;
1821 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1822 int hint = ((instruction >> 16) & 0x0000001F);
1823 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1824 {
1825 address_word vaddr = ((unsigned64)op1 + offset);
1826 address_word paddr;
1827 int uncached;
1828 {
1829 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1830 Prefetch(uncached,paddr,vaddr,isDATA,hint);
1831 }
1832 }
1833}
1834
1835:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
1836{
1837 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1838 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1839 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1840 unsigned int byte;
1841 address_word paddr;
1842 int uncached;
1843 unsigned64 memval;
1844 address_word vaddr;
1845
1846 vaddr = base + offset;
1847 if ((vaddr & access) != 0)
1848 {
1849 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
1850 }
1851 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
1852 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1853 byte = ((vaddr & mask) ^ bigendiancpu);
1854 memval = (word << (8 * byte));
1855 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
1856}
1857
1858
1859101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
1860"sb r<RT>, <OFFSET>(r<BASE>)"
1861*mipsI,mipsII,mipsIII,mipsIV:
1862*vr4100:
1863*vr5000:
1864*r3900:
1865{
1866 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1867}
1868
1869
1870111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
1871"sc r<RT>, <OFFSET>(r<BASE>)"
1872*mipsII:
1873*mipsIII:
1874*mipsIV:
1875*vr4100:
1876*vr5000:
1877{
1878 unsigned32 instruction = instruction_0;
1879 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1880 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
1881 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1882 {
1883 address_word vaddr = ((unsigned64)op1 + offset);
1884 address_word paddr;
1885 int uncached;
1886 if ((vaddr & 3) != 0)
1887 {
1888 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
1889 }
1890 else
1891 {
1892 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
1893 {
1894 unsigned64 memval = 0;
1895 unsigned64 memval1 = 0;
1896 unsigned64 mask = 0x7;
1897 unsigned int byte;
1898 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
1899 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
1900 memval = ((unsigned64) op2 << (8 * byte));
1901 if (LLBIT)
1902 {
1903 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
1904 }
1905 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
1906 }
1907 }
1908 }
1909}
1910
1911
1912111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
1913"scd r<RT>, <OFFSET>(r<BASE>)"
1914*mipsIII:
1915*mipsIV:
1916*vr4100:
1917*vr5000:
1918{
1919 unsigned32 instruction = instruction_0;
1920 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1921 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
1922 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1923 {
1924 address_word vaddr = ((unsigned64)op1 + offset);
1925 address_word paddr;
1926 int uncached;
1927 if ((vaddr & 7) != 0)
1928 {
1929 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
1930 }
1931 else
1932 {
1933 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
1934 {
1935 unsigned64 memval = 0;
1936 unsigned64 memval1 = 0;
1937 memval = op2;
1938 if (LLBIT)
1939 {
1940 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
1941 }
1942 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
1943 }
1944 }
1945 }
1946}
1947
1948
1949111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
1950"sd r<RT>, <OFFSET>(r<BASE>)"
1951*mipsIII:
1952*mipsIV:
1953*vr4100:
1954*vr5000:
1955{
1956 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1957}
1958
1959
19601111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
1961"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1962*mipsII:
1963*mipsIII:
1964*mipsIV:
1965*vr4100:
1966*vr5000:
1967{
1968 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
1969}
1970
1971
1972101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
1973"sdl r<RT>, <OFFSET>(r<BASE>)"
1974*mipsIII:
1975*mipsIV:
1976*vr4100:
1977*vr5000:
1978{
1979 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1980}
1981
1982
1983101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
1984"sdr r<RT>, <OFFSET>(r<BASE>)"
1985*mipsIII:
1986*mipsIV:
1987*vr4100:
1988*vr5000:
1989{
1990 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1991}
1992
1993
1994101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
1995"sh r<RT>, <OFFSET>(r<BASE>)"
1996*mipsI,mipsII,mipsIII,mipsIV:
1997*vr4100:
1998*vr5000:
1999*r3900:
2000{
2001 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2002}
2003
2004
2005:function:::void:do_sll:int rt, int rd, int shift
2006{
2007 unsigned32 temp = (GPR[rt] << shift);
2008 TRACE_ALU_INPUT2 (GPR[rt], shift);
2009 GPR[rd] = EXTEND32 (temp);
2010 TRACE_ALU_RESULT (GPR[rd]);
2011}
2012
f701dad2 2013000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
20ae0098 2014"nop":RD == 0 && RT == 0 && SHIFT == 0
c906108c
SS		 2015"sll r<RD>, r<RT>, <SHIFT>"
2016*mipsI,mipsII,mipsIII,mipsIV:
2017*vr4100:
2018*vr5000:
2019*r3900:
2020{
20ae0098
CD		 2021 /* Skip shift for NOP, so that there won't be lots of extraneous
2022 trace output. */
2023 if (RD != 0 || RT != 0 || SHIFT != 0)
2024 do_sll (SD_, RT, RD, SHIFT);
c906108c
SS		 2025}
2026
2027
2028:function:::void:do_sllv:int rs, int rt, int rd
2029{
2030 int s = MASKED (GPR[rs], 4, 0);
2031 unsigned32 temp = (GPR[rt] << s);
2032 TRACE_ALU_INPUT2 (GPR[rt], s);
2033 GPR[rd] = EXTEND32 (temp);
2034 TRACE_ALU_RESULT (GPR[rd]);
2035}
2036
f701dad2 2037000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
c906108c
SS		 2038"sllv r<RD>, r<RT>, r<RS>"
2039*mipsI,mipsII,mipsIII,mipsIV:
2040*vr4100:
2041*vr5000:
2042*r3900:
2043{
2044 do_sllv (SD_, RS, RT, RD);
2045}
2046
2047
2048:function:::void:do_slt:int rs, int rt, int rd
2049{
2050 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2051 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2052 TRACE_ALU_RESULT (GPR[rd]);
2053}
2054
f701dad2 2055000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
c906108c
SS		 2056"slt r<RD>, r<RS>, r<RT>"
2057*mipsI,mipsII,mipsIII,mipsIV:
2058*vr4100:
2059*vr5000:
2060*r3900:
2061{
2062 do_slt (SD_, RS, RT, RD);
2063}
2064
2065
2066:function:::void:do_slti:int rs, int rt, unsigned16 immediate
2067{
2068 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2069 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2070 TRACE_ALU_RESULT (GPR[rt]);
2071}
2072
2073001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2074"slti r<RT>, r<RS>, <IMMEDIATE>"
2075*mipsI,mipsII,mipsIII,mipsIV:
2076*vr4100:
2077*vr5000:
2078*r3900:
2079{
2080 do_slti (SD_, RS, RT, IMMEDIATE);
2081}
2082
2083
2084:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2085{
2086 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2087 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2088 TRACE_ALU_RESULT (GPR[rt]);
2089}
2090
2091001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2092"sltiu r<RT>, r<RS>, <IMMEDIATE>"
2093*mipsI,mipsII,mipsIII,mipsIV:
2094*vr4100:
2095*vr5000:
2096*r3900:
2097{
2098 do_sltiu (SD_, RS, RT, IMMEDIATE);
2099}
2100
2101
2102
2103:function:::void:do_sltu:int rs, int rt, int rd
2104{
2105 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2106 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2107 TRACE_ALU_RESULT (GPR[rd]);
2108}
2109
f701dad2 2110000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
c906108c
SS		 2111"sltu r<RD>, r<RS>, r<RT>"
2112*mipsI,mipsII,mipsIII,mipsIV:
2113*vr4100:
2114*vr5000:
2115*r3900:
2116{
2117 do_sltu (SD_, RS, RT, RD);
2118}
2119
2120
2121:function:::void:do_sra:int rt, int rd, int shift
2122{
2123 signed32 temp = (signed32) GPR[rt] >> shift;
2124 TRACE_ALU_INPUT2 (GPR[rt], shift);
2125 GPR[rd] = EXTEND32 (temp);
2126 TRACE_ALU_RESULT (GPR[rd]);
2127}
2128
2129000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2130"sra r<RD>, r<RT>, <SHIFT>"
2131*mipsI,mipsII,mipsIII,mipsIV:
2132*vr4100:
2133*vr5000:
2134*r3900:
2135{
2136 do_sra (SD_, RT, RD, SHIFT);
2137}
2138
2139
2140
2141:function:::void:do_srav:int rs, int rt, int rd
2142{
2143 int s = MASKED (GPR[rs], 4, 0);
2144 signed32 temp = (signed32) GPR[rt] >> s;
2145 TRACE_ALU_INPUT2 (GPR[rt], s);
2146 GPR[rd] = EXTEND32 (temp);
2147 TRACE_ALU_RESULT (GPR[rd]);
2148}
2149
f701dad2 2150000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
c906108c
SS		 2151"srav r<RD>, r<RT>, r<RS>"
2152*mipsI,mipsII,mipsIII,mipsIV:
2153*vr4100:
2154*vr5000:
2155*r3900:
2156{
2157 do_srav (SD_, RS, RT, RD);
2158}
2159
2160
2161
2162:function:::void:do_srl:int rt, int rd, int shift
2163{
2164 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2165 TRACE_ALU_INPUT2 (GPR[rt], shift);
2166 GPR[rd] = EXTEND32 (temp);
2167 TRACE_ALU_RESULT (GPR[rd]);
2168}
2169
2170000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2171"srl r<RD>, r<RT>, <SHIFT>"
2172*mipsI,mipsII,mipsIII,mipsIV:
2173*vr4100:
2174*vr5000:
2175*r3900:
2176{
2177 do_srl (SD_, RT, RD, SHIFT);
2178}
2179
2180
2181:function:::void:do_srlv:int rs, int rt, int rd
2182{
2183 int s = MASKED (GPR[rs], 4, 0);
2184 unsigned32 temp = (unsigned32) GPR[rt] >> s;
2185 TRACE_ALU_INPUT2 (GPR[rt], s);
2186 GPR[rd] = EXTEND32 (temp);
2187 TRACE_ALU_RESULT (GPR[rd]);
2188}
2189
f701dad2 2190000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
c906108c
SS		 2191"srlv r<RD>, r<RT>, r<RS>"
2192*mipsI,mipsII,mipsIII,mipsIV:
2193*vr4100:
2194*vr5000:
2195*r3900:
2196{
2197 do_srlv (SD_, RS, RT, RD);
2198}
2199
2200
f701dad2 2201000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
c906108c
SS		 2202"sub r<RD>, r<RS>, r<RT>"
2203*mipsI,mipsII,mipsIII,mipsIV:
2204*vr4100:
2205*vr5000:
2206*r3900:
2207{
2208 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2209 {
2210 ALU32_BEGIN (GPR[RS]);
2211 ALU32_SUB (GPR[RT]);
9805e229 2212 ALU32_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 2213 }
2214 TRACE_ALU_RESULT (GPR[RD]);
2215}
2216
2217
2218:function:::void:do_subu:int rs, int rt, int rd
2219{
2220 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2221 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2222 TRACE_ALU_RESULT (GPR[rd]);
2223}
2224
f701dad2 2225000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
c906108c
SS		 2226"subu r<RD>, r<RS>, r<RT>"
2227*mipsI,mipsII,mipsIII,mipsIV:
2228*vr4100:
2229*vr5000:
2230*r3900:
2231{
2232 do_subu (SD_, RS, RT, RD);
2233}
2234
2235
2236101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2237"sw r<RT>, <OFFSET>(r<BASE>)"
2238*mipsI,mipsII,mipsIII,mipsIV:
2239*vr4100:
2240*r3900:
2241*vr5000:
2242{
2243 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2244}
2245
2246
22471110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2248"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2249*mipsI,mipsII,mipsIII,mipsIV:
2250*vr4100:
2251*vr5000:
2252*r3900:
2253{
2254 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
2255}
2256
2257
2258
2259:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2260{
2261 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2262 address_word reverseendian = (ReverseEndian ? -1 : 0);
2263 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2264 unsigned int byte;
2265 unsigned int word;
2266 address_word paddr;
2267 int uncached;
2268 unsigned64 memval;
2269 address_word vaddr;
2270 int nr_lhs_bits;
2271 int nr_rhs_bits;
2272
2273 vaddr = base + offset;
2274 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2275 paddr = (paddr ^ (reverseendian & mask));
2276 if (BigEndianMem == 0)
2277 paddr = paddr & ~access;
2278
2279 /* compute where within the word/mem we are */
2280 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2281 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2282 nr_lhs_bits = 8 * byte + 8;
2283 nr_rhs_bits = 8 * access - 8 * byte;
2284 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2285 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2286 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2287 (long) ((unsigned64) paddr >> 32), (long) paddr,
2288 word, byte, nr_lhs_bits, nr_rhs_bits); */
2289
2290 if (word == 0)
2291 {
2292 memval = (rt >> nr_rhs_bits);
2293 }
2294 else
2295 {
2296 memval = (rt << nr_lhs_bits);
2297 }
2298 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2299 (long) ((unsigned64) rt >> 32), (long) rt,
2300 (long) ((unsigned64) memval >> 32), (long) memval); */
2301 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2302}
2303
2304
2305101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2306"swl r<RT>, <OFFSET>(r<BASE>)"
2307*mipsI,mipsII,mipsIII,mipsIV:
2308*vr4100:
2309*vr5000:
2310*r3900:
2311{
2312 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2313}
2314
2315
2316:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2317{
2318 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2319 address_word reverseendian = (ReverseEndian ? -1 : 0);
2320 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2321 unsigned int byte;
2322 address_word paddr;
2323 int uncached;
2324 unsigned64 memval;
2325 address_word vaddr;
2326
2327 vaddr = base + offset;
2328 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2329 paddr = (paddr ^ (reverseendian & mask));
2330 if (BigEndianMem != 0)
2331 paddr &= ~access;
2332 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2333 memval = (rt << (byte * 8));
2334 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2335}
2336
2337101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2338"swr r<RT>, <OFFSET>(r<BASE>)"
2339*mipsI,mipsII,mipsIII,mipsIV:
2340*vr4100:
2341*vr5000:
2342*r3900:
2343{
2344 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2345}
2346
2347
f701dad2 2348000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
c906108c
SS		 2349"sync":STYPE == 0
2350"sync <STYPE>"
2351*mipsII:
2352*mipsIII:
2353*mipsIV:
2354*vr4100:
2355*vr5000:
2356*r3900:
2357{
2358 SyncOperation (STYPE);
2359}
2360
2361
2362000000,20.CODE,001100:SPECIAL:32::SYSCALL
2363"syscall <CODE>"
2364*mipsI,mipsII,mipsIII,mipsIV:
2365*vr4100:
2366*vr5000:
2367*r3900:
2368{
2369 SignalException(SystemCall, instruction_0);
2370}
2371
2372
2373000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2374"teq r<RS>, r<RT>"
2375*mipsII:
2376*mipsIII:
2377*mipsIV:
2378*vr4100:
2379*vr5000:
2380{
2381 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
2382 SignalException(Trap, instruction_0);
2383}
2384
2385
2386000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2387"teqi r<RS>, <IMMEDIATE>"
2388*mipsII:
2389*mipsIII:
2390*mipsIV:
2391*vr4100:
2392*vr5000:
2393{
2394 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
2395 SignalException(Trap, instruction_0);
2396}
2397
2398
2399000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2400"tge r<RS>, r<RT>"
2401*mipsII:
2402*mipsIII:
2403*mipsIV:
2404*vr4100:
2405*vr5000:
2406{
2407 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
2408 SignalException(Trap, instruction_0);
2409}
2410
2411
2412000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2413"tgei r<RS>, <IMMEDIATE>"
2414*mipsII:
2415*mipsIII:
2416*mipsIV:
2417*vr4100:
2418*vr5000:
2419{
2420 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
2421 SignalException(Trap, instruction_0);
2422}
2423
2424
2425000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2426"tgeiu r<RS>, <IMMEDIATE>"
2427*mipsII:
2428*mipsIII:
2429*mipsIV:
2430*vr4100:
2431*vr5000:
2432{
2433 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2434 SignalException(Trap, instruction_0);
2435}
2436
2437
2438000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2439"tgeu r<RS>, r<RT>"
2440*mipsII:
2441*mipsIII:
2442*mipsIV:
2443*vr4100:
2444*vr5000:
2445{
2446 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2447 SignalException(Trap, instruction_0);
2448}
2449
2450
2451000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2452"tlt r<RS>, r<RT>"
2453*mipsII:
2454*mipsIII:
2455*mipsIV:
2456*vr4100:
2457*vr5000:
2458{
2459 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
2460 SignalException(Trap, instruction_0);
2461}
2462
2463
2464000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2465"tlti r<RS>, <IMMEDIATE>"
2466*mipsII:
2467*mipsIII:
2468*mipsIV:
2469*vr4100:
2470*vr5000:
2471{
2472 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
2473 SignalException(Trap, instruction_0);
2474}
2475
2476
2477000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2478"tltiu r<RS>, <IMMEDIATE>"
2479*mipsII:
2480*mipsIII:
2481*mipsIV:
2482*vr4100:
2483*vr5000:
2484{
2485 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2486 SignalException(Trap, instruction_0);
2487}
2488
2489
2490000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2491"tltu r<RS>, r<RT>"
2492*mipsII:
2493*mipsIII:
2494*mipsIV:
2495*vr4100:
2496*vr5000:
2497{
2498 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2499 SignalException(Trap, instruction_0);
2500}
2501
2502
2503000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2504"tne r<RS>, r<RT>"
2505*mipsII:
2506*mipsIII:
2507*mipsIV:
2508*vr4100:
2509*vr5000:
2510{
2511 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2512 SignalException(Trap, instruction_0);
2513}
2514
2515
2516000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
2517"tne r<RS>, <IMMEDIATE>"
2518*mipsII:
2519*mipsIII:
2520*mipsIV:
2521*vr4100:
2522*vr5000:
2523{
2524 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
2525 SignalException(Trap, instruction_0);
2526}
2527
2528
2529:function:::void:do_xor:int rs, int rt, int rd
2530{
2531 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2532 GPR[rd] = GPR[rs] ^ GPR[rt];
2533 TRACE_ALU_RESULT (GPR[rd]);
2534}
2535
f701dad2 2536000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
c906108c
SS		 2537"xor r<RD>, r<RS>, r<RT>"
2538*mipsI,mipsII,mipsIII,mipsIV:
2539*vr4100:
2540*vr5000:
2541*r3900:
2542{
2543 do_xor (SD_, RS, RT, RD);
2544}
2545
2546
2547:function:::void:do_xori:int rs, int rt, unsigned16 immediate
2548{
2549 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2550 GPR[rt] = GPR[rs] ^ immediate;
2551 TRACE_ALU_RESULT (GPR[rt]);
2552}
2553
2554001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
2555"xori r<RT>, r<RS>, <IMMEDIATE>"
2556*mipsI,mipsII,mipsIII,mipsIV:
2557*vr4100:
2558*vr5000:
2559*r3900:
2560{
2561 do_xori (SD_, RS, RT, IMMEDIATE);
2562}
2563
2564\f
2565//
2566// MIPS Architecture:
2567//
2568// FPU Instruction Set (COP1 & COP1X)
2569//
2570
2571
2572:%s::::FMT:int fmt
2573{
2574 switch (fmt)
2575 {
2576 case fmt_single: return "s";
2577 case fmt_double: return "d";
2578 case fmt_word: return "w";
2579 case fmt_long: return "l";
2580 default: return "?";
2581 }
2582}
2583
2584:%s::::X:int x
2585{
2586 switch (x)
2587 {
2588 case 0: return "f";
2589 case 1: return "t";
2590 default: return "?";
2591 }
2592}
2593
2594:%s::::TF:int tf
2595{
2596 if (tf)
2597 return "t";
2598 else
2599 return "f";
2600}
2601
2602:%s::::ND:int nd
2603{
2604 if (nd)
2605 return "l";
2606 else
2607 return "";
2608}
2609
2610:%s::::COND:int cond
2611{
2612 switch (cond)
2613 {
2614 case 00: return "f";
2615 case 01: return "un";
2616 case 02: return "eq";
2617 case 03: return "ueq";
2618 case 04: return "olt";
2619 case 05: return "ult";
2620 case 06: return "ole";
2621 case 07: return "ule";
2622 case 010: return "sf";
2623 case 011: return "ngle";
2624 case 012: return "seq";
2625 case 013: return "ngl";
2626 case 014: return "lt";
2627 case 015: return "nge";
2628 case 016: return "le";
2629 case 017: return "ngt";
2630 default: return "?";
2631 }
2632}
2633
2634
2635010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
2636"abs.%s<FMT> f<FD>, f<FS>"
2637*mipsI,mipsII,mipsIII,mipsIV:
2638*vr4100:
2639*vr5000:
2640*r3900:
2641{
2642 unsigned32 instruction = instruction_0;
2643 int destreg = ((instruction >> 6) & 0x0000001F);
2644 int fs = ((instruction >> 11) & 0x0000001F);
2645 int format = ((instruction >> 21) & 0x00000007);
2646 {
2647 if ((format != fmt_single) && (format != fmt_double))
2648 SignalException(ReservedInstruction,instruction);
2649 else
2650 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
2651 }
2652}
2653
2654
2655
2656010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
2657"add.%s<FMT> f<FD>, f<FS>, f<FT>"
2658*mipsI,mipsII,mipsIII,mipsIV:
2659*vr4100:
2660*vr5000:
2661*r3900:
2662{
2663 unsigned32 instruction = instruction_0;
2664 int destreg = ((instruction >> 6) & 0x0000001F);
2665 int fs = ((instruction >> 11) & 0x0000001F);
2666 int ft = ((instruction >> 16) & 0x0000001F);
2667 int format = ((instruction >> 21) & 0x00000007);
2668 {
2669 if ((format != fmt_single) && (format != fmt_double))
2670 SignalException(ReservedInstruction, instruction);
2671 else
2672 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
2673 }
2674}
2675
2676
2677
2678// BC1F
2679// BC1FL
2680// BC1T
2681// BC1TL
2682
2683010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
2684"bc1%s<TF>%s<ND> <OFFSET>"
2685*mipsI,mipsII,mipsIII:
2686{
2687 check_branch_bug ();
2688 TRACE_BRANCH_INPUT (PREVCOC1());
2689 if (PREVCOC1() == TF)
2690 {
2691 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
2692 TRACE_BRANCH_RESULT (dest);
2693 mark_branch_bug (dest);
2694 DELAY_SLOT (dest);
2695 }
2696 else if (ND)
2697 {
2698 TRACE_BRANCH_RESULT (0);
2699 NULLIFY_NEXT_INSTRUCTION ();
2700 }
2701 else
2702 {
2703 TRACE_BRANCH_RESULT (NIA);
2704 }
2705}
2706
2707010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
2708"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
2709"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
2710*mipsIV:
2711*vr5000:
2712#*vr4100:
2713*r3900:
2714{
2715 check_branch_bug ();
2716 if (GETFCC(CC) == TF)
2717 {
2718 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
2719 mark_branch_bug (dest);
2720 DELAY_SLOT (dest);
2721 }
2722 else if (ND)
2723 {
2724 NULLIFY_NEXT_INSTRUCTION ();
2725 }
2726}
2727
2728
2729
2730
2731
2732
2733// C.EQ.S
2734// C.EQ.D
2735// ...
2736
2737:function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
2738{
2739 if ((fmt != fmt_single) && (fmt != fmt_double))
2740 SignalException (ReservedInstruction, insn);
2741 else
2742 {
2743 int less;
2744 int equal;
2745 int unordered;
2746 int condition;
2747 unsigned64 ofs = ValueFPR (fs, fmt);
2748 unsigned64 oft = ValueFPR (ft, fmt);
2749 if (NaN (ofs, fmt) || NaN (oft, fmt))
2750 {
2751 if (FCSR & FP_ENABLE (IO))
2752 {
2753 FCSR |= FP_CAUSE (IO);
2754 SignalExceptionFPE ();
2755 }
2756 less = 0;
2757 equal = 0;
2758 unordered = 1;
2759 }
2760 else
2761 {
2762 less = Less (ofs, oft, fmt);
2763 equal = Equal (ofs, oft, fmt);
2764 unordered = 0;
2765 }
2766 condition = (((cond & (1 << 2)) && less)
2767 || ((cond & (1 << 1)) && equal)
2768 || ((cond & (1 << 0)) && unordered));
2769 SETFCC (cc, condition);
2770 }
2771}
2772
2773010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
2774"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
2775*mipsI,mipsII,mipsIII:
2776{
2777 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
2778}
2779
2780010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
2781"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
2782"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
2783*mipsIV:
2784*vr4100:
2785*vr5000:
2786*r3900:
2787{
2788 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
2789}
2790
2791
2792010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
2793"ceil.l.%s<FMT> f<FD>, f<FS>"
2794*mipsIII:
2795*mipsIV:
2796*vr4100:
2797*vr5000:
2798*r3900:
2799{
2800 unsigned32 instruction = instruction_0;
2801 int destreg = ((instruction >> 6) & 0x0000001F);
2802 int fs = ((instruction >> 11) & 0x0000001F);
2803 int format = ((instruction >> 21) & 0x00000007);
2804 {
2805 if ((format != fmt_single) && (format != fmt_double))
2806 SignalException(ReservedInstruction,instruction);
2807 else
2808 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
2809 }
2810}
2811
2812
2813010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
2814*mipsII:
2815*mipsIII:
2816*mipsIV:
2817*vr4100:
2818*vr5000:
2819*r3900:
2820{
2821 unsigned32 instruction = instruction_0;
2822 int destreg = ((instruction >> 6) & 0x0000001F);
2823 int fs = ((instruction >> 11) & 0x0000001F);
2824 int format = ((instruction >> 21) & 0x00000007);
2825 {
2826 if ((format != fmt_single) && (format != fmt_double))
2827 SignalException(ReservedInstruction,instruction);
2828 else
2829 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
2830 }
2831}
2832
2833
2834// CFC1
2835// CTC1
2836010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
2837"c%s<X>c1 r<RT>, f<FS>"
2838*mipsI:
2839*mipsII:
2840*mipsIII:
2841{
2842 if (X)
2843 {
2844 if (FS == 0)
c0efbca4 2845 PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
c906108c 2846 else if (FS == 31)
c0efbca4 2847 PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
c906108c 2848 /* else NOP */
c0efbca4 2849 PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
c906108c
SS		 2850 }
2851 else
2852 { /* control from */
2853 if (FS == 0)
2854 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
2855 else if (FS == 31)
2856 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
2857 /* else NOP */
2858 }
2859}
2860010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
2861"c%s<X>c1 r<RT>, f<FS>"
2862*mipsIV:
2863*vr4100:
2864*vr5000:
2865*r3900:
2866{
2867 if (X)
2868 {
2869 /* control to */
2870 TRACE_ALU_INPUT1 (GPR[RT]);
2871 if (FS == 0)
2872 {
2873 FCR0 = VL4_8(GPR[RT]);
2874 TRACE_ALU_RESULT (FCR0);
2875 }
2876 else if (FS == 31)
2877 {
2878 FCR31 = VL4_8(GPR[RT]);
2879 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
2880 TRACE_ALU_RESULT (FCR31);
2881 }
2882 else
2883 {
2884 TRACE_ALU_RESULT0 ();
2885 }
2886 /* else NOP */
2887 }
2888 else
2889 { /* control from */
2890 if (FS == 0)
2891 {
2892 TRACE_ALU_INPUT1 (FCR0);
2893 GPR[RT] = SIGNEXTEND (FCR0, 32);
2894 }
2895 else if (FS == 31)
2896 {
2897 TRACE_ALU_INPUT1 (FCR31);
2898 GPR[RT] = SIGNEXTEND (FCR31, 32);
2899 }
2900 TRACE_ALU_RESULT (GPR[RT]);
2901 /* else NOP */
2902 }
2903}
2904
2905
2906//
2907// FIXME: Does not correctly differentiate between mips*
2908//
2909010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
2910"cvt.d.%s<FMT> f<FD>, f<FS>"
2911*mipsI,mipsII,mipsIII,mipsIV:
2912*vr4100:
2913*vr5000:
2914*r3900:
2915{
2916 unsigned32 instruction = instruction_0;
2917 int destreg = ((instruction >> 6) & 0x0000001F);
2918 int fs = ((instruction >> 11) & 0x0000001F);
2919 int format = ((instruction >> 21) & 0x00000007);
2920 {
2921 if ((format == fmt_double) | 0)
2922 SignalException(ReservedInstruction,instruction);
2923 else
2924 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
2925 }
2926}
2927
2928
2929010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
2930"cvt.l.%s<FMT> f<FD>, f<FS>"
2931*mipsIII:
2932*mipsIV:
2933*vr4100:
2934*vr5000:
2935*r3900:
2936{
2937 unsigned32 instruction = instruction_0;
2938 int destreg = ((instruction >> 6) & 0x0000001F);
2939 int fs = ((instruction >> 11) & 0x0000001F);
2940 int format = ((instruction >> 21) & 0x00000007);
2941 {
2942 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
2943 SignalException(ReservedInstruction,instruction);
2944 else
2945 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
2946 }
2947}
2948
2949
2950//
2951// FIXME: Does not correctly differentiate between mips*
2952//
2953010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
2954"cvt.s.%s<FMT> f<FD>, f<FS>"
2955*mipsI,mipsII,mipsIII,mipsIV:
2956*vr4100:
2957*vr5000:
2958*r3900:
2959{
2960 unsigned32 instruction = instruction_0;
2961 int destreg = ((instruction >> 6) & 0x0000001F);
2962 int fs = ((instruction >> 11) & 0x0000001F);
2963 int format = ((instruction >> 21) & 0x00000007);
2964 {
2965 if ((format == fmt_single) | 0)
2966 SignalException(ReservedInstruction,instruction);
2967 else
2968 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
2969 }
2970}
2971
2972
2973010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
2974"cvt.w.%s<FMT> f<FD>, f<FS>"
2975*mipsI,mipsII,mipsIII,mipsIV:
2976*vr4100:
2977*vr5000:
2978*r3900:
2979{
2980 unsigned32 instruction = instruction_0;
2981 int destreg = ((instruction >> 6) & 0x0000001F);
2982 int fs = ((instruction >> 11) & 0x0000001F);
2983 int format = ((instruction >> 21) & 0x00000007);
2984 {
2985 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
2986 SignalException(ReservedInstruction,instruction);
2987 else
2988 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
2989 }
2990}
2991
2992
2993010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
2994"div.%s<FMT> f<FD>, f<FS>, f<FT>"
2995*mipsI,mipsII,mipsIII,mipsIV:
2996*vr4100:
2997*vr5000:
2998*r3900:
2999{
3000 unsigned32 instruction = instruction_0;
3001 int destreg = ((instruction >> 6) & 0x0000001F);
3002 int fs = ((instruction >> 11) & 0x0000001F);
3003 int ft = ((instruction >> 16) & 0x0000001F);
3004 int format = ((instruction >> 21) & 0x00000007);
3005 {
3006 if ((format != fmt_single) && (format != fmt_double))
3007 SignalException(ReservedInstruction,instruction);
3008 else
3009 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3010 }
3011}
3012
3013
3014// DMFC1
3015// DMTC1
3016010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1
3017"dm%s<X>c1 r<RT>, f<FS>"
3018*mipsIII:
3019{
3020 if (X)
3021 {
3022 if (SizeFGR() == 64)
3023 PENDING_FILL((FS + FGRIDX),GPR[RT]);
3024 else if ((FS & 0x1) == 0)
3025 {
3026 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3027 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3028 }
3029 }
3030 else
3031 {
3032 if (SizeFGR() == 64)
3033 PENDING_FILL(RT,FGR[FS]);
3034 else if ((FS & 0x1) == 0)
3035 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3036 else
a3027dd7
FCE		 3037 {
3038 if (STATE_VERBOSE_P(SD))
3039 sim_io_eprintf (SD,
673388c0
AC		 3040 "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
3041 (long) CIA);
a3027dd7
FCE		 3042 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3043 }
c906108c
SS		 3044 }
3045}
3046010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
3047"dm%s<X>c1 r<RT>, f<FS>"
3048*mipsIV:
3049*vr4100:
3050*vr5000:
3051*r3900:
3052{
3053 if (X)
3054 {
3055 if (SizeFGR() == 64)
3056 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
3057 else if ((FS & 0x1) == 0)
3058 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
3059 }
3060 else
3061 {
3062 if (SizeFGR() == 64)
3063 GPR[RT] = FGR[FS];
3064 else if ((FS & 0x1) == 0)
3065 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
3066 else
a3027dd7
FCE		 3067 {
3068 if (STATE_VERBOSE_P(SD))
3069 sim_io_eprintf (SD,
dd37a34b
AC		 3070 "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
3071 (long) CIA);
a3027dd7
FCE		 3072 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
3073 }
c906108c
SS		 3074 }
3075}
3076
3077
3078010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
3079"floor.l.%s<FMT> f<FD>, f<FS>"
3080*mipsIII:
3081*mipsIV:
3082*vr4100:
3083*vr5000:
3084*r3900:
3085{
3086 unsigned32 instruction = instruction_0;
3087 int destreg = ((instruction >> 6) & 0x0000001F);
3088 int fs = ((instruction >> 11) & 0x0000001F);
3089 int format = ((instruction >> 21) & 0x00000007);
3090 {
3091 if ((format != fmt_single) && (format != fmt_double))
3092 SignalException(ReservedInstruction,instruction);
3093 else
3094 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3095 }
3096}
3097
3098
3099010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
3100"floor.w.%s<FMT> f<FD>, f<FS>"
3101*mipsII:
3102*mipsIII:
3103*mipsIV:
3104*vr4100:
3105*vr5000:
3106*r3900:
3107{
3108 unsigned32 instruction = instruction_0;
3109 int destreg = ((instruction >> 6) & 0x0000001F);
3110 int fs = ((instruction >> 11) & 0x0000001F);
3111 int format = ((instruction >> 21) & 0x00000007);
3112 {
3113 if ((format != fmt_single) && (format != fmt_double))
3114 SignalException(ReservedInstruction,instruction);
3115 else
3116 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3117 }
3118}
3119
3120
3121110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
3122"ldc1 f<FT>, <OFFSET>(r<BASE>)"
e514a9d6 3123*mipsI:
c906108c
SS		 3124*mipsII:
3125*mipsIII:
3126*mipsIV:
3127*vr4100:
3128*vr5000:
3129*r3900:
3130{
3131 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3132}
3133
3134
3135010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
3136"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3137*mipsIV:
3138*vr5000:
3139{
3140 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3141}
3142
3143
3144
3145110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
3146"lwc1 f<FT>, <OFFSET>(r<BASE>)"
3147*mipsI,mipsII,mipsIII,mipsIV:
3148*vr4100:
3149*vr5000:
3150*r3900:
3151{
3152 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
3153}
3154
3155
3156010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
3157"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3158*mipsIV:
3159*vr5000:
3160{
3161 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
3162}
3163
3164
3165
3166//
3167// FIXME: Not correct for mips*
3168//
3169010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
3170"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3171*mipsIV:
3172*vr5000:
3173{
3174 unsigned32 instruction = instruction_0;
3175 int destreg = ((instruction >> 6) & 0x0000001F);
3176 int fs = ((instruction >> 11) & 0x0000001F);
3177 int ft = ((instruction >> 16) & 0x0000001F);
3178 int fr = ((instruction >> 21) & 0x0000001F);
3179 {
3180 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3181 }
3182}
3183
3184
3185010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
3186"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3187*mipsIV:
3188*vr5000:
3189{
3190 unsigned32 instruction = instruction_0;
3191 int destreg = ((instruction >> 6) & 0x0000001F);
3192 int fs = ((instruction >> 11) & 0x0000001F);
3193 int ft = ((instruction >> 16) & 0x0000001F);
3194 int fr = ((instruction >> 21) & 0x0000001F);
3195 {
3196 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3197 }
3198}
3199
3200
3201// MFC1
3202// MTC1
3203010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
3204"m%s<X>c1 r<RT>, f<FS>"
3205*mipsI:
3206*mipsII:
3207*mipsIII:
3208{
3209 if (X)
3210 { /*MTC1*/
3211 if (SizeFGR() == 64)
a3027dd7
FCE		 3212 {
3213 if (STATE_VERBOSE_P(SD))
3214 sim_io_eprintf (SD,
673388c0
AC		 3215 "Warning: PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
3216 (long) CIA);
a3027dd7
FCE		 3217 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
3218 }
c906108c
SS		 3219 else
3220 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
3221 }
3222 else /*MFC1*/
3223 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
3224}
3225010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
3226"m%s<X>c1 r<RT>, f<FS>"
3227*mipsIV:
3228*vr4100:
3229*vr5000:
3230*r3900:
3231{
3232 int fs = FS;
3233 if (X)
3234 /*MTC1*/
3235 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
3236 else /*MFC1*/
3237 GPR[RT] = SIGNEXTEND(FGR[FS],32);
3238}
3239
3240
3241010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
3242"mov.%s<FMT> f<FD>, f<FS>"
3243*mipsI,mipsII,mipsIII,mipsIV:
3244*vr4100:
3245*vr5000:
3246*r3900:
3247{
3248 unsigned32 instruction = instruction_0;
3249 int destreg = ((instruction >> 6) & 0x0000001F);
3250 int fs = ((instruction >> 11) & 0x0000001F);
3251 int format = ((instruction >> 21) & 0x00000007);
3252 {
3253 StoreFPR(destreg,format,ValueFPR(fs,format));
3254 }
3255}
3256
3257
3258// MOVF
c2d11a7d 3259// MOVT
f701dad2 3260000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32::MOVtf
c906108c
SS		 3261"mov%s<TF> r<RD>, r<RS>, <CC>"
3262*mipsIV:
3263*vr5000:
3264{
3265 if (GETFCC(CC) == TF)
3266 GPR[RD] = GPR[RS];
3267}
3268
3269
3270// MOVF.fmt
c2d11a7d 3271// MOVT.fmt
c906108c
SS		 3272010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
3273"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
3274*mipsIV:
3275*vr5000:
3276{
3277 unsigned32 instruction = instruction_0;
3278 int format = ((instruction >> 21) & 0x00000007);
3279 {
3280 if (GETFCC(CC) == TF)
3281 StoreFPR (FD, format, ValueFPR (FS, format));
3282 else
3283 StoreFPR (FD, format, ValueFPR (FD, format));
3284 }
3285}
3286
3287
3288010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
80ee11fa 3289"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
c906108c
SS		 3290*mipsIV:
3291*vr5000:
3292{
80ee11fa
AC		 3293 if (GPR[RT] != 0)
3294 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3295 else
3296 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
c906108c
SS		 3297}
3298
3299
3300// MOVT see MOVtf
3301
3302
3303// MOVT.fmt see MOVtf.fmt
3304
3305
3306
3307010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
3308"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3309*mipsIV:
3310*vr5000:
3311{
80ee11fa
AC		 3312 if (GPR[RT] == 0)
3313 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3314 else
3315 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
c906108c
SS		 3316}
3317
3318
3319// MSUB.fmt
3320010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
3321"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3322*mipsIV:
3323*vr5000:
3324{
3325 unsigned32 instruction = instruction_0;
3326 int destreg = ((instruction >> 6) & 0x0000001F);
3327 int fs = ((instruction >> 11) & 0x0000001F);
3328 int ft = ((instruction >> 16) & 0x0000001F);
3329 int fr = ((instruction >> 21) & 0x0000001F);
3330 {
3331 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3332 }
3333}
3334
3335
3336// MSUB.fmt
3337010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
3338"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3339*mipsIV:
3340*vr5000:
3341{
3342 unsigned32 instruction = instruction_0;
3343 int destreg = ((instruction >> 6) & 0x0000001F);
3344 int fs = ((instruction >> 11) & 0x0000001F);
3345 int ft = ((instruction >> 16) & 0x0000001F);
3346 int fr = ((instruction >> 21) & 0x0000001F);
3347 {
3348 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3349 }
3350}
3351
3352
3353// MTC1 see MxC1
3354
3355
3356010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
3357"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
3358*mipsI,mipsII,mipsIII,mipsIV:
3359*vr4100:
3360*vr5000:
3361*r3900:
3362{
3363 unsigned32 instruction = instruction_0;
3364 int destreg = ((instruction >> 6) & 0x0000001F);
3365 int fs = ((instruction >> 11) & 0x0000001F);
3366 int ft = ((instruction >> 16) & 0x0000001F);
3367 int format = ((instruction >> 21) & 0x00000007);
3368 {
3369 if ((format != fmt_single) && (format != fmt_double))
3370 SignalException(ReservedInstruction,instruction);
3371 else
3372 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
3373 }
3374}
3375
3376
3377010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
3378"neg.%s<FMT> f<FD>, f<FS>"
3379*mipsI,mipsII,mipsIII,mipsIV:
3380*vr4100:
3381*vr5000:
3382*r3900:
3383{
3384 unsigned32 instruction = instruction_0;
3385 int destreg = ((instruction >> 6) & 0x0000001F);
3386 int fs = ((instruction >> 11) & 0x0000001F);
3387 int format = ((instruction >> 21) & 0x00000007);
3388 {
3389 if ((format != fmt_single) && (format != fmt_double))
3390 SignalException(ReservedInstruction,instruction);
3391 else
3392 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
3393 }
3394}
3395
3396
3397// NMADD.fmt
3398010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
3399"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3400*mipsIV:
3401*vr5000:
3402{
3403 unsigned32 instruction = instruction_0;
3404 int destreg = ((instruction >> 6) & 0x0000001F);
3405 int fs = ((instruction >> 11) & 0x0000001F);
3406 int ft = ((instruction >> 16) & 0x0000001F);
3407 int fr = ((instruction >> 21) & 0x0000001F);
3408 {
3409 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3410 }
3411}
3412
3413
3414// NMADD.fmt
3415010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
3416"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3417*mipsIV:
3418*vr5000:
3419{
3420 unsigned32 instruction = instruction_0;
3421 int destreg = ((instruction >> 6) & 0x0000001F);
3422 int fs = ((instruction >> 11) & 0x0000001F);
3423 int ft = ((instruction >> 16) & 0x0000001F);
3424 int fr = ((instruction >> 21) & 0x0000001F);
3425 {
3426 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3427 }
3428}
3429
3430
3431// NMSUB.fmt
3432010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
3433"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3434*mipsIV:
3435*vr5000:
3436{
3437 unsigned32 instruction = instruction_0;
3438 int destreg = ((instruction >> 6) & 0x0000001F);
3439 int fs = ((instruction >> 11) & 0x0000001F);
3440 int ft = ((instruction >> 16) & 0x0000001F);
3441 int fr = ((instruction >> 21) & 0x0000001F);
3442 {
3443 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3444 }
3445}
3446
3447
3448// NMSUB.fmt
3449010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
3450"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
3451*mipsIV:
3452*vr5000:
3453{
3454 unsigned32 instruction = instruction_0;
3455 int destreg = ((instruction >> 6) & 0x0000001F);
3456 int fs = ((instruction >> 11) & 0x0000001F);
3457 int ft = ((instruction >> 16) & 0x0000001F);
3458 int fr = ((instruction >> 21) & 0x0000001F);
3459 {
3460 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3461 }
3462}
3463
3464
3465010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
3466"prefx <HINT>, r<INDEX>(r<BASE>)"
3467*mipsIV:
3468*vr5000:
3469{
3470 unsigned32 instruction = instruction_0;
3471 int fs = ((instruction >> 11) & 0x0000001F);
3472 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3473 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3474 {
3475 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
3476 address_word paddr;
3477 int uncached;
3478 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3479 Prefetch(uncached,paddr,vaddr,isDATA,fs);
3480 }
3481}
3482
3483010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
c906108c 3484"recip.%s<FMT> f<FD>, f<FS>"
e514a9d6 3485*mipsIV:
c906108c
SS		 3486*vr5000:
3487{
3488 unsigned32 instruction = instruction_0;
3489 int destreg = ((instruction >> 6) & 0x0000001F);
3490 int fs = ((instruction >> 11) & 0x0000001F);
3491 int format = ((instruction >> 21) & 0x00000007);
3492 {
3493 if ((format != fmt_single) && (format != fmt_double))
3494 SignalException(ReservedInstruction,instruction);
3495 else
3496 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
3497 }
3498}
3499
3500
3501010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
3502"round.l.%s<FMT> f<FD>, f<FS>"
3503*mipsIII:
3504*mipsIV:
3505*vr4100:
3506*vr5000:
3507*r3900:
3508{
3509 unsigned32 instruction = instruction_0;
3510 int destreg = ((instruction >> 6) & 0x0000001F);
3511 int fs = ((instruction >> 11) & 0x0000001F);
3512 int format = ((instruction >> 21) & 0x00000007);
3513 {
3514 if ((format != fmt_single) && (format != fmt_double))
3515 SignalException(ReservedInstruction,instruction);
3516 else
3517 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
3518 }
3519}
3520
3521
3522010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
3523"round.w.%s<FMT> f<FD>, f<FS>"
3524*mipsII:
3525*mipsIII:
3526*mipsIV:
3527*vr4100:
3528*vr5000:
3529*r3900:
3530{
3531 unsigned32 instruction = instruction_0;
3532 int destreg = ((instruction >> 6) & 0x0000001F);
3533 int fs = ((instruction >> 11) & 0x0000001F);
3534 int format = ((instruction >> 21) & 0x00000007);
3535 {
3536 if ((format != fmt_single) && (format != fmt_double))
3537 SignalException(ReservedInstruction,instruction);
3538 else
3539 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
3540 }
3541}
3542
3543
3544010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
3545*mipsIV:
3546"rsqrt.%s<FMT> f<FD>, f<FS>"
3547*vr5000:
3548{
3549 unsigned32 instruction = instruction_0;
3550 int destreg = ((instruction >> 6) & 0x0000001F);
3551 int fs = ((instruction >> 11) & 0x0000001F);
3552 int format = ((instruction >> 21) & 0x00000007);
3553 {
3554 if ((format != fmt_single) && (format != fmt_double))
3555 SignalException(ReservedInstruction,instruction);
3556 else
3557 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
3558 }
3559}
3560
3561
3562111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
3563"sdc1 f<FT>, <OFFSET>(r<BASE>)"
e514a9d6 3564*mipsI:
c906108c
SS		 3565*mipsII:
3566*mipsIII:
3567*mipsIV:
3568*vr4100:
3569*vr5000:
3570*r3900:
3571{
3572 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
3573}
3574
3575
3576010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
3577"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
3578*mipsIV:
3579*vr5000:
3580{
3581 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
3582}
3583
3584
3585010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
3586"sqrt.%s<FMT> f<FD>, f<FS>"
3587*mipsII:
3588*mipsIII:
3589*mipsIV:
3590*vr4100:
3591*vr5000:
3592*r3900:
3593{
3594 unsigned32 instruction = instruction_0;
3595 int destreg = ((instruction >> 6) & 0x0000001F);
3596 int fs = ((instruction >> 11) & 0x0000001F);
3597 int format = ((instruction >> 21) & 0x00000007);
3598 {
3599 if ((format != fmt_single) && (format != fmt_double))
3600 SignalException(ReservedInstruction,instruction);
3601 else
3602 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
3603 }
3604}
3605
3606
3607010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
3608"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
3609*mipsI,mipsII,mipsIII,mipsIV:
3610*vr4100:
3611*vr5000:
3612*r3900:
3613{
3614 unsigned32 instruction = instruction_0;
3615 int destreg = ((instruction >> 6) & 0x0000001F);
3616 int fs = ((instruction >> 11) & 0x0000001F);
3617 int ft = ((instruction >> 16) & 0x0000001F);
3618 int format = ((instruction >> 21) & 0x00000007);
3619 {
3620 if ((format != fmt_single) && (format != fmt_double))
3621 SignalException(ReservedInstruction,instruction);
3622 else
3623 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
3624 }
3625}
3626
3627
3628
3629111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
3630"swc1 f<FT>, <OFFSET>(r<BASE>)"
3631*mipsI,mipsII,mipsIII,mipsIV:
3632*vr4100:
3633*vr5000:
3634*r3900:
3635{
3636 unsigned32 instruction = instruction_0;
3637 signed_word offset = EXTEND16 (OFFSET);
3638 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
3639 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
3640 {
3641 address_word vaddr = ((uword64)op1 + offset);
3642 address_word paddr;
3643 int uncached;
3644 if ((vaddr & 3) != 0)
3645 {
3646 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
3647 }
3648 else
3649 {
3650 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3651 {
3652 uword64 memval = 0;
3653 uword64 memval1 = 0;
3654 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3655 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
3656 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
3657 unsigned int byte;
3658 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3659 byte = ((vaddr & mask) ^ bigendiancpu);
3660 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
3661 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3662 }
3663 }
3664 }
3665}
3666
3667
3668010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
3669"swxc1 f<FS>, r<INDEX>(r<BASE>)"
3670*mipsIV:
3671*vr5000:
3672{
3673 unsigned32 instruction = instruction_0;
3674 int fs = ((instruction >> 11) & 0x0000001F);
3675 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3676 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3677 {
3678 address_word vaddr = ((unsigned64)op1 + op2);
3679 address_word paddr;
3680 int uncached;
3681 if ((vaddr & 3) != 0)
3682 {
3683 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3684 }
3685 else
3686 {
3687 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3688 {
3689 unsigned64 memval = 0;
3690 unsigned64 memval1 = 0;
3691 unsigned64 mask = 0x7;
3692 unsigned int byte;
3693 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3694 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3695 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
3696 {
3697 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3698 }
3699 }
3700 }
3701 }
3702}
3703
3704
3705010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
3706"trunc.l.%s<FMT> f<FD>, f<FS>"
3707*mipsIII:
3708*mipsIV:
3709*vr4100:
3710*vr5000:
3711*r3900:
3712{
3713 unsigned32 instruction = instruction_0;
3714 int destreg = ((instruction >> 6) & 0x0000001F);
3715 int fs = ((instruction >> 11) & 0x0000001F);
3716 int format = ((instruction >> 21) & 0x00000007);
3717 {
3718 if ((format != fmt_single) && (format != fmt_double))
3719 SignalException(ReservedInstruction,instruction);
3720 else
3721 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
3722 }
3723}
3724
3725
3726010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
3727"trunc.w.%s<FMT> f<FD>, f<FS>"
3728*mipsII:
3729*mipsIII:
3730*mipsIV:
3731*vr4100:
3732*vr5000:
3733*r3900:
3734{
3735 unsigned32 instruction = instruction_0;
3736 int destreg = ((instruction >> 6) & 0x0000001F);
3737 int fs = ((instruction >> 11) & 0x0000001F);
3738 int format = ((instruction >> 21) & 0x00000007);
3739 {
3740 if ((format != fmt_single) && (format != fmt_double))
3741 SignalException(ReservedInstruction,instruction);
3742 else
3743 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
3744 }
3745}
3746
3747\f
3748//
3749// MIPS Architecture:
3750//
3751// System Control Instruction Set (COP0)
3752//
3753
3754
3755010000,01000,00000,16.OFFSET:COP0:32::BC0F
3756"bc0f <OFFSET>"
3757*mipsI,mipsII,mipsIII,mipsIV:
3758*vr4100:
3759*vr5000:
3760
7a292a7a
SS		 3761010000,01000,00000,16.OFFSET:COP0:32::BC0F
3762"bc0f <OFFSET>"
3763// stub needed for eCos as tx39 hardware bug workaround
3764*r3900:
3765{
3766 /* do nothing */
3767}
3768
c906108c
SS		 3769
3770010000,01000,00010,16.OFFSET:COP0:32::BC0FL
3771"bc0fl <OFFSET>"
3772*mipsI,mipsII,mipsIII,mipsIV:
3773*vr4100:
3774*vr5000:
3775
3776
3777010000,01000,00001,16.OFFSET:COP0:32::BC0T
3778"bc0t <OFFSET>"
3779*mipsI,mipsII,mipsIII,mipsIV:
3780*vr4100:
3781
3782
3783010000,01000,00011,16.OFFSET:COP0:32::BC0TL
3784"bc0tl <OFFSET>"
3785*mipsI,mipsII,mipsIII,mipsIV:
3786*vr4100:
3787*vr5000:
3788
3789
3790101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
3791*mipsIII:
3792*mipsIV:
3793*vr4100:
3794*vr5000:
3795*r3900:
3796{
3797 unsigned32 instruction = instruction_0;
3798 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3799 int hint = ((instruction >> 16) & 0x0000001F);
3800 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3801 {
3802 address_word vaddr = (op1 + offset);
3803 address_word paddr;
3804 int uncached;
3805 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3806 CacheOp(hint,vaddr,paddr,instruction);
3807 }
3808}
3809
3810
f701dad2 3811010000,1,0000000000000000000,111001:COP0:32::DI
c906108c
SS		 3812"di"
3813*mipsI,mipsII,mipsIII,mipsIV:
3814*vr4100:
3815*vr5000:
3816
3817
f701dad2 3818010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
9846de1b
JM		 3819"dmfc0 r<RT>, r<RD>"
3820*mipsIII,mipsIV:
3821{
3822 DecodeCoproc (instruction_0);
3823}
3824
3825
f701dad2 3826010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
9846de1b
JM		 3827"dmtc0 r<RT>, r<RD>"
3828*mipsIII,mipsIV:
3829{
3830 DecodeCoproc (instruction_0);
3831}
3832
3833
f701dad2 3834010000,1,0000000000000000000,111000:COP0:32::EI
c906108c
SS		 3835"ei"
3836*mipsI,mipsII,mipsIII,mipsIV:
3837*vr4100:
3838*vr5000:
3839
3840
f701dad2 3841010000,1,0000000000000000000,011000:COP0:32::ERET
c906108c
SS		 3842"eret"
3843*mipsIII:
3844*mipsIV:
3845*vr4100:
3846*vr5000:
3847{
3848 if (SR & status_ERL)
3849 {
3850 /* Oops, not yet available */
3851 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
3852 NIA = EPC;
3853 SR &= ~status_ERL;
3854 }
3855 else
3856 {
3857 NIA = EPC;
3858 SR &= ~status_EXL;
3859 }
3860}
3861
3862
3863010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
3864"mfc0 r<RT>, r<RD> # <REGX>"
3865*mipsI,mipsII,mipsIII,mipsIV:
3866*r3900:
3867*vr4100:
3868*vr5000:
3869{
3870 TRACE_ALU_INPUT0 ();
3871 DecodeCoproc (instruction_0);
3872 TRACE_ALU_RESULT (GPR[RT]);
3873}
3874
3875010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
3876"mtc0 r<RT>, r<RD> # <REGX>"
3877*mipsI,mipsII,mipsIII,mipsIV:
3878*r3900:
3879*vr4100:
3880*vr5000:
3881{
3882 DecodeCoproc (instruction_0);
3883}
3884
3885
f701dad2 3886010000,1,0000000000000000000,010000:COP0:32::RFE
c906108c
SS		 3887"rfe"
3888*mipsI,mipsII,mipsIII,mipsIV:
3889*r3900:
3890*vr4100:
3891*vr5000:
3892{
3893 DecodeCoproc (instruction_0);
3894}
3895
3896
38970100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
3898"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
3899*mipsI,mipsII,mipsIII,mipsIV:
3900*vr4100:
3901*r3900:
3902{
3903 DecodeCoproc (instruction_0);
3904}
3905
3906
3907
f701dad2 3908010000,1,0000000000000000000,001000:COP0:32::TLBP
c906108c
SS		 3909"tlbp"
3910*mipsI,mipsII,mipsIII,mipsIV:
3911*vr4100:
3912*vr5000:
3913
3914
f701dad2 3915010000,1,0000000000000000000,000001:COP0:32::TLBR
c906108c
SS		 3916"tlbr"
3917*mipsI,mipsII,mipsIII,mipsIV:
3918*vr4100:
3919*vr5000:
3920
3921
f701dad2 3922010000,1,0000000000000000000,000010:COP0:32::TLBWI
c906108c
SS		 3923"tlbwi"
3924*mipsI,mipsII,mipsIII,mipsIV:
3925*vr4100:
3926*vr5000:
3927
3928
f701dad2 3929010000,1,0000000000000000000,000110:COP0:32::TLBWR
c906108c
SS		 3930"tlbwr"
3931*mipsI,mipsII,mipsIII,mipsIV:
3932*vr4100:
3933*vr5000:
3934
3935\f
3936:include:::m16.igen
3937:include:::tx.igen
3938:include:::vr.igen
3939\f
GDB Binutils - Deliverables
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