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import gdb-1999-09-13 snapshot
[deliverable/binutils-gdb.git] / sim / mips / mips.igen
CommitLineData
c906108c
SS		 1// -*- C -*-
2//
3// In mips.igen, the semantics for many of the instructions were created
4// using code generated by gencode. Those semantic segments could be
5// greatly simplified.
6//
7// <insn> ::=
8// <insn-word> { "+" <insn-word> }
9// ":" <format-name>
10// ":" <filter-flags>
11// ":" <options>
12// ":" <name>
13// <nl>
14// { <insn-model> }
15// { <insn-mnemonic> }
16// <code-block>
17//
18
19
20// IGEN config - mips16
21// :option:16::insn-bit-size:16
22// :option:16::hi-bit-nr:15
23:option:16::insn-specifying-widths:true
24:option:16::gen-delayed-branch:false
25
26// IGEN config - mips32/64..
27// :option:32::insn-bit-size:32
28// :option:32::hi-bit-nr:31
29:option:32::insn-specifying-widths:true
30:option:32::gen-delayed-branch:false
31
32
33// Generate separate simulators for each target
34// :option:::multi-sim:true
35
36
37// Models known by this simulator
38:model:::mipsI:mips3000:
39:model:::mipsII:mips6000:
40:model:::mipsIII:mips4000:
41:model:::mipsIV:mips8000:
42:model:::mips16:mips16:
43:model:::r3900:mips3900:
44:model:::vr4100:mips4100:
45:model:::vr5000:mips5000:
46
47
48
49// Pseudo instructions known by IGEN
50:internal::::illegal:
51{
52 SignalException (ReservedInstruction, 0);
53}
54
55
56// Pseudo instructions known by interp.c
57// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
58000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
59"rsvd <OP>"
60{
61 SignalException (ReservedInstruction, instruction_0);
62}
63
64
65
66// Helper:
67//
68// Simulate a 32 bit delayslot instruction
69//
70
71:function:::address_word:delayslot32:address_word target
72{
73 instruction_word delay_insn;
74 sim_events_slip (SD, 1);
75 DSPC = CIA;
76 CIA = CIA + 4; /* NOTE not mips16 */
77 STATE |= simDELAYSLOT;
78 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
d4f3574e 79 ENGINE_ISSUE_PREFIX_HOOK();
c906108c
SS		 80 idecode_issue (CPU_, delay_insn, (CIA));
81 STATE &= ~simDELAYSLOT;
82 return target;
83}
84
85:function:::address_word:nullify_next_insn32:
86{
87 sim_events_slip (SD, 1);
88 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
89 return CIA + 8;
90}
91
92// Helper:
93//
94// Check that an access to a HI/LO register meets timing requirements
95//
96// The following requirements exist:
97//
98// - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
99// - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
100// - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
101// corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
102//
103
104:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
105{
106 if (history->mf.timestamp + 3 > time)
107 {
108 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
109 itable[MY_INDEX].name,
110 new, (long) CIA,
111 (long) history->mf.cia);
112 return 0;
113 }
114 return 1;
115}
116
117:function:::int:check_mt_hilo:hilo_history *history
118*mipsI,mipsII,mipsIII,mipsIV:
119*vr4100:
120*vr5000:
121{
122 signed64 time = sim_events_time (SD);
123 int ok = check_mf_cycles (SD_, history, time, "MT");
124 history->mt.timestamp = time;
125 history->mt.cia = CIA;
126 return ok;
127}
128
129:function:::int:check_mt_hilo:hilo_history *history
130*r3900:
131{
132 signed64 time = sim_events_time (SD);
133 history->mt.timestamp = time;
134 history->mt.cia = CIA;
135 return 1;
136}
137
138
139:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
140*mipsI,mipsII,mipsIII,mipsIV:
141*vr4100:
142*vr5000:
143*r3900:
144{
145 signed64 time = sim_events_time (SD);
146 int ok = 1;
147 if (peer != NULL
148 && peer->mt.timestamp > history->op.timestamp
149 && history->mt.timestamp < history->op.timestamp
150 && ! (history->mf.timestamp > history->op.timestamp
151 && history->mf.timestamp < peer->mt.timestamp)
152 && ! (peer->mf.timestamp > history->op.timestamp
153 && peer->mf.timestamp < peer->mt.timestamp))
154 {
155 /* The peer has been written to since the last OP yet we have
156 not */
157 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
158 itable[MY_INDEX].name,
159 (long) CIA,
160 (long) history->op.cia,
161 (long) peer->mt.cia);
162 ok = 0;
163 }
164 history->mf.timestamp = time;
165 history->mf.cia = CIA;
166 return ok;
167}
168
169
170
171:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
172*mipsI,mipsII,mipsIII,mipsIV:
173*vr4100:
174*vr5000:
175{
176 signed64 time = sim_events_time (SD);
177 int ok = (check_mf_cycles (SD_, hi, time, "OP")
178 && check_mf_cycles (SD_, lo, time, "OP"));
179 hi->op.timestamp = time;
180 lo->op.timestamp = time;
181 hi->op.cia = CIA;
182 lo->op.cia = CIA;
183 return ok;
184}
185
186// The r3900 mult and multu insns _can_ be exectuted immediatly after
187// a mf{hi,lo}
188:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
189*r3900:
190{
191 /* FIXME: could record the fact that a stall occured if we want */
192 signed64 time = sim_events_time (SD);
193 hi->op.timestamp = time;
194 lo->op.timestamp = time;
195 hi->op.cia = CIA;
196 lo->op.cia = CIA;
197 return 1;
198}
199
200
201:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
202*mipsI,mipsII,mipsIII,mipsIV:
203*vr4100:
204*vr5000:
205*r3900:
206{
207 signed64 time = sim_events_time (SD);
208 int ok = (check_mf_cycles (SD_, hi, time, "OP")
209 && check_mf_cycles (SD_, lo, time, "OP"));
210 hi->op.timestamp = time;
211 lo->op.timestamp = time;
212 hi->op.cia = CIA;
213 lo->op.cia = CIA;
214 return ok;
215}
216
217
218
219
220
221//
222// Mips Architecture:
223//
224// CPU Instruction Set (mipsI - mipsIV)
225//
226
227
228
229000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
230"add r<RD>, r<RS>, r<RT>"
231*mipsI,mipsII,mipsIII,mipsIV:
232*vr4100:
233*vr5000:
234*r3900:
235{
236 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
237 {
238 ALU32_BEGIN (GPR[RS]);
239 ALU32_ADD (GPR[RT]);
240 ALU32_END (GPR[RD]);
241 }
242 TRACE_ALU_RESULT (GPR[RD]);
243}
244
245
246
247001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
248"addi r<RT>, r<RS>, IMMEDIATE"
249*mipsI,mipsII,mipsIII,mipsIV:
250*vr4100:
251*vr5000:
252*r3900:
253{
254 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
255 {
256 ALU32_BEGIN (GPR[RS]);
257 ALU32_ADD (EXTEND16 (IMMEDIATE));
258 ALU32_END (GPR[RT]);
259 }
260 TRACE_ALU_RESULT (GPR[RT]);
261}
262
263
264
265:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
266{
267 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
268 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
269 TRACE_ALU_RESULT (GPR[rt]);
270}
271
272001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
273"addiu r<RT>, r<RS>, <IMMEDIATE>"
274*mipsI,mipsII,mipsIII,mipsIV:
275*vr4100:
276*vr5000:
277*r3900:
278{
279 do_addiu (SD_, RS, RT, IMMEDIATE);
280}
281
282
283
284:function:::void:do_addu:int rs, int rt, int rd
285{
286 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
287 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
288 TRACE_ALU_RESULT (GPR[rd]);
289}
290
291000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
292"addu r<RD>, r<RS>, r<RT>"
293*mipsI,mipsII,mipsIII,mipsIV:
294*vr4100:
295*vr5000:
296*r3900:
297{
298 do_addu (SD_, RS, RT, RD);
299}
300
301
302
303:function:::void:do_and:int rs, int rt, int rd
304{
305 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
306 GPR[rd] = GPR[rs] & GPR[rt];
307 TRACE_ALU_RESULT (GPR[rd]);
308}
309
310000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
311"and r<RD>, r<RS>, r<RT>"
312*mipsI,mipsII,mipsIII,mipsIV:
313*vr4100:
314*vr5000:
315*r3900:
316{
317 do_and (SD_, RS, RT, RD);
318}
319
320
321
322001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
323"and r<RT>, r<RS>, <IMMEDIATE>"
324*mipsI,mipsII,mipsIII,mipsIV:
325*vr4100:
326*vr5000:
327*r3900:
328{
329 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
330 GPR[RT] = GPR[RS] & IMMEDIATE;
331 TRACE_ALU_RESULT (GPR[RT]);
332}
333
334
335
336000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
337"beq r<RS>, r<RT>, <OFFSET>"
338*mipsI,mipsII,mipsIII,mipsIV:
339*vr4100:
340*vr5000:
341*r3900:
342{
343 address_word offset = EXTEND16 (OFFSET) << 2;
344 check_branch_bug ();
345 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
346 {
347 mark_branch_bug (NIA+offset);
348 DELAY_SLOT (NIA + offset);
349 }
350}
351
352
353
354010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
355"beql r<RS>, r<RT>, <OFFSET>"
356*mipsII:
357*mipsIII:
358*mipsIV:
359*vr4100:
360*vr5000:
361*r3900:
362{
363 address_word offset = EXTEND16 (OFFSET) << 2;
364 check_branch_bug ();
365 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
366 {
367 mark_branch_bug (NIA+offset);
368 DELAY_SLOT (NIA + offset);
369 }
370 else
371 NULLIFY_NEXT_INSTRUCTION ();
372}
373
374
375
376000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
377"bgez r<RS>, <OFFSET>"
378*mipsI,mipsII,mipsIII,mipsIV:
379*vr4100:
380*vr5000:
381*r3900:
382{
383 address_word offset = EXTEND16 (OFFSET) << 2;
384 check_branch_bug ();
385 if ((signed_word) GPR[RS] >= 0)
386 {
387 mark_branch_bug (NIA+offset);
388 DELAY_SLOT (NIA + offset);
389 }
390}
391
392
393
394000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
395"bgezal r<RS>, <OFFSET>"
396*mipsI,mipsII,mipsIII,mipsIV:
397*vr4100:
398*vr5000:
399*r3900:
400{
401 address_word offset = EXTEND16 (OFFSET) << 2;
402 check_branch_bug ();
403 RA = (CIA + 8);
404 if ((signed_word) GPR[RS] >= 0)
405 {
406 mark_branch_bug (NIA+offset);
407 DELAY_SLOT (NIA + offset);
408 }
409}
410
411
412
413000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
414"bgezall r<RS>, <OFFSET>"
415*mipsII:
416*mipsIII:
417*mipsIV:
418*vr4100:
419*vr5000:
420*r3900:
421{
422 address_word offset = EXTEND16 (OFFSET) << 2;
423 check_branch_bug ();
424 RA = (CIA + 8);
425 /* NOTE: The branch occurs AFTER the next instruction has been
426 executed */
427 if ((signed_word) GPR[RS] >= 0)
428 {
429 mark_branch_bug (NIA+offset);
430 DELAY_SLOT (NIA + offset);
431 }
432 else
433 NULLIFY_NEXT_INSTRUCTION ();
434}
435
436
437
438000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
439"bgezl r<RS>, <OFFSET>"
440*mipsII:
441*mipsIII:
442*mipsIV:
443*vr4100:
444*vr5000:
445*r3900:
446{
447 address_word offset = EXTEND16 (OFFSET) << 2;
448 check_branch_bug ();
449 if ((signed_word) GPR[RS] >= 0)
450 {
451 mark_branch_bug (NIA+offset);
452 DELAY_SLOT (NIA + offset);
453 }
454 else
455 NULLIFY_NEXT_INSTRUCTION ();
456}
457
458
459
460000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
461"bgtz r<RS>, <OFFSET>"
462*mipsI,mipsII,mipsIII,mipsIV:
463*vr4100:
464*vr5000:
465*r3900:
466{
467 address_word offset = EXTEND16 (OFFSET) << 2;
468 check_branch_bug ();
469 if ((signed_word) GPR[RS] > 0)
470 {
471 mark_branch_bug (NIA+offset);
472 DELAY_SLOT (NIA + offset);
473 }
474}
475
476
477
478010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
479"bgtzl r<RS>, <OFFSET>"
480*mipsII:
481*mipsIII:
482*mipsIV:
483*vr4100:
484*vr5000:
485*r3900:
486{
487 address_word offset = EXTEND16 (OFFSET) << 2;
488 check_branch_bug ();
489 /* NOTE: The branch occurs AFTER the next instruction has been
490 executed */
491 if ((signed_word) GPR[RS] > 0)
492 {
493 mark_branch_bug (NIA+offset);
494 DELAY_SLOT (NIA + offset);
495 }
496 else
497 NULLIFY_NEXT_INSTRUCTION ();
498}
499
500
501
502000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
503"blez r<RS>, <OFFSET>"
504*mipsI,mipsII,mipsIII,mipsIV:
505*vr4100:
506*vr5000:
507*r3900:
508{
509 address_word offset = EXTEND16 (OFFSET) << 2;
510 check_branch_bug ();
511 /* NOTE: The branch occurs AFTER the next instruction has been
512 executed */
513 if ((signed_word) GPR[RS] <= 0)
514 {
515 mark_branch_bug (NIA+offset);
516 DELAY_SLOT (NIA + offset);
517 }
518}
519
520
521
522010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
523"bgezl r<RS>, <OFFSET>"
524*mipsII:
525*mipsIII:
526*mipsIV:
527*vr4100:
528*vr5000:
529*r3900:
530{
531 address_word offset = EXTEND16 (OFFSET) << 2;
532 check_branch_bug ();
533 if ((signed_word) GPR[RS] <= 0)
534 {
535 mark_branch_bug (NIA+offset);
536 DELAY_SLOT (NIA + offset);
537 }
538 else
539 NULLIFY_NEXT_INSTRUCTION ();
540}
541
542
543
544000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
545"bltz r<RS>, <OFFSET>"
546*mipsI,mipsII,mipsIII,mipsIV:
547*vr4100:
548*vr5000:
549*r3900:
550{
551 address_word offset = EXTEND16 (OFFSET) << 2;
552 check_branch_bug ();
553 if ((signed_word) GPR[RS] < 0)
554 {
555 mark_branch_bug (NIA+offset);
556 DELAY_SLOT (NIA + offset);
557 }
558}
559
560
561
562000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
563"bltzal r<RS>, <OFFSET>"
564*mipsI,mipsII,mipsIII,mipsIV:
565*vr4100:
566*vr5000:
567*r3900:
568{
569 address_word offset = EXTEND16 (OFFSET) << 2;
570 check_branch_bug ();
571 RA = (CIA + 8);
572 /* NOTE: The branch occurs AFTER the next instruction has been
573 executed */
574 if ((signed_word) GPR[RS] < 0)
575 {
576 mark_branch_bug (NIA+offset);
577 DELAY_SLOT (NIA + offset);
578 }
579}
580
581
582
583000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
584"bltzall r<RS>, <OFFSET>"
585*mipsII:
586*mipsIII:
587*mipsIV:
588*vr4100:
589*vr5000:
590*r3900:
591{
592 address_word offset = EXTEND16 (OFFSET) << 2;
593 check_branch_bug ();
594 RA = (CIA + 8);
595 if ((signed_word) GPR[RS] < 0)
596 {
597 mark_branch_bug (NIA+offset);
598 DELAY_SLOT (NIA + offset);
599 }
600 else
601 NULLIFY_NEXT_INSTRUCTION ();
602}
603
604
605
606000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
607"bltzl r<RS>, <OFFSET>"
608*mipsII:
609*mipsIII:
610*mipsIV:
611*vr4100:
612*vr5000:
613*r3900:
614{
615 address_word offset = EXTEND16 (OFFSET) << 2;
616 check_branch_bug ();
617 /* NOTE: The branch occurs AFTER the next instruction has been
618 executed */
619 if ((signed_word) GPR[RS] < 0)
620 {
621 mark_branch_bug (NIA+offset);
622 DELAY_SLOT (NIA + offset);
623 }
624 else
625 NULLIFY_NEXT_INSTRUCTION ();
626}
627
628
629
630000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
631"bne r<RS>, r<RT>, <OFFSET>"
632*mipsI,mipsII,mipsIII,mipsIV:
633*vr4100:
634*vr5000:
635*r3900:
636{
637 address_word offset = EXTEND16 (OFFSET) << 2;
638 check_branch_bug ();
639 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
640 {
641 mark_branch_bug (NIA+offset);
642 DELAY_SLOT (NIA + offset);
643 }
644}
645
646
647
648010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
649"bnel r<RS>, r<RT>, <OFFSET>"
650*mipsII:
651*mipsIII:
652*mipsIV:
653*vr4100:
654*vr5000:
655*r3900:
656{
657 address_word offset = EXTEND16 (OFFSET) << 2;
658 check_branch_bug ();
659 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
660 {
661 mark_branch_bug (NIA+offset);
662 DELAY_SLOT (NIA + offset);
663 }
664 else
665 NULLIFY_NEXT_INSTRUCTION ();
666}
667
668
669
670000000,20.CODE,001101:SPECIAL:32::BREAK
671"break"
672*mipsI,mipsII,mipsIII,mipsIV:
673*vr4100:
674*vr5000:
675*r3900:
676{
677 /* Check for some break instruction which are reserved for use by the simulator. */
678 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
679 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
680 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
681 {
682 sim_engine_halt (SD, CPU, NULL, cia,
683 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
684 }
685 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
686 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
687 {
688 if (STATE & simDELAYSLOT)
689 PC = cia - 4; /* reference the branch instruction */
690 else
691 PC = cia;
692 SignalException(BreakPoint, instruction_0);
693 }
694
695 else
696 {
697 /* If we get this far, we're not an instruction reserved by the sim. Raise
698 the exception. */
699 SignalException(BreakPoint, instruction_0);
700 }
701}
702
703
704
705
706
707
708000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
709"dadd r<RD>, r<RS>, r<RT>"
710*mipsIII:
711*mipsIV:
712*vr4100:
713*vr5000:
714{
715 /* this check's for overflow */
716 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
717 {
718 ALU64_BEGIN (GPR[RS]);
719 ALU64_ADD (GPR[RT]);
720 ALU64_END (GPR[RD]);
721 }
722 TRACE_ALU_RESULT (GPR[RD]);
723}
724
725
726
727011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
728"daddi r<RT>, r<RS>, <IMMEDIATE>"
729*mipsIII:
730*mipsIV:
731*vr4100:
732*vr5000:
733{
734 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
735 {
736 ALU64_BEGIN (GPR[RS]);
737 ALU64_ADD (EXTEND16 (IMMEDIATE));
738 ALU64_END (GPR[RT]);
739 }
740 TRACE_ALU_RESULT (GPR[RT]);
741}
742
743
744
745:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
746{
747 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
748 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
749 TRACE_ALU_RESULT (GPR[rt]);
750}
751
752011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
753"daddu r<RT>, r<RS>, <IMMEDIATE>"
754*mipsIII:
755*mipsIV:
756*vr4100:
757*vr5000:
758{
759 do_daddiu (SD_, RS, RT, IMMEDIATE);
760}
761
762
763
764:function:::void:do_daddu:int rs, int rt, int rd
765{
766 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
767 GPR[rd] = GPR[rs] + GPR[rt];
768 TRACE_ALU_RESULT (GPR[rd]);
769}
770
771000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
772"daddu r<RD>, r<RS>, r<RT>"
773*mipsIII:
774*mipsIV:
775*vr4100:
776*vr5000:
777{
778 do_daddu (SD_, RS, RT, RD);
779}
780
781
782
783:function:::void:do_ddiv:int rs, int rt
784{
785 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
786 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
787 {
788 signed64 n = GPR[rs];
789 signed64 d = GPR[rt];
790 signed64 hi;
791 signed64 lo;
792 if (d == 0)
793 {
794 lo = SIGNED64 (0x8000000000000000);
795 hi = 0;
796 }
797 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
798 {
799 lo = SIGNED64 (0x8000000000000000);
800 hi = 0;
801 }
802 else
803 {
804 lo = (n / d);
805 hi = (n % d);
806 }
807 HI = hi;
808 LO = lo;
809 }
810 TRACE_ALU_RESULT2 (HI, LO);
811}
812
813000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
814"ddiv r<RS>, r<RT>"
815*mipsIII:
816*mipsIV:
817*vr4100:
818*vr5000:
819{
820 do_ddiv (SD_, RS, RT);
821}
822
823
824
825:function:::void:do_ddivu:int rs, int rt
826{
827 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
828 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
829 {
830 unsigned64 n = GPR[rs];
831 unsigned64 d = GPR[rt];
832 unsigned64 hi;
833 unsigned64 lo;
834 if (d == 0)
835 {
836 lo = SIGNED64 (0x8000000000000000);
837 hi = 0;
838 }
839 else
840 {
841 lo = (n / d);
842 hi = (n % d);
843 }
844 HI = hi;
845 LO = lo;
846 }
847 TRACE_ALU_RESULT2 (HI, LO);
848}
849
850000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
851"ddivu r<RS>, r<RT>"
852*mipsIII:
853*mipsIV:
854*vr4100:
855*vr5000:
856{
857 do_ddivu (SD_, RS, RT);
858}
859
860
861
862:function:::void:do_div:int rs, int rt
863{
864 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
865 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
866 {
867 signed32 n = GPR[rs];
868 signed32 d = GPR[rt];
869 if (d == 0)
870 {
871 LO = EXTEND32 (0x80000000);
872 HI = EXTEND32 (0);
873 }
874 else if (n == SIGNED32 (0x80000000) && d == -1)
875 {
876 LO = EXTEND32 (0x80000000);
877 HI = EXTEND32 (0);
878 }
879 else
880 {
881 LO = EXTEND32 (n / d);
882 HI = EXTEND32 (n % d);
883 }
884 }
885 TRACE_ALU_RESULT2 (HI, LO);
886}
887
888000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
889"div r<RS>, r<RT>"
890*mipsI,mipsII,mipsIII,mipsIV:
891*vr4100:
892*vr5000:
893*r3900:
894{
895 do_div (SD_, RS, RT);
896}
897
898
899
900:function:::void:do_divu:int rs, int rt
901{
902 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
903 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
904 {
905 unsigned32 n = GPR[rs];
906 unsigned32 d = GPR[rt];
907 if (d == 0)
908 {
909 LO = EXTEND32 (0x80000000);
910 HI = EXTEND32 (0);
911 }
912 else
913 {
914 LO = EXTEND32 (n / d);
915 HI = EXTEND32 (n % d);
916 }
917 }
918 TRACE_ALU_RESULT2 (HI, LO);
919}
920
921000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
922"divu r<RS>, r<RT>"
923*mipsI,mipsII,mipsIII,mipsIV:
924*vr4100:
925*vr5000:
926*r3900:
927{
928 do_divu (SD_, RS, RT);
929}
930
931
932
933:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
934{
935 unsigned64 lo;
936 unsigned64 hi;
937 unsigned64 m00;
938 unsigned64 m01;
939 unsigned64 m10;
940 unsigned64 m11;
941 unsigned64 mid;
942 int sign;
943 unsigned64 op1 = GPR[rs];
944 unsigned64 op2 = GPR[rt];
945 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
946 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
947 /* make signed multiply unsigned */
948 sign = 0;
949 if (signed_p)
950 {
951 if (op1 < 0)
952 {
953 op1 = - op1;
954 ++sign;
955 }
956 if (op2 < 0)
957 {
958 op2 = - op2;
959 ++sign;
960 }
961 }
962 /* multuply out the 4 sub products */
963 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
964 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
965 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
966 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
967 /* add the products */
968 mid = ((unsigned64) VH4_8 (m00)
969 + (unsigned64) VL4_8 (m10)
970 + (unsigned64) VL4_8 (m01));
971 lo = U8_4 (mid, m00);
972 hi = (m11
973 + (unsigned64) VH4_8 (mid)
974 + (unsigned64) VH4_8 (m01)
975 + (unsigned64) VH4_8 (m10));
976 /* fix the sign */
977 if (sign & 1)
978 {
979 lo = -lo;
980 if (lo == 0)
981 hi = -hi;
982 else
983 hi = -hi - 1;
984 }
985 /* save the result HI/LO (and a gpr) */
986 LO = lo;
987 HI = hi;
988 if (rd != 0)
989 GPR[rd] = lo;
990 TRACE_ALU_RESULT2 (HI, LO);
991}
992
993:function:::void:do_dmult:int rs, int rt, int rd
994{
995 do_dmultx (SD_, rs, rt, rd, 1);
996}
997
998000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
999"dmult r<RS>, r<RT>"
1000*mipsIII,mipsIV:
1001*vr4100:
1002{
1003 do_dmult (SD_, RS, RT, 0);
1004}
1005
1006000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1007"dmult r<RS>, r<RT>":RD == 0
1008"dmult r<RD>, r<RS>, r<RT>"
1009*vr5000:
1010{
1011 do_dmult (SD_, RS, RT, RD);
1012}
1013
1014
1015
1016:function:::void:do_dmultu:int rs, int rt, int rd
1017{
1018 do_dmultx (SD_, rs, rt, rd, 0);
1019}
1020
1021000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1022"dmultu r<RS>, r<RT>"
1023*mipsIII,mipsIV:
1024*vr4100:
1025{
1026 do_dmultu (SD_, RS, RT, 0);
1027}
1028
1029000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1030"dmultu r<RD>, r<RS>, r<RT>":RD == 0
1031"dmultu r<RS>, r<RT>"
1032*vr5000:
1033{
1034 do_dmultu (SD_, RS, RT, RD);
1035}
1036
1037:function:::void:do_dsll:int rt, int rd, int shift
1038{
1039 GPR[rd] = GPR[rt] << shift;
1040}
1041
1042:function:::void:do_dsllv:int rs, int rt, int rd
1043{
1044 int s = MASKED64 (GPR[rs], 5, 0);
1045 GPR[rd] = GPR[rt] << s;
1046}
1047
1048
104900000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1050"dsll r<RD>, r<RT>, <SHIFT>"
1051*mipsIII:
1052*mipsIV:
1053*vr4100:
1054*vr5000:
1055{
1056 do_dsll (SD_, RT, RD, SHIFT);
1057}
1058
1059
106000000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1061"dsll32 r<RD>, r<RT>, <SHIFT>"
1062*mipsIII:
1063*mipsIV:
1064*vr4100:
1065*vr5000:
1066{
1067 int s = 32 + SHIFT;
1068 GPR[RD] = GPR[RT] << s;
1069}
1070
1071000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1072"dsllv r<RD>, r<RT>, r<RS>"
1073*mipsIII:
1074*mipsIV:
1075*vr4100:
1076*vr5000:
1077{
1078 do_dsllv (SD_, RS, RT, RD);
1079}
1080
1081:function:::void:do_dsra:int rt, int rd, int shift
1082{
1083 GPR[rd] = ((signed64) GPR[rt]) >> shift;
1084}
1085
1086
108700000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1088"dsra r<RD>, r<RT>, <SHIFT>"
1089*mipsIII:
1090*mipsIV:
1091*vr4100:
1092*vr5000:
1093{
1094 do_dsra (SD_, RT, RD, SHIFT);
1095}
1096
1097
109800000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1099"dsra32 r<RT>, r<RD>, <SHIFT>"
1100*mipsIII:
1101*mipsIV:
1102*vr4100:
1103*vr5000:
1104{
1105 int s = 32 + SHIFT;
1106 GPR[RD] = ((signed64) GPR[RT]) >> s;
1107}
1108
1109
1110:function:::void:do_dsrav:int rs, int rt, int rd
1111{
1112 int s = MASKED64 (GPR[rs], 5, 0);
1113 TRACE_ALU_INPUT2 (GPR[rt], s);
1114 GPR[rd] = ((signed64) GPR[rt]) >> s;
1115 TRACE_ALU_RESULT (GPR[rd]);
1116}
1117
1118000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1119"dsra32 r<RT>, r<RD>, r<RS>"
1120*mipsIII:
1121*mipsIV:
1122*vr4100:
1123*vr5000:
1124{
1125 do_dsrav (SD_, RS, RT, RD);
1126}
1127
1128:function:::void:do_dsrl:int rt, int rd, int shift
1129{
1130 GPR[rd] = (unsigned64) GPR[rt] >> shift;
1131}
1132
1133
113400000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1135"dsrl r<RD>, r<RT>, <SHIFT>"
1136*mipsIII:
1137*mipsIV:
1138*vr4100:
1139*vr5000:
1140{
1141 do_dsrl (SD_, RT, RD, SHIFT);
1142}
1143
1144
114500000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1146"dsrl32 r<RD>, r<RT>, <SHIFT>"
1147*mipsIII:
1148*mipsIV:
1149*vr4100:
1150*vr5000:
1151{
1152 int s = 32 + SHIFT;
1153 GPR[RD] = (unsigned64) GPR[RT] >> s;
1154}
1155
1156
1157:function:::void:do_dsrlv:int rs, int rt, int rd
1158{
1159 int s = MASKED64 (GPR[rs], 5, 0);
1160 GPR[rd] = (unsigned64) GPR[rt] >> s;
1161}
1162
1163
1164
1165000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1166"dsrl32 r<RD>, r<RT>, r<RS>"
1167*mipsIII:
1168*mipsIV:
1169*vr4100:
1170*vr5000:
1171{
1172 do_dsrlv (SD_, RS, RT, RD);
1173}
1174
1175
1176000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1177"dsub r<RD>, r<RS>, r<RT>"
1178*mipsIII:
1179*mipsIV:
1180*vr4100:
1181*vr5000:
1182{
1183 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1184 {
1185 ALU64_BEGIN (GPR[RS]);
1186 ALU64_SUB (GPR[RT]);
1187 ALU64_END (GPR[RD]);
1188 }
1189 TRACE_ALU_RESULT (GPR[RD]);
1190}
1191
1192
1193:function:::void:do_dsubu:int rs, int rt, int rd
1194{
1195 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1196 GPR[rd] = GPR[rs] - GPR[rt];
1197 TRACE_ALU_RESULT (GPR[rd]);
1198}
1199
1200000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1201"dsubu r<RD>, r<RS>, r<RT>"
1202*mipsIII:
1203*mipsIV:
1204*vr4100:
1205*vr5000:
1206{
1207 do_dsubu (SD_, RS, RT, RD);
1208}
1209
1210
1211000010,26.INSTR_INDEX:NORMAL:32::J
1212"j <INSTR_INDEX>"
1213*mipsI,mipsII,mipsIII,mipsIV:
1214*vr4100:
1215*vr5000:
1216*r3900:
1217{
1218 /* NOTE: The region used is that of the delay slot NIA and NOT the
1219 current instruction */
1220 address_word region = (NIA & MASK (63, 28));
1221 DELAY_SLOT (region | (INSTR_INDEX << 2));
1222}
1223
1224
1225000011,26.INSTR_INDEX:NORMAL:32::JAL
1226"jal <INSTR_INDEX>"
1227*mipsI,mipsII,mipsIII,mipsIV:
1228*vr4100:
1229*vr5000:
1230*r3900:
1231{
1232 /* NOTE: The region used is that of the delay slot and NOT the
1233 current instruction */
1234 address_word region = (NIA & MASK (63, 28));
1235 GPR[31] = CIA + 8;
1236 DELAY_SLOT (region | (INSTR_INDEX << 2));
1237}
1238
1239000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1240"jalr r<RS>":RD == 31
1241"jalr r<RD>, r<RS>"
1242*mipsI,mipsII,mipsIII,mipsIV:
1243*vr4100:
1244*vr5000:
1245*r3900:
1246{
1247 address_word temp = GPR[RS];
1248 GPR[RD] = CIA + 8;
1249 DELAY_SLOT (temp);
1250}
1251
1252
1253000000,5.RS,000000000000000001000:SPECIAL:32::JR
1254"jr r<RS>"
1255*mipsI,mipsII,mipsIII,mipsIV:
1256*vr4100:
1257*vr5000:
1258*r3900:
1259{
1260 DELAY_SLOT (GPR[RS]);
1261}
1262
1263
1264:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1265{
1266 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1267 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1268 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1269 unsigned int byte;
1270 address_word paddr;
1271 int uncached;
1272 unsigned64 memval;
1273 address_word vaddr;
1274
1275 vaddr = base + offset;
1276 if ((vaddr & access) != 0)
1277 {
1278 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1279 }
1280 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1281 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1282 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1283 byte = ((vaddr & mask) ^ bigendiancpu);
1284 return (memval >> (8 * byte));
1285}
1286
1287
1288100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1289"lb r<RT>, <OFFSET>(r<BASE>)"
1290*mipsI,mipsII,mipsIII,mipsIV:
1291*vr4100:
1292*vr5000:
1293*r3900:
1294{
1295 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1296}
1297
1298
1299100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1300"lbu r<RT>, <OFFSET>(r<BASE>)"
1301*mipsI,mipsII,mipsIII,mipsIV:
1302*vr4100:
1303*vr5000:
1304*r3900:
1305{
1306 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1307}
1308
1309
1310110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1311"ld r<RT>, <OFFSET>(r<BASE>)"
1312*mipsIII:
1313*mipsIV:
1314*vr4100:
1315*vr5000:
1316{
1317 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1318}
1319
1320
13211101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1322"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1323*mipsII:
1324*mipsIII:
1325*mipsIV:
1326*vr4100:
1327*vr5000:
1328*r3900:
1329{
1330 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1331}
1332
1333
1334
1335
1336011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1337"ldl r<RT>, <OFFSET>(r<BASE>)"
1338*mipsIII:
1339*mipsIV:
1340*vr4100:
1341*vr5000:
1342{
1343 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1344}
1345
1346
1347011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1348"ldr r<RT>, <OFFSET>(r<BASE>)"
1349*mipsIII:
1350*mipsIV:
1351*vr4100:
1352*vr5000:
1353{
1354 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1355}
1356
1357
1358100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1359"lh r<RT>, <OFFSET>(r<BASE>)"
1360*mipsI,mipsII,mipsIII,mipsIV:
1361*vr4100:
1362*vr5000:
1363*r3900:
1364{
1365 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1366}
1367
1368
1369100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1370"lhu r<RT>, <OFFSET>(r<BASE>)"
1371*mipsI,mipsII,mipsIII,mipsIV:
1372*vr4100:
1373*vr5000:
1374*r3900:
1375{
1376 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1377}
1378
1379
1380110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1381"ll r<RT>, <OFFSET>(r<BASE>)"
1382*mipsII:
1383*mipsIII:
1384*mipsIV:
1385*vr4100:
1386*vr5000:
1387{
1388 unsigned32 instruction = instruction_0;
1389 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1390 int destreg = ((instruction >> 16) & 0x0000001F);
1391 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1392 {
1393 address_word vaddr = ((unsigned64)op1 + offset);
1394 address_word paddr;
1395 int uncached;
1396 if ((vaddr & 3) != 0)
1397 {
1398 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
1399 }
1400 else
1401 {
1402 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1403 {
1404 unsigned64 memval = 0;
1405 unsigned64 memval1 = 0;
1406 unsigned64 mask = 0x7;
1407 unsigned int shift = 2;
1408 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1409 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1410 unsigned int byte;
1411 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1412 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1413 byte = ((vaddr & mask) ^ (bigend << shift));
1414 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1415 LLBIT = 1;
1416 }
1417 }
1418 }
1419}
1420
1421
1422110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1423"lld r<RT>, <OFFSET>(r<BASE>)"
1424*mipsIII:
1425*mipsIV:
1426*vr4100:
1427*vr5000:
1428{
1429 unsigned32 instruction = instruction_0;
1430 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1431 int destreg = ((instruction >> 16) & 0x0000001F);
1432 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1433 {
1434 address_word vaddr = ((unsigned64)op1 + offset);
1435 address_word paddr;
1436 int uncached;
1437 if ((vaddr & 7) != 0)
1438 {
1439 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
1440 }
1441 else
1442 {
1443 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1444 {
1445 unsigned64 memval = 0;
1446 unsigned64 memval1 = 0;
1447 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1448 GPR[destreg] = memval;
1449 LLBIT = 1;
1450 }
1451 }
1452 }
1453}
1454
1455
1456001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1457"lui r<RT>, <IMMEDIATE>"
1458*mipsI,mipsII,mipsIII,mipsIV:
1459*vr4100:
1460*vr5000:
1461*r3900:
1462{
1463 TRACE_ALU_INPUT1 (IMMEDIATE);
1464 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1465 TRACE_ALU_RESULT (GPR[RT]);
1466}
1467
1468
1469100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1470"lw r<RT>, <OFFSET>(r<BASE>)"
1471*mipsI,mipsII,mipsIII,mipsIV:
1472*vr4100:
1473*vr5000:
1474*r3900:
1475{
1476 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1477}
1478
1479
14801100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1481"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1482*mipsI,mipsII,mipsIII,mipsIV:
1483*vr4100:
1484*vr5000:
1485*r3900:
1486{
1487 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1488}
1489
1490
1491:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1492{
1493 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1494 address_word reverseendian = (ReverseEndian ? -1 : 0);
1495 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1496 unsigned int byte;
1497 unsigned int word;
1498 address_word paddr;
1499 int uncached;
1500 unsigned64 memval;
1501 address_word vaddr;
1502 int nr_lhs_bits;
1503 int nr_rhs_bits;
1504 unsigned_word lhs_mask;
1505 unsigned_word temp;
1506
1507 vaddr = base + offset;
1508 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1509 paddr = (paddr ^ (reverseendian & mask));
1510 if (BigEndianMem == 0)
1511 paddr = paddr & ~access;
1512
1513 /* compute where within the word/mem we are */
1514 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1515 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1516 nr_lhs_bits = 8 * byte + 8;
1517 nr_rhs_bits = 8 * access - 8 * byte;
1518 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1519
1520 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1521 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1522 (long) ((unsigned64) paddr >> 32), (long) paddr,
1523 word, byte, nr_lhs_bits, nr_rhs_bits); */
1524
1525 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1526 if (word == 0)
1527 {
1528 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1529 temp = (memval << nr_rhs_bits);
1530 }
1531 else
1532 {
1533 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1534 temp = (memval >> nr_lhs_bits);
1535 }
1536 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1537 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1538
1539 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1540 (long) ((unsigned64) memval >> 32), (long) memval,
1541 (long) ((unsigned64) temp >> 32), (long) temp,
1542 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1543 (long) (rt >> 32), (long) rt); */
1544 return rt;
1545}
1546
1547
1548100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1549"lwl r<RT>, <OFFSET>(r<BASE>)"
1550*mipsI,mipsII,mipsIII,mipsIV:
1551*vr4100:
1552*vr5000:
1553*r3900:
1554{
7a292a7a 1555 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
c906108c
SS		 1556}
1557
1558
1559:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1560{
1561 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1562 address_word reverseendian = (ReverseEndian ? -1 : 0);
1563 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1564 unsigned int byte;
1565 address_word paddr;
1566 int uncached;
1567 unsigned64 memval;
1568 address_word vaddr;
1569
1570 vaddr = base + offset;
1571 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1572 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1573 paddr = (paddr ^ (reverseendian & mask));
1574 if (BigEndianMem != 0)
1575 paddr = paddr & ~access;
1576 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1577 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
1578 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1579 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1580 (long) paddr, byte, (long) paddr, (long) memval); */
1581 {
1582 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1583 rt &= ~screen;
1584 rt |= (memval >> (8 * byte)) & screen;
1585 }
1586 return rt;
1587}
1588
1589
1590100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1591"lwr r<RT>, <OFFSET>(r<BASE>)"
1592*mipsI,mipsII,mipsIII,mipsIV:
1593*vr4100:
1594*vr5000:
1595*r3900:
1596{
1597 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1598}
1599
1600
1601100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1602"lwu r<RT>, <OFFSET>(r<BASE>)"
1603*mipsIII:
1604*mipsIV:
1605*vr4100:
1606*vr5000:
1607{
1608 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
1609}
1610
1611
1612:function:::void:do_mfhi:int rd
1613{
1614 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
1615 TRACE_ALU_INPUT1 (HI);
1616 GPR[rd] = HI;
1617 TRACE_ALU_RESULT (GPR[rd]);
1618}
1619
1620000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1621"mfhi r<RD>"
1622*mipsI,mipsII,mipsIII,mipsIV:
1623*vr4100:
1624*vr5000:
1625*r3900:
1626{
1627 do_mfhi (SD_, RD);
1628}
1629
1630
1631
1632:function:::void:do_mflo:int rd
1633{
1634 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
1635 TRACE_ALU_INPUT1 (LO);
1636 GPR[rd] = LO;
1637 TRACE_ALU_RESULT (GPR[rd]);
1638}
1639
1640000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1641"mflo r<RD>"
1642*mipsI,mipsII,mipsIII,mipsIV:
1643*vr4100:
1644*vr5000:
1645*r3900:
1646{
1647 do_mflo (SD_, RD);
1648}
1649
1650
1651
1652000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
1653"movn r<RD>, r<RS>, r<RT>"
1654*mipsIV:
1655*vr5000:
1656{
1657 if (GPR[RT] != 0)
1658 GPR[RD] = GPR[RS];
1659}
1660
1661
1662
1663000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
1664"movz r<RD>, r<RS>, r<RT>"
1665*mipsIV:
1666*vr5000:
1667{
1668 if (GPR[RT] == 0)
1669 GPR[RD] = GPR[RS];
1670}
1671
1672
1673
1674000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1675"mthi r<RS>"
1676*mipsI,mipsII,mipsIII,mipsIV:
1677*vr4100:
1678*vr5000:
1679*r3900:
1680{
1681 check_mt_hilo (SD_, HIHISTORY);
1682 HI = GPR[RS];
1683}
1684
1685
1686
1687000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
1688"mtlo r<RS>"
1689*mipsI,mipsII,mipsIII,mipsIV:
1690*vr4100:
1691*vr5000:
1692*r3900:
1693{
1694 check_mt_hilo (SD_, LOHISTORY);
1695 LO = GPR[RS];
1696}
1697
1698
1699
1700:function:::void:do_mult:int rs, int rt, int rd
1701{
1702 signed64 prod;
1703 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1704 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1705 prod = (((signed64)(signed32) GPR[rs])
1706 * ((signed64)(signed32) GPR[rt]));
1707 LO = EXTEND32 (VL4_8 (prod));
1708 HI = EXTEND32 (VH4_8 (prod));
1709 if (rd != 0)
1710 GPR[rd] = LO;
1711 TRACE_ALU_RESULT2 (HI, LO);
1712}
1713
1714000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
1715"mult r<RS>, r<RT>"
1716*mipsI,mipsII,mipsIII,mipsIV:
1717*vr4100:
1718{
1719 do_mult (SD_, RS, RT, 0);
1720}
1721
1722
1723000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
9846de1b 1724"mult r<RS>, r<RT>":RD == 0
c906108c
SS		 1725"mult r<RD>, r<RS>, r<RT>"
1726*vr5000:
1727*r3900:
1728{
1729 do_mult (SD_, RS, RT, RD);
1730}
1731
1732
1733:function:::void:do_multu:int rs, int rt, int rd
1734{
1735 unsigned64 prod;
1736 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1737 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1738 prod = (((unsigned64)(unsigned32) GPR[rs])
1739 * ((unsigned64)(unsigned32) GPR[rt]));
1740 LO = EXTEND32 (VL4_8 (prod));
1741 HI = EXTEND32 (VH4_8 (prod));
1742 if (rd != 0)
1743 GPR[rd] = LO;
1744 TRACE_ALU_RESULT2 (HI, LO);
1745}
1746
1747000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
1748"multu r<RS>, r<RT>"
1749*mipsI,mipsII,mipsIII,mipsIV:
1750*vr4100:
1751{
cff3e48b 1752 do_multu (SD_, RS, RT, 0);
c906108c
SS		 1753}
1754
1755000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
9846de1b 1756"multu r<RS>, r<RT>":RD == 0
c906108c
SS		 1757"multu r<RD>, r<RS>, r<RT>"
1758*vr5000:
1759*r3900:
1760{
cff3e48b 1761 do_multu (SD_, RS, RT, RD);
c906108c
SS		 1762}
1763
1764
1765:function:::void:do_nor:int rs, int rt, int rd
1766{
1767 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1768 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
1769 TRACE_ALU_RESULT (GPR[rd]);
1770}
1771
1772000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
1773"nor r<RD>, r<RS>, r<RT>"
1774*mipsI,mipsII,mipsIII,mipsIV:
1775*vr4100:
1776*vr5000:
1777*r3900:
1778{
1779 do_nor (SD_, RS, RT, RD);
1780}
1781
1782
1783:function:::void:do_or:int rs, int rt, int rd
1784{
1785 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1786 GPR[rd] = (GPR[rs] | GPR[rt]);
1787 TRACE_ALU_RESULT (GPR[rd]);
1788}
1789
1790000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
1791"or r<RD>, r<RS>, r<RT>"
1792*mipsI,mipsII,mipsIII,mipsIV:
1793*vr4100:
1794*vr5000:
1795*r3900:
1796{
1797 do_or (SD_, RS, RT, RD);
1798}
1799
1800
1801
1802:function:::void:do_ori:int rs, int rt, unsigned immediate
1803{
1804 TRACE_ALU_INPUT2 (GPR[rs], immediate);
1805 GPR[rt] = (GPR[rs] | immediate);
1806 TRACE_ALU_RESULT (GPR[rt]);
1807}
1808
1809001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
1810"ori r<RT>, r<RS>, <IMMEDIATE>"
1811*mipsI,mipsII,mipsIII,mipsIV:
1812*vr4100:
1813*vr5000:
1814*r3900:
1815{
1816 do_ori (SD_, RS, RT, IMMEDIATE);
1817}
1818
1819
1820110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
1821*mipsIV:
1822*vr5000:
1823{
1824 unsigned32 instruction = instruction_0;
1825 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1826 int hint = ((instruction >> 16) & 0x0000001F);
1827 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1828 {
1829 address_word vaddr = ((unsigned64)op1 + offset);
1830 address_word paddr;
1831 int uncached;
1832 {
1833 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1834 Prefetch(uncached,paddr,vaddr,isDATA,hint);
1835 }
1836 }
1837}
1838
1839:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
1840{
1841 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1842 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1843 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1844 unsigned int byte;
1845 address_word paddr;
1846 int uncached;
1847 unsigned64 memval;
1848 address_word vaddr;
1849
1850 vaddr = base + offset;
1851 if ((vaddr & access) != 0)
1852 {
1853 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
1854 }
1855 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
1856 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1857 byte = ((vaddr & mask) ^ bigendiancpu);
1858 memval = (word << (8 * byte));
1859 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
1860}
1861
1862
1863101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
1864"sb r<RT>, <OFFSET>(r<BASE>)"
1865*mipsI,mipsII,mipsIII,mipsIV:
1866*vr4100:
1867*vr5000:
1868*r3900:
1869{
1870 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1871}
1872
1873
1874111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
1875"sc r<RT>, <OFFSET>(r<BASE>)"
1876*mipsII:
1877*mipsIII:
1878*mipsIV:
1879*vr4100:
1880*vr5000:
1881{
1882 unsigned32 instruction = instruction_0;
1883 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1884 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
1885 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1886 {
1887 address_word vaddr = ((unsigned64)op1 + offset);
1888 address_word paddr;
1889 int uncached;
1890 if ((vaddr & 3) != 0)
1891 {
1892 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
1893 }
1894 else
1895 {
1896 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
1897 {
1898 unsigned64 memval = 0;
1899 unsigned64 memval1 = 0;
1900 unsigned64 mask = 0x7;
1901 unsigned int byte;
1902 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
1903 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
1904 memval = ((unsigned64) op2 << (8 * byte));
1905 if (LLBIT)
1906 {
1907 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
1908 }
1909 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
1910 }
1911 }
1912 }
1913}
1914
1915
1916111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
1917"scd r<RT>, <OFFSET>(r<BASE>)"
1918*mipsIII:
1919*mipsIV:
1920*vr4100:
1921*vr5000:
1922{
1923 unsigned32 instruction = instruction_0;
1924 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1925 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
1926 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1927 {
1928 address_word vaddr = ((unsigned64)op1 + offset);
1929 address_word paddr;
1930 int uncached;
1931 if ((vaddr & 7) != 0)
1932 {
1933 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
1934 }
1935 else
1936 {
1937 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
1938 {
1939 unsigned64 memval = 0;
1940 unsigned64 memval1 = 0;
1941 memval = op2;
1942 if (LLBIT)
1943 {
1944 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
1945 }
1946 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
1947 }
1948 }
1949 }
1950}
1951
1952
1953111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
1954"sd r<RT>, <OFFSET>(r<BASE>)"
1955*mipsIII:
1956*mipsIV:
1957*vr4100:
1958*vr5000:
1959{
1960 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1961}
1962
1963
19641111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
1965"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1966*mipsII:
1967*mipsIII:
1968*mipsIV:
1969*vr4100:
1970*vr5000:
1971{
1972 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
1973}
1974
1975
1976101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
1977"sdl r<RT>, <OFFSET>(r<BASE>)"
1978*mipsIII:
1979*mipsIV:
1980*vr4100:
1981*vr5000:
1982{
1983 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1984}
1985
1986
1987101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
1988"sdr r<RT>, <OFFSET>(r<BASE>)"
1989*mipsIII:
1990*mipsIV:
1991*vr4100:
1992*vr5000:
1993{
1994 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1995}
1996
1997
1998101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
1999"sh r<RT>, <OFFSET>(r<BASE>)"
2000*mipsI,mipsII,mipsIII,mipsIV:
2001*vr4100:
2002*vr5000:
2003*r3900:
2004{
2005 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2006}
2007
2008
2009:function:::void:do_sll:int rt, int rd, int shift
2010{
2011 unsigned32 temp = (GPR[rt] << shift);
2012 TRACE_ALU_INPUT2 (GPR[rt], shift);
2013 GPR[rd] = EXTEND32 (temp);
2014 TRACE_ALU_RESULT (GPR[rd]);
2015}
2016
201700000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2018"sll r<RD>, r<RT>, <SHIFT>"
2019*mipsI,mipsII,mipsIII,mipsIV:
2020*vr4100:
2021*vr5000:
2022*r3900:
2023{
2024 do_sll (SD_, RT, RD, SHIFT);
2025}
2026
2027
2028:function:::void:do_sllv:int rs, int rt, int rd
2029{
2030 int s = MASKED (GPR[rs], 4, 0);
2031 unsigned32 temp = (GPR[rt] << s);
2032 TRACE_ALU_INPUT2 (GPR[rt], s);
2033 GPR[rd] = EXTEND32 (temp);
2034 TRACE_ALU_RESULT (GPR[rd]);
2035}
2036
2037000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2038"sllv r<RD>, r<RT>, r<RS>"
2039*mipsI,mipsII,mipsIII,mipsIV:
2040*vr4100:
2041*vr5000:
2042*r3900:
2043{
2044 do_sllv (SD_, RS, RT, RD);
2045}
2046
2047
2048:function:::void:do_slt:int rs, int rt, int rd
2049{
2050 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2051 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2052 TRACE_ALU_RESULT (GPR[rd]);
2053}
2054
2055000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2056"slt r<RD>, r<RS>, r<RT>"
2057*mipsI,mipsII,mipsIII,mipsIV:
2058*vr4100:
2059*vr5000:
2060*r3900:
2061{
2062 do_slt (SD_, RS, RT, RD);
2063}
2064
2065
2066:function:::void:do_slti:int rs, int rt, unsigned16 immediate
2067{
2068 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2069 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2070 TRACE_ALU_RESULT (GPR[rt]);
2071}
2072
2073001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2074"slti r<RT>, r<RS>, <IMMEDIATE>"
2075*mipsI,mipsII,mipsIII,mipsIV:
2076*vr4100:
2077*vr5000:
2078*r3900:
2079{
2080 do_slti (SD_, RS, RT, IMMEDIATE);
2081}
2082
2083
2084:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2085{
2086 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2087 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2088 TRACE_ALU_RESULT (GPR[rt]);
2089}
2090
2091001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2092"sltiu r<RT>, r<RS>, <IMMEDIATE>"
2093*mipsI,mipsII,mipsIII,mipsIV:
2094*vr4100:
2095*vr5000:
2096*r3900:
2097{
2098 do_sltiu (SD_, RS, RT, IMMEDIATE);
2099}
2100
2101
2102
2103:function:::void:do_sltu:int rs, int rt, int rd
2104{
2105 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2106 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2107 TRACE_ALU_RESULT (GPR[rd]);
2108}
2109
2110000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2111"sltu r<RD>, r<RS>, r<RT>"
2112*mipsI,mipsII,mipsIII,mipsIV:
2113*vr4100:
2114*vr5000:
2115*r3900:
2116{
2117 do_sltu (SD_, RS, RT, RD);
2118}
2119
2120
2121:function:::void:do_sra:int rt, int rd, int shift
2122{
2123 signed32 temp = (signed32) GPR[rt] >> shift;
2124 TRACE_ALU_INPUT2 (GPR[rt], shift);
2125 GPR[rd] = EXTEND32 (temp);
2126 TRACE_ALU_RESULT (GPR[rd]);
2127}
2128
2129000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2130"sra r<RD>, r<RT>, <SHIFT>"
2131*mipsI,mipsII,mipsIII,mipsIV:
2132*vr4100:
2133*vr5000:
2134*r3900:
2135{
2136 do_sra (SD_, RT, RD, SHIFT);
2137}
2138
2139
2140
2141:function:::void:do_srav:int rs, int rt, int rd
2142{
2143 int s = MASKED (GPR[rs], 4, 0);
2144 signed32 temp = (signed32) GPR[rt] >> s;
2145 TRACE_ALU_INPUT2 (GPR[rt], s);
2146 GPR[rd] = EXTEND32 (temp);
2147 TRACE_ALU_RESULT (GPR[rd]);
2148}
2149
2150000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2151"srav r<RD>, r<RT>, r<RS>"
2152*mipsI,mipsII,mipsIII,mipsIV:
2153*vr4100:
2154*vr5000:
2155*r3900:
2156{
2157 do_srav (SD_, RS, RT, RD);
2158}
2159
2160
2161
2162:function:::void:do_srl:int rt, int rd, int shift
2163{
2164 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2165 TRACE_ALU_INPUT2 (GPR[rt], shift);
2166 GPR[rd] = EXTEND32 (temp);
2167 TRACE_ALU_RESULT (GPR[rd]);
2168}
2169
2170000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2171"srl r<RD>, r<RT>, <SHIFT>"
2172*mipsI,mipsII,mipsIII,mipsIV:
2173*vr4100:
2174*vr5000:
2175*r3900:
2176{
2177 do_srl (SD_, RT, RD, SHIFT);
2178}
2179
2180
2181:function:::void:do_srlv:int rs, int rt, int rd
2182{
2183 int s = MASKED (GPR[rs], 4, 0);
2184 unsigned32 temp = (unsigned32) GPR[rt] >> s;
2185 TRACE_ALU_INPUT2 (GPR[rt], s);
2186 GPR[rd] = EXTEND32 (temp);
2187 TRACE_ALU_RESULT (GPR[rd]);
2188}
2189
2190000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2191"srlv r<RD>, r<RT>, r<RS>"
2192*mipsI,mipsII,mipsIII,mipsIV:
2193*vr4100:
2194*vr5000:
2195*r3900:
2196{
2197 do_srlv (SD_, RS, RT, RD);
2198}
2199
2200
2201000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2202"sub r<RD>, r<RS>, r<RT>"
2203*mipsI,mipsII,mipsIII,mipsIV:
2204*vr4100:
2205*vr5000:
2206*r3900:
2207{
2208 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2209 {
2210 ALU32_BEGIN (GPR[RS]);
2211 ALU32_SUB (GPR[RT]);
2212 ALU32_END (GPR[RD]);
2213 }
2214 TRACE_ALU_RESULT (GPR[RD]);
2215}
2216
2217
2218:function:::void:do_subu:int rs, int rt, int rd
2219{
2220 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2221 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2222 TRACE_ALU_RESULT (GPR[rd]);
2223}
2224
2225000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2226"subu r<RD>, r<RS>, r<RT>"
2227*mipsI,mipsII,mipsIII,mipsIV:
2228*vr4100:
2229*vr5000:
2230*r3900:
2231{
2232 do_subu (SD_, RS, RT, RD);
2233}
2234
2235
2236101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2237"sw r<RT>, <OFFSET>(r<BASE>)"
2238*mipsI,mipsII,mipsIII,mipsIV:
2239*vr4100:
2240*r3900:
2241*vr5000:
2242{
2243 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2244}
2245
2246
22471110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2248"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2249*mipsI,mipsII,mipsIII,mipsIV:
2250*vr4100:
2251*vr5000:
2252*r3900:
2253{
2254 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
2255}
2256
2257
2258
2259:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2260{
2261 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2262 address_word reverseendian = (ReverseEndian ? -1 : 0);
2263 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2264 unsigned int byte;
2265 unsigned int word;
2266 address_word paddr;
2267 int uncached;
2268 unsigned64 memval;
2269 address_word vaddr;
2270 int nr_lhs_bits;
2271 int nr_rhs_bits;
2272
2273 vaddr = base + offset;
2274 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2275 paddr = (paddr ^ (reverseendian & mask));
2276 if (BigEndianMem == 0)
2277 paddr = paddr & ~access;
2278
2279 /* compute where within the word/mem we are */
2280 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2281 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2282 nr_lhs_bits = 8 * byte + 8;
2283 nr_rhs_bits = 8 * access - 8 * byte;
2284 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2285 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2286 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2287 (long) ((unsigned64) paddr >> 32), (long) paddr,
2288 word, byte, nr_lhs_bits, nr_rhs_bits); */
2289
2290 if (word == 0)
2291 {
2292 memval = (rt >> nr_rhs_bits);
2293 }
2294 else
2295 {
2296 memval = (rt << nr_lhs_bits);
2297 }
2298 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2299 (long) ((unsigned64) rt >> 32), (long) rt,
2300 (long) ((unsigned64) memval >> 32), (long) memval); */
2301 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2302}
2303
2304
2305101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2306"swl r<RT>, <OFFSET>(r<BASE>)"
2307*mipsI,mipsII,mipsIII,mipsIV:
2308*vr4100:
2309*vr5000:
2310*r3900:
2311{
2312 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2313}
2314
2315
2316:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2317{
2318 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2319 address_word reverseendian = (ReverseEndian ? -1 : 0);
2320 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2321 unsigned int byte;
2322 address_word paddr;
2323 int uncached;
2324 unsigned64 memval;
2325 address_word vaddr;
2326
2327 vaddr = base + offset;
2328 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2329 paddr = (paddr ^ (reverseendian & mask));
2330 if (BigEndianMem != 0)
2331 paddr &= ~access;
2332 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2333 memval = (rt << (byte * 8));
2334 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2335}
2336
2337101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2338"swr r<RT>, <OFFSET>(r<BASE>)"
2339*mipsI,mipsII,mipsIII,mipsIV:
2340*vr4100:
2341*vr5000:
2342*r3900:
2343{
2344 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2345}
2346
2347
2348000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
2349"sync":STYPE == 0
2350"sync <STYPE>"
2351*mipsII:
2352*mipsIII:
2353*mipsIV:
2354*vr4100:
2355*vr5000:
2356*r3900:
2357{
2358 SyncOperation (STYPE);
2359}
2360
2361
2362000000,20.CODE,001100:SPECIAL:32::SYSCALL
2363"syscall <CODE>"
2364*mipsI,mipsII,mipsIII,mipsIV:
2365*vr4100:
2366*vr5000:
2367*r3900:
2368{
2369 SignalException(SystemCall, instruction_0);
2370}
2371
2372
2373000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2374"teq r<RS>, r<RT>"
2375*mipsII:
2376*mipsIII:
2377*mipsIV:
2378*vr4100:
2379*vr5000:
2380{
2381 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
2382 SignalException(Trap, instruction_0);
2383}
2384
2385
2386000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2387"teqi r<RS>, <IMMEDIATE>"
2388*mipsII:
2389*mipsIII:
2390*mipsIV:
2391*vr4100:
2392*vr5000:
2393{
2394 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
2395 SignalException(Trap, instruction_0);
2396}
2397
2398
2399000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2400"tge r<RS>, r<RT>"
2401*mipsII:
2402*mipsIII:
2403*mipsIV:
2404*vr4100:
2405*vr5000:
2406{
2407 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
2408 SignalException(Trap, instruction_0);
2409}
2410
2411
2412000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2413"tgei r<RS>, <IMMEDIATE>"
2414*mipsII:
2415*mipsIII:
2416*mipsIV:
2417*vr4100:
2418*vr5000:
2419{
2420 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
2421 SignalException(Trap, instruction_0);
2422}
2423
2424
2425000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2426"tgeiu r<RS>, <IMMEDIATE>"
2427*mipsII:
2428*mipsIII:
2429*mipsIV:
2430*vr4100:
2431*vr5000:
2432{
2433 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2434 SignalException(Trap, instruction_0);
2435}
2436
2437
2438000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2439"tgeu r<RS>, r<RT>"
2440*mipsII:
2441*mipsIII:
2442*mipsIV:
2443*vr4100:
2444*vr5000:
2445{
2446 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2447 SignalException(Trap, instruction_0);
2448}
2449
2450
2451000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2452"tlt r<RS>, r<RT>"
2453*mipsII:
2454*mipsIII:
2455*mipsIV:
2456*vr4100:
2457*vr5000:
2458{
2459 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
2460 SignalException(Trap, instruction_0);
2461}
2462
2463
2464000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2465"tlti r<RS>, <IMMEDIATE>"
2466*mipsII:
2467*mipsIII:
2468*mipsIV:
2469*vr4100:
2470*vr5000:
2471{
2472 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
2473 SignalException(Trap, instruction_0);
2474}
2475
2476
2477000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2478"tltiu r<RS>, <IMMEDIATE>"
2479*mipsII:
2480*mipsIII:
2481*mipsIV:
2482*vr4100:
2483*vr5000:
2484{
2485 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2486 SignalException(Trap, instruction_0);
2487}
2488
2489
2490000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2491"tltu r<RS>, r<RT>"
2492*mipsII:
2493*mipsIII:
2494*mipsIV:
2495*vr4100:
2496*vr5000:
2497{
2498 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2499 SignalException(Trap, instruction_0);
2500}
2501
2502
2503000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2504"tne r<RS>, r<RT>"
2505*mipsII:
2506*mipsIII:
2507*mipsIV:
2508*vr4100:
2509*vr5000:
2510{
2511 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2512 SignalException(Trap, instruction_0);
2513}
2514
2515
2516000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
2517"tne r<RS>, <IMMEDIATE>"
2518*mipsII:
2519*mipsIII:
2520*mipsIV:
2521*vr4100:
2522*vr5000:
2523{
2524 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
2525 SignalException(Trap, instruction_0);
2526}
2527
2528
2529:function:::void:do_xor:int rs, int rt, int rd
2530{
2531 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2532 GPR[rd] = GPR[rs] ^ GPR[rt];
2533 TRACE_ALU_RESULT (GPR[rd]);
2534}
2535
2536000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
2537"xor r<RD>, r<RS>, r<RT>"
2538*mipsI,mipsII,mipsIII,mipsIV:
2539*vr4100:
2540*vr5000:
2541*r3900:
2542{
2543 do_xor (SD_, RS, RT, RD);
2544}
2545
2546
2547:function:::void:do_xori:int rs, int rt, unsigned16 immediate
2548{
2549 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2550 GPR[rt] = GPR[rs] ^ immediate;
2551 TRACE_ALU_RESULT (GPR[rt]);
2552}
2553
2554001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
2555"xori r<RT>, r<RS>, <IMMEDIATE>"
2556*mipsI,mipsII,mipsIII,mipsIV:
2557*vr4100:
2558*vr5000:
2559*r3900:
2560{
2561 do_xori (SD_, RS, RT, IMMEDIATE);
2562}
2563
2564\f
2565//
2566// MIPS Architecture:
2567//
2568// FPU Instruction Set (COP1 & COP1X)
2569//
2570
2571
2572:%s::::FMT:int fmt
2573{
2574 switch (fmt)
2575 {
2576 case fmt_single: return "s";
2577 case fmt_double: return "d";
2578 case fmt_word: return "w";
2579 case fmt_long: return "l";
2580 default: return "?";
2581 }
2582}
2583
2584:%s::::X:int x
2585{
2586 switch (x)
2587 {
2588 case 0: return "f";
2589 case 1: return "t";
2590 default: return "?";
2591 }
2592}
2593
2594:%s::::TF:int tf
2595{
2596 if (tf)
2597 return "t";
2598 else
2599 return "f";
2600}
2601
2602:%s::::ND:int nd
2603{
2604 if (nd)
2605 return "l";
2606 else
2607 return "";
2608}
2609
2610:%s::::COND:int cond
2611{
2612 switch (cond)
2613 {
2614 case 00: return "f";
2615 case 01: return "un";
2616 case 02: return "eq";
2617 case 03: return "ueq";
2618 case 04: return "olt";
2619 case 05: return "ult";
2620 case 06: return "ole";
2621 case 07: return "ule";
2622 case 010: return "sf";
2623 case 011: return "ngle";
2624 case 012: return "seq";
2625 case 013: return "ngl";
2626 case 014: return "lt";
2627 case 015: return "nge";
2628 case 016: return "le";
2629 case 017: return "ngt";
2630 default: return "?";
2631 }
2632}
2633
2634
2635010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
2636"abs.%s<FMT> f<FD>, f<FS>"
2637*mipsI,mipsII,mipsIII,mipsIV:
2638*vr4100:
2639*vr5000:
2640*r3900:
2641{
2642 unsigned32 instruction = instruction_0;
2643 int destreg = ((instruction >> 6) & 0x0000001F);
2644 int fs = ((instruction >> 11) & 0x0000001F);
2645 int format = ((instruction >> 21) & 0x00000007);
2646 {
2647 if ((format != fmt_single) && (format != fmt_double))
2648 SignalException(ReservedInstruction,instruction);
2649 else
2650 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
2651 }
2652}
2653
2654
2655
2656010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
2657"add.%s<FMT> f<FD>, f<FS>, f<FT>"
2658*mipsI,mipsII,mipsIII,mipsIV:
2659*vr4100:
2660*vr5000:
2661*r3900:
2662{
2663 unsigned32 instruction = instruction_0;
2664 int destreg = ((instruction >> 6) & 0x0000001F);
2665 int fs = ((instruction >> 11) & 0x0000001F);
2666 int ft = ((instruction >> 16) & 0x0000001F);
2667 int format = ((instruction >> 21) & 0x00000007);
2668 {
2669 if ((format != fmt_single) && (format != fmt_double))
2670 SignalException(ReservedInstruction, instruction);
2671 else
2672 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
2673 }
2674}
2675
2676
2677
2678// BC1F
2679// BC1FL
2680// BC1T
2681// BC1TL
2682
2683010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
2684"bc1%s<TF>%s<ND> <OFFSET>"
2685*mipsI,mipsII,mipsIII:
2686{
2687 check_branch_bug ();
2688 TRACE_BRANCH_INPUT (PREVCOC1());
2689 if (PREVCOC1() == TF)
2690 {
2691 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
2692 TRACE_BRANCH_RESULT (dest);
2693 mark_branch_bug (dest);
2694 DELAY_SLOT (dest);
2695 }
2696 else if (ND)
2697 {
2698 TRACE_BRANCH_RESULT (0);
2699 NULLIFY_NEXT_INSTRUCTION ();
2700 }
2701 else
2702 {
2703 TRACE_BRANCH_RESULT (NIA);
2704 }
2705}
2706
2707010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
2708"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
2709"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
2710*mipsIV:
2711*vr5000:
2712#*vr4100:
2713*r3900:
2714{
2715 check_branch_bug ();
2716 if (GETFCC(CC) == TF)
2717 {
2718 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
2719 mark_branch_bug (dest);
2720 DELAY_SLOT (dest);
2721 }
2722 else if (ND)
2723 {
2724 NULLIFY_NEXT_INSTRUCTION ();
2725 }
2726}
2727
2728
2729
2730
2731
2732
2733// C.EQ.S
2734// C.EQ.D
2735// ...
2736
2737:function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
2738{
2739 if ((fmt != fmt_single) && (fmt != fmt_double))
2740 SignalException (ReservedInstruction, insn);
2741 else
2742 {
2743 int less;
2744 int equal;
2745 int unordered;
2746 int condition;
2747 unsigned64 ofs = ValueFPR (fs, fmt);
2748 unsigned64 oft = ValueFPR (ft, fmt);
2749 if (NaN (ofs, fmt) || NaN (oft, fmt))
2750 {
2751 if (FCSR & FP_ENABLE (IO))
2752 {
2753 FCSR |= FP_CAUSE (IO);
2754 SignalExceptionFPE ();
2755 }
2756 less = 0;
2757 equal = 0;
2758 unordered = 1;
2759 }
2760 else
2761 {
2762 less = Less (ofs, oft, fmt);
2763 equal = Equal (ofs, oft, fmt);
2764 unordered = 0;
2765 }
2766 condition = (((cond & (1 << 2)) && less)
2767 || ((cond & (1 << 1)) && equal)
2768 || ((cond & (1 << 0)) && unordered));
2769 SETFCC (cc, condition);
2770 }
2771}
2772
2773010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
2774"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
2775*mipsI,mipsII,mipsIII:
2776{
2777 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
2778}
2779
2780010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
2781"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
2782"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
2783*mipsIV:
2784*vr4100:
2785*vr5000:
2786*r3900:
2787{
2788 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
2789}
2790
2791
2792010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
2793"ceil.l.%s<FMT> f<FD>, f<FS>"
2794*mipsIII:
2795*mipsIV:
2796*vr4100:
2797*vr5000:
2798*r3900:
2799{
2800 unsigned32 instruction = instruction_0;
2801 int destreg = ((instruction >> 6) & 0x0000001F);
2802 int fs = ((instruction >> 11) & 0x0000001F);
2803 int format = ((instruction >> 21) & 0x00000007);
2804 {
2805 if ((format != fmt_single) && (format != fmt_double))
2806 SignalException(ReservedInstruction,instruction);
2807 else
2808 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
2809 }
2810}
2811
2812
2813010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
2814*mipsII:
2815*mipsIII:
2816*mipsIV:
2817*vr4100:
2818*vr5000:
2819*r3900:
2820{
2821 unsigned32 instruction = instruction_0;
2822 int destreg = ((instruction >> 6) & 0x0000001F);
2823 int fs = ((instruction >> 11) & 0x0000001F);
2824 int format = ((instruction >> 21) & 0x00000007);
2825 {
2826 if ((format != fmt_single) && (format != fmt_double))
2827 SignalException(ReservedInstruction,instruction);
2828 else
2829 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
2830 }
2831}
2832
2833
2834// CFC1
2835// CTC1
2836010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
2837"c%s<X>c1 r<RT>, f<FS>"
2838*mipsI:
2839*mipsII:
2840*mipsIII:
2841{
2842 if (X)
2843 {
2844 if (FS == 0)
2845 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
2846 else if (FS == 31)
2847 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
2848 /* else NOP */
2849 PENDING_FILL(COCIDX,0); /* special case */
2850 }
2851 else
2852 { /* control from */
2853 if (FS == 0)
2854 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
2855 else if (FS == 31)
2856 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
2857 /* else NOP */
2858 }
2859}
2860010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
2861"c%s<X>c1 r<RT>, f<FS>"
2862*mipsIV:
2863*vr4100:
2864*vr5000:
2865*r3900:
2866{
2867 if (X)
2868 {
2869 /* control to */
2870 TRACE_ALU_INPUT1 (GPR[RT]);
2871 if (FS == 0)
2872 {
2873 FCR0 = VL4_8(GPR[RT]);
2874 TRACE_ALU_RESULT (FCR0);
2875 }
2876 else if (FS == 31)
2877 {
2878 FCR31 = VL4_8(GPR[RT]);
2879 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
2880 TRACE_ALU_RESULT (FCR31);
2881 }
2882 else
2883 {
2884 TRACE_ALU_RESULT0 ();
2885 }
2886 /* else NOP */
2887 }
2888 else
2889 { /* control from */
2890 if (FS == 0)
2891 {
2892 TRACE_ALU_INPUT1 (FCR0);
2893 GPR[RT] = SIGNEXTEND (FCR0, 32);
2894 }
2895 else if (FS == 31)
2896 {
2897 TRACE_ALU_INPUT1 (FCR31);
2898 GPR[RT] = SIGNEXTEND (FCR31, 32);
2899 }
2900 TRACE_ALU_RESULT (GPR[RT]);
2901 /* else NOP */
2902 }
2903}
2904
2905
2906//
2907// FIXME: Does not correctly differentiate between mips*
2908//
2909010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
2910"cvt.d.%s<FMT> f<FD>, f<FS>"
2911*mipsI,mipsII,mipsIII,mipsIV:
2912*vr4100:
2913*vr5000:
2914*r3900:
2915{
2916 unsigned32 instruction = instruction_0;
2917 int destreg = ((instruction >> 6) & 0x0000001F);
2918 int fs = ((instruction >> 11) & 0x0000001F);
2919 int format = ((instruction >> 21) & 0x00000007);
2920 {
2921 if ((format == fmt_double) | 0)
2922 SignalException(ReservedInstruction,instruction);
2923 else
2924 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
2925 }
2926}
2927
2928
2929010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
2930"cvt.l.%s<FMT> f<FD>, f<FS>"
2931*mipsIII:
2932*mipsIV:
2933*vr4100:
2934*vr5000:
2935*r3900:
2936{
2937 unsigned32 instruction = instruction_0;
2938 int destreg = ((instruction >> 6) & 0x0000001F);
2939 int fs = ((instruction >> 11) & 0x0000001F);
2940 int format = ((instruction >> 21) & 0x00000007);
2941 {
2942 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
2943 SignalException(ReservedInstruction,instruction);
2944 else
2945 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
2946 }
2947}
2948
2949
2950//
2951// FIXME: Does not correctly differentiate between mips*
2952//
2953010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
2954"cvt.s.%s<FMT> f<FD>, f<FS>"
2955*mipsI,mipsII,mipsIII,mipsIV:
2956*vr4100:
2957*vr5000:
2958*r3900:
2959{
2960 unsigned32 instruction = instruction_0;
2961 int destreg = ((instruction >> 6) & 0x0000001F);
2962 int fs = ((instruction >> 11) & 0x0000001F);
2963 int format = ((instruction >> 21) & 0x00000007);
2964 {
2965 if ((format == fmt_single) | 0)
2966 SignalException(ReservedInstruction,instruction);
2967 else
2968 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
2969 }
2970}
2971
2972
2973010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
2974"cvt.w.%s<FMT> f<FD>, f<FS>"
2975*mipsI,mipsII,mipsIII,mipsIV:
2976*vr4100:
2977*vr5000:
2978*r3900:
2979{
2980 unsigned32 instruction = instruction_0;
2981 int destreg = ((instruction >> 6) & 0x0000001F);
2982 int fs = ((instruction >> 11) & 0x0000001F);
2983 int format = ((instruction >> 21) & 0x00000007);
2984 {
2985 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
2986 SignalException(ReservedInstruction,instruction);
2987 else
2988 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
2989 }
2990}
2991
2992
2993010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
2994"div.%s<FMT> f<FD>, f<FS>, f<FT>"
2995*mipsI,mipsII,mipsIII,mipsIV:
2996*vr4100:
2997*vr5000:
2998*r3900:
2999{
3000 unsigned32 instruction = instruction_0;
3001 int destreg = ((instruction >> 6) & 0x0000001F);
3002 int fs = ((instruction >> 11) & 0x0000001F);
3003 int ft = ((instruction >> 16) & 0x0000001F);
3004 int format = ((instruction >> 21) & 0x00000007);
3005 {
3006 if ((format != fmt_single) && (format != fmt_double))
3007 SignalException(ReservedInstruction,instruction);
3008 else
3009 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3010 }
3011}
3012
3013
3014// DMFC1
3015// DMTC1
3016010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1
3017"dm%s<X>c1 r<RT>, f<FS>"
3018*mipsIII:
3019{
3020 if (X)
3021 {
3022 if (SizeFGR() == 64)
3023 PENDING_FILL((FS + FGRIDX),GPR[RT]);
3024 else if ((FS & 0x1) == 0)
3025 {
3026 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3027 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3028 }
3029 }
3030 else
3031 {
3032 if (SizeFGR() == 64)
3033 PENDING_FILL(RT,FGR[FS]);
3034 else if ((FS & 0x1) == 0)
3035 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3036 else
3037 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3038 }
3039}
3040010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
3041"dm%s<X>c1 r<RT>, f<FS>"
3042*mipsIV:
3043*vr4100:
3044*vr5000:
3045*r3900:
3046{
3047 if (X)
3048 {
3049 if (SizeFGR() == 64)
3050 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
3051 else if ((FS & 0x1) == 0)
3052 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
3053 }
3054 else
3055 {
3056 if (SizeFGR() == 64)
3057 GPR[RT] = FGR[FS];
3058 else if ((FS & 0x1) == 0)
3059 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
3060 else
3061 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
3062 }
3063}
3064
3065
3066010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
3067"floor.l.%s<FMT> f<FD>, f<FS>"
3068*mipsIII:
3069*mipsIV:
3070*vr4100:
3071*vr5000:
3072*r3900:
3073{
3074 unsigned32 instruction = instruction_0;
3075 int destreg = ((instruction >> 6) & 0x0000001F);
3076 int fs = ((instruction >> 11) & 0x0000001F);
3077 int format = ((instruction >> 21) & 0x00000007);
3078 {
3079 if ((format != fmt_single) && (format != fmt_double))
3080 SignalException(ReservedInstruction,instruction);
3081 else
3082 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3083 }
3084}
3085
3086
3087010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
3088"floor.w.%s<FMT> f<FD>, f<FS>"
3089*mipsII:
3090*mipsIII:
3091*mipsIV:
3092*vr4100:
3093*vr5000:
3094*r3900:
3095{
3096 unsigned32 instruction = instruction_0;
3097 int destreg = ((instruction >> 6) & 0x0000001F);
3098 int fs = ((instruction >> 11) & 0x0000001F);
3099 int format = ((instruction >> 21) & 0x00000007);
3100 {
3101 if ((format != fmt_single) && (format != fmt_double))
3102 SignalException(ReservedInstruction,instruction);
3103 else
3104 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3105 }
3106}
3107
3108
3109110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
3110"ldc1 f<FT>, <OFFSET>(r<BASE>)"
3111*mipsII:
3112*mipsIII:
3113*mipsIV:
3114*vr4100:
3115*vr5000:
3116*r3900:
3117{
3118 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3119}
3120
3121
3122010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
3123"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3124*mipsIV:
3125*vr5000:
3126{
3127 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3128}
3129
3130
3131
3132110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
3133"lwc1 f<FT>, <OFFSET>(r<BASE>)"
3134*mipsI,mipsII,mipsIII,mipsIV:
3135*vr4100:
3136*vr5000:
3137*r3900:
3138{
3139 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
3140}
3141
3142
3143010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
3144"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3145*mipsIV:
3146*vr5000:
3147{
3148 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
3149}
3150
3151
3152
3153//
3154// FIXME: Not correct for mips*
3155//
3156010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
3157"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3158*mipsIV:
3159*vr5000:
3160{
3161 unsigned32 instruction = instruction_0;
3162 int destreg = ((instruction >> 6) & 0x0000001F);
3163 int fs = ((instruction >> 11) & 0x0000001F);
3164 int ft = ((instruction >> 16) & 0x0000001F);
3165 int fr = ((instruction >> 21) & 0x0000001F);
3166 {
3167 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3168 }
3169}
3170
3171
3172010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
3173"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3174*mipsIV:
3175*vr5000:
3176{
3177 unsigned32 instruction = instruction_0;
3178 int destreg = ((instruction >> 6) & 0x0000001F);
3179 int fs = ((instruction >> 11) & 0x0000001F);
3180 int ft = ((instruction >> 16) & 0x0000001F);
3181 int fr = ((instruction >> 21) & 0x0000001F);
3182 {
3183 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3184 }
3185}
3186
3187
3188// MFC1
3189// MTC1
3190010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
3191"m%s<X>c1 r<RT>, f<FS>"
3192*mipsI:
3193*mipsII:
3194*mipsIII:
3195{
3196 if (X)
3197 { /*MTC1*/
3198 if (SizeFGR() == 64)
3199 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
3200 else
3201 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
3202 }
3203 else /*MFC1*/
3204 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
3205}
3206010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
3207"m%s<X>c1 r<RT>, f<FS>"
3208*mipsIV:
3209*vr4100:
3210*vr5000:
3211*r3900:
3212{
3213 int fs = FS;
3214 if (X)
3215 /*MTC1*/
3216 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
3217 else /*MFC1*/
3218 GPR[RT] = SIGNEXTEND(FGR[FS],32);
3219}
3220
3221
3222010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
3223"mov.%s<FMT> f<FD>, f<FS>"
3224*mipsI,mipsII,mipsIII,mipsIV:
3225*vr4100:
3226*vr5000:
3227*r3900:
3228{
3229 unsigned32 instruction = instruction_0;
3230 int destreg = ((instruction >> 6) & 0x0000001F);
3231 int fs = ((instruction >> 11) & 0x0000001F);
3232 int format = ((instruction >> 21) & 0x00000007);
3233 {
3234 StoreFPR(destreg,format,ValueFPR(fs,format));
3235 }
3236}
3237
3238
3239// MOVF
3240000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
3241"mov%s<TF> r<RD>, r<RS>, <CC>"
3242*mipsIV:
3243*vr5000:
3244{
3245 if (GETFCC(CC) == TF)
3246 GPR[RD] = GPR[RS];
3247}
3248
3249
3250// MOVF.fmt
3251010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
3252"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
3253*mipsIV:
3254*vr5000:
3255{
3256 unsigned32 instruction = instruction_0;
3257 int format = ((instruction >> 21) & 0x00000007);
3258 {
3259 if (GETFCC(CC) == TF)
3260 StoreFPR (FD, format, ValueFPR (FS, format));
3261 else
3262 StoreFPR (FD, format, ValueFPR (FD, format));
3263 }
3264}
3265
3266
3267010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
3268*mipsIV:
3269*vr5000:
3270{
3271 unsigned32 instruction = instruction_0;
3272 int destreg = ((instruction >> 6) & 0x0000001F);
3273 int fs = ((instruction >> 11) & 0x0000001F);
3274 int format = ((instruction >> 21) & 0x00000007);
3275 {
3276 StoreFPR(destreg,format,ValueFPR(fs,format));
3277 }
3278}
3279
3280
3281// MOVT see MOVtf
3282
3283
3284// MOVT.fmt see MOVtf.fmt
3285
3286
3287
3288010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
3289"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3290*mipsIV:
3291*vr5000:
3292{
3293 unsigned32 instruction = instruction_0;
3294 int destreg = ((instruction >> 6) & 0x0000001F);
3295 int fs = ((instruction >> 11) & 0x0000001F);
3296 int format = ((instruction >> 21) & 0x00000007);
3297 {
3298 StoreFPR(destreg,format,ValueFPR(fs,format));
3299 }
3300}
3301
3302
3303// MSUB.fmt
3304010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
3305"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3306*mipsIV:
3307*vr5000:
3308{
3309 unsigned32 instruction = instruction_0;
3310 int destreg = ((instruction >> 6) & 0x0000001F);
3311 int fs = ((instruction >> 11) & 0x0000001F);
3312 int ft = ((instruction >> 16) & 0x0000001F);
3313 int fr = ((instruction >> 21) & 0x0000001F);
3314 {
3315 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3316 }
3317}
3318
3319
3320// MSUB.fmt
3321010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
3322"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3323*mipsIV:
3324*vr5000:
3325{
3326 unsigned32 instruction = instruction_0;
3327 int destreg = ((instruction >> 6) & 0x0000001F);
3328 int fs = ((instruction >> 11) & 0x0000001F);
3329 int ft = ((instruction >> 16) & 0x0000001F);
3330 int fr = ((instruction >> 21) & 0x0000001F);
3331 {
3332 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3333 }
3334}
3335
3336
3337// MTC1 see MxC1
3338
3339
3340010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
3341"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
3342*mipsI,mipsII,mipsIII,mipsIV:
3343*vr4100:
3344*vr5000:
3345*r3900:
3346{
3347 unsigned32 instruction = instruction_0;
3348 int destreg = ((instruction >> 6) & 0x0000001F);
3349 int fs = ((instruction >> 11) & 0x0000001F);
3350 int ft = ((instruction >> 16) & 0x0000001F);
3351 int format = ((instruction >> 21) & 0x00000007);
3352 {
3353 if ((format != fmt_single) && (format != fmt_double))
3354 SignalException(ReservedInstruction,instruction);
3355 else
3356 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
3357 }
3358}
3359
3360
3361010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
3362"neg.%s<FMT> f<FD>, f<FS>"
3363*mipsI,mipsII,mipsIII,mipsIV:
3364*vr4100:
3365*vr5000:
3366*r3900:
3367{
3368 unsigned32 instruction = instruction_0;
3369 int destreg = ((instruction >> 6) & 0x0000001F);
3370 int fs = ((instruction >> 11) & 0x0000001F);
3371 int format = ((instruction >> 21) & 0x00000007);
3372 {
3373 if ((format != fmt_single) && (format != fmt_double))
3374 SignalException(ReservedInstruction,instruction);
3375 else
3376 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
3377 }
3378}
3379
3380
3381// NMADD.fmt
3382010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
3383"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3384*mipsIV:
3385*vr5000:
3386{
3387 unsigned32 instruction = instruction_0;
3388 int destreg = ((instruction >> 6) & 0x0000001F);
3389 int fs = ((instruction >> 11) & 0x0000001F);
3390 int ft = ((instruction >> 16) & 0x0000001F);
3391 int fr = ((instruction >> 21) & 0x0000001F);
3392 {
3393 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3394 }
3395}
3396
3397
3398// NMADD.fmt
3399010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
3400"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3401*mipsIV:
3402*vr5000:
3403{
3404 unsigned32 instruction = instruction_0;
3405 int destreg = ((instruction >> 6) & 0x0000001F);
3406 int fs = ((instruction >> 11) & 0x0000001F);
3407 int ft = ((instruction >> 16) & 0x0000001F);
3408 int fr = ((instruction >> 21) & 0x0000001F);
3409 {
3410 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3411 }
3412}
3413
3414
3415// NMSUB.fmt
3416010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
3417"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3418*mipsIV:
3419*vr5000:
3420{
3421 unsigned32 instruction = instruction_0;
3422 int destreg = ((instruction >> 6) & 0x0000001F);
3423 int fs = ((instruction >> 11) & 0x0000001F);
3424 int ft = ((instruction >> 16) & 0x0000001F);
3425 int fr = ((instruction >> 21) & 0x0000001F);
3426 {
3427 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3428 }
3429}
3430
3431
3432// NMSUB.fmt
3433010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
3434"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
3435*mipsIV:
3436*vr5000:
3437{
3438 unsigned32 instruction = instruction_0;
3439 int destreg = ((instruction >> 6) & 0x0000001F);
3440 int fs = ((instruction >> 11) & 0x0000001F);
3441 int ft = ((instruction >> 16) & 0x0000001F);
3442 int fr = ((instruction >> 21) & 0x0000001F);
3443 {
3444 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3445 }
3446}
3447
3448
3449010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
3450"prefx <HINT>, r<INDEX>(r<BASE>)"
3451*mipsIV:
3452*vr5000:
3453{
3454 unsigned32 instruction = instruction_0;
3455 int fs = ((instruction >> 11) & 0x0000001F);
3456 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3457 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3458 {
3459 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
3460 address_word paddr;
3461 int uncached;
3462 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3463 Prefetch(uncached,paddr,vaddr,isDATA,fs);
3464 }
3465}
3466
3467010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
3468*mipsIV:
3469"recip.%s<FMT> f<FD>, f<FS>"
3470*vr5000:
3471{
3472 unsigned32 instruction = instruction_0;
3473 int destreg = ((instruction >> 6) & 0x0000001F);
3474 int fs = ((instruction >> 11) & 0x0000001F);
3475 int format = ((instruction >> 21) & 0x00000007);
3476 {
3477 if ((format != fmt_single) && (format != fmt_double))
3478 SignalException(ReservedInstruction,instruction);
3479 else
3480 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
3481 }
3482}
3483
3484
3485010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
3486"round.l.%s<FMT> f<FD>, f<FS>"
3487*mipsIII:
3488*mipsIV:
3489*vr4100:
3490*vr5000:
3491*r3900:
3492{
3493 unsigned32 instruction = instruction_0;
3494 int destreg = ((instruction >> 6) & 0x0000001F);
3495 int fs = ((instruction >> 11) & 0x0000001F);
3496 int format = ((instruction >> 21) & 0x00000007);
3497 {
3498 if ((format != fmt_single) && (format != fmt_double))
3499 SignalException(ReservedInstruction,instruction);
3500 else
3501 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
3502 }
3503}
3504
3505
3506010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
3507"round.w.%s<FMT> f<FD>, f<FS>"
3508*mipsII:
3509*mipsIII:
3510*mipsIV:
3511*vr4100:
3512*vr5000:
3513*r3900:
3514{
3515 unsigned32 instruction = instruction_0;
3516 int destreg = ((instruction >> 6) & 0x0000001F);
3517 int fs = ((instruction >> 11) & 0x0000001F);
3518 int format = ((instruction >> 21) & 0x00000007);
3519 {
3520 if ((format != fmt_single) && (format != fmt_double))
3521 SignalException(ReservedInstruction,instruction);
3522 else
3523 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
3524 }
3525}
3526
3527
3528010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
3529*mipsIV:
3530"rsqrt.%s<FMT> f<FD>, f<FS>"
3531*vr5000:
3532{
3533 unsigned32 instruction = instruction_0;
3534 int destreg = ((instruction >> 6) & 0x0000001F);
3535 int fs = ((instruction >> 11) & 0x0000001F);
3536 int format = ((instruction >> 21) & 0x00000007);
3537 {
3538 if ((format != fmt_single) && (format != fmt_double))
3539 SignalException(ReservedInstruction,instruction);
3540 else
3541 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
3542 }
3543}
3544
3545
3546111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
3547"sdc1 f<FT>, <OFFSET>(r<BASE>)"
3548*mipsII:
3549*mipsIII:
3550*mipsIV:
3551*vr4100:
3552*vr5000:
3553*r3900:
3554{
3555 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
3556}
3557
3558
3559010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
3560"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
3561*mipsIV:
3562*vr5000:
3563{
3564 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
3565}
3566
3567
3568010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
3569"sqrt.%s<FMT> f<FD>, f<FS>"
3570*mipsII:
3571*mipsIII:
3572*mipsIV:
3573*vr4100:
3574*vr5000:
3575*r3900:
3576{
3577 unsigned32 instruction = instruction_0;
3578 int destreg = ((instruction >> 6) & 0x0000001F);
3579 int fs = ((instruction >> 11) & 0x0000001F);
3580 int format = ((instruction >> 21) & 0x00000007);
3581 {
3582 if ((format != fmt_single) && (format != fmt_double))
3583 SignalException(ReservedInstruction,instruction);
3584 else
3585 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
3586 }
3587}
3588
3589
3590010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
3591"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
3592*mipsI,mipsII,mipsIII,mipsIV:
3593*vr4100:
3594*vr5000:
3595*r3900:
3596{
3597 unsigned32 instruction = instruction_0;
3598 int destreg = ((instruction >> 6) & 0x0000001F);
3599 int fs = ((instruction >> 11) & 0x0000001F);
3600 int ft = ((instruction >> 16) & 0x0000001F);
3601 int format = ((instruction >> 21) & 0x00000007);
3602 {
3603 if ((format != fmt_single) && (format != fmt_double))
3604 SignalException(ReservedInstruction,instruction);
3605 else
3606 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
3607 }
3608}
3609
3610
3611
3612111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
3613"swc1 f<FT>, <OFFSET>(r<BASE>)"
3614*mipsI,mipsII,mipsIII,mipsIV:
3615*vr4100:
3616*vr5000:
3617*r3900:
3618{
3619 unsigned32 instruction = instruction_0;
3620 signed_word offset = EXTEND16 (OFFSET);
3621 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
3622 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
3623 {
3624 address_word vaddr = ((uword64)op1 + offset);
3625 address_word paddr;
3626 int uncached;
3627 if ((vaddr & 3) != 0)
3628 {
3629 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
3630 }
3631 else
3632 {
3633 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3634 {
3635 uword64 memval = 0;
3636 uword64 memval1 = 0;
3637 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3638 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
3639 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
3640 unsigned int byte;
3641 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3642 byte = ((vaddr & mask) ^ bigendiancpu);
3643 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
3644 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3645 }
3646 }
3647 }
3648}
3649
3650
3651010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
3652"swxc1 f<FS>, r<INDEX>(r<BASE>)"
3653*mipsIV:
3654*vr5000:
3655{
3656 unsigned32 instruction = instruction_0;
3657 int fs = ((instruction >> 11) & 0x0000001F);
3658 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3659 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3660 {
3661 address_word vaddr = ((unsigned64)op1 + op2);
3662 address_word paddr;
3663 int uncached;
3664 if ((vaddr & 3) != 0)
3665 {
3666 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3667 }
3668 else
3669 {
3670 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3671 {
3672 unsigned64 memval = 0;
3673 unsigned64 memval1 = 0;
3674 unsigned64 mask = 0x7;
3675 unsigned int byte;
3676 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3677 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3678 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
3679 {
3680 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3681 }
3682 }
3683 }
3684 }
3685}
3686
3687
3688010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
3689"trunc.l.%s<FMT> f<FD>, f<FS>"
3690*mipsIII:
3691*mipsIV:
3692*vr4100:
3693*vr5000:
3694*r3900:
3695{
3696 unsigned32 instruction = instruction_0;
3697 int destreg = ((instruction >> 6) & 0x0000001F);
3698 int fs = ((instruction >> 11) & 0x0000001F);
3699 int format = ((instruction >> 21) & 0x00000007);
3700 {
3701 if ((format != fmt_single) && (format != fmt_double))
3702 SignalException(ReservedInstruction,instruction);
3703 else
3704 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
3705 }
3706}
3707
3708
3709010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
3710"trunc.w.%s<FMT> f<FD>, f<FS>"
3711*mipsII:
3712*mipsIII:
3713*mipsIV:
3714*vr4100:
3715*vr5000:
3716*r3900:
3717{
3718 unsigned32 instruction = instruction_0;
3719 int destreg = ((instruction >> 6) & 0x0000001F);
3720 int fs = ((instruction >> 11) & 0x0000001F);
3721 int format = ((instruction >> 21) & 0x00000007);
3722 {
3723 if ((format != fmt_single) && (format != fmt_double))
3724 SignalException(ReservedInstruction,instruction);
3725 else
3726 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
3727 }
3728}
3729
3730\f
3731//
3732// MIPS Architecture:
3733//
3734// System Control Instruction Set (COP0)
3735//
3736
3737
3738010000,01000,00000,16.OFFSET:COP0:32::BC0F
3739"bc0f <OFFSET>"
3740*mipsI,mipsII,mipsIII,mipsIV:
3741*vr4100:
3742*vr5000:
3743
7a292a7a
SS		 3744010000,01000,00000,16.OFFSET:COP0:32::BC0F
3745"bc0f <OFFSET>"
3746// stub needed for eCos as tx39 hardware bug workaround
3747*r3900:
3748{
3749 /* do nothing */
3750}
3751
c906108c
SS		 3752
3753010000,01000,00010,16.OFFSET:COP0:32::BC0FL
3754"bc0fl <OFFSET>"
3755*mipsI,mipsII,mipsIII,mipsIV:
3756*vr4100:
3757*vr5000:
3758
3759
3760010000,01000,00001,16.OFFSET:COP0:32::BC0T
3761"bc0t <OFFSET>"
3762*mipsI,mipsII,mipsIII,mipsIV:
3763*vr4100:
3764
3765
3766010000,01000,00011,16.OFFSET:COP0:32::BC0TL
3767"bc0tl <OFFSET>"
3768*mipsI,mipsII,mipsIII,mipsIV:
3769*vr4100:
3770*vr5000:
3771
3772
3773101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
3774*mipsIII:
3775*mipsIV:
3776*vr4100:
3777*vr5000:
3778*r3900:
3779{
3780 unsigned32 instruction = instruction_0;
3781 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3782 int hint = ((instruction >> 16) & 0x0000001F);
3783 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3784 {
3785 address_word vaddr = (op1 + offset);
3786 address_word paddr;
3787 int uncached;
3788 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3789 CacheOp(hint,vaddr,paddr,instruction);
3790 }
3791}
3792
3793
3794010000,10000,000000000000000,111001:COP0:32::DI
3795"di"
3796*mipsI,mipsII,mipsIII,mipsIV:
3797*vr4100:
3798*vr5000:
3799
3800
9846de1b
JM		 3801010000,00001,5.RT,5.RD,000,0000,0000:COP0:64::DMFC0
3802"dmfc0 r<RT>, r<RD>"
3803*mipsIII,mipsIV:
3804{
3805 DecodeCoproc (instruction_0);
3806}
3807
3808
3809010000,00101,5.RT,5.RD,000,0000,0000:COP0:64::DMTC0
3810"dmtc0 r<RT>, r<RD>"
3811*mipsIII,mipsIV:
3812{
3813 DecodeCoproc (instruction_0);
3814}
3815
3816
c906108c
SS		 3817010000,10000,000000000000000,111000:COP0:32::EI
3818"ei"
3819*mipsI,mipsII,mipsIII,mipsIV:
3820*vr4100:
3821*vr5000:
3822
3823
3824010000,10000,000000000000000,011000:COP0:32::ERET
3825"eret"
3826*mipsIII:
3827*mipsIV:
3828*vr4100:
3829*vr5000:
3830{
3831 if (SR & status_ERL)
3832 {
3833 /* Oops, not yet available */
3834 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
3835 NIA = EPC;
3836 SR &= ~status_ERL;
3837 }
3838 else
3839 {
3840 NIA = EPC;
3841 SR &= ~status_EXL;
3842 }
3843}
3844
3845
3846010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
3847"mfc0 r<RT>, r<RD> # <REGX>"
3848*mipsI,mipsII,mipsIII,mipsIV:
3849*r3900:
3850*vr4100:
3851*vr5000:
3852{
3853 TRACE_ALU_INPUT0 ();
3854 DecodeCoproc (instruction_0);
3855 TRACE_ALU_RESULT (GPR[RT]);
3856}
3857
3858010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
3859"mtc0 r<RT>, r<RD> # <REGX>"
3860*mipsI,mipsII,mipsIII,mipsIV:
3861*r3900:
3862*vr4100:
3863*vr5000:
3864{
3865 DecodeCoproc (instruction_0);
3866}
3867
3868
3869010000,10000,000000000000000,010000:COP0:32::RFE
3870"rfe"
3871*mipsI,mipsII,mipsIII,mipsIV:
3872*r3900:
3873*vr4100:
3874*vr5000:
3875{
3876 DecodeCoproc (instruction_0);
3877}
3878
3879
38800100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
3881"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
3882*mipsI,mipsII,mipsIII,mipsIV:
3883*vr4100:
3884*r3900:
3885{
3886 DecodeCoproc (instruction_0);
3887}
3888
3889
3890
3891010000,10000,000000000000000,001000:COP0:32::TLBP
3892"tlbp"
3893*mipsI,mipsII,mipsIII,mipsIV:
3894*vr4100:
3895*vr5000:
3896
3897
3898010000,10000,000000000000000,000001:COP0:32::TLBR
3899"tlbr"
3900*mipsI,mipsII,mipsIII,mipsIV:
3901*vr4100:
3902*vr5000:
3903
3904
3905010000,10000,000000000000000,000010:COP0:32::TLBWI
3906"tlbwi"
3907*mipsI,mipsII,mipsIII,mipsIV:
3908*vr4100:
3909*vr5000:
3910
3911
3912010000,10000,000000000000000,000110:COP0:32::TLBWR
3913"tlbwr"
3914*mipsI,mipsII,mipsIII,mipsIV:
3915*vr4100:
3916*vr5000:
3917
3918\f
3919:include:::m16.igen
3920:include:::tx.igen
3921:include:::vr.igen
3922\f
GDB Binutils - Deliverables
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