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sim: split sim-signal.h include out
[deliverable/binutils-gdb.git] / sim / mips / sim-main.h
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c906108c 1/* MIPS Simulator definition.
3666a048 2 Copyright (C) 1997-2021 Free Software Foundation, Inc.
c906108c
SS		 3 Contributed by Cygnus Support.
4
8e394ffc 5This file is part of the MIPS sim.
c906108c
SS		 6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
4744ac1b
JB		 9the Free Software Foundation; either version 3 of the License, or
10(at your option) any later version.
c906108c
SS		 11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
4744ac1b
JB		 17You should have received a copy of the GNU General Public License
18along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS		 19
20#ifndef SIM_MAIN_H
21#define SIM_MAIN_H
22
cb379ede
MF		 23/* MIPS uses an unusual format for floating point quiet NaNs. */
24#define SIM_QUIET_NAN_NEGATED
25
c906108c
SS		 26#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
27mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
28
29#include "sim-basics.h"
c906108c 30#include "sim-base.h"
4c54fc26 31#include "bfd.h"
c906108c 32
5accf1ff 33/* Deprecated macros and types for manipulating 64bit values. Use
c906108c
SS		 34 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
35
36typedef signed64 word64;
37typedef unsigned64 uword64;
38
39#define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
40#define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
41#define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
42#define SET64HI(t) (((uword64)(t))<<32)
43#define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
44#define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
45
c906108c
SS		 46/* Check if a value will fit within a halfword: */
47#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
48
49
8e394ffc
AB		 50typedef enum {
51 cp0_dmfc0,
52 cp0_dmtc0,
53 cp0_mfc0,
54 cp0_mtc0,
55 cp0_tlbr,
56 cp0_tlbwi,
57 cp0_tlbwr,
58 cp0_tlbp,
59 cp0_cache,
60 cp0_eret,
61 cp0_deret,
62 cp0_rfe
63} CP0_operation;
c906108c
SS		 64
65/* Floating-point operations: */
66
67#include "sim-fpu.h"
cfe9ea23 68#include "cp1.h"
c906108c
SS		 69
70/* FPU registers must be one of the following types. All other values
71 are reserved (and undefined). */
72typedef enum {
73 fmt_single = 0,
74 fmt_double = 1,
75 fmt_word = 4,
76 fmt_long = 5,
3a2b820e 77 fmt_ps = 6,
c906108c
SS		 78 /* The following are well outside the normal acceptable format
79 range, and are used in the register status vector. */
80 fmt_unknown = 0x10000000,
81 fmt_uninterpreted = 0x20000000,
82 fmt_uninterpreted_32 = 0x40000000,
83 fmt_uninterpreted_64 = 0x80000000U,
84} FP_formats;
85
e7e81181
CD		 86/* For paired word (pw) operations, the opcode representation is fmt_word,
87 but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */
88#define fmt_pw fmt_long
89
c906108c
SS		 90/* This should be the COC1 value at the start of the preceding
91 instruction: */
92#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
93
94#ifdef TARGET_ENABLE_FR
95/* FIXME: this should be enabled for all targets, but needs testing first. */
96#define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
97 ? ((SR & status_FR) ? 64 : 32) \
98 : (WITH_TARGET_FLOATING_POINT_BITSIZE))
99#else
100#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
101#endif
102
c906108c
SS		 103
104
105
106
107/* HI/LO register accesses */
108
109/* For some MIPS targets, the HI/LO registers have certain timing
110 restrictions in that, for instance, a read of a HI register must be
111 separated by at least three instructions from a preceeding read.
112
113 The struct below is used to record the last access by each of A MT,
114 MF or other OP instruction to a HI/LO register. See mips.igen for
115 more details. */
116
117typedef struct _hilo_access {
118 signed64 timestamp;
119 address_word cia;
120} hilo_access;
121
122typedef struct _hilo_history {
123 hilo_access mt;
124 hilo_access mf;
125 hilo_access op;
126} hilo_history;
127
128
129
130
131/* Integer ALU operations: */
132
133#include "sim-alu.h"
134
135#define ALU32_END(ANS) \
136 if (ALU32_HAD_OVERFLOW) \
137 SignalExceptionIntegerOverflow (); \
138 (ANS) = (signed32) ALU32_OVERFLOW_RESULT
139
140
141#define ALU64_END(ANS) \
142 if (ALU64_HAD_OVERFLOW) \
143 SignalExceptionIntegerOverflow (); \
144 (ANS) = ALU64_OVERFLOW_RESULT;
145
146
147
148
149
150/* The following is probably not used for MIPS IV onwards: */
151/* Slots for delayed register updates. For the moment we just have a
152 fixed number of slots (rather than a more generic, dynamic
153 system). This keeps the simulator fast. However, we only allow
154 for the register update to be delayed for a single instruction
155 cycle. */
156#define PSLOTS (8) /* Maximum number of instruction cycles */
157
158typedef struct _pending_write_queue {
159 int in;
160 int out;
161 int total;
162 int slot_delay[PSLOTS];
163 int slot_size[PSLOTS];
164 int slot_bit[PSLOTS];
165 void *slot_dest[PSLOTS];
166 unsigned64 slot_value[PSLOTS];
167} pending_write_queue;
168
169#ifndef PENDING_TRACE
170#define PENDING_TRACE 0
171#endif
172#define PENDING_IN ((CPU)->pending.in)
173#define PENDING_OUT ((CPU)->pending.out)
174#define PENDING_TOTAL ((CPU)->pending.total)
175#define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
176#define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
177#define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
178#define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
179#define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
180
181/* Invalidate the pending write queue, all pending writes are
182 discarded. */
183
184#define PENDING_INVALIDATE() \
185memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
186
187/* Schedule a write to DEST for N cycles time. For 64 bit
188 destinations, schedule two writes. For floating point registers,
189 the caller should schedule a write to both the dest register and
190 the FPR_STATE register. When BIT is non-negative, only BIT of DEST
191 is updated. */
192
193#define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
194 do { \
195 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
196 sim_engine_abort (SD, CPU, cia, \
197 "PENDING_SCHED - buffer overflow\n"); \
198 if (PENDING_TRACE) \
199 sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \
200 (unsigned long) cia, (unsigned long) &(DEST), \
201 (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
202 PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
203 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
204 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
205 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
206 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
207 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
208 PENDING_IN = (PENDING_IN + 1) % PSLOTS; \
209 PENDING_TOTAL += 1; \
210 } while (0)
211
212#define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
213#define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
214
215#define PENDING_TICK() pending_tick (SD, CPU, cia)
216
217#define PENDING_FLUSH() abort () /* think about this one */
218#define PENDING_FP() abort () /* think about this one */
219
220/* For backward compatibility */
221#define PENDING_FILL(R,VAL) \
222do { \
ee7254b0 223 if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \
c906108c 224 { \
ee7254b0
CD		 225 PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \
226 PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
c906108c
SS		 227 } \
228 else \
229 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
230} while (0)
231
232
9e52972e
FF		 233enum float_operation
234 {
235 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
236 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
237 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
238 };
239
c906108c 240
f4f1b9f1
CD		 241/* The internal representation of an MDMX accumulator.
242 Note that 24 and 48 bit accumulator elements are represented in
243 32 or 64 bits. Since the accumulators are 2's complement with
244 overflow suppressed, high-order bits can be ignored in most contexts. */
245
246typedef signed32 signed24;
247typedef signed64 signed48;
248
249typedef union {
250 signed24 ob[8];
251 signed48 qh[4];
252} MDMX_accumulator;
253
254
255/* Conventional system arguments. */
256#define SIM_STATE sim_cpu *cpu, address_word cia
257#define SIM_ARGS CPU, cia
258
c906108c
SS		 259struct _sim_cpu {
260
261
262 /* The following are internal simulator state variables: */
c906108c
SS		 263 address_word dspc; /* delay-slot PC */
264#define DSPC ((CPU)->dspc)
265
266#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
267#define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
268
269
270 /* State of the simulator */
271 unsigned int state;
272 unsigned int dsstate;
273#define STATE ((CPU)->state)
274#define DSSTATE ((CPU)->dsstate)
275
276/* Flags in the "state" variable: */
277#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
278#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
279#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
280#define simPCOC0 (1 << 17) /* COC[1] from current */
281#define simPCOC1 (1 << 18) /* COC[1] from previous */
282#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
283#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
284#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
285#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
286
fb891446 287#ifndef ENGINE_ISSUE_PREFIX_HOOK
c906108c
SS		 288#define ENGINE_ISSUE_PREFIX_HOOK() \
289 { \
290 /* Perform any pending writes */ \
291 PENDING_TICK(); \
292 /* Set previous flag, depending on current: */ \
293 if (STATE & simPCOC0) \
294 STATE |= simPCOC1; \
295 else \
296 STATE &= ~simPCOC1; \
297 /* and update the current value: */ \
298 if (GETFCC(0)) \
299 STATE |= simPCOC0; \
300 else \
301 STATE &= ~simPCOC0; \
302 }
fb891446 303#endif /* ENGINE_ISSUE_PREFIX_HOOK */
c906108c
SS		 304
305
306/* This is nasty, since we have to rely on matching the register
307 numbers used by GDB. Unfortunately, depending on the MIPS target
308 GDB uses different register numbers. We cannot just include the
309 relevant "gdb/tm.h" link, since GDB may not be configured before
310 the sim world, and also the GDB header file requires too much other
311 state. */
312
313#ifndef TM_MIPS_H
40a5538e 314#define LAST_EMBED_REGNUM (96)
c906108c
SS		 315#define NUM_REGS (LAST_EMBED_REGNUM + 1)
316
ee7254b0
CD		 317#define FP0_REGNUM 38 /* Floating point register 0 (single float) */
318#define FCRCS_REGNUM 70 /* FP control/status */
319#define FCRIR_REGNUM 71 /* FP implementation/revision */
c906108c
SS		 320#endif
321
322
c906108c
SS		 323/* To keep this default simulator simple, and fast, we use a direct
324 vector of registers. The internal simulator engine then uses
325 manifests to access the correct slot. */
326
327 unsigned_word registers[LAST_EMBED_REGNUM + 1];
328
329 int register_widths[NUM_REGS];
330#define REGISTERS ((CPU)->registers)
331
332#define GPR (&REGISTERS[0])
333#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
334
c906108c
SS		 335#define LO (REGISTERS[33])
336#define HI (REGISTERS[34])
337#define PCIDX 37
338#define PC (REGISTERS[PCIDX])
339#define CAUSE (REGISTERS[36])
340#define SRIDX (32)
341#define SR (REGISTERS[SRIDX]) /* CPU status register */
342#define FCR0IDX (71)
343#define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
344#define FCR31IDX (70)
345#define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
346#define FCSR (FCR31)
347#define Debug (REGISTERS[86])
348#define DEPC (REGISTERS[87])
349#define EPC (REGISTERS[88])
2d2733fc 350#define ACX (REGISTERS[89])
c906108c 351
40a5538e
CF		 352#define AC0LOIDX (33) /* Must be the same register as LO */
353#define AC0HIIDX (34) /* Must be the same register as HI */
354#define AC1LOIDX (90)
355#define AC1HIIDX (91)
356#define AC2LOIDX (92)
357#define AC2HIIDX (93)
358#define AC3LOIDX (94)
359#define AC3HIIDX (95)
360
361#define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]])
362#define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]])
363
364#define DSPCRIDX (96) /* DSP control register */
365#define DSPCR (REGISTERS[DSPCRIDX])
366
367#define DSPCR_POS_SHIFT (0)
368#define DSPCR_POS_MASK (0x3f)
369#define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
370
371#define DSPCR_SCOUNT_SHIFT (7)
372#define DSPCR_SCOUNT_MASK (0x3f)
373#define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
374
375#define DSPCR_CARRY_SHIFT (13)
376#define DSPCR_CARRY_MASK (1)
377#define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
378#define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT)
379
380#define DSPCR_EFI_SHIFT (14)
381#define DSPCR_EFI_MASK (1)
382#define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
383#define DSPCR_EFI (1 << DSPCR_EFI_MASK)
384
385#define DSPCR_OUFLAG_SHIFT (16)
386#define DSPCR_OUFLAG_MASK (0xff)
387#define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
388#define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4))
389#define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5))
390#define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6))
391#define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7))
392
393#define DSPCR_CCOND_SHIFT (24)
394#define DSPCR_CCOND_MASK (0xf)
395#define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
396
c906108c
SS		 397 /* All internal state modified by signal_exception() that may need to be
398 rolled back for passing moment-of-exception image back to gdb. */
399 unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
400 unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
401 int exc_suspended;
402
403#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
404#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
405#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
406
407 unsigned_word c0_config_reg;
408#define C0_CONFIG ((CPU)->c0_config_reg)
409
410/* The following are pseudonyms for standard registers */
411#define ZERO (REGISTERS[0])
412#define V0 (REGISTERS[2])
413#define A0 (REGISTERS[4])
414#define A1 (REGISTERS[5])
415#define A2 (REGISTERS[6])
416#define A3 (REGISTERS[7])
417#define T8IDX 24
418#define T8 (REGISTERS[T8IDX])
419#define SPIDX 29
420#define SP (REGISTERS[SPIDX])
421#define RAIDX 31
422#define RA (REGISTERS[RAIDX])
423
424 /* While space is allocated in the main registers arrray for some of
425 the COP0 registers, that space isn't sufficient. Unknown COP0
426 registers overflow into the array below */
427
428#define NR_COP0_GPR 32
429 unsigned_word cop0_gpr[NR_COP0_GPR];
430#define COP0_GPR ((CPU)->cop0_gpr)
1a27f959 431#define COP0_BADVADDR (COP0_GPR[8])
c906108c 432
ee7254b0
CD		 433 /* While space is allocated for the floating point registers in the
434 main registers array, they are stored separatly. This is because
435 their size may not necessarily match the size of either the
436 general-purpose or system specific registers. */
437#define NR_FGR (32)
438#define FGR_BASE FP0_REGNUM
439 fp_word fgr[NR_FGR];
440#define FGR ((CPU)->fgr)
441
c906108c
SS		 442 /* Keep the current format state for each register: */
443 FP_formats fpr_state[32];
444#define FPR_STATE ((CPU)->fpr_state)
445
446 pending_write_queue pending;
447
f4f1b9f1
CD		 448 /* The MDMX accumulator (used only for MDMX ASE). */
449 MDMX_accumulator acc;
450#define ACC ((CPU)->acc)
451
c906108c
SS		 452 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
453 read-write instructions. It is set when a linked load occurs. It
454 is tested and cleared by the conditional store. It is cleared
455 (during other CPU operations) when a store to the location would
456 no longer be atomic. In particular, it is cleared by exception
457 return instructions. */
458 int llbit;
459#define LLBIT ((CPU)->llbit)
460
461
462/* The HIHISTORY and LOHISTORY timestamps are used to ensure that
463 corruptions caused by using the HI or LO register too close to a
464 following operation is spotted. See mips.igen for more details. */
465
466 hilo_history hi_history;
467#define HIHISTORY (&(CPU)->hi_history)
468 hilo_history lo_history;
469#define LOHISTORY (&(CPU)->lo_history)
470
c906108c
SS		 471
472 sim_cpu_base base;
473};
474
6e4f085c
MF		 475extern void mips_sim_close (SIM_DESC sd, int quitting);
476#define SIM_CLOSE_HOOK(...) mips_sim_close (__VA_ARGS__)
c906108c 477
c906108c 478/* FIXME: At present much of the simulator is still static */
8ea7241c 479struct mips_sim_state {
8e394ffc
AB		 480 /* microMIPS ISA mode. */
481 int isa_mode;
c906108c 482};
8ea7241c 483#define MIPS_SIM_STATE(sd) ((struct mips_sim_state *) STATE_ARCH_DATA (sd))
c906108c
SS		 484
485
486/* Status information: */
487
488/* TODO : these should be the bitmasks for these bits within the
489 status register. At the moment the following are VR4300
490 bit-positions: */
491#define status_KSU_mask (0x18) /* mask for KSU bits */
492#define status_KSU_shift (3) /* shift for field */
493#define ksu_kernel (0x0)
494#define ksu_supervisor (0x1)
495#define ksu_user (0x2)
496#define ksu_unknown (0x3)
497
498#define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift)
499
500#define status_IE (1 << 0) /* Interrupt enable */
501#define status_EIE (1 << 16) /* Enable Interrupt Enable */
502#define status_EXL (1 << 1) /* Exception level */
503#define status_RE (1 << 25) /* Reverse Endian in user mode */
504#define status_FR (1 << 26) /* enables MIPS III additional FP registers */
505#define status_SR (1 << 20) /* soft reset or NMI */
506#define status_BEV (1 << 22) /* Location of general exception vectors */
507#define status_TS (1 << 21) /* TLB shutdown has occurred */
508#define status_ERL (1 << 2) /* Error level */
509#define status_IM7 (1 << 15) /* Timer Interrupt Mask */
510#define status_RP (1 << 27) /* Reduced Power mode */
511
512/* Specializations for TX39 family */
513#define status_IEc (1 << 0) /* Interrupt enable (current) */
514#define status_KUc (1 << 1) /* Kernel/User mode */
515#define status_IEp (1 << 2) /* Interrupt enable (previous) */
516#define status_KUp (1 << 3) /* Kernel/User mode */
517#define status_IEo (1 << 4) /* Interrupt enable (old) */
518#define status_KUo (1 << 5) /* Kernel/User mode */
519#define status_IM_mask (0xff) /* Interrupt mask */
520#define status_IM_shift (8)
521#define status_NMI (1 << 20) /* NMI */
522#define status_NMI (1 << 20) /* NMI */
523
d35d4f70
CD		 524/* Status bits used by MIPS32/MIPS64. */
525#define status_UX (1 << 5) /* 64-bit user addrs */
526#define status_SX (1 << 6) /* 64-bit supervisor addrs */
527#define status_KX (1 << 7) /* 64-bit kernel addrs */
528#define status_TS (1 << 21) /* TLB shutdown has occurred */
529#define status_PX (1 << 23) /* Enable 64 bit operations */
530#define status_MX (1 << 24) /* Enable MDMX resources */
531#define status_CU0 (1 << 28) /* Coprocessor 0 usable */
532#define status_CU1 (1 << 29) /* Coprocessor 1 usable */
533#define status_CU2 (1 << 30) /* Coprocessor 2 usable */
534#define status_CU3 (1 << 31) /* Coprocessor 3 usable */
7cbea089
CD		 535/* Bits reserved for implementations: */
536#define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */
d35d4f70 537
c906108c
SS		 538#define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
539#define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
540#define cause_CE_mask 0x30000000 /* Coprocessor exception */
541#define cause_CE_shift 28
542#define cause_EXC2_mask 0x00070000
543#define cause_EXC2_shift 16
544#define cause_IP7 (1 << 15) /* Interrupt pending */
545#define cause_SIOP (1 << 12) /* SIO pending */
546#define cause_IP3 (1 << 11) /* Int 0 pending */
547#define cause_IP2 (1 << 10) /* Int 1 pending */
548
549#define cause_EXC_mask (0x1c) /* Exception code */
550#define cause_EXC_shift (2)
551
552#define cause_SW0 (1 << 8) /* Software interrupt 0 */
553#define cause_SW1 (1 << 9) /* Software interrupt 1 */
554#define cause_IP_mask (0x3f) /* Interrupt pending field */
555#define cause_IP_shift (10)
556
557#define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask)
558#define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
559
560
561/* NOTE: We keep the following status flags as bit values (1 for true,
562 0 for false). This allows them to be used in binary boolean
563 operations without worrying about what exactly the non-zero true
564 value is. */
565
566/* UserMode */
567#ifdef SUBTARGET_R3900
568#define UserMode ((SR & status_KUc) ? 1 : 0)
569#else
570#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
571#endif /* SUBTARGET_R3900 */
572
573/* BigEndianMem */
574/* Hardware configuration. Affects endianness of LoadMemory and
575 StoreMemory and the endianness of Kernel and Supervisor mode
576 execution. The value is 0 for little-endian; 1 for big-endian. */
1ac72f06 577#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
c906108c
SS		 578/*(state & simBE) ? 1 : 0)*/
579
580/* ReverseEndian */
581/* This mode is selected if in User mode with the RE bit being set in
582 SR (Status Register). It reverses the endianness of load and store
583 instructions. */
584#define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
585
586/* BigEndianCPU */
587/* The endianness for load and store instructions (0=little;1=big). In
588 User mode this endianness may be switched by setting the state_RE
589 bit in the SR register. Thus, BigEndianCPU may be computed as
590 (BigEndianMem EOR ReverseEndian). */
591#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
592
593
594
595/* Exceptions: */
596
597/* NOTE: These numbers depend on the processor architecture being
598 simulated: */
599enum ExceptionCause {
600 Interrupt = 0,
601 TLBModification = 1,
602 TLBLoad = 2,
603 TLBStore = 3,
604 AddressLoad = 4,
605 AddressStore = 5,
606 InstructionFetch = 6,
607 DataReference = 7,
608 SystemCall = 8,
609 BreakPoint = 9,
610 ReservedInstruction = 10,
611 CoProcessorUnusable = 11,
612 IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */
613 Trap = 13,
614 FPE = 15,
d35d4f70
CD		 615 DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */
616 MDMX = 22,
c906108c 617 Watch = 23,
d35d4f70
CD		 618 MCheck = 24,
619 CacheErr = 30,
620 NMIReset = 31, /* Reserved in MIPS32/MIPS64. */
c906108c
SS		 621
622
623/* The following exception code is actually private to the simulator
624 world. It is *NOT* a processor feature, and is used to signal
625 run-time errors in the simulator. */
626 SimulatorFault = 0xFFFFFFFF
627};
628
629#define TLB_REFILL (0)
630#define TLB_INVALID (1)
631
632
633/* The following break instructions are reserved for use by the
634 simulator. The first is used to halt the simulation. The second
635 is used by gdb for break-points. NOTE: Care must be taken, since
636 this value may be used in later revisions of the MIPS ISA. */
637#define HALT_INSTRUCTION_MASK (0x03FFFFC0)
638
639#define HALT_INSTRUCTION (0x03ff000d)
640#define HALT_INSTRUCTION2 (0x0000ffcd)
641
642
643#define BREAKPOINT_INSTRUCTION (0x0005000d)
644#define BREAKPOINT_INSTRUCTION2 (0x0000014d)
645
646
647
648void interrupt_event (SIM_DESC sd, void *data);
649
650void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
651#define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
652#define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level)
653#define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
654#define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
655#define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
656#define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference)
657#define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
658#define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
659#define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
3ad6f714 660#define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
c906108c
SS		 661#define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
662#define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
663#define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
664#define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
665#define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
666#define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification)
d35d4f70
CD		 667#define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX)
668#define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch)
669#define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck)
670#define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr)
c906108c
SS		 671
672/* Co-processor accesses */
673
3ad6f714
CD		 674/* XXX FIXME: For now, assume that FPU (cp1) is always usable. */
675#define COP_Usable(coproc_num) (coproc_num == 1)
676
bdca5ee4
TT		 677void cop_lw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword);
678void cop_ld (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword);
679unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
680uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
c906108c
SS		 681
682#define COP_LW(coproc_num,coproc_reg,memword) \
683cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
684#define COP_LD(coproc_num,coproc_reg,memword) \
685cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
686#define COP_SW(coproc_num,coproc_reg) \
687cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
688#define COP_SD(coproc_num,coproc_reg) \
689cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
690
691
8e394ffc
AB		 692void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia,
693 unsigned int instruction, int coprocnum, CP0_operation op,
694 int rt, int rd, int sel);
695#define DecodeCoproc(instruction,coprocnum,op,rt,rd,sel) \
696 decode_coproc (SD, CPU, cia, (instruction), (coprocnum), (op), \
697 (rt), (rd), (sel))
c906108c 698
8030f857 699int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
c906108c
SS		 700
701
18d8a52d
CD		 702/* FPR access. */
703unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
704#define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
705void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
706#define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
3a2b820e
CD		 707unsigned64 ps_lower (SIM_STATE, unsigned64 op);
708#define PSLower(op) ps_lower (SIM_ARGS, op)
709unsigned64 ps_upper (SIM_STATE, unsigned64 op);
710#define PSUpper(op) ps_upper (SIM_ARGS, op)
711unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
712#define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
18d8a52d
CD		 713
714
cfe9ea23
CD		 715/* FCR access. */
716unsigned_word value_fcr (SIM_STATE, int fcr);
717#define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
718void store_fcr (SIM_STATE, int fcr, unsigned_word value);
719#define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
720void test_fcsr (SIM_STATE);
721#define TestFCSR() test_fcsr (SIM_ARGS)
722
723
18d8a52d 724/* FPU operations. */
cfe9ea23
CD		 725void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
726#define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
ba46ddd0
CD		 727unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
728#define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
729unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
730#define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
731unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
732#define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
733unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
734#define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
735unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
736#define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
737unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
738#define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
739unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
740#define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
741unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
742#define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
f3c08b7e
CD		 743unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
744#define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
745unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
746 unsigned64 op3, FP_formats fmt);
747#define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
748unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
749 unsigned64 op3, FP_formats fmt);
750#define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
751unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
752 unsigned64 op3, FP_formats fmt);
753#define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
754unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
755 unsigned64 op3, FP_formats fmt);
756#define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
18d8a52d
CD		 757unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
758#define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
3a2b820e
CD		 759unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
760 FP_formats to);
761#define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
18d8a52d
CD		 762
763
e7e81181
CD		 764/* MIPS-3D ASE operations. */
765#define CompareAbs(op1,op2,fmt,cond,cc) \
766fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
767unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
768#define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
769unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
770#define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
771unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
772#define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
773unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
774#define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
775unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
776#define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
777unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
778#define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
779
780
f4f1b9f1
CD		 781/* MDMX access. */
782
783typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */
784#define ob_fmtsel(sel) (((sel)<<1)|0x0)
785#define qh_fmtsel(sel) (((sel)<<2)|0x1)
786
787#define fmt_mdmx fmt_uninterpreted
788
789#define MX_VECT_AND (0)
790#define MX_VECT_NOR (1)
791#define MX_VECT_OR (2)
792#define MX_VECT_XOR (3)
793#define MX_VECT_SLL (4)
794#define MX_VECT_SRL (5)
f4f1b9f1
CD		 795#define MX_VECT_ADD (6)
796#define MX_VECT_SUB (7)
797#define MX_VECT_MIN (8)
798#define MX_VECT_MAX (9)
799#define MX_VECT_MUL (10)
800#define MX_VECT_MSGN (11)
801#define MX_VECT_SRA (12)
7cbea089
CD		 802#define MX_VECT_ABSD (13) /* SB-1 only. */
803#define MX_VECT_AVG (14) /* SB-1 only. */
f4f1b9f1
CD		 804
805unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
806#define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
807#define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
808#define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
809#define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
810#define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
811#define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
812#define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
813#define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel)
814#define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
815#define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
816#define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
817#define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
818#define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
7cbea089
CD		 819#define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
820#define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
f4f1b9f1
CD		 821
822#define MX_C_EQ 0x1
823#define MX_C_LT 0x4
824
825void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
826#define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
827
828unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
829#define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
830
831#define MX_VECT_ADDA (0)
832#define MX_VECT_ADDL (1)
833#define MX_VECT_MULA (2)
834#define MX_VECT_MULL (3)
835#define MX_VECT_MULS (4)
836#define MX_VECT_MULSL (5)
837#define MX_VECT_SUBA (6)
838#define MX_VECT_SUBL (7)
7cbea089 839#define MX_VECT_ABSDA (8) /* SB-1 only. */
f4f1b9f1
CD		 840
841void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
842#define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
843#define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
844#define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
845#define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
846#define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
847#define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
848#define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
849#define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
7cbea089 850#define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
f4f1b9f1
CD		 851
852#define MX_FMT_OB (0)
853#define MX_FMT_QH (1)
854
855/* The following codes chosen to indicate the units of shift. */
856#define MX_RAC_L (0)
857#define MX_RAC_M (1)
858#define MX_RAC_H (2)
859
860unsigned64 mdmx_rac_op (SIM_STATE, int, int);
861#define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
862
863void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
864#define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
865void mdmx_wach (SIM_STATE, int, unsigned64);
866#define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
867
868#define MX_RND_AS (0)
869#define MX_RND_AU (1)
870#define MX_RND_ES (2)
871#define MX_RND_EU (3)
872#define MX_RND_ZS (4)
873#define MX_RND_ZU (5)
874
875unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
876#define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
877#define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
878#define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
879#define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
880#define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
881#define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
882
883unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
884#define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
885
886
c906108c
SS		 887
888/* Memory accesses */
889
890/* The following are generic to all versions of the MIPS architecture
891 to date: */
892
c906108c
SS		 893#define isINSTRUCTION (1 == 0) /* FALSE */
894#define isDATA (1 == 1) /* TRUE */
895#define isLOAD (1 == 0) /* FALSE */
896#define isSTORE (1 == 1) /* TRUE */
897#define isREAL (1 == 0) /* FALSE */
898#define isRAW (1 == 1) /* TRUE */
899/* The parameter HOST (isTARGET / isHOST) is ignored */
900#define isTARGET (1 == 0) /* FALSE */
901/* #define isHOST (1 == 1) TRUE */
902
903/* The "AccessLength" specifications for Loads and Stores. NOTE: This
904 is the number of bytes minus 1. */
905#define AccessLength_BYTE (0)
906#define AccessLength_HALFWORD (1)
907#define AccessLength_TRIPLEBYTE (2)
908#define AccessLength_WORD (3)
909#define AccessLength_QUINTIBYTE (4)
910#define AccessLength_SEXTIBYTE (5)
911#define AccessLength_SEPTIBYTE (6)
912#define AccessLength_DOUBLEWORD (7)
913#define AccessLength_QUADWORD (15)
914
915#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
916 ? AccessLength_DOUBLEWORD /*7*/ \
917 : AccessLength_WORD /*3*/)
918#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
919
920
bdca5ee4 921INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
26f8bf63
MF		 922#define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \
923load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD)
c906108c 924
bdca5ee4 925INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
26f8bf63
MF		 926#define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
927store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr)
c906108c 928
bdca5ee4 929INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
c906108c
SS		 930#define CacheOp(op,pAddr,vAddr,instruction) \
931cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
932
bdca5ee4 933INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype);
c906108c
SS		 934#define SyncOperation(stype) \
935sync_operation (SD, CPU, cia, (stype))
936
402586aa
CD		 937void unpredictable_action (sim_cpu *cpu, address_word cia);
938#define NotWordValue(val) not_word_value (SD_, (val))
939#define Unpredictable() unpredictable (SD_)
f4f1b9f1 940#define UnpredictableResult() /* For now, do nothing. */
b96e7ef1 941
bdca5ee4 942INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
c906108c 943#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
bdca5ee4 944INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
c906108c
SS		 945#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
946#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
8e394ffc
AB		 947#define IMEM32_MICROMIPS(CIA) \
948 (ifetch16 (SD, CPU, (CIA), (CIA)) << 16 | ifetch16 (SD, CPU, (CIA + 2), \
949 (CIA + 2)))
950#define IMEM16_MICROMIPS(CIA) ifetch16 (SD, CPU, (CIA), ((CIA)))
951
952#define MICROMIPS_MINOR_OPCODE(INSN) ((INSN & 0x1C00) >> 10)
953
954#define MICROMIPS_DELAYSLOT_SIZE_ANY 0
955#define MICROMIPS_DELAYSLOT_SIZE_16 2
956#define MICROMIPS_DELAYSLOT_SIZE_32 4
957
958extern int isa_mode;
959
960#define ISA_MODE_MIPS32 0
961#define ISA_MODE_MICROMIPS 1
962
963address_word micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu,
964 address_word cia,
965 int instruction_size);
c906108c 966
29bc024d 967#if WITH_TRACE_ANY_P
b80d4475 968void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, const char *comment, ...) ATTRIBUTE_PRINTF (7, 8);
c906108c 969extern FILE *tracefh;
29bc024d
MF		 970#else
971#define dotrace(sd, cpu, tracefh, type, address, width, comment, ...)
972#endif
c906108c 973
40a5538e
CF		 974extern int DSPLO_REGNUM[4];
975extern int DSPHI_REGNUM[4];
976
bdca5ee4 977INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia);
c906108c
SS		 978extern SIM_CORE_SIGNAL_FN mips_core_signal;
979
bdca5ee4
TT		 980char* pr_addr (SIM_ADDR addr);
981char* pr_uword64 (uword64 addr);
c906108c
SS		 982
983
4c0deff4 984#define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
4c0deff4 985
c906108c
SS		 986void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
987void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
988void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
989
4c54fc26
CD		 990#ifdef MIPS_MACH_MULTI
991extern int mips_mach_multi(SIM_DESC sd);
992#define MIPS_MACH(SD) mips_mach_multi(SD)
993#else
994#define MIPS_MACH(SD) MIPS_MACH_DEFAULT
995#endif
c906108c 996
0e1b7197
RS		 997/* Macros for determining whether a MIPS IV or MIPS V part is subject
998 to the hi/lo restrictions described in mips.igen. */
999
1000#define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
1001 (MIPS_MACH (SD) != bfd_mach_mips5500)
1002
1003#define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
1004 (MIPS_MACH (SD) != bfd_mach_mips5500)
1005
1006#define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
1007 (MIPS_MACH (SD) != bfd_mach_mips5500)
1008
c906108c
SS		 1009#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1010#include "sim-main.c"
1011#endif
1012
1013#endif
GDB Binutils - Deliverables
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