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Correct the generation of OR1K pc-relative relocations.
[deliverable/binutils-gdb.git] / sim / mips / sim-main.h
CommitLineData
c906108c 1/* MIPS Simulator definition.
32d0add0 2 Copyright (C) 1997-2015 Free Software Foundation, Inc.
c906108c
SS		 3 Contributed by Cygnus Support.
4
5This file is part of GDB, the GNU debugger.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
4744ac1b
JB		 9the Free Software Foundation; either version 3 of the License, or
10(at your option) any later version.
c906108c
SS		 11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
4744ac1b
JB		 17You should have received a copy of the GNU General Public License
18along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS		 19
20#ifndef SIM_MAIN_H
21#define SIM_MAIN_H
22
c906108c
SS		 23/* hobble some common features for moment */
24#define WITH_WATCHPOINTS 1
25#define WITH_MODULO_MEMORY 1
26
27
28#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
29mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
30
31#include "sim-basics.h"
c906108c 32#include "sim-base.h"
4c54fc26 33#include "bfd.h"
c906108c 34
5accf1ff 35/* Deprecated macros and types for manipulating 64bit values. Use
c906108c
SS		 36 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
37
38typedef signed64 word64;
39typedef unsigned64 uword64;
40
41#define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
42#define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
43#define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
44#define SET64HI(t) (((uword64)(t))<<32)
45#define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
46#define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
47
c906108c
SS		 48/* Check if a value will fit within a halfword: */
49#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
50
51
52
53/* Floating-point operations: */
54
55#include "sim-fpu.h"
cfe9ea23 56#include "cp1.h"
c906108c
SS		 57
58/* FPU registers must be one of the following types. All other values
59 are reserved (and undefined). */
60typedef enum {
61 fmt_single = 0,
62 fmt_double = 1,
63 fmt_word = 4,
64 fmt_long = 5,
3a2b820e 65 fmt_ps = 6,
c906108c
SS		 66 /* The following are well outside the normal acceptable format
67 range, and are used in the register status vector. */
68 fmt_unknown = 0x10000000,
69 fmt_uninterpreted = 0x20000000,
70 fmt_uninterpreted_32 = 0x40000000,
71 fmt_uninterpreted_64 = 0x80000000U,
72} FP_formats;
73
e7e81181
CD		 74/* For paired word (pw) operations, the opcode representation is fmt_word,
75 but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */
76#define fmt_pw fmt_long
77
c906108c
SS		 78/* This should be the COC1 value at the start of the preceding
79 instruction: */
80#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
81
82#ifdef TARGET_ENABLE_FR
83/* FIXME: this should be enabled for all targets, but needs testing first. */
84#define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
85 ? ((SR & status_FR) ? 64 : 32) \
86 : (WITH_TARGET_FLOATING_POINT_BITSIZE))
87#else
88#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
89#endif
90
c906108c
SS		 91
92
93
94
95/* HI/LO register accesses */
96
97/* For some MIPS targets, the HI/LO registers have certain timing
98 restrictions in that, for instance, a read of a HI register must be
99 separated by at least three instructions from a preceeding read.
100
101 The struct below is used to record the last access by each of A MT,
102 MF or other OP instruction to a HI/LO register. See mips.igen for
103 more details. */
104
105typedef struct _hilo_access {
106 signed64 timestamp;
107 address_word cia;
108} hilo_access;
109
110typedef struct _hilo_history {
111 hilo_access mt;
112 hilo_access mf;
113 hilo_access op;
114} hilo_history;
115
116
117
118
119/* Integer ALU operations: */
120
121#include "sim-alu.h"
122
123#define ALU32_END(ANS) \
124 if (ALU32_HAD_OVERFLOW) \
125 SignalExceptionIntegerOverflow (); \
126 (ANS) = (signed32) ALU32_OVERFLOW_RESULT
127
128
129#define ALU64_END(ANS) \
130 if (ALU64_HAD_OVERFLOW) \
131 SignalExceptionIntegerOverflow (); \
132 (ANS) = ALU64_OVERFLOW_RESULT;
133
134
135
136
137
138/* The following is probably not used for MIPS IV onwards: */
139/* Slots for delayed register updates. For the moment we just have a
140 fixed number of slots (rather than a more generic, dynamic
141 system). This keeps the simulator fast. However, we only allow
142 for the register update to be delayed for a single instruction
143 cycle. */
144#define PSLOTS (8) /* Maximum number of instruction cycles */
145
146typedef struct _pending_write_queue {
147 int in;
148 int out;
149 int total;
150 int slot_delay[PSLOTS];
151 int slot_size[PSLOTS];
152 int slot_bit[PSLOTS];
153 void *slot_dest[PSLOTS];
154 unsigned64 slot_value[PSLOTS];
155} pending_write_queue;
156
157#ifndef PENDING_TRACE
158#define PENDING_TRACE 0
159#endif
160#define PENDING_IN ((CPU)->pending.in)
161#define PENDING_OUT ((CPU)->pending.out)
162#define PENDING_TOTAL ((CPU)->pending.total)
163#define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
164#define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
165#define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
166#define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
167#define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
168
169/* Invalidate the pending write queue, all pending writes are
170 discarded. */
171
172#define PENDING_INVALIDATE() \
173memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
174
175/* Schedule a write to DEST for N cycles time. For 64 bit
176 destinations, schedule two writes. For floating point registers,
177 the caller should schedule a write to both the dest register and
178 the FPR_STATE register. When BIT is non-negative, only BIT of DEST
179 is updated. */
180
181#define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
182 do { \
183 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
184 sim_engine_abort (SD, CPU, cia, \
185 "PENDING_SCHED - buffer overflow\n"); \
186 if (PENDING_TRACE) \
187 sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \
188 (unsigned long) cia, (unsigned long) &(DEST), \
189 (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
190 PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
191 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
192 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
193 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
194 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
195 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
196 PENDING_IN = (PENDING_IN + 1) % PSLOTS; \
197 PENDING_TOTAL += 1; \
198 } while (0)
199
200#define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
201#define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
202
203#define PENDING_TICK() pending_tick (SD, CPU, cia)
204
205#define PENDING_FLUSH() abort () /* think about this one */
206#define PENDING_FP() abort () /* think about this one */
207
208/* For backward compatibility */
209#define PENDING_FILL(R,VAL) \
210do { \
ee7254b0 211 if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \
c906108c 212 { \
ee7254b0
CD		 213 PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \
214 PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
c906108c
SS		 215 } \
216 else \
217 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
218} while (0)
219
220
9e52972e
FF		 221enum float_operation
222 {
223 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
224 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
225 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
226 };
227
c906108c 228
f4f1b9f1
CD		 229/* The internal representation of an MDMX accumulator.
230 Note that 24 and 48 bit accumulator elements are represented in
231 32 or 64 bits. Since the accumulators are 2's complement with
232 overflow suppressed, high-order bits can be ignored in most contexts. */
233
234typedef signed32 signed24;
235typedef signed64 signed48;
236
237typedef union {
238 signed24 ob[8];
239 signed48 qh[4];
240} MDMX_accumulator;
241
242
243/* Conventional system arguments. */
244#define SIM_STATE sim_cpu *cpu, address_word cia
245#define SIM_ARGS CPU, cia
246
c906108c
SS		 247struct _sim_cpu {
248
249
250 /* The following are internal simulator state variables: */
c906108c
SS		 251 address_word dspc; /* delay-slot PC */
252#define DSPC ((CPU)->dspc)
253
254#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
255#define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
256
257
258 /* State of the simulator */
259 unsigned int state;
260 unsigned int dsstate;
261#define STATE ((CPU)->state)
262#define DSSTATE ((CPU)->dsstate)
263
264/* Flags in the "state" variable: */
265#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
266#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
267#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
268#define simPCOC0 (1 << 17) /* COC[1] from current */
269#define simPCOC1 (1 << 18) /* COC[1] from previous */
270#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
271#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
272#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
273#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
274
fb891446 275#ifndef ENGINE_ISSUE_PREFIX_HOOK
c906108c
SS		 276#define ENGINE_ISSUE_PREFIX_HOOK() \
277 { \
278 /* Perform any pending writes */ \
279 PENDING_TICK(); \
280 /* Set previous flag, depending on current: */ \
281 if (STATE & simPCOC0) \
282 STATE |= simPCOC1; \
283 else \
284 STATE &= ~simPCOC1; \
285 /* and update the current value: */ \
286 if (GETFCC(0)) \
287 STATE |= simPCOC0; \
288 else \
289 STATE &= ~simPCOC0; \
290 }
fb891446 291#endif /* ENGINE_ISSUE_PREFIX_HOOK */
c906108c
SS		 292
293
294/* This is nasty, since we have to rely on matching the register
295 numbers used by GDB. Unfortunately, depending on the MIPS target
296 GDB uses different register numbers. We cannot just include the
297 relevant "gdb/tm.h" link, since GDB may not be configured before
298 the sim world, and also the GDB header file requires too much other
299 state. */
300
301#ifndef TM_MIPS_H
40a5538e 302#define LAST_EMBED_REGNUM (96)
c906108c
SS		 303#define NUM_REGS (LAST_EMBED_REGNUM + 1)
304
ee7254b0
CD		 305#define FP0_REGNUM 38 /* Floating point register 0 (single float) */
306#define FCRCS_REGNUM 70 /* FP control/status */
307#define FCRIR_REGNUM 71 /* FP implementation/revision */
c906108c
SS		 308#endif
309
310
c906108c
SS		 311/* To keep this default simulator simple, and fast, we use a direct
312 vector of registers. The internal simulator engine then uses
313 manifests to access the correct slot. */
314
315 unsigned_word registers[LAST_EMBED_REGNUM + 1];
316
317 int register_widths[NUM_REGS];
318#define REGISTERS ((CPU)->registers)
319
320#define GPR (&REGISTERS[0])
321#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
322
c906108c
SS		 323#define LO (REGISTERS[33])
324#define HI (REGISTERS[34])
325#define PCIDX 37
326#define PC (REGISTERS[PCIDX])
327#define CAUSE (REGISTERS[36])
328#define SRIDX (32)
329#define SR (REGISTERS[SRIDX]) /* CPU status register */
330#define FCR0IDX (71)
331#define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
332#define FCR31IDX (70)
333#define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
334#define FCSR (FCR31)
335#define Debug (REGISTERS[86])
336#define DEPC (REGISTERS[87])
337#define EPC (REGISTERS[88])
2d2733fc 338#define ACX (REGISTERS[89])
c906108c 339
40a5538e
CF		 340#define AC0LOIDX (33) /* Must be the same register as LO */
341#define AC0HIIDX (34) /* Must be the same register as HI */
342#define AC1LOIDX (90)
343#define AC1HIIDX (91)
344#define AC2LOIDX (92)
345#define AC2HIIDX (93)
346#define AC3LOIDX (94)
347#define AC3HIIDX (95)
348
349#define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]])
350#define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]])
351
352#define DSPCRIDX (96) /* DSP control register */
353#define DSPCR (REGISTERS[DSPCRIDX])
354
355#define DSPCR_POS_SHIFT (0)
356#define DSPCR_POS_MASK (0x3f)
357#define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
358
359#define DSPCR_SCOUNT_SHIFT (7)
360#define DSPCR_SCOUNT_MASK (0x3f)
361#define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
362
363#define DSPCR_CARRY_SHIFT (13)
364#define DSPCR_CARRY_MASK (1)
365#define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
366#define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT)
367
368#define DSPCR_EFI_SHIFT (14)
369#define DSPCR_EFI_MASK (1)
370#define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
371#define DSPCR_EFI (1 << DSPCR_EFI_MASK)
372
373#define DSPCR_OUFLAG_SHIFT (16)
374#define DSPCR_OUFLAG_MASK (0xff)
375#define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
376#define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4))
377#define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5))
378#define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6))
379#define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7))
380
381#define DSPCR_CCOND_SHIFT (24)
382#define DSPCR_CCOND_MASK (0xf)
383#define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
384
c906108c
SS		 385 /* All internal state modified by signal_exception() that may need to be
386 rolled back for passing moment-of-exception image back to gdb. */
387 unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
388 unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
389 int exc_suspended;
390
391#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
392#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
393#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
394
395 unsigned_word c0_config_reg;
396#define C0_CONFIG ((CPU)->c0_config_reg)
397
398/* The following are pseudonyms for standard registers */
399#define ZERO (REGISTERS[0])
400#define V0 (REGISTERS[2])
401#define A0 (REGISTERS[4])
402#define A1 (REGISTERS[5])
403#define A2 (REGISTERS[6])
404#define A3 (REGISTERS[7])
405#define T8IDX 24
406#define T8 (REGISTERS[T8IDX])
407#define SPIDX 29
408#define SP (REGISTERS[SPIDX])
409#define RAIDX 31
410#define RA (REGISTERS[RAIDX])
411
412 /* While space is allocated in the main registers arrray for some of
413 the COP0 registers, that space isn't sufficient. Unknown COP0
414 registers overflow into the array below */
415
416#define NR_COP0_GPR 32
417 unsigned_word cop0_gpr[NR_COP0_GPR];
418#define COP0_GPR ((CPU)->cop0_gpr)
1a27f959 419#define COP0_BADVADDR (COP0_GPR[8])
c906108c 420
ee7254b0
CD		 421 /* While space is allocated for the floating point registers in the
422 main registers array, they are stored separatly. This is because
423 their size may not necessarily match the size of either the
424 general-purpose or system specific registers. */
425#define NR_FGR (32)
426#define FGR_BASE FP0_REGNUM
427 fp_word fgr[NR_FGR];
428#define FGR ((CPU)->fgr)
429
c906108c
SS		 430 /* Keep the current format state for each register: */
431 FP_formats fpr_state[32];
432#define FPR_STATE ((CPU)->fpr_state)
433
434 pending_write_queue pending;
435
f4f1b9f1
CD		 436 /* The MDMX accumulator (used only for MDMX ASE). */
437 MDMX_accumulator acc;
438#define ACC ((CPU)->acc)
439
c906108c
SS		 440 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
441 read-write instructions. It is set when a linked load occurs. It
442 is tested and cleared by the conditional store. It is cleared
443 (during other CPU operations) when a store to the location would
444 no longer be atomic. In particular, it is cleared by exception
445 return instructions. */
446 int llbit;
447#define LLBIT ((CPU)->llbit)
448
449
450/* The HIHISTORY and LOHISTORY timestamps are used to ensure that
451 corruptions caused by using the HI or LO register too close to a
452 following operation is spotted. See mips.igen for more details. */
453
454 hilo_history hi_history;
455#define HIHISTORY (&(CPU)->hi_history)
456 hilo_history lo_history;
457#define LOHISTORY (&(CPU)->lo_history)
458
c906108c
SS		 459
460 sim_cpu_base base;
461};
462
463
464/* MIPS specific simulator watch config */
465
bdca5ee4 466void watch_options_install (SIM_DESC sd);
c906108c
SS		 467
468struct swatch {
469 sim_event *pc;
470 sim_event *clock;
471 sim_event *cycles;
472};
473
474
475/* FIXME: At present much of the simulator is still static */
476struct sim_state {
477
478 struct swatch watch;
479
7bebb329 480 sim_cpu *cpu[MAX_NR_PROCESSORS];
c906108c 481
c906108c
SS		 482 sim_state_base base;
483};
484
485
486
487/* Status information: */
488
489/* TODO : these should be the bitmasks for these bits within the
490 status register. At the moment the following are VR4300
491 bit-positions: */
492#define status_KSU_mask (0x18) /* mask for KSU bits */
493#define status_KSU_shift (3) /* shift for field */
494#define ksu_kernel (0x0)
495#define ksu_supervisor (0x1)
496#define ksu_user (0x2)
497#define ksu_unknown (0x3)
498
499#define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift)
500
501#define status_IE (1 << 0) /* Interrupt enable */
502#define status_EIE (1 << 16) /* Enable Interrupt Enable */
503#define status_EXL (1 << 1) /* Exception level */
504#define status_RE (1 << 25) /* Reverse Endian in user mode */
505#define status_FR (1 << 26) /* enables MIPS III additional FP registers */
506#define status_SR (1 << 20) /* soft reset or NMI */
507#define status_BEV (1 << 22) /* Location of general exception vectors */
508#define status_TS (1 << 21) /* TLB shutdown has occurred */
509#define status_ERL (1 << 2) /* Error level */
510#define status_IM7 (1 << 15) /* Timer Interrupt Mask */
511#define status_RP (1 << 27) /* Reduced Power mode */
512
513/* Specializations for TX39 family */
514#define status_IEc (1 << 0) /* Interrupt enable (current) */
515#define status_KUc (1 << 1) /* Kernel/User mode */
516#define status_IEp (1 << 2) /* Interrupt enable (previous) */
517#define status_KUp (1 << 3) /* Kernel/User mode */
518#define status_IEo (1 << 4) /* Interrupt enable (old) */
519#define status_KUo (1 << 5) /* Kernel/User mode */
520#define status_IM_mask (0xff) /* Interrupt mask */
521#define status_IM_shift (8)
522#define status_NMI (1 << 20) /* NMI */
523#define status_NMI (1 << 20) /* NMI */
524
d35d4f70
CD		 525/* Status bits used by MIPS32/MIPS64. */
526#define status_UX (1 << 5) /* 64-bit user addrs */
527#define status_SX (1 << 6) /* 64-bit supervisor addrs */
528#define status_KX (1 << 7) /* 64-bit kernel addrs */
529#define status_TS (1 << 21) /* TLB shutdown has occurred */
530#define status_PX (1 << 23) /* Enable 64 bit operations */
531#define status_MX (1 << 24) /* Enable MDMX resources */
532#define status_CU0 (1 << 28) /* Coprocessor 0 usable */
533#define status_CU1 (1 << 29) /* Coprocessor 1 usable */
534#define status_CU2 (1 << 30) /* Coprocessor 2 usable */
535#define status_CU3 (1 << 31) /* Coprocessor 3 usable */
7cbea089
CD		 536/* Bits reserved for implementations: */
537#define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */
d35d4f70 538
c906108c
SS		 539#define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
540#define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
541#define cause_CE_mask 0x30000000 /* Coprocessor exception */
542#define cause_CE_shift 28
543#define cause_EXC2_mask 0x00070000
544#define cause_EXC2_shift 16
545#define cause_IP7 (1 << 15) /* Interrupt pending */
546#define cause_SIOP (1 << 12) /* SIO pending */
547#define cause_IP3 (1 << 11) /* Int 0 pending */
548#define cause_IP2 (1 << 10) /* Int 1 pending */
549
550#define cause_EXC_mask (0x1c) /* Exception code */
551#define cause_EXC_shift (2)
552
553#define cause_SW0 (1 << 8) /* Software interrupt 0 */
554#define cause_SW1 (1 << 9) /* Software interrupt 1 */
555#define cause_IP_mask (0x3f) /* Interrupt pending field */
556#define cause_IP_shift (10)
557
558#define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask)
559#define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
560
561
562/* NOTE: We keep the following status flags as bit values (1 for true,
563 0 for false). This allows them to be used in binary boolean
564 operations without worrying about what exactly the non-zero true
565 value is. */
566
567/* UserMode */
568#ifdef SUBTARGET_R3900
569#define UserMode ((SR & status_KUc) ? 1 : 0)
570#else
571#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
572#endif /* SUBTARGET_R3900 */
573
574/* BigEndianMem */
575/* Hardware configuration. Affects endianness of LoadMemory and
576 StoreMemory and the endianness of Kernel and Supervisor mode
577 execution. The value is 0 for little-endian; 1 for big-endian. */
578#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
579/*(state & simBE) ? 1 : 0)*/
580
581/* ReverseEndian */
582/* This mode is selected if in User mode with the RE bit being set in
583 SR (Status Register). It reverses the endianness of load and store
584 instructions. */
585#define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
586
587/* BigEndianCPU */
588/* The endianness for load and store instructions (0=little;1=big). In
589 User mode this endianness may be switched by setting the state_RE
590 bit in the SR register. Thus, BigEndianCPU may be computed as
591 (BigEndianMem EOR ReverseEndian). */
592#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
593
594
595
596/* Exceptions: */
597
598/* NOTE: These numbers depend on the processor architecture being
599 simulated: */
600enum ExceptionCause {
601 Interrupt = 0,
602 TLBModification = 1,
603 TLBLoad = 2,
604 TLBStore = 3,
605 AddressLoad = 4,
606 AddressStore = 5,
607 InstructionFetch = 6,
608 DataReference = 7,
609 SystemCall = 8,
610 BreakPoint = 9,
611 ReservedInstruction = 10,
612 CoProcessorUnusable = 11,
613 IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */
614 Trap = 13,
615 FPE = 15,
d35d4f70
CD		 616 DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */
617 MDMX = 22,
c906108c 618 Watch = 23,
d35d4f70
CD		 619 MCheck = 24,
620 CacheErr = 30,
621 NMIReset = 31, /* Reserved in MIPS32/MIPS64. */
c906108c
SS		 622
623
624/* The following exception code is actually private to the simulator
625 world. It is *NOT* a processor feature, and is used to signal
626 run-time errors in the simulator. */
627 SimulatorFault = 0xFFFFFFFF
628};
629
630#define TLB_REFILL (0)
631#define TLB_INVALID (1)
632
633
634/* The following break instructions are reserved for use by the
635 simulator. The first is used to halt the simulation. The second
636 is used by gdb for break-points. NOTE: Care must be taken, since
637 this value may be used in later revisions of the MIPS ISA. */
638#define HALT_INSTRUCTION_MASK (0x03FFFFC0)
639
640#define HALT_INSTRUCTION (0x03ff000d)
641#define HALT_INSTRUCTION2 (0x0000ffcd)
642
643
644#define BREAKPOINT_INSTRUCTION (0x0005000d)
645#define BREAKPOINT_INSTRUCTION2 (0x0000014d)
646
647
648
649void interrupt_event (SIM_DESC sd, void *data);
650
651void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
652#define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
653#define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level)
654#define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
655#define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
656#define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
657#define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference)
658#define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
659#define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
660#define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
3ad6f714 661#define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
c906108c
SS		 662#define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
663#define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
664#define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
665#define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
666#define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
667#define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification)
d35d4f70
CD		 668#define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX)
669#define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch)
670#define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck)
671#define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr)
c906108c
SS		 672
673/* Co-processor accesses */
674
3ad6f714
CD		 675/* XXX FIXME: For now, assume that FPU (cp1) is always usable. */
676#define COP_Usable(coproc_num) (coproc_num == 1)
677
bdca5ee4
TT		 678void cop_lw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword);
679void cop_ld (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword);
680unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
681uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
c906108c
SS		 682
683#define COP_LW(coproc_num,coproc_reg,memword) \
684cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
685#define COP_LD(coproc_num,coproc_reg,memword) \
686cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
687#define COP_SW(coproc_num,coproc_reg) \
688cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
689#define COP_SD(coproc_num,coproc_reg) \
690cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
691
692
bdca5ee4 693void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction);
c906108c
SS		 694#define DecodeCoproc(instruction) \
695decode_coproc (SD, CPU, cia, (instruction))
696
8030f857 697int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
c906108c
SS		 698
699
18d8a52d
CD		 700/* FPR access. */
701unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
702#define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
703void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
704#define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
3a2b820e
CD		 705unsigned64 ps_lower (SIM_STATE, unsigned64 op);
706#define PSLower(op) ps_lower (SIM_ARGS, op)
707unsigned64 ps_upper (SIM_STATE, unsigned64 op);
708#define PSUpper(op) ps_upper (SIM_ARGS, op)
709unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
710#define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
18d8a52d
CD		 711
712
cfe9ea23
CD		 713/* FCR access. */
714unsigned_word value_fcr (SIM_STATE, int fcr);
715#define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
716void store_fcr (SIM_STATE, int fcr, unsigned_word value);
717#define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
718void test_fcsr (SIM_STATE);
719#define TestFCSR() test_fcsr (SIM_ARGS)
720
721
18d8a52d 722/* FPU operations. */
cfe9ea23
CD		 723void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
724#define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
ba46ddd0
CD		 725unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
726#define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
727unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
728#define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
729unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
730#define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
731unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
732#define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
733unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
734#define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
735unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
736#define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
737unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
738#define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
739unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
740#define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
f3c08b7e
CD		 741unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
742#define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
743unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
744 unsigned64 op3, FP_formats fmt);
745#define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
746unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
747 unsigned64 op3, FP_formats fmt);
748#define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
749unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
750 unsigned64 op3, FP_formats fmt);
751#define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
752unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
753 unsigned64 op3, FP_formats fmt);
754#define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
18d8a52d
CD		 755unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
756#define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
3a2b820e
CD		 757unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
758 FP_formats to);
759#define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
18d8a52d
CD		 760
761
e7e81181
CD		 762/* MIPS-3D ASE operations. */
763#define CompareAbs(op1,op2,fmt,cond,cc) \
764fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
765unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
766#define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
767unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
768#define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
769unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
770#define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
771unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
772#define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
773unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
774#define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
775unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
776#define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
777
778
f4f1b9f1
CD		 779/* MDMX access. */
780
781typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */
782#define ob_fmtsel(sel) (((sel)<<1)|0x0)
783#define qh_fmtsel(sel) (((sel)<<2)|0x1)
784
785#define fmt_mdmx fmt_uninterpreted
786
787#define MX_VECT_AND (0)
788#define MX_VECT_NOR (1)
789#define MX_VECT_OR (2)
790#define MX_VECT_XOR (3)
791#define MX_VECT_SLL (4)
792#define MX_VECT_SRL (5)
f4f1b9f1
CD		 793#define MX_VECT_ADD (6)
794#define MX_VECT_SUB (7)
795#define MX_VECT_MIN (8)
796#define MX_VECT_MAX (9)
797#define MX_VECT_MUL (10)
798#define MX_VECT_MSGN (11)
799#define MX_VECT_SRA (12)
7cbea089
CD		 800#define MX_VECT_ABSD (13) /* SB-1 only. */
801#define MX_VECT_AVG (14) /* SB-1 only. */
f4f1b9f1
CD		 802
803unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
804#define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
805#define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
806#define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
807#define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
808#define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
809#define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
810#define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
811#define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel)
812#define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
813#define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
814#define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
815#define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
816#define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
7cbea089
CD		 817#define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
818#define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
f4f1b9f1
CD		 819
820#define MX_C_EQ 0x1
821#define MX_C_LT 0x4
822
823void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
824#define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
825
826unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
827#define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
828
829#define MX_VECT_ADDA (0)
830#define MX_VECT_ADDL (1)
831#define MX_VECT_MULA (2)
832#define MX_VECT_MULL (3)
833#define MX_VECT_MULS (4)
834#define MX_VECT_MULSL (5)
835#define MX_VECT_SUBA (6)
836#define MX_VECT_SUBL (7)
7cbea089 837#define MX_VECT_ABSDA (8) /* SB-1 only. */
f4f1b9f1
CD		 838
839void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
840#define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
841#define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
842#define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
843#define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
844#define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
845#define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
846#define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
847#define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
7cbea089 848#define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
f4f1b9f1
CD		 849
850#define MX_FMT_OB (0)
851#define MX_FMT_QH (1)
852
853/* The following codes chosen to indicate the units of shift. */
854#define MX_RAC_L (0)
855#define MX_RAC_M (1)
856#define MX_RAC_H (2)
857
858unsigned64 mdmx_rac_op (SIM_STATE, int, int);
859#define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
860
861void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
862#define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
863void mdmx_wach (SIM_STATE, int, unsigned64);
864#define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
865
866#define MX_RND_AS (0)
867#define MX_RND_AU (1)
868#define MX_RND_ES (2)
869#define MX_RND_EU (3)
870#define MX_RND_ZS (4)
871#define MX_RND_ZU (5)
872
873unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
874#define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
875#define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
876#define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
877#define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
878#define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
879#define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
880
881unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
882#define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
883
884
c906108c
SS		 885
886/* Memory accesses */
887
888/* The following are generic to all versions of the MIPS architecture
889 to date: */
890
891/* Memory Access Types (for CCA): */
892#define Uncached (0)
893#define CachedNoncoherent (1)
894#define CachedCoherent (2)
895#define Cached (3)
896
897#define isINSTRUCTION (1 == 0) /* FALSE */
898#define isDATA (1 == 1) /* TRUE */
899#define isLOAD (1 == 0) /* FALSE */
900#define isSTORE (1 == 1) /* TRUE */
901#define isREAL (1 == 0) /* FALSE */
902#define isRAW (1 == 1) /* TRUE */
903/* The parameter HOST (isTARGET / isHOST) is ignored */
904#define isTARGET (1 == 0) /* FALSE */
905/* #define isHOST (1 == 1) TRUE */
906
907/* The "AccessLength" specifications for Loads and Stores. NOTE: This
908 is the number of bytes minus 1. */
909#define AccessLength_BYTE (0)
910#define AccessLength_HALFWORD (1)
911#define AccessLength_TRIPLEBYTE (2)
912#define AccessLength_WORD (3)
913#define AccessLength_QUINTIBYTE (4)
914#define AccessLength_SEXTIBYTE (5)
915#define AccessLength_SEPTIBYTE (6)
916#define AccessLength_DOUBLEWORD (7)
917#define AccessLength_QUADWORD (15)
918
919#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
920 ? AccessLength_DOUBLEWORD /*7*/ \
921 : AccessLength_WORD /*3*/)
922#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
923
924
bdca5ee4 925INLINE_SIM_MAIN (int) address_translation (SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw);
c906108c
SS		 926#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
927address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
928
bdca5ee4 929INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
c906108c
SS		 930#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
931load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
932
bdca5ee4 933INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
c906108c
SS		 934#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
935store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
936
bdca5ee4 937INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
c906108c
SS		 938#define CacheOp(op,pAddr,vAddr,instruction) \
939cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
940
bdca5ee4 941INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype);
c906108c
SS		 942#define SyncOperation(stype) \
943sync_operation (SD, CPU, cia, (stype))
944
bdca5ee4 945INLINE_SIM_MAIN (void) prefetch (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint);
c906108c
SS		 946#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
947prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
948
402586aa
CD		 949void unpredictable_action (sim_cpu *cpu, address_word cia);
950#define NotWordValue(val) not_word_value (SD_, (val))
951#define Unpredictable() unpredictable (SD_)
f4f1b9f1 952#define UnpredictableResult() /* For now, do nothing. */
b96e7ef1 953
bdca5ee4 954INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
c906108c 955#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
bdca5ee4 956INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
c906108c
SS		 957#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
958#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
959
29bc024d 960#if WITH_TRACE_ANY_P
bdca5ee4 961void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...);
c906108c 962extern FILE *tracefh;
29bc024d
MF		 963#else
964#define dotrace(sd, cpu, tracefh, type, address, width, comment, ...)
965#endif
c906108c 966
40a5538e
CF		 967extern int DSPLO_REGNUM[4];
968extern int DSPHI_REGNUM[4];
969
bdca5ee4 970INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia);
c906108c
SS		 971extern SIM_CORE_SIGNAL_FN mips_core_signal;
972
bdca5ee4
TT		 973char* pr_addr (SIM_ADDR addr);
974char* pr_uword64 (uword64 addr);
c906108c
SS		 975
976
4c0deff4 977#define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
4c0deff4 978
c906108c
SS		 979void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
980void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
981void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
982
4c54fc26
CD		 983#ifdef MIPS_MACH_MULTI
984extern int mips_mach_multi(SIM_DESC sd);
985#define MIPS_MACH(SD) mips_mach_multi(SD)
986#else
987#define MIPS_MACH(SD) MIPS_MACH_DEFAULT
988#endif
c906108c 989
0e1b7197
RS		 990/* Macros for determining whether a MIPS IV or MIPS V part is subject
991 to the hi/lo restrictions described in mips.igen. */
992
993#define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
994 (MIPS_MACH (SD) != bfd_mach_mips5500)
995
996#define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
997 (MIPS_MACH (SD) != bfd_mach_mips5500)
998
999#define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
1000 (MIPS_MACH (SD) != bfd_mach_mips5500)
1001
c906108c
SS		 1002#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1003#include "sim-main.c"
1004#endif
1005
1006#endif
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