projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* sim-main.h: shadow NUM_CORE_REGS from tm-txvu.h
[deliverable/binutils-gdb.git] / sim / mips / sim-main.h
CommitLineData
18c64df6 1/* MIPS Simulator definition.
eb00d706 2 Copyright (C) 1997, 1998 Free Software Foundation, Inc.
18c64df6
AC		 3 Contributed by Cygnus Support.
4
5This file is part of GDB, the GNU debugger.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License along
18with this program; if not, write to the Free Software Foundation, Inc.,
1959 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#ifndef SIM_MAIN_H
22#define SIM_MAIN_H
23
24/* This simulator doesn't cache the Current Instruction Address */
7ce8b917
AC		 25/* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
26/* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
18c64df6
AC		 27
28#define SIM_HAVE_BIENDIAN
18c64df6
AC		 29
30
31/* hobble some common features for moment */
18c64df6 32#define WITH_WATCHPOINTS 1
63be8feb 33#define WITH_MODULO_MEMORY 1
18c64df6
AC		 34
35#include "sim-basics.h"
36
dad6f1f3 37typedef address_word sim_cia;
18c64df6 38
63be8feb
AC		 39#if (WITH_IGEN)
40/* Get the number of instructions. FIXME: must be a more elegant way
41 of doing this. */
42#include "itable.h"
43#define MAX_INSNS (nr_itable_entries)
eb00d706 44#define INSN_NAME(cpu,i) itable[(i)].name
63be8feb
AC		 45#endif
46
18c64df6
AC		 47#include "sim-base.h"
48
49
50/* Depreciated macros and types for manipulating 64bit values. Use
51 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
52
53typedef signed64 word64;
54typedef unsigned64 uword64;
55
56#define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
57#define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
58#define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
59#define SET64HI(t) (((uword64)(t))<<32)
60#define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
61#define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
62
63/* Sign-extend the given value (e) as a value (b) bits long. We cannot
64 assume the HI32bits of the operand are zero, so we must perform a
65 mask to ensure we can use the simple subtraction to sign-extend. */
66#define SIGNEXTEND(e,b) \
fb5a2a3e 67 ((unsigned_word) \
18c64df6
AC		 68 (((e) & ((uword64) 1 << ((b) - 1))) \
69 ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
fb5a2a3e 70 : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
18c64df6
AC		 71
72/* Check if a value will fit within a halfword: */
73#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
74
18c64df6 75
ea985d24 76
0c2c5f61
AC		 77/* Floating-point operations: */
78
2d44e12a
AC		 79#include "sim-fpu.h"
80
0c2c5f61
AC		 81/* FPU registers must be one of the following types. All other values
82 are reserved (and undefined). */
83typedef enum {
84 fmt_single = 0,
85 fmt_double = 1,
86 fmt_word = 4,
87 fmt_long = 5,
88 /* The following are well outside the normal acceptable format
89 range, and are used in the register status vector. */
90 fmt_unknown = 0x10000000,
91 fmt_uninterpreted = 0x20000000,
a09a30d2
AC		 92 fmt_uninterpreted_32 = 0x40000000,
93 fmt_uninterpreted_64 = 0x80000000,
0c2c5f61
AC		 94} FP_formats;
95
01737f42
AC		 96unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
97#define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
0c2c5f61 98
01737f42
AC		 99void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
100#define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
0c2c5f61
AC		 101
102int NaN PARAMS ((unsigned64 op, FP_formats fmt));
103int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
104int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
105int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
106unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
107unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
108unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
109unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
110unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
111unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
112unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
113unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
a48e8c8d
AC		 114unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
115unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
01737f42
AC		 116unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
117#define Convert(rm,op,from,to) \
118convert (SD, CPU, cia, rm, op, from, to)
0c2c5f61 119
ea985d24
AC		 120/* Macro to update FPSR condition-code field. This is complicated by
121 the fact that there is a hole in the index range of the bits within
122 the FCSR register. Also, the number of bits visible depends on the
123 MIPS ISA version being supported. */
124
125#define SETFCC(cc,v) {\
126 int bit = ((cc == 0) ? 23 : (24 + (cc)));\
127 FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
128}
ca6f76d1 129#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
ea985d24
AC		 130
131/* This should be the COC1 value at the start of the preceding
132 instruction: */
133#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
134
135#if 1
a48e8c8d 136#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
ea985d24
AC		 137#else
138/* They depend on the CPU being simulated */
139#define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
140#endif
141
142/* Standard FCRS bits: */
143#define IR (0) /* Inexact Result */
144#define UF (1) /* UnderFlow */
145#define OF (2) /* OverFlow */
146#define DZ (3) /* Division by Zero */
147#define IO (4) /* Invalid Operation */
148#define UO (5) /* Unimplemented Operation */
149
150/* Get masks for individual flags: */
151#if 1 /* SAFE version */
152#define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
153#define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
154#define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
155#else
156#define FP_FLAGS(b) (1 << ((b) + 2))
157#define FP_ENABLE(b) (1 << ((b) + 7))
158#define FP_CAUSE(b) (1 << ((b) + 12))
159#endif
160
161#define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
162
163#define FP_MASK_RM (0x3)
164#define FP_SH_RM (0)
165#define FP_RM_NEAREST (0) /* Round to nearest (Round) */
166#define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
167#define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
168#define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
169#define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
170
8c8dd0c4
JL		 171/* start-sanitize-sky */
172#ifdef TARGET_SKY
173#ifdef SKY_FUNIT
60372a3f 174#include <assert.h>
8c8dd0c4
JL		 175#include "wf.h"
176#endif
177#endif
178/* end-sanitize-sky */
179
180
181
ea985d24
AC		 182
183
421cbaae
AC		 184/* HI/LO register accesses */
185
186/* For some MIPS targets, the HI/LO registers have certain timing
187 restrictions in that, for instance, a read of a HI register must be
188 separated by at least three instructions from a preceeding read.
189
190 The struct below is used to record the last access by each of A MT,
191 MF or other OP instruction to a HI/LO register. See mips.igen for
192 more details. */
193
194typedef struct _hilo_access {
195 signed64 timestamp;
196 address_word cia;
197} hilo_access;
198
199typedef struct _hilo_history {
200 hilo_access mt;
201 hilo_access mf;
202 hilo_access op;
203} hilo_history;
204
205
206
207
ea985d24
AC		 208/* Integer ALU operations: */
209
210#include "sim-alu.h"
211
212#define ALU32_END(ANS) \
213 if (ALU32_HAD_OVERFLOW) \
214 SignalExceptionIntegerOverflow (); \
895a7dc2 215 (ANS) = (signed32) ALU32_OVERFLOW_RESULT
ea985d24
AC		 216
217
218#define ALU64_END(ANS) \
219 if (ALU64_HAD_OVERFLOW) \
220 SignalExceptionIntegerOverflow (); \
92ad193b 221 (ANS) = ALU64_OVERFLOW_RESULT;
ea985d24 222
a48e8c8d 223
ea985d24
AC		 224/* start-sanitize-r5900 */
225
f89c0689
AC		 226/* Figure 10-5 FPU Control/Status Register.
227 Note: some of these bits are different to what is found in a
228 standard MIPS manual. */
229enum {
230 R5900_FCSR_C = BIT (23), /* OK */
231 R5900_FCSR_I = BIT (17),
232 R5900_FCSR_D = BIT (16),
233 R5900_FCSR_O = BIT (15),
234 R5900_FCSR_U = BIT (14),
235 R5900_FCSR_CAUSE = MASK (16,14),
236 R5900_FCSR_SI = BIT (6),
237 R5900_FCSR_SD = BIT (5),
238 R5900_FCSR_SO = BIT (4),
239 R5900_FCSR_SU = BIT (3),
240};
241
421cbaae
AC		 242/* Table 10-1 FP format values.
243 Note: some of these bits are different to what is found in a
244 standard MIPS manual. */
245enum {
246 R5900_EXPMAX = 128,
247 R5900_EXPMIN = -127,
248 R5900_EXPBIAS = 127,
249};
250
eb00d706
DE		 251/* MAX and MIN FP values */
252enum {
253 R5900_FPMAX = LSMASK32 (30, 0),
254 R5900_FPMIN = LSMASK32 (31, 0),
255};
256
421cbaae
AC		 257
258
a48e8c8d
AC		 259typedef struct _sim_r5900_cpu {
260
261 /* The R5900 has 32 x 128bit general purpose registers.
262 Fortunatly, the high 64 bits are only touched by multimedia (MMI)
263 instructions. The normal mips instructions just use the lower 64
264 bits. To avoid changing the older parts of the simulator to
265 handle this weirdness, the high 64 bits of each register are kept
266 in a separate array (registers1). The high 64 bits of any
267 register are by convention refered by adding a '1' to the end of
268 the normal register's name. So LO still refers to the low 64
269 bits of the LO register, LO1 refers to the high 64 bits of that
270 same register. */
271 signed_word gpr1[32];
272#define GPR1 ((CPU)->r5900.gpr1)
273 signed_word lo1;
274 signed_word hi1;
275#define LO1 ((CPU)->r5900.lo1)
276#define HI1 ((CPU)->r5900.hi1)
277
278 /* The R5900 defines a shift amount register, that controls the
279 amount of certain shift instructions */
280 unsigned_word sa; /* the shift amount register */
281#define REGISTER_SA (124) /* GET RID IF THIS! */
282#define SA ((CPU)->r5900.sa)
283
284 /* The R5900, in addition to the (almost) standard floating point
285 registers, defines a 32 bit accumulator. This is used in
286 multiply/accumulate style instructions */
287 fp_word acc; /* floating-point accumulator */
288#define ACC ((CPU)->r5900.acc)
289
290 /* See comments below about needing to count cycles between updating
291 and setting HI/LO registers */
421cbaae
AC		 292 hilo_history hi1_history;
293#define HI1HISTORY (&(CPU)->r5900.hi1_history)
294 hilo_history lo1_history;
295#define LO1HISTORY (&(CPU)->r5900.lo1_history)
a48e8c8d
AC		 296
297} sim_r5900_cpu;
298
ea985d24
AC		 299#define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word))
300#define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
301#define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
302#define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
303
304#define BYTES_IN_MIPS_REGS (sizeof(signed_word))
305#define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
306#define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
307#define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
308
309/* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
310 T - type of the sub part
311 TC - # of T's in the mips part of the "register"
312 I - index (from 0) of desired sub part
313 A - low part of "register"
314 A1 - high part of register
315*/
316#define SUB_REG_FETCH(T,TC,A,A1,I) \
317(*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
318 + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
319 ? ((TC) - 1 - (I) % (TC)) \
320 : ((I) % (TC)) \
321 ) \
322 ) \
323 )
324
325/*
326GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
327 where <type> has two letters:
328 1 is S=signed or U=unsigned
329 2 is B=byte H=halfword W=word D=doubleword
330*/
331
332#define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I)
333#define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
334#define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I)
335#define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
336
337#define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I)
338#define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
339#define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
340#define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
341
a48e8c8d
AC		 342#define GPR_SB(R,I) SUB_REG_SB(&GPR[R], &GPR1[R], I)
343#define GPR_SH(R,I) SUB_REG_SH(&GPR[R], &GPR1[R], I)
344#define GPR_SW(R,I) SUB_REG_SW(&GPR[R], &GPR1[R], I)
345#define GPR_SD(R,I) SUB_REG_SD(&GPR[R], &GPR1[R], I)
ea985d24 346
a48e8c8d
AC		 347#define GPR_UB(R,I) SUB_REG_UB(&GPR[R], &GPR1[R], I)
348#define GPR_UH(R,I) SUB_REG_UH(&GPR[R], &GPR1[R], I)
349#define GPR_UW(R,I) SUB_REG_UW(&GPR[R], &GPR1[R], I)
350#define GPR_UD(R,I) SUB_REG_UD(&GPR[R], &GPR1[R], I)
ea985d24
AC		 351
352
353#define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
354#define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
355#define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
356#define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
357
358#define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
359#define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
360#define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
361#define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
362
363#define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
364#define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
365#define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
366#define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
367
368#define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
369#define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
370#define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
371#define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
372
373
374
375#define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
376#define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
377#define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
378#define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
379
380#define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
381#define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
382#define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
383#define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
384
385#define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
386#define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
387#define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
388#define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
389
390#define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
391#define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
392#define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
393#define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
394
395/* end-sanitize-r5900 */
396
0c2c5f61
AC		 397
398
2acd126a
AC		 399/* The following is probably not used for MIPS IV onwards: */
400/* Slots for delayed register updates. For the moment we just have a
401 fixed number of slots (rather than a more generic, dynamic
402 system). This keeps the simulator fast. However, we only allow
403 for the register update to be delayed for a single instruction
404 cycle. */
405#define PSLOTS (8) /* Maximum number of instruction cycles */
406
407typedef struct _pending_write_queue {
408 int in;
409 int out;
410 int total;
411 int slot_delay[PSLOTS];
412 int slot_size[PSLOTS];
413 int slot_bit[PSLOTS];
414 void *slot_dest[PSLOTS];
415 unsigned64 slot_value[PSLOTS];
416} pending_write_queue;
417
418#ifndef PENDING_TRACE
419#define PENDING_TRACE 0
420#endif
421#define PENDING_IN ((CPU)->pending.in)
422#define PENDING_OUT ((CPU)->pending.out)
423#define PENDING_TOTAL ((CPU)->pending.total)
424#define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
425#define PENDING_SLOT_BIT ((CPU)->pending.slot_size)
426#define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
427#define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
428#define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
429
430/* Invalidate the pending write queue, all pending writes are
431 discarded. */
432
433#define PENDING_INVALIDATE() \
434memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
435
436/* Schedule a write to DEST for N cycles time. For 64 bit
437 destinations, schedule two writes. For floating point registers,
438 the caller should schedule a write to both the dest register and
439 the FPR_STATE register. When BIT is non-negative, only BIT of DEST
440 is updated. */
441
442#define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
443 do { \
444 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
445 sim_engine_abort (SD, CPU, cia, \
446 "PENDING_SCHED - buffer overflow\n"); \
447 if (PENDING_TRACE) \
448 sim_io_printf (SD, "PENDING_SCHED - dest 0x%lx, val 0x%lx, pending_in %d, pending_out %d, pending_total %d\n", (unsigned long) (DEST), (unsigned long) (VAL), PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
449 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
450 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
451 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
452 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
453 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
454 } while (0)
455
456#define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
457#define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
458
459#define PENDING_TICK() pending_tick (SD, CPU, cia)
460
461#define PENDING_FLUSH() abort () /* think about this one */
462#define PENDING_FP() abort () /* think about this one */
463
464/* For backward compatibility */
465#define PENDING_FILL(R,VAL) \
466{ \
467 if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR) \
468 PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 2, -1); \
469 else \
470 PENDING_SCHED(GPR[(R)], VAL, 2, -1); \
471}
472
473
0c2c5f61 474
18c64df6 475struct _sim_cpu {
0c2c5f61
AC		 476
477
478 /* The following are internal simulator state variables: */
9ec6741b
AC		 479#define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
480#define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
0c2c5f61 481 address_word dspc; /* delay-slot PC */
01737f42 482#define DSPC ((CPU)->dspc)
0c2c5f61 483
f3bdd368 484#if !WITH_IGEN
dad6f1f3
AC		 485 /* Issue a delay slot instruction immediatly by re-calling
486 idecode_issue */
487#define DELAY_SLOT(TARGET) \
488 do { \
489 address_word target = (TARGET); \
490 instruction_word delay_insn; \
01737f42 491 sim_events_slip (SD, 1); \
a48e8c8d 492 CIA = CIA + 4; /* NOTE not mips16 */ \
dad6f1f3 493 STATE |= simDELAYSLOT; \
a48e8c8d 494 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ \
01737f42 495 idecode_issue (CPU_, delay_insn, (CIA)); \
7ce8b917
AC		 496 STATE &= ~simDELAYSLOT; \
497 NIA = target; \
dad6f1f3
AC		 498 } while (0)
499#define NULLIFY_NEXT_INSTRUCTION() \
500 do { \
01737f42
AC		 501 sim_events_slip (SD, 1); \
502 dotrace (SD, CPU, tracefh, 2, NIA, 4, "load instruction"); \
7ce8b917 503 NIA = CIA + 8; \
dad6f1f3 504 } while (0)
f3bdd368
AC		 505#else
506#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
507#define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
508#endif
509
ea985d24 510
0c2c5f61
AC		 511 /* State of the simulator */
512 unsigned int state;
513 unsigned int dsstate;
01737f42
AC		 514#define STATE ((CPU)->state)
515#define DSSTATE ((CPU)->dsstate)
0c2c5f61 516
ea985d24
AC		 517/* Flags in the "state" variable: */
518#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
519#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
520#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
ea985d24
AC		 521#define simPCOC0 (1 << 17) /* COC[1] from current */
522#define simPCOC1 (1 << 18) /* COC[1] from previous */
523#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
524#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
525#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
526#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
527
a09a30d2
AC		 528#define ENGINE_ISSUE_PREFIX_HOOK() \
529 { \
2acd126a
AC		 530 /* Perform any pending writes */ \
531 PENDING_TICK(); \
a09a30d2
AC		 532 /* Set previous flag, depending on current: */ \
533 if (STATE & simPCOC0) \
534 STATE |= simPCOC1; \
535 else \
536 STATE &= ~simPCOC1; \
537 /* and update the current value: */ \
538 if (GETFCC(0)) \
539 STATE |= simPCOC0; \
540 else \
541 STATE &= ~simPCOC0; \
542 }
ea985d24 543
0c2c5f61
AC		 544
545/* This is nasty, since we have to rely on matching the register
546 numbers used by GDB. Unfortunately, depending on the MIPS target
547 GDB uses different register numbers. We cannot just include the
548 relevant "gdb/tm.h" link, since GDB may not be configured before
549 the sim world, and also the GDB header file requires too much other
550 state. */
551
552#ifndef TM_MIPS_H
553#define LAST_EMBED_REGNUM (89)
554#define NUM_REGS (LAST_EMBED_REGNUM + 1)
555/* start-sanitize-r5900 */
556#undef NUM_REGS
557#define NUM_REGS (128)
558/* end-sanitize-r5900 */
559#endif
560
a48e8c8d
AC		 561/* start-sanitize-sky */
562#ifdef TARGET_SKY
563#ifndef TM_TXVU_H
a48e8c8d 564/* Number of machine registers */
2151467d
RU		 565#define NUM_VU_REGS 153
566#define NUM_VU_INTEGER_REGS 16
a48e8c8d 567
2905d173 568#define NUM_VIF_REGS 26
64ed8b6a 569
2151467d 570#define FIRST_VEC_REG 25
b8140a08 571#define NUM_CORE_REGS 128
a48e8c8d
AC		 572
573#undef NUM_REGS
b8140a08 574#define NUM_REGS (NUM_CORE_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
a48e8c8d 575#endif /* no tm-txvu.h */
3fa454e9
FCE		 576#endif /* TARGET_SKY */
577/* end-sanitize-sky */
8c8dd0c4
JL		 578
579enum float_operation
580/* start-sanitize-sky */
581/* NOTE: THE VALUES of THESE CONSTANTS MUST BE IN SYNC WITH THOSE IN WF.H */
a48e8c8d 582/* end-sanitize-sky */
8c8dd0c4
JL		 583 {
584 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
585 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
586 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
587 };
a48e8c8d 588
0c2c5f61
AC		 589/* To keep this default simulator simple, and fast, we use a direct
590 vector of registers. The internal simulator engine then uses
591 manifests to access the correct slot. */
592
fb5a2a3e 593 unsigned_word registers[LAST_EMBED_REGNUM + 1];
0c2c5f61 594 int register_widths[NUM_REGS];
01737f42 595#define REGISTERS ((CPU)->registers)
0c2c5f61
AC		 596
597#define GPR (&REGISTERS[0])
2d44e12a 598#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
a48e8c8d
AC		 599
600 /* While space is allocated for the floating point registers in the
601 main registers array, they are stored separatly. This is because
602 their size may not necessarily match the size of either the
603 general-purpose or system specific registers */
2acd126a 604#define NR_FGR (32)
0c2c5f61 605#define FGRIDX (38)
a48e8c8d
AC		 606 fp_word fgr[NR_FGR];
607#define FGR ((CPU)->fgr)
608
0c2c5f61
AC		 609#define LO (REGISTERS[33])
610#define HI (REGISTERS[34])
9ec6741b
AC		 611#define PCIDX 37
612#define PC (REGISTERS[PCIDX])
0c2c5f61
AC		 613#define CAUSE (REGISTERS[36])
614#define SRIDX (32)
615#define SR (REGISTERS[SRIDX]) /* CPU status register */
616#define FCR0IDX (71)
617#define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
618#define FCR31IDX (70)
619#define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
620#define FCSR (FCR31)
621#define Debug (REGISTERS[86])
622#define DEPC (REGISTERS[87])
623#define EPC (REGISTERS[88])
624#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
625
a09a30d2 626 unsigned_word c0_config_reg;
01737f42 627#define C0_CONFIG ((CPU)->c0_config_reg)
a09a30d2 628
0c2c5f61
AC		 629/* The following are pseudonyms for standard registers */
630#define ZERO (REGISTERS[0])
631#define V0 (REGISTERS[2])
632#define A0 (REGISTERS[4])
633#define A1 (REGISTERS[5])
634#define A2 (REGISTERS[6])
635#define A3 (REGISTERS[7])
c0a4c3ba
AC		 636#define T8IDX 24
637#define T8 (REGISTERS[T8IDX])
638#define SPIDX 29
639#define SP (REGISTERS[SPIDX])
640#define RAIDX 31
641#define RA (REGISTERS[RAIDX])
0c2c5f61 642
46eb9e5a
GRK		 643 /* While space is allocated in the main registers arrray for some of
644 the COP0 registers, that space isn't sufficient. Unknown COP0
645 registers overflow into the array below */
646
647#define NR_COP0_GPR 32
648 unsigned_word cop0_gpr[NR_COP0_GPR];
649#define COP0_GPR ((CPU)->cop0_gpr)
650 /* start-sanitize-r5900 */
651#define NR_COP0_BP 8
652 unsigned_word cop0_bp[NR_COP0_BP];
653#define COP0_BP ((CPU)->cop0_bp)
654#define NR_COP0_P 64
655 unsigned_word cop0_p[NR_COP0_P];
656#define COP0_P ((CPU)->cop0_p)
657 /* end-sanitize-r5900 */
658
659
0c2c5f61
AC		 660 /* Keep the current format state for each register: */
661 FP_formats fpr_state[32];
01737f42 662#define FPR_STATE ((CPU)->fpr_state)
0c2c5f61 663
2acd126a 664 pending_write_queue pending;
0c2c5f61
AC		 665
666 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
667 read-write instructions. It is set when a linked load occurs. It
668 is tested and cleared by the conditional store. It is cleared
669 (during other CPU operations) when a store to the location would
670 no longer be atomic. In particular, it is cleared by exception
671 return instructions. */
672 int llbit;
01737f42 673#define LLBIT ((CPU)->llbit)
0c2c5f61
AC		 674
675
421cbaae
AC		 676/* The HIHISTORY and LOHISTORY timestamps are used to ensure that
677 corruptions caused by using the HI or LO register too close to a
678 following operation is spotted. See mips.igen for more details. */
679
680 hilo_history hi_history;
681#define HIHISTORY (&(CPU)->hi_history)
682 hilo_history lo_history;
683#define LOHISTORY (&(CPU)->lo_history)
0c2c5f61 684
46eb9e5a
GRK		 685 /* start-sanitize-branchbug4011 */
686#if 1
687 int branchbug4011_option;
688#define BRANCHBUG4011_OPTION ((CPU)->branchbug4011_option)
689 address_word branchbug4011_last_target;
690#define BRANCHBUG4011_LAST_TARGET ((CPU)->branchbug4011_last_target)
691 address_word branchbug4011_last_cia;
692#define BRANCHBUG4011_LAST_CIA ((CPU)->branchbug4011_last_cia)
693
694#define check_branch_bug() (check_4011_branch_bug (_SD))
695#define mark_branch_bug(TARGET) (mark_4011_branch_bug (_SD,TARGET))
696#else
697 /* end-sanitize-branchbug4011 */
698#define check_branch_bug()
699#define mark_branch_bug(TARGET)
700 /* start-sanitize-branchbug4011 */
701#endif
702 /* end-sanitize-branchbug4011 */
0c2c5f61 703 /* start-sanitize-r5900 */
a48e8c8d 704 sim_r5900_cpu r5900;
0c2c5f61
AC		 705
706 /* end-sanitize-r5900 */
01b9cd49
AC		 707 /* start-sanitize-vr5400 */
708
2d44e12a
AC		 709 /* The MDMX ISA has a very very large accumulator */
710 unsigned8 acc[3 * 8];
01b9cd49 711 /* end-sanitize-vr5400 */
3fa454e9 712 /* start-sanitize-sky */
0c2c5f61 713
3fa454e9
FCE		 714#ifdef TARGET_SKY
715 /* Device on which instruction issue last occured. */
716 char cur_device;
717#endif
718 /* end-sanitize-sky */
18c64df6
AC		 719 sim_cpu_base base;
720};
721
722
723/* MIPS specific simulator watch config */
724
725void watch_options_install PARAMS ((SIM_DESC sd));
726
727struct swatch {
728 sim_event *pc;
729 sim_event *clock;
730 sim_event *cycles;
731};
732
733
734/* FIXME: At present much of the simulator is still static */
735struct sim_state {
736
737 struct swatch watch;
738
01737f42 739 sim_cpu cpu[MAX_NR_PROCESSORS];
18c64df6
AC		 740#if (WITH_SMP)
741#define STATE_CPU(sd,n) (&(sd)->cpu[n])
742#else
743#define STATE_CPU(sd,n) (&(sd)->cpu[0])
744#endif
745
60372a3f
JL		 746/* start-sanitize-sky */
747#ifdef TARGET_SKY
748#ifdef SKY_FUNIT
749 /* Record of option for floating point implementation type. */
750 int fp_type_opt;
751#define STATE_FP_TYPE_OPT(sd) ((sd)->fp_type_opt)
3fa454e9 752#define STATE_FP_TYPE_OPT_ACCURATE 0x80000000
60372a3f
JL		 753#endif
754#endif
755/* end-sanitize-sky */
756
18c64df6
AC		 757 sim_state_base base;
758};
759
760
ea985d24
AC		 761
762/* Status information: */
763
764/* TODO : these should be the bitmasks for these bits within the
765 status register. At the moment the following are VR4300
766 bit-positions: */
767#define status_KSU_mask (0x3) /* mask for KSU bits */
768#define status_KSU_shift (3) /* shift for field */
769#define ksu_kernel (0x0)
770#define ksu_supervisor (0x1)
771#define ksu_user (0x2)
772#define ksu_unknown (0x3)
773
774#define status_IE (1 << 0) /* Interrupt enable */
46eb9e5a 775#define status_EIE (1 << 16) /* Enable Interrupt Enable */
ea985d24
AC		 776#define status_EXL (1 << 1) /* Exception level */
777#define status_RE (1 << 25) /* Reverse Endian in user mode */
778#define status_FR (1 << 26) /* enables MIPS III additional FP registers */
779#define status_SR (1 << 20) /* soft reset or NMI */
780#define status_BEV (1 << 22) /* Location of general exception vectors */
781#define status_TS (1 << 21) /* TLB shutdown has occurred */
782#define status_ERL (1 << 2) /* Error level */
783#define status_RP (1 << 27) /* Reduced Power mode */
5fe24ce0 784/* start-sanitize-r5900 */
15232df4
FCE		 785#define status_CU0 (1 << 28) /* COP0 usable */
786#define status_CU1 (1 << 29) /* COP1 usable */
787#define status_CU2 (1 << 30) /* COP2 usable */
5fe24ce0 788/* end-sanitize-r5900 */
ea985d24 789
3fa454e9
FCE		 790/* Specializations for TX39 family */
791#define status_IEc (1 << 0) /* Interrupt enable (current) */
792#define status_KUc (1 << 1) /* Kernel/User mode */
793#define status_IEp (1 << 2) /* Interrupt enable (previous) */
794#define status_KUp (1 << 3) /* Kernel/User mode */
795#define status_IEo (1 << 4) /* Interrupt enable (old) */
796#define status_KUo (1 << 5) /* Kernel/User mode */
797#define status_IM_mask (0xff) /* Interrupt mask */
798#define status_IM_shift (8)
799#define status_NMI (1 << 20) /* NMI */
800#define status_NMI (1 << 20) /* NMI */
801
802#define cause_EXC_mask (0x1f) /* Exception code */
803#define cause_EXC_shift (2)
804#define cause_SW0 (1 << 8) /* Software interrupt 0 */
805#define cause_SW1 (1 << 9) /* Software interrupt 1 */
806#define cause_IP_mask (0x3f) /* Interrupt pending field */
807#define cause_IP_shift (10)
808#define cause_CE_mask (0x3) /* Coprocessor error */
809#define cause_CE_shift (28)
810
811#define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
812
ea985d24
AC		 813
814/* NOTE: We keep the following status flags as bit values (1 for true,
815 0 for false). This allows them to be used in binary boolean
816 operations without worrying about what exactly the non-zero true
817 value is. */
818
819/* UserMode */
3fa454e9
FCE		 820#ifdef SUBTARGET_R3900
821#define UserMode ((SR & status_KUc) ? 1 : 0)
822#else
ea985d24 823#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
3fa454e9 824#endif /* SUBTARGET_R3900 */
ea985d24
AC		 825
826/* BigEndianMem */
827/* Hardware configuration. Affects endianness of LoadMemory and
828 StoreMemory and the endianness of Kernel and Supervisor mode
829 execution. The value is 0 for little-endian; 1 for big-endian. */
830#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
831/*(state & simBE) ? 1 : 0)*/
832
ea985d24
AC		 833/* ReverseEndian */
834/* This mode is selected if in User mode with the RE bit being set in
835 SR (Status Register). It reverses the endianness of load and store
836 instructions. */
837#define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
838
839/* BigEndianCPU */
840/* The endianness for load and store instructions (0=little;1=big). In
841 User mode this endianness may be switched by setting the state_RE
842 bit in the SR register. Thus, BigEndianCPU may be computed as
843 (BigEndianMem EOR ReverseEndian). */
844#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
845
846
847
18c64df6
AC		 848/* Exceptions: */
849
850/* NOTE: These numbers depend on the processor architecture being
851 simulated: */
852#define Interrupt (0)
853#define TLBModification (1)
854#define TLBLoad (2)
855#define TLBStore (3)
856#define AddressLoad (4)
857#define AddressStore (5)
858#define InstructionFetch (6)
859#define DataReference (7)
860#define SystemCall (8)
861#define BreakPoint (9)
862#define ReservedInstruction (10)
863#define CoProcessorUnusable (11)
864#define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
865#define Trap (13)
866#define FPE (15)
867#define DebugBreakPoint (16)
868#define Watch (23)
3fa454e9
FCE		 869#define NMIReset (31)
870
18c64df6
AC		 871
872/* The following exception code is actually private to the simulator
873 world. It is *NOT* a processor feature, and is used to signal
874 run-time errors in the simulator. */
875#define SimulatorFault (0xFFFFFFFF)
876
895a7dc2
IC		 877/* The following break instructions are reserved for use by the
878 simulator. The first is used to halt the simulation. The second
879 is used by gdb for break-points. NOTE: Care must be taken, since
880 this value may be used in later revisions of the MIPS ISA. */
881#define HALT_INSTRUCTION_MASK (0x03FFFFC0)
882
883#define HALT_INSTRUCTION (0x03ff000d)
884#define HALT_INSTRUCTION2 (0x0000ffcd)
885
886/* start-sanitize-sky */
887#define HALT_INSTRUCTION_PASS (0x03fffc0d)
888#define HALT_INSTRUCTION_FAIL (0x03ffffcd)
889/* end-sanitize-sky */
890
891#define BREAKPOINT_INSTRUCTION (0x0005000d)
892#define BREAKPOINT_INSTRUCTION2 (0x0000014d)
893
894
46eb9e5a
GRK		 895void interrupt_event (SIM_DESC sd, void *data);
896
01737f42
AC		 897void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
898#define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
3fa454e9 899#define SignalExceptionInterrupt() signal_exception (SD, CPU, cia, Interrupt)
01737f42
AC		 900#define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
901#define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
902#define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
903#define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
904#define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
905#define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
906#define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
3fa454e9 907#define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
18c64df6 908
18c64df6
AC		 909/* Co-processor accesses */
910
01737f42
AC		 911void cop_lw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
912void cop_ld PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
913unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
914uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
18c64df6 915
01737f42
AC		 916#define COP_LW(coproc_num,coproc_reg,memword) \
917cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
918#define COP_LD(coproc_num,coproc_reg,memword) \
919cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
920#define COP_SW(coproc_num,coproc_reg) \
921cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
922#define COP_SD(coproc_num,coproc_reg) \
923cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
6ed00b06
FCE		 924
925/* start-sanitize-sky */
ebcfd86a
FCE		 926#ifdef TARGET_SKY
927void cop_lq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
928 int coproc_num, int coproc_reg, unsigned128 memword));
929unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
930 int coproc_num, int coproc_reg));
6ed00b06
FCE		 931#define COP_LQ(coproc_num,coproc_reg,memword) \
932cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
15232df4
FCE		 933#define COP_SQ(coproc_num,coproc_reg) \
934cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
ebcfd86a 935#endif /* TARGET_SKY */
6ed00b06 936/* end-sanitize-sky */
18c64df6 937
01737f42
AC		 938void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
939#define DecodeCoproc(instruction) \
940decode_coproc (SD, CPU, cia, (instruction))
ea985d24 941
18c64df6
AC		 942
943
944/* Memory accesses */
945
ea985d24
AC		 946/* The following are generic to all versions of the MIPS architecture
947 to date: */
948
949/* Memory Access Types (for CCA): */
950#define Uncached (0)
951#define CachedNoncoherent (1)
952#define CachedCoherent (2)
953#define Cached (3)
954
955#define isINSTRUCTION (1 == 0) /* FALSE */
956#define isDATA (1 == 1) /* TRUE */
957#define isLOAD (1 == 0) /* FALSE */
958#define isSTORE (1 == 1) /* TRUE */
959#define isREAL (1 == 0) /* FALSE */
960#define isRAW (1 == 1) /* TRUE */
525d929e 961/* The parameter HOST (isTARGET / isHOST) is ignored */
ea985d24 962#define isTARGET (1 == 0) /* FALSE */
525d929e 963/* #define isHOST (1 == 1) TRUE */
ea985d24
AC		 964
965/* The "AccessLength" specifications for Loads and Stores. NOTE: This
966 is the number of bytes minus 1. */
967#define AccessLength_BYTE (0)
968#define AccessLength_HALFWORD (1)
969#define AccessLength_TRIPLEBYTE (2)
970#define AccessLength_WORD (3)
971#define AccessLength_QUINTIBYTE (4)
972#define AccessLength_SEXTIBYTE (5)
973#define AccessLength_SEPTIBYTE (6)
974#define AccessLength_DOUBLEWORD (7)
975#define AccessLength_QUADWORD (15)
976
69d5a566
AC		 977#if (WITH_IGEN)
978#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
979 ? AccessLength_DOUBLEWORD /*7*/ \
980 : AccessLength_WORD /*3*/)
981#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
982#endif
983
2ebb2a68 984
64ed8b6a 985INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
18c64df6 986#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
01737f42 987address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
18c64df6 988
64ed8b6a 989INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
18c64df6 990#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
01737f42 991load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
18c64df6 992
64ed8b6a 993INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
18c64df6 994#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
01737f42 995store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
18c64df6 996
64ed8b6a 997INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
01737f42
AC		 998#define CacheOp(op,pAddr,vAddr,instruction) \
999cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
18c64df6 1000
64ed8b6a 1001INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
01737f42
AC		 1002#define SyncOperation(stype) \
1003sync_operation (SD, CPU, cia, (stype))
ea985d24 1004
64ed8b6a 1005INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
01737f42
AC		 1006#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
1007prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
ea985d24 1008
64ed8b6a 1009INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
a48e8c8d 1010#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
f3bdd368 1011INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
c0a4c3ba 1012#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
a48e8c8d 1013#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
ea985d24 1014
01737f42 1015void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
46eb9e5a 1016extern FILE *tracefh;
ea985d24 1017
64ed8b6a
AC		 1018INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
1019
1020char* pr_addr PARAMS ((SIM_ADDR addr));
1021char* pr_uword64 PARAMS ((uword64 addr));
1022
3fa454e9
FCE		 1023/* start-sanitize-sky */
1024#ifdef TARGET_SKY
1025#ifdef SIM_ENGINE_HALT_HOOK
1026#undef SIM_ENGINE_HALT_HOOK
1027#endif
1028
1029void sky_sim_engine_halt PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
b8140a08 1030#define SIM_ENGINE_HALT_HOOK(sd, last, cia) sky_sim_engine_halt(sd, last, cia)
3fa454e9 1031
2905d173
RU		 1032#ifdef SIM_ENGINE_RESTART_HOOK
1033#undef SIM_ENGINE_RESTART_HOOK
1034#endif
1035
1036void sky_sim_engine_restart PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
b8140a08 1037#define SIM_ENGINE_RESTART_HOOK(sd, L, pc) sky_sim_engine_restart(sd, L, pc)
2905d173 1038
b8140a08
RU		 1039/* for resume/suspend modules */
1040SIM_RC sky_sim_module_install PARAMS ((SIM_DESC sd));
1041
1042#define MODULE_LIST sky_sim_module_install,
1043
3fa454e9
FCE		 1044#ifndef TM_TXVU_H /* In case GDB hasn't been configured yet */
1045enum txvu_cpu_context
1046{
f083fff3
RU		 1047 TXVU_CPU_AUTO = -1, /* context-sensitive context */
1048 TXVU_CPU_MASTER = 0, /* R5900 core */
1049 TXVU_CPU_VU0 = 1, /* Vector units */
1050 TXVU_CPU_VU1 = 2,
1051 TXVU_CPU_VIF0 = 3, /* FIFO's */
1052 TXVU_CPU_VIF1 = 4,
1053 TXVU_CPU_LAST /* Count of context types */
3fa454e9
FCE		 1054};
1055
1056/* memory segment for communication with GDB */
b8140a08 1057#define GDB_COMM_AREA 0x21010000 /* Random choice */
3fa454e9
FCE		 1058#define GDB_COMM_SIZE 0x4000
1059
1060/* Memory address containing last device to execute */
1061#define LAST_DEVICE GDB_COMM_AREA
1062
2905d173
RU		 1063/* The FIFO breakpoint count and table */
1064#define FIFO_BPT_CNT (GDB_COMM_AREA + 4)
1065#define FIFO_BPT_TBL (GDB_COMM_AREA + 8)
1066
b8140a08
RU		 1067/* Each element of the breakpoint table is three four-byte integers. */
1068#define BPT_ELEM_SZ 4*3
1069
2905d173 1070#define TXVU_VU_BRK_MASK 0x02 /* Breakpoint bit is #57 for VU insns */
b8140a08 1071#define TXVU_VIF_BRK_MASK 0x80 /* Use interrupt bit for VIF insns */
2905d173 1072
3fa454e9
FCE		 1073#endif /* !TM_TXVU_H */
1074#endif /* TARGET_SKY */
1075/* end-sanitize-sky */
64ed8b6a
AC		 1076
1077#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1078#include "sim-main.c"
1079#endif
2acd126a 1080
18c64df6 1081#endif
GDB Binutils - Deliverables
This page took 0.10606 seconds and 4 git commands to generate.