Commit | Line | Data |
---|---|---|
0a8fa63c JL |
1 | Tue Jun 10 12:31:32 1997 Jeffrey A Law (law@cygnus.com) |
2 | ||
dbdb5bd8 JL |
3 | * simops.c: "call" stores the callee saved registers into the |
4 | stack! Update the stack pointer properly when done with | |
5 | register saves. | |
6 | ||
0a8fa63c JL |
7 | * simops.c: Fix return address computation for "call" instructions. |
8 | ||
9 | Thu May 22 01:43:11 1997 Jeffrey A Law (law@cygnus.com) | |
10 | ||
11 | * interp.c (sim_open): Fix typo. | |
12 | ||
09e142d5 JL |
13 | Wed May 21 23:27:58 1997 Jeffrey A Law (law@cygnus.com) |
14 | ||
15 | * interp.c (sim_resume): Add missing case in big switch | |
16 | statement (for extb instruction). | |
17 | ||
003c91be JL |
18 | Tue May 20 17:51:30 1997 Jeffrey A Law (law@cygnus.com) |
19 | ||
20 | * interp.c: Replace all references to load_mem and store_mem | |
21 | with references to load_byte, load_half, load_3_byte, load_word | |
22 | and store_byte, store_half, store_3_byte, store_word. | |
23 | (INLINE): Delete definition. | |
24 | (load_mem_big): Likewise. | |
25 | (max_mem): Make it global. | |
26 | (dispatch): Make this function inline. | |
27 | (load_mem, store_mem): Delete functions. | |
28 | * mn10300_sim.h (INLINE): Define. | |
29 | (RLW): Delete unused definition. | |
30 | (load_mem, store_mem): Delete declarations. | |
31 | (load_mem_big): New definition. | |
32 | (load_byte, load_half, load_3_byte, load_word): New functions. | |
33 | (store_byte, store_half, store_3_byte, store_word): New functions. | |
34 | * simops.c: Replace all references to load_mem and store_mem | |
35 | with references to load_byte, load_half, load_3_byte, load_word | |
36 | and store_byte, store_half, store_3_byte, store_word. | |
37 | ||
38 | Tue May 20 10:21:51 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
39 | ||
40 | * interp.c (sim_open): Add callback to arguments. | |
41 | (sim_set_callbacks): Delete SIM_DESC argument. | |
42 | ||
4df7aeb3 JL |
43 | Mon May 19 13:54:22 1997 Jeffrey A Law (law@cygnus.com) |
44 | ||
45 | * interp.c (dispatch): Make this an inline function. | |
46 | ||
47 | * simops.c (syscall): Use callback->write regardless of | |
48 | what file descriptor we're writing too. | |
49 | ||
b07a1e78 JL |
50 | Sun May 18 16:46:31 1997 Jeffrey A Law (law@cygnus.com) |
51 | ||
52 | * interp.c (load_mem_big): Remove function. It's now a macro | |
53 | defined elsewhere. | |
54 | (compare_simops): New function. | |
55 | (sim_open): Sort the Simops table before inserting entries | |
56 | into the hash table. | |
57 | * mn10300_sim.h: Remove unused #defines. | |
58 | (load_mem_big): Define. | |
59 | ||
234a9a49 JL |
60 | Fri May 16 16:36:17 1997 Jeffrey A Law (law@cygnus.com) |
61 | ||
62 | * interp.c (load_mem): If we get a load from an out of range | |
63 | address, abort. | |
64 | (store_mem): Likewise for stores. | |
65 | (max_mem): New variable. | |
66 | ||
baa83bcc JL |
67 | Tue May 6 13:24:36 1997 Jeffrey A Law (law@cygnus.com) |
68 | ||
8def9220 JL |
69 | * mn10300_sim.h: Fix ordering of bits in the PSW. |
70 | ||
baa83bcc JL |
71 | * interp.c: Improve hashing routine to avoid long list |
72 | traversals for common instructions. Add HASH_STAT support. | |
73 | Rewrite opcode dispatch code using a big switch instead of | |
74 | cascaded if/else statements. Avoid useless calls to load_mem. | |
75 | ||
26e9f63c JL |
76 | Mon May 5 18:07:48 1997 Jeffrey A Law (law@cygnus.com) |
77 | ||
78 | * mn10300_sim.h (struct _state): Add space for mdrq register. | |
79 | (REG_MDRQ): Define. | |
80 | * simops.c: Don't abort for trap. Add support for the extended | |
81 | instructions, "getx", "putx", "mulq", "mulqu", "sat16", "sat24", | |
82 | and "bsch". | |
83 | ||
84 | Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com> | |
85 | ||
86 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
87 | ||
8517f62b AC |
88 | Fri Apr 18 14:04:04 1997 Andrew Cagney <cagney@b1.cygnus.com> |
89 | ||
90 | * interp.c (sim_stop): Add stub function. | |
91 | ||
6cc6987e DE |
92 | Thu Apr 17 03:26:59 1997 Doug Evans <dje@canuck.cygnus.com> |
93 | ||
94 | * Makefile.in (SIM_OBJS): Add sim-load.o. | |
95 | * interp.c (sim_kind, myname): New static locals. | |
96 | (sim_open): Set sim_kind, myname. Ignore -E arg. | |
97 | (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to | |
98 | load file into simulator. Set start address from bfd. | |
99 | (sim_create_inferior): Return SIM_RC. Delete arg start_address. | |
100 | ||
87e43259 AC |
101 | Wed Apr 16 19:30:44 1997 Andrew Cagney <cagney@b1.cygnus.com> |
102 | ||
103 | * simops.c (OP_F020): SYS_execv, SYS_time, SYS_times, SYS_utime | |
104 | only include if implemented by host. | |
105 | (OP_F020): Typecast arg passed to time function; | |
106 | ||
107 | Mon Apr 7 23:57:49 1997 Jeffrey A Law (law@cygnus.com) | |
108 | ||
109 | * simops.c (syscall): Handle new mn10300 calling conventions. | |
110 | ||
08db4a65 AC |
111 | Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com> |
112 | ||
113 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
114 | * config.in: Ditto. | |
115 | ||
ea553f56 ILT |
116 | Fri Apr 4 20:02:37 1997 Ian Lance Taylor <ian@cygnus.com> |
117 | ||
118 | * Makefile.in: Change mn10300-opc.o to m10300-opc.o, to match | |
119 | corresponding change in opcodes directory. | |
120 | ||
fbda74b1 DE |
121 | Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com> |
122 | ||
8a7c3105 DE |
123 | * interp.c (sim_open): New arg `kind'. |
124 | ||
fbda74b1 DE |
125 | * configure: Regenerated to track ../common/aclocal.m4 changes. |
126 | ||
a35e91c3 AC |
127 | Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com> |
128 | ||
129 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
130 | ||
131 | Thu Mar 20 11:58:02 1997 Jeffrey A Law (law@cygnus.com) | |
132 | ||
133 | * simops.c: Fix register extraction for a two "movbu" variants. | |
134 | Somewhat simplify "sub" instructions. | |
135 | Correctly sign extend operands for "mul". Put the correct | |
136 | half of the result in MDR for "mul" and "mulu". | |
137 | Implement remaining instructions. | |
138 | Tweak opcode for "syscall". | |
139 | ||
140 | Tue Mar 18 14:21:21 1997 Jeffrey A Law (law@cygnus.com) | |
141 | ||
142 | * simops.c: Do syscall emulation in "syscall" instruction. Add | |
143 | dummy "trap" instruction. | |
144 | ||
c695046a AC |
145 | Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com> |
146 | ||
147 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
148 | ||
a77aa7ec AC |
149 | Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com> |
150 | ||
151 | * configure: Re-generate. | |
152 | ||
601fb8ae MM |
153 | Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com> |
154 | ||
155 | * configure: Regenerate to track ../common/aclocal.m4 changes. | |
156 | ||
53b9417e DE |
157 | Thu Mar 13 12:54:45 1997 Doug Evans <dje@canuck.cygnus.com> |
158 | ||
159 | * interp.c (sim_open): New SIM_DESC result. Argument is now | |
160 | in argv form. | |
161 | (other sim_*): New SIM_DESC argument. | |
162 | ||
09eef8af JL |
163 | Wed Mar 12 15:04:00 1997 Jeffrey A Law (law@cygnus.com) |
164 | ||
0ade484f JL |
165 | * simops.c: Fix carry bit computation for "add" instructions. |
166 | ||
09eef8af JL |
167 | * simops.c: Fix typos in bset insns. Fix arguments to store_mem |
168 | for bset imm8,(d8,an) and bclr imm8,(d8,an). | |
169 | ||
170 | Wed Mar 5 15:00:10 1997 Jeffrey A Law (law@cygnus.com) | |
171 | ||
172 | * simops.c: Fix register references when computing Z and N bits | |
173 | for lsr imm8,dn. | |
174 | ||
175 | Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com> | |
176 | ||
177 | * Makefile.in (@COMMON_MAKEFILE_FRAG): Use | |
178 | COMMON_{PRE,POST}_CONFIG_FRAG instead. | |
179 | * configure.in: sinclude ../common/aclocal.m4. | |
180 | * configure: Regenerated. | |
181 | ||
018f9eb4 JL |
182 | Fri Jan 24 10:47:25 1997 Jeffrey A Law (law@cygnus.com) |
183 | ||
184 | * interp.c (init_system): Allocate 2^19 bytes of space for the | |
185 | simulator. | |
186 | ||
295dbbe4 SG |
187 | Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) |
188 | ||
189 | * configure configure.in Makefile.in: Update to new configure | |
190 | scheme which is more compatible with WinGDB builds. | |
191 | * configure.in: Improve comment on how to run autoconf. | |
192 | * configure: Re-run autoconf to get new ../common/aclocal.m4. | |
193 | * Makefile.in: Use autoconf substitution to install common | |
194 | makefile fragment. | |
195 | ||
f95251f0 JL |
196 | Tue Jan 21 15:03:04 1997 Jeffrey A Law (law@cygnus.com) |
197 | ||
198 | * simops.c: Undo last change to "rol" and "ror", original code | |
199 | was correct! | |
200 | ||
b4b290a0 JL |
201 | Thu Jan 16 11:28:14 1997 Jeffrey A Law (law@cygnus.com) |
202 | ||
203 | * simops.c: Fix "rol" and "ror". | |
204 | ||
205 | Wed Jan 15 06:45:58 1997 Jeffrey A Law (law@cygnus.com) | |
206 | ||
207 | * simops.c: Fix typo in last change. | |
208 | ||
2da0bc1b JL |
209 | Mon Jan 13 13:22:35 1997 Jeffrey A Law (law@cygnus.com) |
210 | ||
211 | * simops.c: Use REG macros in few places not using them yet. | |
212 | ||
bbd17062 JL |
213 | Mon Jan 6 16:21:19 1997 Jeffrey A Law (law@cygnus.com) |
214 | ||
215 | * mn10300_sim.h (struct _state): Fix number of registers! | |
216 | ||
b774c0e4 JL |
217 | Tue Dec 31 16:20:41 1996 Jeffrey A Law (law@cygnus.com) |
218 | ||
219 | * mn10300_sim.h (struct _state): Put all registers into a single | |
220 | array to make gdb implementation easier. | |
221 | (REG_*): Add definitions for all registers in the state array. | |
222 | (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros. | |
223 | * simops.c: Related changes. | |
224 | ||
d657034d JL |
225 | Wed Dec 18 10:10:45 1996 Jeffrey A Law (law@cygnus.com) |
226 | ||
227 | * interp.c (sim_resume): Handle 0xff as a single byte insn. | |
228 | ||
229 | * simops.c: Fix overflow computation for "add" and "inc" | |
230 | instructions. | |
231 | ||
16d2e2b6 JL |
232 | Mon Dec 16 10:03:52 1996 Jeffrey A Law (law@cygnus.com) |
233 | ||
093e9a32 JL |
234 | * simops.c: Handle "break" instruction. |
235 | ||
16d2e2b6 JL |
236 | * simops.c: Fix restoring the PC for "ret" and "retf" instructions. |
237 | ||
238 | Wed Dec 11 09:53:10 1996 Jeffrey A Law (law@cygnus.com) | |
239 | ||
240 | * gencode.c (write_opcodes): Also write out the format of the | |
241 | opcode. | |
242 | * mn10300_sim.h (simops): Add "format" field. | |
243 | * interp.c (sim_resume): Deal with endianness issues here. | |
244 | ||
95d18eb7 JL |
245 | Tue Dec 10 15:05:37 1996 Jeffrey A Law (law@cygnus.com) |
246 | ||
247 | * simops.c (REG0_4): Define. | |
248 | Use REG0_4 for indexed loads/stores. | |
249 | ||
2e8f4133 JL |
250 | Sat Dec 7 09:50:28 1996 Jeffrey A Law (law@cygnus.com) |
251 | ||
252 | * simops.c (REG0_16): Fix typo. | |
253 | ||
d2523010 JL |
254 | Fri Dec 6 14:13:34 1996 Jeffrey A Law (law@cygnus.com) |
255 | ||
b2f7a7e5 JL |
256 | * simops.c: Call abort for any instruction that's not currently |
257 | simulated. | |
258 | ||
9f4a551e JL |
259 | * simops.c: Define accessor macros to extract register |
260 | values from instructions. Use them consistently. | |
261 | ||
7c52bf32 JL |
262 | * interp.c: Delete unused global variable "OP". |
263 | (sim_resume): Remove unused variable "opcode". | |
264 | * simops.c: Fix some uninitialized variable problems, add | |
265 | parens to fix various -Wall warnings. | |
266 | ||
d2523010 JL |
267 | * gencode.c (write_header): Add "insn" and "extension" arguments |
268 | to the OP_* declarations. | |
269 | (write_template): Similarly for function templates. | |
270 | * interp.c (insn, extension): Remove global variables. Instead | |
271 | pass them as arguments to the OP_* functions. | |
272 | * mn10300_sim.h: Remove decls for "insn" and "extension". | |
273 | * simops.c (OP_*): Accept "insn" and "extension" as arguments | |
274 | instead of using globals. | |
275 | ||
4d8ced6c JL |
276 | Thu Dec 5 22:26:31 1996 Jeffrey A Law (law@cygnus.com) |
277 | ||
e5a7a537 JL |
278 | * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)" |
279 | ||
4d8ced6c JL |
280 | * simops.c: Fix thinkos in last change to "inc dn". |
281 | ||
61ecca95 JL |
282 | Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com) |
283 | ||
284 | * simops.c: "add imm,sp" does not effect the condition codes. | |
285 | "inc dn" does effect the condition codes. | |
286 | ||
e4e13022 JL |
287 | Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com) |
288 | ||
289 | * simops.c: Treat both operands as signed values for | |
290 | "div" instruction. | |
291 | ||
292 | * simops.c: Fix simulation of division instructions. | |
293 | Fix typos/thinkos in several "cmp" and "sub" instructions. | |
294 | ||
fcfaf40d JL |
295 | Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com) |
296 | ||
e4e13022 JL |
297 | * simops.c: Fix carry bit handling in "sub" and "cmp" |
298 | instructions. | |
299 | ||
fcfaf40d JL |
300 | * simops.c: Fix "mov imm8,an" and "mov imm16,dn". |
301 | ||
6db7fc49 JL |
302 | Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com) |
303 | ||
b7b89deb JL |
304 | * simops.c: Fix overflow computation for many instructions. |
305 | ||
e5a7a537 | 306 | * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)". |
af388638 | 307 | |
c8f0171f JL |
308 | * simops.c: Fix "mov am, dn". |
309 | ||
6db7fc49 JL |
310 | * simops.c: Fix more bugs in "add imm,an" and |
311 | "add imm,dn". | |
312 | ||
f5f13c1d JL |
313 | Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com) |
314 | ||
6e7a01c1 JL |
315 | * simops.c: Fix bugs in "movm" and "add imm,an". |
316 | ||
3bb3fe44 JL |
317 | * simops.c: Don't lose the upper 24 bits of the return |
318 | pointer in "call" and "calls" instructions. Rough cut | |
319 | at emulated system calls. | |
320 | ||
de0dce7c JL |
321 | * simops.c: Implement the remaining 5, 6 and 7 byte instructions. |
322 | ||
ecb4b5a3 JL |
323 | * simops.c: Implement remaining 4 byte instructions. |
324 | ||
325 | * simops.c: Implement remaining 3 byte instructions. | |
2e35551c | 326 | |
f5f13c1d JL |
327 | * simops.c: Implement remaining 2 byte instructions. Call |
328 | abort for instructions we're not implementing now. | |
329 | ||
73e65298 JL |
330 | Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com) |
331 | ||
707641f6 JL |
332 | * simops.c: Implement lots of random instructions. |
333 | ||
1f3bea21 JL |
334 | * simops.c: Implement "movm" and "bCC" insns. |
335 | ||
92284aaa JL |
336 | * mn10300_sim.h (_state): Add another register (MDR). |
337 | (REG_MDR): Define. | |
338 | * simops.c: Implement "cmp", "calls", "rets", "jmp" and | |
339 | a few additional random insns. | |
340 | ||
73e65298 JL |
341 | * mn10300_sim.h (PSW_*): Define for CC status tracking. |
342 | (REG_D0, REG_A0, REG_SP): Define. | |
343 | * simops.c: Implement "add", "addc" and a few other random | |
344 | instructions. | |
b5f831ac JL |
345 | |
346 | * gencode.c, interp.c: Snapshot current simulator code. | |
347 | ||
05ccbdfd JL |
348 | Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com) |
349 | ||
350 | * Makefile.in, config.in, configure, configure.in: New files. | |
351 | * gencode.c, interp.c, mn10300_sim.h, simops.c: New files. | |
352 |