projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 4d8ced6c JL |
1 | Thu Dec 5 22:26:31 1996 Jeffrey A Law (law@cygnus.com) |
| 2 | ||
| 3 | * simops.c: Fix thinkos in last change to "inc dn". | |
| 4 | ||
| 61ecca95 JL |
5 | Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com) |
| 6 | ||
| 7 | * simops.c: "add imm,sp" does not effect the condition codes. | |
| 8 | "inc dn" does effect the condition codes. | |
| 9 | ||
| e4e13022 JL |
10 | Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com) |
| 11 | ||
| 12 | * simops.c: Treat both operands as signed values for | |
| 13 | "div" instruction. | |
| 14 | ||
| 15 | * simops.c: Fix simulation of division instructions. | |
| 16 | Fix typos/thinkos in several "cmp" and "sub" instructions. | |
| 17 | ||
| fcfaf40d JL |
18 | Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com) |
| 19 | ||
| e4e13022 JL |
20 | * simops.c: Fix carry bit handling in "sub" and "cmp" |
| 21 | instructions. | |
| 22 | ||
| fcfaf40d JL |
23 | * simops.c: Fix "mov imm8,an" and "mov imm16,dn". |
| 24 | ||
| 6db7fc49 JL |
25 | Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com) |
| 26 | ||
| b7b89deb JL |
27 | * simops.c: Fix overflow computation for many instructions. |
| 28 | ||
| af388638 JL |
29 | * simops.c: Fix "movdm, an", "movbu dm, (an)", and "movhu dm, (an)". |
| 30 | ||
| c8f0171f JL |
31 | * simops.c: Fix "mov am, dn". |
| 32 | ||
| 6db7fc49 JL |
33 | * simops.c: Fix more bugs in "add imm,an" and |
| 34 | "add imm,dn". | |
| 35 | ||
| f5f13c1d JL |
36 | Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com) |
| 37 | ||
| 6e7a01c1 JL |
38 | * simops.c: Fix bugs in "movm" and "add imm,an". |
| 39 | ||
| 3bb3fe44 JL |
40 | * simops.c: Don't lose the upper 24 bits of the return |
| 41 | pointer in "call" and "calls" instructions. Rough cut | |
| 42 | at emulated system calls. | |
| 43 | ||
| de0dce7c JL |
44 | * simops.c: Implement the remaining 5, 6 and 7 byte instructions. |
| 45 | ||
| ecb4b5a3 JL |
46 | * simops.c: Implement remaining 4 byte instructions. |
| 47 | ||
| 48 | * simops.c: Implement remaining 3 byte instructions. | |
| 2e35551c | 49 | |
| f5f13c1d JL |
50 | * simops.c: Implement remaining 2 byte instructions. Call |
| 51 | abort for instructions we're not implementing now. | |
| 52 | ||
| 73e65298 JL |
53 | Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com) |
| 54 | ||
| 707641f6 JL |
55 | * simops.c: Implement lots of random instructions. |
| 56 | ||
| 1f3bea21 JL |
57 | * simops.c: Implement "movm" and "bCC" insns. |
| 58 | ||
| 92284aaa JL |
59 | * mn10300_sim.h (_state): Add another register (MDR). |
| 60 | (REG_MDR): Define. | |
| 61 | * simops.c: Implement "cmp", "calls", "rets", "jmp" and | |
| 62 | a few additional random insns. | |
| 63 | ||
| 73e65298 JL |
64 | * mn10300_sim.h (PSW_*): Define for CC status tracking. |
| 65 | (REG_D0, REG_A0, REG_SP): Define. | |
| 66 | * simops.c: Implement "add", "addc" and a few other random | |
| 67 | instructions. | |
| b5f831ac JL |
68 | |
| 69 | * gencode.c, interp.c: Snapshot current simulator code. | |
| 70 | ||
| 05ccbdfd JL |
71 | Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com) |
| 72 | ||
| 73 | * Makefile.in, config.in, configure, configure.in: New files. | |
| 74 | * gencode.c, interp.c, mn10300_sim.h, simops.c: New files. | |
| 75 |