Commit | Line | Data |
---|---|---|
c2d11a7d JM |
1 | // Helper: |
2 | // | |
3 | // Given an extended register number, translate it into an index into the | |
4 | // register array. This is necessary as the upper 8 extended registers are | |
5 | // actually synonyms for the d0-d3/a0-a3 registers. | |
6 | // | |
7 | // | |
8 | ||
9 | :function:::int:translate_rreg:int rreg | |
10 | { | |
11 | ||
12 | /* The higher register numbers actually correspond to the | |
13 | basic machine's address and data registers. */ | |
14 | if (rreg > 7 && rreg < 12) | |
15 | return REG_A0 + rreg - 8; | |
16 | else if (rreg > 11 && rreg < 16) | |
17 | return REG_D0 + rreg - 12; | |
18 | else | |
19 | return REG_E0 + rreg; | |
20 | } | |
21 | ||
22 | :function:::int:translate_xreg:int xreg | |
23 | { | |
24 | switch (xreg) | |
25 | { | |
26 | case 0: | |
27 | return REG_SP; | |
28 | case 1: | |
29 | return REG_MDRQ; | |
30 | case 2: | |
31 | return REG_MCRH; | |
32 | case 3: | |
33 | return REG_MCRL; | |
34 | case 4: | |
35 | return REG_MCVF; | |
36 | default: | |
37 | abort (); | |
38 | } | |
39 | } | |
40 | ||
41 | // 1111 0000 0010 00An; mov USP,An | |
42 | 8.0xf0+4.0x2,00,2.AN0:D0m:::mov | |
43 | "mov" | |
44 | *am33 | |
45 | { | |
46 | PC = cia; | |
47 | State.regs[REG_A0 + AN0] = State.regs[REG_USP]; | |
48 | } | |
49 | ||
50 | ||
51 | // 1111 0000 0010 01An; mov SSP,An | |
52 | 8.0xf0+4.0x2,01,2.AN0:D0n:::mov | |
53 | "mov" | |
54 | *am33 | |
55 | { | |
56 | PC = cia; | |
57 | State.regs[REG_A0 + AN0] = State.regs[REG_SSP]; | |
58 | } | |
59 | ||
60 | ||
61 | // 1111 0000 0010 10An; mov MSP,An | |
62 | 8.0xf0+4.0x2,10,2.AN0:D0o:::mov | |
63 | "mov" | |
64 | *am33 | |
65 | { | |
66 | PC = cia; | |
67 | State.regs[REG_A0 + AN0] = State.regs[REG_MSP]; | |
68 | } | |
69 | ||
70 | ||
71 | // 1111 0000 0010 11An; mov PC,An | |
72 | 8.0xf0+4.0x2,11,2.AN0:D0p:::mov | |
73 | "mov" | |
74 | *am33 | |
75 | { | |
76 | PC = cia; | |
77 | State.regs[REG_A0 + AN0] = PC; | |
78 | } | |
79 | ||
80 | ||
81 | // 1111 0000 0011 Am00; mov Am,USP | |
82 | 8.0xf0+4.0x3,2.AM1,00:D0q:::mov | |
83 | "mov" | |
84 | *am33 | |
85 | { | |
86 | PC = cia; | |
87 | State.regs[REG_USP] = State.regs[REG_A0 + AM1]; | |
88 | } | |
89 | ||
90 | // 1111 0000 0011 Am01; mov Am,SSP | |
91 | 8.0xf0+4.0x3,2.AM1,01:D0r:::mov | |
92 | "mov" | |
93 | *am33 | |
94 | { | |
95 | PC = cia; | |
96 | State.regs[REG_SSP] = State.regs[REG_A0 + AM1]; | |
97 | } | |
98 | ||
99 | // 1111 0000 0011 Am10; mov Am,MSP | |
100 | 8.0xf0+4.0x3,2.AM1,10:D0s:::mov | |
101 | "mov" | |
102 | *am33 | |
103 | { | |
104 | PC = cia; | |
105 | State.regs[REG_MSP] = State.regs[REG_A0 + AM1]; | |
106 | } | |
107 | ||
108 | ||
109 | // 1111 0000 1110 imm4; syscall | |
110 | 8.0xf0+4.0xe,IMM4:D0t:::syscall | |
111 | "syscall" | |
112 | *am33 | |
113 | { | |
24a39d88 | 114 | unsigned32 sp, next_pc; |
c2d11a7d JM |
115 | |
116 | PC = cia; | |
117 | sp = State.regs[REG_SP]; | |
118 | next_pc = State.regs[REG_PC] + 2; | |
119 | store_word (sp - 4, next_pc); | |
120 | store_word (sp - 8, PSW); | |
121 | State.regs[REG_PC] = 0x40000000 + IMM4 * 8; | |
122 | nia = PC; | |
123 | } | |
124 | ||
125 | ||
126 | // 1111 0010 1110 11Dn; mov EPSW,Dn | |
127 | 8.0xf2+4.0xe,11,2.DN0:D0u:::mov | |
128 | "mov" | |
129 | *am33 | |
130 | { | |
131 | PC = cia; | |
132 | State.regs[REG_D0 + DN0] = PSW; | |
133 | } | |
134 | ||
135 | ||
136 | // 1111 0010 1111 Dm01; mov Dm,EPSW | |
137 | 8.0xf2+4.0xf,2.DM1,01:D0v:::mov | |
138 | "mov" | |
139 | *am33 | |
140 | { | |
141 | PC = cia; | |
142 | PSW = State.regs[REG_D0 + DM1]; | |
143 | } | |
144 | ||
145 | // 1111 0101 00Am Rn; mov Am,Rn | |
146 | 8.0xf5+00,2.AM1,4.RN0:D0w:::mov | |
147 | "mov" | |
148 | *am33 | |
149 | { | |
150 | int destreg = translate_rreg (SD_, RN0); | |
151 | ||
152 | PC = cia; | |
153 | State.regs[destreg] = State.regs[REG_A0 + AM1]; | |
154 | } | |
155 | ||
156 | // 1111 0101 01Dm Rn; mov Dm,Rn | |
157 | 8.0xf5+01,2.DM1,4.RN0:D0x:::mov | |
158 | "mov" | |
159 | *am33 | |
160 | { | |
161 | int destreg = translate_rreg (SD_, RN0); | |
162 | ||
163 | PC = cia; | |
164 | State.regs[destreg] = State.regs[REG_D0 + DM1]; | |
165 | } | |
166 | ||
167 | // 1111 0101 10Rm An; mov Rm,An | |
168 | 8.0xf5+10,4.RM1,2.AN0:D0y:::mov | |
169 | "mov" | |
170 | *am33 | |
171 | { | |
172 | int destreg = translate_rreg (SD_, RM1); | |
173 | ||
174 | PC = cia; | |
175 | State.regs[REG_A0 + AN0] = State.regs[destreg]; | |
176 | } | |
177 | ||
178 | // 1111 0101 11Rm Dn; mov Rm,Dn | |
179 | 8.0xf5+11,4.RM1,2.DN0:D0z:::mov | |
180 | "mov" | |
181 | *am33 | |
182 | { | |
183 | int destreg = translate_rreg (SD_, RM1); | |
184 | ||
185 | PC = cia; | |
186 | State.regs[REG_D0 + DN0] = State.regs[destreg]; | |
187 | } | |
188 | ||
189 | ||
190 | // 1111 1000 1100 1110 regs....; movm (USP),regs | |
191 | 8.0xf8+8.0xce+8.REGS:D1a:::movm | |
192 | "movm" | |
193 | *am33 | |
194 | { | |
24a39d88 AO |
195 | unsigned32 usp = State.regs[REG_USP]; |
196 | unsigned32 mask; | |
c2d11a7d JM |
197 | |
198 | PC = cia; | |
199 | mask = REGS; | |
200 | ||
201 | if (mask & 0x8) | |
202 | { | |
203 | usp += 4; | |
204 | State.regs[REG_LAR] = load_word (usp); | |
205 | usp += 4; | |
206 | State.regs[REG_LIR] = load_word (usp); | |
207 | usp += 4; | |
208 | State.regs[REG_MDR] = load_word (usp); | |
209 | usp += 4; | |
210 | State.regs[REG_A0 + 1] = load_word (usp); | |
211 | usp += 4; | |
212 | State.regs[REG_A0] = load_word (usp); | |
213 | usp += 4; | |
214 | State.regs[REG_D0 + 1] = load_word (usp); | |
215 | usp += 4; | |
216 | State.regs[REG_D0] = load_word (usp); | |
217 | usp += 4; | |
218 | } | |
219 | ||
220 | if (mask & 0x10) | |
221 | { | |
222 | State.regs[REG_A0 + 3] = load_word (usp); | |
223 | usp += 4; | |
224 | } | |
225 | ||
226 | if (mask & 0x20) | |
227 | { | |
228 | State.regs[REG_A0 + 2] = load_word (usp); | |
229 | usp += 4; | |
230 | } | |
231 | ||
232 | if (mask & 0x40) | |
233 | { | |
234 | State.regs[REG_D0 + 3] = load_word (usp); | |
235 | usp += 4; | |
236 | } | |
237 | ||
238 | if (mask & 0x80) | |
239 | { | |
240 | State.regs[REG_D0 + 2] = load_word (usp); | |
241 | usp += 4; | |
242 | } | |
243 | ||
ceec3559 NC |
244 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33 |
245 | ) | |
c2d11a7d JM |
246 | { |
247 | if (mask & 0x1) | |
248 | { | |
249 | /* Need to restore MDQR, MCRH, MCRL, and MCVF */ | |
250 | usp += 16; | |
251 | State.regs[REG_E0 + 1] = load_word (usp); | |
252 | usp += 4; | |
253 | State.regs[REG_E0 + 0] = load_word (usp); | |
254 | usp += 4; | |
255 | } | |
256 | ||
257 | if (mask & 0x2) | |
258 | { | |
259 | State.regs[REG_E0 + 7] = load_word (usp); | |
260 | usp += 4; | |
261 | State.regs[REG_E0 + 6] = load_word (usp); | |
262 | usp += 4; | |
263 | State.regs[REG_E0 + 5] = load_word (usp); | |
264 | usp += 4; | |
265 | State.regs[REG_E0 + 4] = load_word (usp); | |
266 | usp += 4; | |
267 | } | |
268 | ||
269 | if (mask & 0x4) | |
270 | { | |
271 | State.regs[REG_E0 + 3] = load_word (usp); | |
272 | usp += 4; | |
273 | State.regs[REG_E0 + 2] = load_word (usp); | |
274 | usp += 4; | |
275 | } | |
276 | } | |
277 | ||
278 | /* And make sure to update the stack pointer. */ | |
279 | State.regs[REG_USP] = usp; | |
280 | } | |
281 | ||
282 | // 1111 1000 1100 1111 regs....; movm (USP),regs | |
283 | 8.0xf8+8.0xcf+8.REGS:D1b:::movm | |
284 | "movm" | |
285 | *am33 | |
286 | { | |
24a39d88 AO |
287 | unsigned32 usp = State.regs[REG_USP]; |
288 | unsigned32 mask; | |
c2d11a7d | 289 | |
5425ca99 AO |
290 | PC = cia; |
291 | mask = REGS; | |
292 | ||
ceec3559 NC |
293 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33 |
294 | ) | |
c2d11a7d JM |
295 | { |
296 | if (mask & 0x4) | |
297 | { | |
298 | usp -= 4; | |
299 | store_word (usp, State.regs[REG_E0 + 2]); | |
300 | usp -= 4; | |
301 | store_word (usp, State.regs[REG_E0 + 3]); | |
302 | } | |
303 | ||
304 | if (mask & 0x2) | |
305 | { | |
306 | usp -= 4; | |
307 | store_word (usp, State.regs[REG_E0 + 4]); | |
308 | usp -= 4; | |
309 | store_word (usp, State.regs[REG_E0 + 5]); | |
310 | usp -= 4; | |
311 | store_word (usp, State.regs[REG_E0 + 6]); | |
312 | usp -= 4; | |
313 | store_word (usp, State.regs[REG_E0 + 7]); | |
314 | } | |
315 | ||
316 | if (mask & 0x1) | |
317 | { | |
318 | usp -= 4; | |
319 | store_word (usp, State.regs[REG_E0 + 0]); | |
320 | usp -= 4; | |
321 | store_word (usp, State.regs[REG_E0 + 1]); | |
322 | usp -= 16; | |
323 | /* Need to save MDQR, MCRH, MCRL, and MCVF */ | |
324 | } | |
325 | } | |
326 | ||
327 | if (mask & 0x80) | |
328 | { | |
329 | usp -= 4; | |
330 | store_word (usp, State.regs[REG_D0 + 2]); | |
331 | } | |
332 | ||
333 | if (mask & 0x40) | |
334 | { | |
335 | usp -= 4; | |
336 | store_word (usp, State.regs[REG_D0 + 3]); | |
337 | } | |
338 | ||
339 | if (mask & 0x20) | |
340 | { | |
341 | usp -= 4; | |
342 | store_word (usp, State.regs[REG_A0 + 2]); | |
343 | } | |
344 | ||
345 | if (mask & 0x10) | |
346 | { | |
347 | usp -= 4; | |
348 | store_word (usp, State.regs[REG_A0 + 3]); | |
349 | } | |
350 | ||
351 | if (mask & 0x8) | |
352 | { | |
353 | usp -= 4; | |
354 | store_word (usp, State.regs[REG_D0]); | |
355 | usp -= 4; | |
356 | store_word (usp, State.regs[REG_D0 + 1]); | |
357 | usp -= 4; | |
358 | store_word (usp, State.regs[REG_A0]); | |
359 | usp -= 4; | |
360 | store_word (usp, State.regs[REG_A0 + 1]); | |
361 | usp -= 4; | |
362 | store_word (usp, State.regs[REG_MDR]); | |
363 | usp -= 4; | |
364 | store_word (usp, State.regs[REG_LIR]); | |
365 | usp -= 4; | |
366 | store_word (usp, State.regs[REG_LAR]); | |
367 | usp -= 4; | |
368 | } | |
369 | ||
370 | /* And make sure to update the stack pointer. */ | |
371 | State.regs[REG_USP] = usp; | |
372 | } | |
373 | ||
374 | // 1111 1100 1111 1100 imm32...; and imm32,EPSW | |
375 | 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and | |
376 | "and" | |
377 | *am33 | |
378 | { | |
379 | PC = cia; | |
380 | PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); | |
381 | } | |
382 | ||
383 | // 1111 1100 1111 1101 imm32...; or imm32,EPSW | |
384 | 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or | |
385 | "or" | |
386 | *am33 | |
387 | { | |
388 | PC = cia; | |
389 | PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); | |
390 | } | |
391 | ||
392 | // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn) | |
393 | 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov | |
394 | "mov" | |
395 | *am33 | |
396 | { | |
397 | int srcreg, dstreg; | |
398 | ||
399 | PC = cia; | |
400 | ||
401 | srcreg = translate_rreg (SD_, RM2); | |
402 | dstreg = translate_rreg (SD_, RN0); | |
403 | State.regs[dstreg] = State.regs[srcreg]; | |
404 | } | |
405 | ||
406 | // 1111 1001 0001 1000 Rn Rn; ext Rn | |
407 | 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext | |
408 | "mov" | |
409 | *am33 | |
410 | { | |
411 | int srcreg; | |
412 | ||
413 | PC = cia; | |
414 | srcreg = translate_rreg (SD_, RN0); | |
415 | if (State.regs[srcreg] & 0x80000000) | |
416 | State.regs[REG_MDR] = -1; | |
417 | else | |
418 | State.regs[REG_MDR] = 0; | |
419 | } | |
420 | ||
421 | // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn | |
422 | 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb | |
423 | "extb" | |
424 | *am33 | |
425 | { | |
426 | int srcreg, dstreg; | |
427 | ||
428 | PC = cia; | |
429 | srcreg = translate_rreg (SD_, RM2); | |
430 | dstreg = translate_rreg (SD_, RN0); | |
431 | State.regs[dstreg] = EXTEND8 (State.regs[srcreg]); | |
432 | } | |
433 | ||
434 | // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn | |
435 | 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu | |
436 | "extbu" | |
437 | *am33 | |
438 | { | |
439 | int srcreg, dstreg; | |
440 | ||
441 | PC = cia; | |
442 | srcreg = translate_rreg (SD_, RM2); | |
443 | dstreg = translate_rreg (SD_, RN0); | |
444 | State.regs[dstreg] = State.regs[srcreg] & 0xff; | |
445 | } | |
446 | ||
447 | // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn | |
448 | 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth | |
449 | "exth" | |
450 | *am33 | |
451 | { | |
452 | int srcreg, dstreg; | |
453 | ||
454 | PC = cia; | |
455 | srcreg = translate_rreg (SD_, RM2); | |
456 | dstreg = translate_rreg (SD_, RN0); | |
457 | State.regs[dstreg] = EXTEND16 (State.regs[srcreg]); | |
458 | } | |
459 | ||
460 | // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn | |
461 | 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu | |
462 | "exthu" | |
463 | *am33 | |
464 | { | |
465 | int srcreg, dstreg; | |
466 | ||
467 | PC = cia; | |
468 | srcreg = translate_rreg (SD_, RM2); | |
469 | dstreg = translate_rreg (SD_, RN0); | |
470 | State.regs[dstreg] = State.regs[srcreg] & 0xffff; | |
471 | } | |
472 | ||
473 | // 1111 1001 0110 1000 Rn Rn; clr Rn | |
474 | 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr | |
475 | "clr" | |
476 | *am33 | |
477 | { | |
478 | int dstreg; | |
479 | ||
480 | PC = cia; | |
481 | dstreg = translate_rreg (SD_, RN0); | |
482 | State.regs[dstreg] = 0; | |
483 | PSW |= PSW_Z; | |
484 | PSW &= ~(PSW_V | PSW_C | PSW_N); | |
485 | } | |
486 | ||
487 | // 1111 1001 0111 1000 Rm Rn; add Rm,Rn | |
488 | 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add | |
489 | "add" | |
490 | *am33 | |
491 | { | |
492 | int srcreg, dstreg; | |
493 | ||
494 | PC = cia; | |
495 | srcreg = translate_rreg (SD_, RM2); | |
496 | dstreg = translate_rreg (SD_, RN0); | |
497 | genericAdd (State.regs[srcreg], dstreg); | |
498 | } | |
499 | ||
500 | // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn | |
501 | 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc | |
502 | "addc" | |
503 | *am33 | |
504 | { | |
505 | int srcreg, dstreg; | |
506 | int z, c, n, v; | |
24a39d88 | 507 | unsigned32 reg1, reg2, sum; |
c2d11a7d JM |
508 | |
509 | PC = cia; | |
510 | srcreg = translate_rreg (SD_, RM2); | |
511 | dstreg = translate_rreg (SD_, RN0); | |
512 | ||
513 | reg1 = State.regs[srcreg]; | |
514 | reg2 = State.regs[dstreg]; | |
515 | sum = reg1 + reg2 + ((PSW & PSW_C) != 0); | |
516 | State.regs[dstreg] = sum; | |
517 | ||
518 | z = ((PSW & PSW_Z) != 0) && (sum == 0); | |
519 | n = (sum & 0x80000000); | |
520 | c = (sum < reg1) || (sum < reg2); | |
521 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) | |
522 | && (reg2 & 0x80000000) != (sum & 0x80000000)); | |
523 | ||
524 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
525 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
526 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
527 | } | |
528 | ||
529 | // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn | |
530 | 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub | |
531 | "sub" | |
532 | *am33 | |
533 | { | |
534 | int srcreg, dstreg; | |
535 | ||
536 | PC = cia; | |
537 | srcreg = translate_rreg (SD_, RM2); | |
538 | dstreg = translate_rreg (SD_, RN0); | |
539 | genericSub (State.regs[srcreg], dstreg); | |
540 | } | |
541 | ||
542 | // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn | |
543 | 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc | |
544 | "subc" | |
545 | *am33 | |
546 | { | |
547 | int srcreg, dstreg; | |
548 | int z, c, n, v; | |
24a39d88 | 549 | unsigned32 reg1, reg2, difference; |
c2d11a7d JM |
550 | |
551 | PC = cia; | |
552 | srcreg = translate_rreg (SD_, RM2); | |
553 | dstreg = translate_rreg (SD_, RN0); | |
554 | ||
555 | reg1 = State.regs[srcreg]; | |
556 | reg2 = State.regs[dstreg]; | |
557 | difference = reg2 - reg1 - ((PSW & PSW_C) != 0); | |
558 | State.regs[dstreg] = difference; | |
559 | ||
560 | z = ((PSW & PSW_Z) != 0) && (difference == 0); | |
561 | n = (difference & 0x80000000); | |
562 | c = (reg1 > reg2); | |
563 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) | |
564 | && (reg2 & 0x80000000) != (difference & 0x80000000)); | |
565 | ||
566 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
567 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
568 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
569 | } | |
570 | ||
571 | // 1111 1001 1011 1000 Rn Rn; inc Rn | |
572 | 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc | |
573 | "inc" | |
574 | *am33 | |
575 | { | |
576 | int dstreg; | |
577 | ||
578 | PC = cia; | |
579 | dstreg = translate_rreg (SD_, RN0); | |
580 | genericAdd (1, dstreg); | |
581 | } | |
582 | ||
583 | // 1111 1001 1101 1000 Rn Rn; inc Rn | |
584 | 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4 | |
585 | "inc4" | |
586 | *am33 | |
587 | { | |
588 | int dstreg; | |
589 | ||
590 | PC = cia; | |
591 | dstreg = translate_rreg (SD_, RN0); | |
bfa8561f | 592 | genericAdd (4, dstreg); |
c2d11a7d JM |
593 | } |
594 | ||
595 | // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn | |
596 | 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp | |
597 | "cmp" | |
598 | *am33 | |
599 | { | |
600 | int srcreg1, srcreg2; | |
601 | ||
602 | PC = cia; | |
603 | srcreg1 = translate_rreg (SD_, RN0); | |
604 | srcreg2 = translate_rreg (SD_, RM2); | |
605 | genericCmp (State.regs[srcreg2], State.regs[srcreg1]); | |
606 | } | |
607 | ||
608 | // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn | |
609 | 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov | |
610 | "mov" | |
611 | *am33 | |
612 | { | |
613 | int dstreg, srcreg; | |
614 | ||
615 | PC = cia; | |
616 | dstreg = translate_rreg (SD_, RN0); | |
617 | srcreg = translate_xreg (SD_, XRM2); | |
618 | ||
619 | State.regs[dstreg] = State.regs[srcreg]; | |
620 | } | |
621 | ||
622 | // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn | |
623 | 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov | |
624 | "mov" | |
625 | *am33 | |
626 | { | |
627 | int srcreg, dstreg; | |
628 | ||
629 | PC = cia; | |
630 | srcreg = translate_rreg (SD_, RM2); | |
631 | dstreg = translate_xreg (SD_, XRN0); | |
632 | ||
633 | State.regs[dstreg] = State.regs[srcreg]; | |
634 | } | |
635 | ||
636 | // 1111 1001 0000 1001 Rm Rn; and Rm,Rn | |
637 | 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and | |
638 | "and" | |
639 | *am33 | |
640 | { | |
641 | int srcreg, dstreg; | |
642 | int z, n; | |
643 | ||
644 | PC = cia; | |
645 | ||
646 | srcreg = translate_rreg (SD_, RM2); | |
647 | dstreg = translate_rreg (SD_, RN0); | |
648 | ||
649 | State.regs[dstreg] &= State.regs[srcreg]; | |
650 | z = (State.regs[dstreg] == 0); | |
651 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
652 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
653 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
654 | } | |
655 | ||
656 | // 1111 1001 0001 1001 Rm Rn; or Rm,Rn | |
657 | 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or | |
658 | "or" | |
659 | *am33 | |
660 | { | |
661 | int srcreg, dstreg; | |
662 | int z, n; | |
663 | ||
664 | PC = cia; | |
665 | srcreg = translate_rreg (SD_, RM2); | |
666 | dstreg = translate_rreg (SD_, RN0); | |
667 | ||
668 | State.regs[dstreg] |= State.regs[srcreg]; | |
669 | z = (State.regs[dstreg] == 0); | |
670 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
671 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
672 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
673 | } | |
674 | ||
675 | // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn | |
676 | 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor | |
677 | "xor" | |
678 | *am33 | |
679 | { | |
680 | int srcreg, dstreg; | |
681 | int z, n; | |
682 | ||
683 | PC = cia; | |
684 | srcreg = translate_rreg (SD_, RM2); | |
685 | dstreg = translate_rreg (SD_, RN0); | |
686 | ||
687 | State.regs[dstreg] ^= State.regs[srcreg]; | |
688 | z = (State.regs[dstreg] == 0); | |
689 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
690 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
691 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
692 | } | |
693 | ||
694 | // 1111 1001 0011 1001 Rn Rn; not Rn | |
695 | 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not | |
696 | "not" | |
697 | *am33 | |
698 | { | |
699 | int dstreg; | |
700 | int z, n; | |
701 | ||
702 | PC = cia; | |
703 | dstreg = translate_rreg (SD_, RN0); | |
704 | ||
705 | State.regs[dstreg] = ~State.regs[dstreg]; | |
706 | z = (State.regs[dstreg] == 0); | |
707 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
708 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
709 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
710 | } | |
711 | ||
712 | // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn | |
713 | 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr | |
714 | "asr" | |
715 | *am33 | |
716 | { | |
717 | int srcreg, dstreg; | |
24a39d88 | 718 | signed32 temp; |
c2d11a7d JM |
719 | int c, z, n; |
720 | ||
721 | PC = cia; | |
722 | srcreg = translate_rreg (SD_, RM2); | |
723 | dstreg = translate_rreg (SD_, RN0); | |
724 | ||
725 | temp = State.regs[dstreg]; | |
726 | c = temp & 1; | |
727 | temp >>= State.regs[srcreg]; | |
728 | State.regs[dstreg] = temp; | |
729 | z = (State.regs[dstreg] == 0); | |
730 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
731 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
732 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
733 | } | |
734 | ||
735 | // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn | |
736 | 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr | |
737 | "lsr" | |
738 | *am33 | |
739 | { | |
740 | int srcreg, dstreg; | |
741 | int z, n, c; | |
742 | ||
743 | PC = cia; | |
744 | ||
745 | srcreg = translate_rreg (SD_, RM2); | |
746 | dstreg = translate_rreg (SD_, RN0); | |
747 | ||
748 | c = State.regs[dstreg] & 1; | |
749 | State.regs[dstreg] >>= State.regs[srcreg]; | |
750 | z = (State.regs[dstreg] == 0); | |
751 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
752 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
753 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
754 | } | |
755 | ||
756 | // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn | |
757 | 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl | |
758 | "asl" | |
759 | *am33 | |
760 | { | |
761 | int srcreg, dstreg; | |
762 | int z, n; | |
763 | ||
764 | PC = cia; | |
765 | srcreg = translate_rreg (SD_, RM2); | |
766 | dstreg = translate_rreg (SD_, RN0); | |
767 | ||
768 | State.regs[dstreg] <<= State.regs[srcreg]; | |
769 | z = (State.regs[dstreg] == 0); | |
770 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
771 | PSW &= ~(PSW_Z | PSW_N); | |
772 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
773 | } | |
774 | ||
775 | // 1111 1001 0111 1001 Rn Rn; asl2 Rn | |
776 | 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2 | |
777 | "asl2" | |
778 | *am33 | |
779 | { | |
780 | int dstreg; | |
781 | int n, z; | |
782 | ||
783 | PC = cia; | |
784 | dstreg = translate_rreg (SD_, RN0); | |
785 | ||
786 | State.regs[dstreg] <<= 2; | |
787 | z = (State.regs[dstreg] == 0); | |
788 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
789 | PSW &= ~(PSW_Z | PSW_N); | |
790 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
791 | } | |
792 | ||
793 | // 1111 1001 1000 1001 Rn Rn; ror Rn | |
794 | 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror | |
795 | "ror" | |
796 | *am33 | |
797 | { | |
798 | int dstreg; | |
799 | int c, n, z; | |
24a39d88 | 800 | unsigned32 value; |
c2d11a7d JM |
801 | |
802 | PC = cia; | |
803 | dstreg = translate_rreg (SD_, RN0); | |
804 | ||
805 | value = State.regs[dstreg]; | |
806 | c = (value & 0x1); | |
807 | ||
808 | value >>= 1; | |
809 | value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0; | |
810 | State.regs[dstreg] = value; | |
811 | z = (value == 0); | |
812 | n = (value & 0x80000000) != 0; | |
813 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
814 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
815 | } | |
816 | ||
817 | // 1111 1001 1001 1001 Rn Rn; rol Rn | |
818 | 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol | |
819 | "rol" | |
820 | *am33 | |
821 | { | |
822 | int dstreg; | |
823 | int c, n, z; | |
24a39d88 | 824 | unsigned32 value; |
c2d11a7d JM |
825 | |
826 | PC = cia; | |
827 | dstreg = translate_rreg (SD_, RN0); | |
828 | ||
829 | value = State.regs[dstreg]; | |
830 | c = (value & 0x80000000) ? 1 : 0; | |
831 | ||
832 | value <<= 1; | |
833 | value |= ((PSW & PSW_C) != 0); | |
834 | State.regs[dstreg] = value; | |
835 | z = (value == 0); | |
836 | n = (value & 0x80000000) != 0; | |
837 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
838 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
839 | } | |
840 | ||
841 | // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn | |
842 | 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul | |
843 | "mul" | |
844 | *am33 | |
845 | { | |
846 | int srcreg, dstreg; | |
24a39d88 | 847 | unsigned64 temp; |
c2d11a7d JM |
848 | int n, z; |
849 | ||
850 | PC = cia; | |
851 | srcreg = translate_rreg (SD_, RM2); | |
852 | dstreg = translate_rreg (SD_, RN0); | |
853 | ||
854 | temp = ((signed64)(signed32)State.regs[dstreg] | |
855 | * (signed64)(signed32)State.regs[srcreg]); | |
856 | State.regs[dstreg] = temp & 0xffffffff; | |
857 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; | |
858 | z = (State.regs[dstreg] == 0); | |
859 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
860 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
861 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
862 | } | |
863 | ||
864 | // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn | |
865 | 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu | |
866 | "mulu" | |
867 | *am33 | |
868 | { | |
869 | int srcreg, dstreg; | |
24a39d88 | 870 | unsigned64 temp; |
c2d11a7d JM |
871 | int n, z; |
872 | ||
873 | PC = cia; | |
874 | srcreg = translate_rreg (SD_, RM2); | |
875 | dstreg = translate_rreg (SD_, RN0); | |
876 | ||
877 | temp = ((unsigned64)State.regs[dstreg] | |
878 | * (unsigned64)State.regs[srcreg]); | |
879 | State.regs[dstreg] = temp & 0xffffffff; | |
880 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; | |
881 | z = (State.regs[dstreg] == 0); | |
882 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
883 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
884 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
885 | } | |
886 | ||
887 | // 1111 1001 1100 1001 Rm Rn; div Rm,Rn | |
888 | 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div | |
889 | "div" | |
890 | *am33 | |
891 | { | |
892 | int srcreg, dstreg; | |
24a39d88 | 893 | signed64 temp; |
c2d11a7d JM |
894 | int n, z; |
895 | ||
896 | PC = cia; | |
897 | srcreg = translate_rreg (SD_, RM2); | |
898 | dstreg = translate_rreg (SD_, RN0); | |
899 | ||
900 | temp = State.regs[REG_MDR]; | |
901 | temp <<= 32; | |
902 | temp |= State.regs[dstreg]; | |
903 | State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg]; | |
904 | temp /= (signed32)State.regs[srcreg]; | |
905 | State.regs[dstreg] = temp & 0xffffffff; | |
906 | z = (State.regs[dstreg] == 0); | |
907 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
908 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
909 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
910 | } | |
911 | ||
912 | // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn | |
913 | 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu | |
914 | "divu" | |
915 | *am33 | |
916 | { | |
917 | int srcreg, dstreg; | |
24a39d88 | 918 | unsigned64 temp; |
c2d11a7d JM |
919 | int n, z; |
920 | ||
921 | PC = cia; | |
922 | srcreg = translate_rreg (SD_, RM2); | |
923 | dstreg = translate_rreg (SD_, RN0); | |
924 | ||
925 | temp = State.regs[REG_MDR]; | |
926 | temp <<= 32; | |
927 | temp |= State.regs[dstreg]; | |
928 | State.regs[REG_MDR] = temp % State.regs[srcreg]; | |
929 | temp /= State.regs[srcreg]; | |
930 | State.regs[dstreg] = temp & 0xffffffff; | |
931 | z = (State.regs[dstreg] == 0); | |
932 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
933 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
934 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
935 | } | |
936 | ||
937 | ||
938 | // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn | |
939 | 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov | |
940 | "mov" | |
941 | *am33 | |
942 | { | |
943 | int srcreg, dstreg; | |
944 | ||
945 | PC = cia; | |
946 | srcreg = translate_rreg (SD_, RM0); | |
947 | dstreg = translate_rreg (SD_, RN2); | |
948 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
949 | } | |
950 | ||
951 | // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn) | |
952 | 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov | |
953 | "mov" | |
954 | *am33 | |
955 | { | |
956 | int srcreg, dstreg; | |
957 | ||
958 | PC = cia; | |
959 | srcreg = translate_rreg (SD_, RM2); | |
960 | dstreg = translate_rreg (SD_, RN0); | |
961 | store_word (State.regs[dstreg], State.regs[srcreg]); | |
962 | } | |
963 | ||
964 | // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn | |
965 | 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu | |
966 | "movbu" | |
967 | *am33 | |
968 | { | |
969 | int srcreg, dstreg; | |
970 | ||
971 | PC = cia; | |
972 | srcreg = translate_rreg (SD_, RM0); | |
973 | dstreg = translate_rreg (SD_, RN2); | |
974 | State.regs[dstreg] = load_byte (State.regs[srcreg]); | |
975 | } | |
976 | ||
977 | // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn) | |
978 | 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu | |
979 | "movbu" | |
980 | *am33 | |
981 | { | |
982 | int srcreg, dstreg; | |
983 | ||
984 | PC = cia; | |
985 | srcreg = translate_rreg (SD_, RM2); | |
986 | dstreg = translate_rreg (SD_, RN0); | |
987 | store_byte (State.regs[dstreg], State.regs[srcreg]); | |
988 | } | |
989 | ||
990 | // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn | |
991 | 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu | |
992 | "movhu" | |
993 | *am33 | |
994 | { | |
995 | int srcreg, dstreg; | |
996 | ||
997 | PC = cia; | |
998 | srcreg = translate_rreg (SD_, RM0); | |
999 | dstreg = translate_rreg (SD_, RN2); | |
1000 | State.regs[dstreg] = load_half (State.regs[srcreg]); | |
1001 | } | |
1002 | ||
1003 | // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn) | |
1004 | 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu | |
1005 | "movhu" | |
1006 | *am33 | |
1007 | { | |
1008 | int srcreg, dstreg; | |
1009 | ||
1010 | PC = cia; | |
1011 | srcreg = translate_rreg (SD_, RM2); | |
1012 | dstreg = translate_rreg (SD_, RN0); | |
1013 | store_half (State.regs[dstreg], State.regs[srcreg]); | |
1014 | } | |
1015 | ||
1016 | // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn | |
1017 | 8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov | |
1018 | "mov" | |
1019 | *am33 | |
1020 | { | |
1021 | int srcreg, dstreg; | |
1022 | ||
1023 | PC = cia; | |
1024 | srcreg = translate_rreg (SD_, RM0); | |
1025 | dstreg = translate_rreg (SD_, RN2); | |
1026 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
1027 | State.regs[srcreg] += 4; | |
1028 | } | |
1029 | ||
1030 | // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+) | |
1031 | 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov | |
1032 | "mov" | |
1033 | *am33 | |
1034 | { | |
1035 | int srcreg, dstreg; | |
1036 | ||
1037 | PC = cia; | |
1038 | srcreg = translate_rreg (SD_, RM2); | |
1039 | dstreg = translate_rreg (SD_, RN0); | |
1040 | store_word (State.regs[dstreg], State.regs[srcreg]); | |
1041 | State.regs[dstreg] += 4; | |
1042 | } | |
1043 | ||
1044 | // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn | |
1045 | 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov | |
1046 | "mov" | |
1047 | *am33 | |
1048 | { | |
1049 | int dstreg; | |
1050 | ||
1051 | PC = cia; | |
1052 | dstreg = translate_rreg (SD_, RN2); | |
1053 | State.regs[dstreg] = load_word (State.regs[REG_SP]); | |
1054 | } | |
1055 | ||
1056 | // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp) | |
1057 | 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov | |
1058 | "mov" | |
1059 | *am33 | |
1060 | { | |
1061 | int srcreg; | |
1062 | ||
1063 | PC = cia; | |
1064 | srcreg = translate_rreg (SD_, RM2); | |
1065 | store_word (State.regs[REG_SP], State.regs[srcreg]); | |
1066 | } | |
1067 | ||
1068 | // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn | |
1069 | 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu | |
1070 | "movbu" | |
1071 | *am33 | |
1072 | { | |
1073 | int dstreg; | |
1074 | ||
1075 | PC = cia; | |
1076 | dstreg = translate_rreg (SD_, RN2); | |
1077 | State.regs[dstreg] = load_byte (State.regs[REG_SP]); | |
1078 | } | |
1079 | ||
1080 | // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp) | |
1081 | 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu | |
1082 | "movbu" | |
1083 | *am33 | |
1084 | { | |
1085 | int srcreg; | |
1086 | ||
1087 | PC = cia; | |
1088 | srcreg = translate_rreg (SD_, RM2); | |
1089 | store_byte (State.regs[REG_SP], State.regs[srcreg]); | |
1090 | } | |
1091 | ||
1092 | // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn | |
1093 | 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu | |
1094 | "movhu" | |
1095 | *am33 | |
1096 | { | |
1097 | int dstreg; | |
1098 | ||
1099 | PC = cia; | |
1100 | dstreg = translate_rreg (SD_, RN2); | |
1101 | State.regs[dstreg] = load_half (State.regs[REG_SP]); | |
1102 | } | |
1103 | ||
1104 | // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp) | |
1105 | 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu | |
1106 | "movhu" | |
1107 | *am33 | |
1108 | { | |
1109 | int srcreg; | |
1110 | ||
1111 | PC = cia; | |
1112 | srcreg = translate_rreg (SD_, RM2); | |
1113 | store_half (State.regs[REG_SP], State.regs[srcreg]); | |
1114 | } | |
1115 | ||
1116 | // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn | |
1117 | 8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu | |
1118 | "movhu" | |
1119 | *am33 | |
1120 | { | |
1121 | int srcreg, dstreg; | |
1122 | ||
1123 | PC = cia; | |
1124 | srcreg = translate_rreg (SD_, RM0); | |
1125 | dstreg = translate_rreg (SD_, RN2); | |
1126 | State.regs[dstreg] = load_half (State.regs[srcreg]); | |
1127 | State.regs[srcreg] += 2; | |
1128 | } | |
1129 | ||
1130 | // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+) | |
1131 | 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu | |
1132 | "movhu" | |
1133 | *am33 | |
1134 | { | |
1135 | int srcreg, dstreg; | |
1136 | ||
1137 | PC = cia; | |
1138 | srcreg = translate_rreg (SD_, RM2); | |
1139 | dstreg = translate_rreg (SD_, RN0); | |
1140 | store_half (State.regs[dstreg], State.regs[srcreg]); | |
1141 | State.regs[dstreg] += 2; | |
1142 | } | |
1143 | ||
1144 | ||
1145 | // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn | |
1146 | 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac | |
1147 | "mac" | |
1148 | *am33 | |
1149 | { | |
1150 | int srcreg1, srcreg2; | |
24a39d88 | 1151 | signed64 temp, sum; |
c2d11a7d JM |
1152 | int c, v; |
1153 | ||
1154 | PC = cia; | |
1155 | srcreg1 = translate_rreg (SD_, RM2); | |
1156 | srcreg2 = translate_rreg (SD_, RN0); | |
1157 | ||
1158 | temp = ((signed64)(signed32)State.regs[srcreg2] | |
1159 | * (signed64)(signed32)State.regs[srcreg1]); | |
1160 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
1161 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
1162 | State.regs[REG_MCRL] = sum; | |
1163 | temp >>= 32; | |
1164 | temp &= 0xffffffff; | |
1165 | sum = State.regs[REG_MCRH] + temp + c; | |
1166 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
1167 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
1168 | State.regs[REG_MCRH] = sum; | |
1169 | if (v) | |
1170 | State.regs[REG_MCVF] = 1; | |
1171 | } | |
1172 | ||
1173 | // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn | |
1174 | 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu | |
1175 | "macu" | |
1176 | *am33 | |
1177 | { | |
1178 | int srcreg1, srcreg2; | |
24a39d88 | 1179 | unsigned64 temp, sum; |
c2d11a7d JM |
1180 | int c, v; |
1181 | ||
1182 | PC = cia; | |
1183 | srcreg1 = translate_rreg (SD_, RM2); | |
1184 | srcreg2 = translate_rreg (SD_, RN0); | |
1185 | ||
1186 | temp = ((unsigned64)State.regs[srcreg2] | |
1187 | * (unsigned64)State.regs[srcreg1]); | |
1188 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
1189 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
1190 | State.regs[REG_MCRL] = sum; | |
1191 | temp >>= 32; | |
1192 | temp &= 0xffffffff; | |
1193 | sum = State.regs[REG_MCRH] + temp + c; | |
1194 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
1195 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
1196 | State.regs[REG_MCRH] = sum; | |
1197 | if (v) | |
1198 | State.regs[REG_MCVF] = 1; | |
1199 | } | |
1200 | ||
1201 | // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn | |
1202 | 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb | |
1203 | "macb" | |
1204 | *am33 | |
1205 | { | |
1206 | int srcreg1, srcreg2; | |
24a39d88 | 1207 | signed32 temp, sum; |
c2d11a7d JM |
1208 | int v; |
1209 | ||
1210 | PC = cia; | |
1211 | srcreg1 = translate_rreg (SD_, RM2); | |
1212 | srcreg2 = translate_rreg (SD_, RN0); | |
1213 | ||
1214 | temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff) | |
1215 | * (signed32)(signed8)(State.regs[srcreg1] & 0xff)); | |
1216 | sum = State.regs[REG_MCRL] + temp; | |
1217 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) | |
1218 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
1219 | State.regs[REG_MCRL] = sum; | |
1220 | if (v) | |
1221 | State.regs[REG_MCVF] = 1; | |
1222 | } | |
1223 | ||
1224 | // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn | |
1225 | 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu | |
1226 | "macbu" | |
1227 | *am33 | |
1228 | { | |
1229 | int srcreg1, srcreg2; | |
24a39d88 | 1230 | signed64 temp, sum; |
c2d11a7d JM |
1231 | int v; |
1232 | ||
1233 | PC = cia; | |
1234 | srcreg1 = translate_rreg (SD_, RM2); | |
1235 | srcreg2 = translate_rreg (SD_, RN0); | |
1236 | ||
1237 | temp = ((unsigned32)(State.regs[srcreg2] & 0xff) | |
1238 | * (unsigned32)(State.regs[srcreg1] & 0xff)); | |
1239 | sum = State.regs[REG_MCRL] + temp; | |
1240 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) | |
1241 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
1242 | State.regs[REG_MCRL] = sum; | |
1243 | if (v) | |
1244 | State.regs[REG_MCVF] = 1; | |
1245 | } | |
1246 | ||
1247 | // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn | |
1248 | 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach | |
1249 | "mach" | |
1250 | *am33 | |
1251 | { | |
1252 | int srcreg1, srcreg2; | |
24a39d88 | 1253 | signed64 temp, sum; |
c2d11a7d JM |
1254 | int c, v; |
1255 | ||
1256 | PC = cia; | |
1257 | srcreg1 = translate_rreg (SD_, RM2); | |
1258 | srcreg2 = translate_rreg (SD_, RN0); | |
1259 | ||
1260 | temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff) | |
1261 | * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff)); | |
1262 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
1263 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
1264 | State.regs[REG_MCRL] = sum; | |
1265 | temp >>= 32; | |
1266 | temp &= 0xffffffff; | |
1267 | sum = State.regs[REG_MCRH] + temp + c; | |
1268 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
1269 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
1270 | State.regs[REG_MCRH] = sum; | |
1271 | if (v) | |
1272 | State.regs[REG_MCVF] = 1; | |
1273 | } | |
1274 | ||
1275 | // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn | |
1276 | 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu | |
1277 | "machu" | |
1278 | *am33 | |
1279 | { | |
1280 | int srcreg1, srcreg2; | |
24a39d88 | 1281 | signed64 temp, sum; |
c2d11a7d JM |
1282 | int c, v; |
1283 | ||
1284 | PC = cia; | |
1285 | srcreg1 = translate_rreg (SD_, RM2); | |
1286 | srcreg2 = translate_rreg (SD_, RN0); | |
1287 | ||
1288 | temp = ((unsigned64)(State.regs[srcreg2] & 0xffff) | |
1289 | * (unsigned64)(State.regs[srcreg1] & 0xffff)); | |
1290 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
1291 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
1292 | State.regs[REG_MCRL] = sum; | |
1293 | temp >>= 32; | |
1294 | temp &= 0xffffffff; | |
1295 | sum = State.regs[REG_MCRH] + temp + c; | |
1296 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
1297 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
1298 | State.regs[REG_MCRH] = sum; | |
1299 | if (v) | |
1300 | State.regs[REG_MCVF] = 1; | |
1301 | } | |
1302 | ||
1303 | // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn | |
1304 | 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach | |
1305 | "dmach" | |
1306 | *am33 | |
1307 | { | |
1308 | int srcreg1, srcreg2; | |
24a39d88 | 1309 | signed32 temp, temp2, sum; |
c2d11a7d JM |
1310 | int v; |
1311 | ||
1312 | PC = cia; | |
1313 | srcreg1 = translate_rreg (SD_, RM2); | |
1314 | srcreg2 = translate_rreg (SD_, RN0); | |
1315 | ||
1316 | temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff) | |
1317 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
1318 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
1319 | * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff)); | |
1320 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
1321 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) | |
1322 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
1323 | State.regs[REG_MCRL] = sum; | |
1324 | if (v) | |
1325 | State.regs[REG_MCVF] = 1; | |
1326 | } | |
1327 | ||
1328 | // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn | |
1329 | 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu | |
1330 | "dmachu" | |
1331 | *am33 | |
1332 | { | |
1333 | int srcreg1, srcreg2; | |
24a39d88 | 1334 | unsigned32 temp, temp2, sum; |
c2d11a7d JM |
1335 | int v; |
1336 | ||
1337 | PC = cia; | |
1338 | srcreg1 = translate_rreg (SD_, RM2); | |
1339 | srcreg2 = translate_rreg (SD_, RN0); | |
1340 | ||
1341 | temp = ((unsigned32)(State.regs[srcreg2] & 0xffff) | |
1342 | * (unsigned32)(State.regs[srcreg1] & 0xffff)); | |
1343 | temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff) | |
1344 | * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff)); | |
1345 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
1346 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) | |
1347 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
1348 | State.regs[REG_MCRL] = sum; | |
1349 | if (v) | |
1350 | State.regs[REG_MCVF] = 1; | |
1351 | } | |
1352 | ||
1353 | // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn | |
1354 | 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh | |
1355 | "dmulh" | |
1356 | *am33 | |
1357 | { | |
1358 | int srcreg, dstreg; | |
24a39d88 | 1359 | signed32 temp; |
c2d11a7d JM |
1360 | |
1361 | PC = cia; | |
1362 | srcreg = translate_rreg (SD_, RM2); | |
1363 | dstreg = translate_rreg (SD_, RN0); | |
1364 | ||
1365 | temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff) | |
1366 | * (signed32)(signed16)(State.regs[srcreg] & 0xffff)); | |
1367 | State.regs[REG_MDRQ] = temp; | |
1368 | temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff) | |
1369 | * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff)); | |
1370 | State.regs[dstreg] = temp; | |
1371 | } | |
1372 | ||
1373 | // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn | |
1374 | 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu | |
1375 | "dmachu" | |
1376 | *am33 | |
1377 | { | |
1378 | int srcreg, dstreg; | |
24a39d88 | 1379 | unsigned32 temp; |
c2d11a7d JM |
1380 | |
1381 | PC = cia; | |
1382 | srcreg = translate_rreg (SD_, RM2); | |
1383 | dstreg = translate_rreg (SD_, RN0); | |
1384 | ||
1385 | temp = ((unsigned32)(State.regs[dstreg] & 0xffff) | |
1386 | * (unsigned32)(State.regs[srcreg] & 0xffff)); | |
1387 | State.regs[REG_MDRQ] = temp; | |
1388 | temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff) | |
1389 | * (unsigned32)((State.regs[srcreg] >>16) & 0xffff)); | |
1390 | State.regs[dstreg] = temp; | |
1391 | } | |
1392 | ||
1393 | // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn | |
1394 | 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16 | |
1395 | "sat16" | |
1396 | *am33 | |
1397 | { | |
1398 | int srcreg, dstreg; | |
1399 | int value, z, n; | |
1400 | ||
1401 | PC = cia; | |
1402 | srcreg = translate_rreg (SD_, RM2); | |
1403 | dstreg = translate_rreg (SD_, RN0); | |
1404 | ||
1405 | value = State.regs[srcreg]; | |
1406 | ||
1407 | if (value >= 0x7fff) | |
1408 | State.regs[dstreg] = 0x7fff; | |
1409 | else if (value <= 0xffff8000) | |
1410 | State.regs[dstreg] = 0xffff8000; | |
1411 | else | |
1412 | State.regs[dstreg] = value; | |
1413 | ||
1414 | n = (State.regs[dstreg] & 0x8000) != 0; | |
1415 | z = (State.regs[dstreg] == 0); | |
1416 | PSW &= ~(PSW_Z | PSW_N); | |
1417 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
1418 | } | |
1419 | ||
1420 | // 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn | |
1421 | 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste | |
1422 | "mcste" | |
1423 | *am33 | |
1424 | { | |
1425 | int srcreg, dstreg; | |
1426 | ||
1427 | PC = cia; | |
1428 | srcreg = translate_rreg (SD_, RM2); | |
1429 | dstreg = translate_rreg (SD_, RN0); | |
1430 | ||
1431 | PSW &= ~(PSW_V | PSW_C); | |
1432 | PSW |= (State.regs[REG_MCVF] ? PSW_V : 0); | |
1433 | ||
1434 | /* 32bit saturation. */ | |
1435 | if (State.regs[srcreg] == 0x20) | |
1436 | { | |
24a39d88 | 1437 | signed64 tmp; |
c2d11a7d JM |
1438 | |
1439 | tmp = State.regs[REG_MCRH]; | |
1440 | tmp <<= 32; | |
1441 | tmp += State.regs[REG_MCRL]; | |
1442 | ||
1443 | if (tmp > 0x7fffffff) | |
1444 | State.regs[dstreg] = 0x7fffffff; | |
1445 | else if (tmp < 0xffffffff80000000LL) | |
1446 | State.regs[dstreg] = 0x80000000; | |
1447 | else | |
1448 | State.regs[dstreg] = tmp; | |
1449 | } | |
1450 | /* 16bit saturation */ | |
1451 | else if (State.regs[srcreg] == 0x10) | |
1452 | { | |
24a39d88 | 1453 | signed64 tmp; |
c2d11a7d JM |
1454 | |
1455 | tmp = State.regs[REG_MCRH]; | |
1456 | tmp <<= 32; | |
1457 | tmp += State.regs[REG_MCRL]; | |
1458 | ||
1459 | if (tmp > 0x7fff) | |
1460 | State.regs[dstreg] = 0x7fff; | |
1461 | else if (tmp < 0xffffffffffff8000LL) | |
1462 | State.regs[dstreg] = 0x8000; | |
1463 | else | |
1464 | State.regs[dstreg] = tmp; | |
1465 | } | |
1466 | /* 8 bit saturation */ | |
1467 | else if (State.regs[srcreg] == 0x8) | |
1468 | { | |
24a39d88 | 1469 | signed64 tmp; |
c2d11a7d JM |
1470 | |
1471 | tmp = State.regs[REG_MCRH]; | |
1472 | tmp <<= 32; | |
1473 | tmp += State.regs[REG_MCRL]; | |
1474 | ||
1475 | if (tmp > 0x7f) | |
1476 | State.regs[dstreg] = 0x7f; | |
1477 | else if (tmp < 0xffffffffffffff80LL) | |
1478 | State.regs[dstreg] = 0x80; | |
1479 | else | |
1480 | State.regs[dstreg] = tmp; | |
1481 | } | |
1482 | /* 9 bit saturation */ | |
1483 | else if (State.regs[srcreg] == 0x9) | |
1484 | { | |
24a39d88 | 1485 | signed64 tmp; |
c2d11a7d JM |
1486 | |
1487 | tmp = State.regs[REG_MCRH]; | |
1488 | tmp <<= 32; | |
1489 | tmp += State.regs[REG_MCRL]; | |
1490 | ||
1491 | if (tmp > 0x80) | |
1492 | State.regs[dstreg] = 0x80; | |
1493 | else if (tmp < 0xffffffffffffff81LL) | |
1494 | State.regs[dstreg] = 0x81; | |
1495 | else | |
1496 | State.regs[dstreg] = tmp; | |
1497 | } | |
1498 | /* 9 bit saturation */ | |
1499 | else if (State.regs[srcreg] == 0x30) | |
1500 | { | |
24a39d88 | 1501 | signed64 tmp; |
c2d11a7d JM |
1502 | |
1503 | tmp = State.regs[REG_MCRH]; | |
1504 | tmp <<= 32; | |
1505 | tmp += State.regs[REG_MCRL]; | |
1506 | ||
1507 | if (tmp > 0x7fffffffffffLL) | |
1508 | tmp = 0x7fffffffffffLL; | |
1509 | else if (tmp < 0xffff800000000000LL) | |
1510 | tmp = 0xffff800000000000LL; | |
1511 | ||
1512 | tmp >>= 16; | |
1513 | State.regs[dstreg] = tmp; | |
1514 | } | |
1515 | } | |
1516 | ||
1517 | // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn | |
1518 | 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap | |
1519 | "swap" | |
1520 | *am33 | |
1521 | { | |
1522 | int srcreg, dstreg; | |
1523 | ||
1524 | PC = cia; | |
1525 | srcreg = translate_rreg (SD_, RM2); | |
1526 | dstreg = translate_rreg (SD_, RN0); | |
1527 | ||
1528 | State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24) | |
1529 | | (((State.regs[srcreg] >> 8) & 0xff) << 16) | |
1530 | | (((State.regs[srcreg] >> 16) & 0xff) << 8) | |
1531 | | ((State.regs[srcreg] >> 24) & 0xff)); | |
1532 | } | |
1533 | ||
1534 | // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn | |
1535 | 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph | |
1536 | "swaph" | |
1537 | *am33 | |
1538 | { | |
1539 | int srcreg, dstreg; | |
1540 | ||
1541 | PC = cia; | |
1542 | srcreg = translate_rreg (SD_, RM2); | |
1543 | dstreg = translate_rreg (SD_, RN0); | |
1544 | ||
1545 | State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8) | |
1546 | | ((State.regs[srcreg] >> 8) & 0xff) | |
1547 | | (((State.regs[srcreg] >> 16) & 0xff) << 24) | |
1548 | | (((State.regs[srcreg] >> 24) & 0xff) << 16)); | |
1549 | } | |
1550 | ||
1551 | // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn | |
1552 | 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw | |
1553 | "swhw" | |
1554 | *am33 | |
1555 | { | |
1556 | int srcreg, dstreg; | |
1557 | ||
1558 | PC = cia; | |
1559 | srcreg = translate_rreg (SD_, RM2); | |
1560 | dstreg = translate_rreg (SD_, RN0); | |
1561 | ||
1562 | State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16) | |
1563 | | ((State.regs[srcreg] >> 16) & 0xffff)); | |
1564 | } | |
1565 | ||
1566 | // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn | |
1567 | 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch | |
1568 | "bsch" | |
1569 | *am33 | |
1570 | { | |
1571 | int temp, c, i; | |
1572 | int srcreg, dstreg; | |
1573 | int start; | |
1574 | ||
1575 | PC = cia; | |
1576 | srcreg = translate_rreg (SD_, RM2); | |
1577 | dstreg = translate_rreg (SD_, RN0); | |
1578 | ||
1579 | temp = State.regs[srcreg]; | |
1580 | start = (State.regs[dstreg] & 0x1f) - 1; | |
1581 | if (start == -1) | |
1582 | start = 31; | |
1583 | ||
5425ca99 | 1584 | c = 0; |
c2d11a7d JM |
1585 | for (i = start; i >= 0; i--) |
1586 | { | |
1587 | if (temp & (1 << i)) | |
1588 | { | |
1589 | c = 1; | |
1590 | State.regs[dstreg] = i; | |
1591 | break; | |
1592 | } | |
1593 | } | |
1594 | ||
1595 | if (i < 0) | |
1596 | { | |
1597 | c = 0; | |
1598 | State.regs[dstreg] = 0; | |
1599 | } | |
1600 | PSW &= ~(PSW_C); | |
1601 | PSW |= (c ? PSW_C : 0); | |
1602 | } | |
1603 | ||
1604 | ||
1605 | // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn | |
1606 | 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov | |
1607 | "mov" | |
1608 | *am33 | |
1609 | { | |
1610 | int dstreg; | |
1611 | ||
1612 | PC = cia; | |
1613 | dstreg = translate_rreg (SD_, RN0); | |
1614 | State.regs[dstreg] = EXTEND8 (IMM8); | |
1615 | } | |
1616 | ||
1617 | // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn | |
1618 | 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu | |
1619 | "movu" | |
1620 | *am33 | |
1621 | { | |
1622 | int dstreg; | |
1623 | ||
1624 | PC = cia; | |
1625 | dstreg = translate_rreg (SD_, RN0); | |
1626 | State.regs[dstreg] = IMM8 & 0xff; | |
1627 | } | |
1628 | ||
1629 | // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn | |
1630 | 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add | |
1631 | "add" | |
1632 | *am33 | |
1633 | { | |
1634 | int dstreg; | |
1635 | ||
1636 | PC = cia; | |
1637 | dstreg = translate_rreg (SD_, RN0); | |
1638 | genericAdd (EXTEND8 (IMM8), dstreg); | |
1639 | } | |
1640 | ||
1641 | // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn | |
1642 | 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc | |
1643 | "addc" | |
1644 | *am33 | |
1645 | { | |
1646 | int dstreg, imm; | |
1647 | int z, c, n, v; | |
5425ca99 | 1648 | unsigned32 reg2, sum; |
c2d11a7d JM |
1649 | |
1650 | PC = cia; | |
1651 | dstreg = translate_rreg (SD_, RN0); | |
1652 | ||
1653 | imm = EXTEND8 (IMM8); | |
1654 | reg2 = State.regs[dstreg]; | |
1655 | sum = imm + reg2 + ((PSW & PSW_C) != 0); | |
1656 | State.regs[dstreg] = sum; | |
1657 | ||
1658 | z = ((PSW & PSW_Z) != 0) && (sum == 0); | |
1659 | n = (sum & 0x80000000); | |
1660 | c = (sum < imm) || (sum < reg2); | |
1661 | v = ((reg2 & 0x80000000) == (imm & 0x80000000) | |
1662 | && (reg2 & 0x80000000) != (sum & 0x80000000)); | |
1663 | ||
1664 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1665 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1666 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
1667 | } | |
1668 | ||
1669 | // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn | |
1670 | 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub | |
1671 | "sub" | |
1672 | *am33 | |
1673 | { | |
1674 | int dstreg; | |
1675 | ||
1676 | PC = cia; | |
1677 | dstreg = translate_rreg (SD_, RN0); | |
1678 | ||
1679 | genericSub (EXTEND8 (IMM8), dstreg); | |
1680 | } | |
1681 | ||
1682 | // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn | |
1683 | 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc | |
1684 | "subc" | |
1685 | *am33 | |
1686 | { | |
1687 | int imm, dstreg; | |
1688 | int z, c, n, v; | |
5425ca99 | 1689 | unsigned32 reg2, difference; |
c2d11a7d JM |
1690 | |
1691 | PC = cia; | |
1692 | dstreg = translate_rreg (SD_, RN0); | |
1693 | ||
1694 | imm = EXTEND8 (IMM8); | |
1695 | reg2 = State.regs[dstreg]; | |
1696 | difference = reg2 - imm - ((PSW & PSW_C) != 0); | |
1697 | State.regs[dstreg] = difference; | |
1698 | ||
1699 | z = ((PSW & PSW_Z) != 0) && (difference == 0); | |
1700 | n = (difference & 0x80000000); | |
1701 | c = (imm > reg2); | |
1702 | v = ((reg2 & 0x80000000) == (imm & 0x80000000) | |
1703 | && (reg2 & 0x80000000) != (difference & 0x80000000)); | |
1704 | ||
1705 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1706 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1707 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
1708 | } | |
1709 | ||
1710 | // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn | |
1711 | 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp | |
1712 | "cmp" | |
1713 | *am33 | |
1714 | { | |
1715 | int srcreg; | |
1716 | ||
1717 | PC = cia; | |
1718 | srcreg = translate_rreg (SD_, RN0); | |
1719 | genericCmp (EXTEND8 (IMM8), State.regs[srcreg]); | |
1720 | } | |
1721 | ||
1722 | // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn | |
1723 | 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov | |
1724 | "mov" | |
1725 | *am33 | |
1726 | { | |
1727 | int dstreg; | |
1728 | ||
1729 | PC = cia; | |
1730 | dstreg = translate_xreg (SD_, XRN0); | |
1731 | ||
1732 | State.regs[dstreg] = IMM8; | |
1733 | } | |
1734 | ||
1735 | // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn | |
1736 | 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and | |
1737 | "and" | |
1738 | *am33 | |
1739 | { | |
1740 | int dstreg; | |
1741 | int z, n; | |
1742 | ||
1743 | PC = cia; | |
1744 | dstreg = translate_rreg (SD_, RN0); | |
1745 | ||
1746 | State.regs[dstreg] &= (IMM8 & 0xff); | |
1747 | z = (State.regs[dstreg] == 0); | |
1748 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
1749 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1750 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
1751 | } | |
1752 | ||
1753 | // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn | |
1754 | 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or | |
1755 | "or" | |
1756 | *am33 | |
1757 | { | |
1758 | int dstreg; | |
1759 | int z, n; | |
1760 | ||
1761 | PC = cia; | |
1762 | dstreg = translate_rreg (SD_, RN0); | |
1763 | ||
1764 | State.regs[dstreg] |= (IMM8 & 0xff); | |
1765 | z = (State.regs[dstreg] == 0); | |
1766 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
1767 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1768 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
1769 | } | |
1770 | ||
1771 | // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn | |
1772 | 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor | |
1773 | "xor" | |
1774 | *am33 | |
1775 | { | |
1776 | int dstreg; | |
1777 | int z, n; | |
1778 | ||
1779 | PC = cia; | |
1780 | dstreg = translate_rreg (SD_, RN0); | |
1781 | ||
1782 | State.regs[dstreg] ^= (IMM8 & 0xff); | |
1783 | z = (State.regs[dstreg] == 0); | |
1784 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
1785 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1786 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
1787 | } | |
1788 | ||
1789 | // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn | |
1790 | 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr | |
1791 | "asr" | |
1792 | *am33 | |
1793 | { | |
1794 | int dstreg; | |
24a39d88 | 1795 | signed32 temp; |
c2d11a7d JM |
1796 | int c, z, n; |
1797 | ||
1798 | PC = cia; | |
1799 | dstreg = translate_rreg (SD_, RN0); | |
1800 | ||
1801 | temp = State.regs[dstreg]; | |
1802 | c = temp & 1; | |
1803 | temp >>= (IMM8 & 0xff); | |
1804 | State.regs[dstreg] = temp; | |
1805 | z = (State.regs[dstreg] == 0); | |
1806 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
1807 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
1808 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
1809 | } | |
1810 | ||
1811 | // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn | |
1812 | 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr | |
1813 | "lsr" | |
1814 | *am33 | |
1815 | { | |
1816 | int dstreg; | |
1817 | int z, n, c; | |
1818 | ||
1819 | PC = cia; | |
1820 | dstreg = translate_rreg (SD_, RN0); | |
1821 | ||
1822 | c = State.regs[dstreg] & 1; | |
1823 | State.regs[dstreg] >>= (IMM8 & 0xff); | |
1824 | z = (State.regs[dstreg] == 0); | |
1825 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
1826 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
1827 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
1828 | } | |
1829 | ||
1830 | // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn | |
1831 | 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl | |
1832 | "asl" | |
1833 | *am33 | |
1834 | { | |
5425ca99 | 1835 | int dstreg; |
c2d11a7d JM |
1836 | int z, n; |
1837 | ||
1838 | PC = cia; | |
1839 | dstreg = translate_rreg (SD_, RN0); | |
1840 | ||
1841 | State.regs[dstreg] <<= (IMM8 & 0xff); | |
1842 | z = (State.regs[dstreg] == 0); | |
1843 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
1844 | PSW &= ~(PSW_Z | PSW_N); | |
1845 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
1846 | } | |
1847 | ||
1848 | // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn | |
1849 | 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul | |
1850 | "mul" | |
1851 | *am33 | |
1852 | { | |
1853 | int dstreg; | |
24a39d88 | 1854 | unsigned64 temp; |
c2d11a7d JM |
1855 | int z, n; |
1856 | ||
1857 | PC = cia; | |
1858 | dstreg = translate_rreg (SD_, RN0); | |
1859 | ||
1860 | temp = ((signed64)(signed32)State.regs[dstreg] | |
1861 | * (signed64)(signed32)EXTEND8 (IMM8)); | |
1862 | State.regs[dstreg] = temp & 0xffffffff; | |
1863 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; | |
1864 | z = (State.regs[dstreg] == 0); | |
1865 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
1866 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1867 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
1868 | } | |
1869 | ||
1870 | // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn | |
1871 | 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu | |
1872 | "mulu" | |
1873 | *am33 | |
1874 | { | |
1875 | int dstreg; | |
24a39d88 | 1876 | unsigned64 temp; |
c2d11a7d JM |
1877 | int z, n; |
1878 | ||
1879 | PC = cia; | |
1880 | dstreg = translate_rreg (SD_, RN0); | |
1881 | ||
1882 | temp = ((unsigned64)State.regs[dstreg] | |
1883 | * (unsigned64)(IMM8 & 0xff)); | |
1884 | State.regs[dstreg] = temp & 0xffffffff; | |
1885 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; | |
1886 | z = (State.regs[dstreg] == 0); | |
1887 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
1888 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1889 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
1890 | } | |
1891 | ||
1892 | // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn | |
1893 | 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst | |
1894 | "btst" | |
1895 | *am33 | |
1896 | { | |
1897 | int srcreg; | |
1898 | ||
1899 | PC = cia; | |
1900 | srcreg = translate_rreg (SD_, RM0); | |
1901 | genericBtst(IMM8, State.regs[srcreg]); | |
1902 | } | |
1903 | ||
1904 | // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn | |
1905 | 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov | |
1906 | "mov" | |
1907 | *am33 | |
1908 | { | |
1909 | int srcreg, dstreg; | |
1910 | ||
1911 | PC = cia; | |
1912 | srcreg = translate_rreg (SD_, RM0); | |
1913 | dstreg = translate_rreg (SD_, RN2); | |
1914 | State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8)); | |
1915 | } | |
1916 | ||
1917 | // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn) | |
1918 | 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov | |
1919 | "mov" | |
d8e7020f | 1920 | *am33 |
c2d11a7d JM |
1921 | { |
1922 | int srcreg, dstreg; | |
1923 | ||
1924 | PC = cia; | |
1925 | srcreg = translate_rreg (SD_, RM2); | |
1926 | dstreg = translate_rreg (SD_, RN0); | |
1927 | store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]); | |
1928 | } | |
1929 | ||
1930 | // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn | |
1931 | 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu | |
1932 | "movbu" | |
d8e7020f | 1933 | *am33 |
c2d11a7d JM |
1934 | { |
1935 | int srcreg, dstreg; | |
1936 | ||
1937 | PC = cia; | |
1938 | srcreg = translate_rreg (SD_, RM0); | |
1939 | dstreg = translate_rreg (SD_, RN2); | |
1940 | State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8)); | |
1941 | } | |
1942 | ||
1943 | // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn) | |
1944 | 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu | |
1945 | "movbu" | |
d8e7020f | 1946 | *am33 |
c2d11a7d JM |
1947 | { |
1948 | int srcreg, dstreg; | |
1949 | ||
1950 | PC = cia; | |
1951 | srcreg = translate_rreg (SD_, RM2); | |
1952 | dstreg = translate_rreg (SD_, RN0); | |
1953 | store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]); | |
1954 | } | |
1955 | ||
1956 | // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn | |
1957 | 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu | |
1958 | "movhu" | |
d8e7020f | 1959 | *am33 |
c2d11a7d JM |
1960 | { |
1961 | int srcreg, dstreg; | |
1962 | ||
1963 | PC = cia; | |
1964 | srcreg = translate_rreg (SD_, RM0); | |
1965 | dstreg = translate_rreg (SD_, RN2); | |
1966 | State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8)); | |
1967 | } | |
1968 | ||
1969 | // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn) | |
1970 | 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu | |
1971 | "movhu" | |
d8e7020f | 1972 | *am33 |
c2d11a7d JM |
1973 | { |
1974 | int srcreg, dstreg; | |
1975 | ||
1976 | PC = cia; | |
1977 | srcreg = translate_rreg (SD_, RM2); | |
1978 | dstreg = translate_rreg (SD_, RN0); | |
1979 | store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]); | |
1980 | } | |
1981 | ||
1982 | // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn | |
1983 | 8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov | |
1984 | "mov" | |
1985 | *am33 | |
1986 | { | |
1987 | int srcreg, dstreg; | |
1988 | ||
1989 | PC = cia; | |
1990 | srcreg = translate_rreg (SD_, RM0); | |
1991 | dstreg = translate_rreg (SD_, RN2); | |
1992 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
1993 | State.regs[srcreg] += EXTEND8 (IMM8); | |
1994 | } | |
1995 | ||
1996 | // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+) | |
1997 | 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov | |
1998 | "mov" | |
d8e7020f | 1999 | *am33 |
c2d11a7d JM |
2000 | { |
2001 | int srcreg, dstreg; | |
2002 | ||
2003 | PC = cia; | |
2004 | srcreg = translate_rreg (SD_, RM2); | |
2005 | dstreg = translate_rreg (SD_, RN0); | |
2006 | store_word (State.regs[dstreg], State.regs[srcreg]); | |
2007 | State.regs[dstreg] += EXTEND8 (IMM8); | |
2008 | } | |
2009 | ||
2010 | ||
2011 | // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn | |
2012 | 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov | |
2013 | "mov" | |
d8e7020f | 2014 | *am33 |
c2d11a7d JM |
2015 | { |
2016 | int dstreg; | |
2017 | ||
2018 | PC = cia; | |
2019 | dstreg = translate_rreg (SD_, RN2); | |
d8e7020f | 2020 | State.regs[dstreg] = load_word (State.regs[REG_SP] + IMM8); |
c2d11a7d JM |
2021 | } |
2022 | ||
e33c0364 | 2023 | // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,sp) |
c2d11a7d JM |
2024 | 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov |
2025 | "mov" | |
d8e7020f | 2026 | *am33 |
c2d11a7d JM |
2027 | { |
2028 | int srcreg; | |
2029 | ||
2030 | PC = cia; | |
2031 | srcreg = translate_rreg (SD_, RM2); | |
e33c0364 | 2032 | store_word (State.regs[REG_SP] + IMM8, State.regs[srcreg]); |
c2d11a7d JM |
2033 | } |
2034 | ||
2035 | // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn | |
2036 | 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu | |
2037 | "movbu" | |
d8e7020f | 2038 | *am33 |
c2d11a7d JM |
2039 | { |
2040 | int dstreg; | |
2041 | ||
2042 | PC = cia; | |
2043 | dstreg = translate_rreg (SD_, RN2); | |
d8e7020f | 2044 | State.regs[dstreg] = load_byte (State.regs[REG_SP] + IMM8); |
c2d11a7d JM |
2045 | } |
2046 | ||
e33c0364 | 2047 | // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(d8,sp) |
c2d11a7d JM |
2048 | 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu |
2049 | "movbu" | |
d8e7020f | 2050 | *am33 |
c2d11a7d JM |
2051 | { |
2052 | int srcreg; | |
2053 | ||
2054 | PC = cia; | |
2055 | srcreg = translate_rreg (SD_, RM2); | |
e33c0364 | 2056 | store_byte (State.regs[REG_SP] + IMM8, State.regs[srcreg]); |
c2d11a7d JM |
2057 | } |
2058 | ||
2059 | // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn | |
2060 | 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu | |
2061 | "movhu" | |
d8e7020f | 2062 | *am33 |
c2d11a7d JM |
2063 | { |
2064 | int dstreg; | |
2065 | ||
2066 | PC = cia; | |
2067 | dstreg = translate_rreg (SD_, RN2); | |
d8e7020f | 2068 | State.regs[dstreg] = load_half (State.regs[REG_SP] + IMM8); |
c2d11a7d JM |
2069 | } |
2070 | ||
2071 | // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp) | |
2072 | 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu | |
2073 | "movhu" | |
d8e7020f | 2074 | *am33 |
c2d11a7d JM |
2075 | { |
2076 | int srcreg; | |
2077 | ||
2078 | PC = cia; | |
2079 | srcreg = translate_rreg (SD_, RM2); | |
d8e7020f | 2080 | store_half (State.regs[REG_SP] + IMM8, State.regs[srcreg]); |
c2d11a7d JM |
2081 | } |
2082 | ||
2083 | // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn | |
2084 | 8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu | |
2085 | "movhu" | |
2086 | *am33 | |
2087 | { | |
2088 | int srcreg, dstreg; | |
2089 | ||
2090 | PC = cia; | |
2091 | srcreg = translate_rreg (SD_, RM0); | |
2092 | dstreg = translate_rreg (SD_, RN2); | |
2093 | State.regs[dstreg] = load_half (State.regs[srcreg]); | |
2094 | State.regs[srcreg] += EXTEND8 (IMM8); | |
2095 | } | |
2096 | ||
2097 | // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+) | |
2098 | 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu | |
2099 | "movhu" | |
d8e7020f | 2100 | *am33 |
c2d11a7d JM |
2101 | { |
2102 | int srcreg, dstreg; | |
2103 | ||
2104 | PC = cia; | |
2105 | srcreg = translate_rreg (SD_, RM2); | |
2106 | dstreg = translate_rreg (SD_, RN0); | |
2107 | store_half (State.regs[dstreg], State.regs[srcreg]); | |
2108 | State.regs[dstreg] += EXTEND8 (IMM8); | |
2109 | } | |
2110 | ||
2111 | ||
2112 | // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn | |
2113 | 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac | |
2114 | "mac" | |
d8e7020f | 2115 | *am33 |
c2d11a7d JM |
2116 | { |
2117 | int srcreg; | |
24a39d88 | 2118 | signed64 temp, sum; |
c2d11a7d JM |
2119 | int c, v; |
2120 | ||
2121 | PC = cia; | |
2122 | srcreg = translate_rreg (SD_, RN2); | |
2123 | ||
2124 | temp = ((signed64)(signed32)EXTEND8 (IMM8) | |
2125 | * (signed64)(signed32)State.regs[srcreg]); | |
2126 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
2127 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
2128 | State.regs[REG_MCRL] = sum; | |
2129 | temp >>= 32; | |
2130 | temp &= 0xffffffff; | |
2131 | sum = State.regs[REG_MCRH] + temp + c; | |
2132 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
2133 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
2134 | State.regs[REG_MCRH] = sum; | |
2135 | if (v) | |
2136 | State.regs[REG_MCVF] = 1; | |
2137 | } | |
2138 | ||
2139 | // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn | |
2140 | 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu | |
2141 | "macu" | |
d8e7020f | 2142 | *am33 |
c2d11a7d JM |
2143 | { |
2144 | int srcreg; | |
24a39d88 | 2145 | signed64 temp, sum; |
c2d11a7d JM |
2146 | int c, v; |
2147 | ||
2148 | PC = cia; | |
2149 | srcreg = translate_rreg (SD_, RN2); | |
2150 | ||
2151 | temp = ((unsigned64) (IMM8) | |
2152 | * (unsigned64)State.regs[srcreg]); | |
2153 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
2154 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
2155 | State.regs[REG_MCRL] = sum; | |
2156 | temp >>= 32; | |
2157 | temp &= 0xffffffff; | |
2158 | sum = State.regs[REG_MCRH] + temp + c; | |
2159 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
2160 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
2161 | State.regs[REG_MCRH] = sum; | |
2162 | if (v) | |
2163 | State.regs[REG_MCVF] = 1; | |
2164 | } | |
2165 | ||
2166 | // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn | |
2167 | 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb | |
2168 | "macb" | |
d8e7020f | 2169 | *am33 |
c2d11a7d JM |
2170 | { |
2171 | int srcreg; | |
24a39d88 | 2172 | signed64 temp, sum; |
c2d11a7d JM |
2173 | int c, v; |
2174 | ||
2175 | PC = cia; | |
2176 | srcreg = translate_rreg (SD_, RN2); | |
2177 | ||
2178 | temp = ((signed64)(signed8)EXTEND8 (IMM8) | |
2179 | * (signed64)(signed8)State.regs[srcreg] & 0xff); | |
2180 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
2181 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
2182 | State.regs[REG_MCRL] = sum; | |
2183 | temp >>= 32; | |
2184 | temp &= 0xffffffff; | |
2185 | sum = State.regs[REG_MCRH] + temp + c; | |
2186 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
2187 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
2188 | State.regs[REG_MCRH] = sum; | |
2189 | if (v) | |
2190 | State.regs[REG_MCVF] = 1; | |
2191 | } | |
2192 | ||
2193 | // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn | |
2194 | 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu | |
2195 | "macbu" | |
d8e7020f | 2196 | *am33 |
c2d11a7d JM |
2197 | { |
2198 | int srcreg; | |
24a39d88 | 2199 | signed64 temp, sum; |
c2d11a7d JM |
2200 | int c, v; |
2201 | ||
2202 | PC = cia; | |
2203 | srcreg = translate_rreg (SD_, RN2); | |
2204 | ||
2205 | temp = ((unsigned64) (IMM8) | |
2206 | * (unsigned64)State.regs[srcreg] & 0xff); | |
2207 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
2208 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
2209 | State.regs[REG_MCRL] = sum; | |
2210 | temp >>= 32; | |
2211 | temp &= 0xffffffff; | |
2212 | sum = State.regs[REG_MCRH] + temp + c; | |
2213 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
2214 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
2215 | State.regs[REG_MCRH] = sum; | |
2216 | if (v) | |
2217 | State.regs[REG_MCVF] = 1; | |
2218 | } | |
2219 | ||
2220 | // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn | |
2221 | 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach | |
2222 | "mach" | |
d8e7020f | 2223 | *am33 |
c2d11a7d JM |
2224 | { |
2225 | int srcreg; | |
24a39d88 | 2226 | signed64 temp, sum; |
c2d11a7d JM |
2227 | int c, v; |
2228 | ||
2229 | PC = cia; | |
2230 | srcreg = translate_rreg (SD_, RN2); | |
2231 | ||
2232 | temp = ((signed64)(signed16)EXTEND8 (IMM8) | |
2233 | * (signed64)(signed16)State.regs[srcreg] & 0xffff); | |
2234 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
2235 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
2236 | State.regs[REG_MCRL] = sum; | |
2237 | temp >>= 32; | |
2238 | temp &= 0xffffffff; | |
2239 | sum = State.regs[REG_MCRH] + temp + c; | |
2240 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
2241 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
2242 | State.regs[REG_MCRH] = sum; | |
2243 | if (v) | |
2244 | State.regs[REG_MCVF] = 1; | |
2245 | } | |
2246 | ||
2247 | // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn | |
2248 | 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu | |
2249 | "machu" | |
d8e7020f | 2250 | *am33 |
c2d11a7d JM |
2251 | { |
2252 | int srcreg; | |
24a39d88 | 2253 | signed64 temp, sum; |
c2d11a7d JM |
2254 | int c, v; |
2255 | ||
2256 | PC = cia; | |
2257 | srcreg = translate_rreg (SD_, RN2); | |
2258 | ||
2259 | temp = ((unsigned64) (IMM8) | |
2260 | * (unsigned64)State.regs[srcreg] & 0xffff); | |
2261 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
2262 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
2263 | State.regs[REG_MCRL] = sum; | |
2264 | temp >>= 32; | |
2265 | temp &= 0xffffffff; | |
2266 | sum = State.regs[REG_MCRH] + temp + c; | |
2267 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
2268 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
2269 | State.regs[REG_MCRH] = sum; | |
2270 | if (v) | |
2271 | State.regs[REG_MCVF] = 1; | |
2272 | } | |
2273 | ||
2274 | // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn | |
2275 | 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste | |
2276 | "mcste" | |
d8e7020f | 2277 | *am33 |
c2d11a7d JM |
2278 | { |
2279 | int dstreg; | |
2280 | ||
2281 | PC = cia; | |
2282 | dstreg = translate_rreg (SD_, RN0); | |
2283 | ||
2284 | PSW &= ~(PSW_V | PSW_C); | |
2285 | PSW |= (State.regs[REG_MCVF] ? PSW_V : 0); | |
2286 | ||
2287 | /* 32bit saturation. */ | |
2288 | if (IMM8 == 0x20) | |
2289 | { | |
24a39d88 | 2290 | signed64 tmp; |
c2d11a7d JM |
2291 | |
2292 | tmp = State.regs[REG_MCRH]; | |
2293 | tmp <<= 32; | |
2294 | tmp += State.regs[REG_MCRL]; | |
2295 | ||
2296 | if (tmp > 0x7fffffff) | |
2297 | State.regs[dstreg] = 0x7fffffff; | |
2298 | else if (tmp < 0xffffffff80000000LL) | |
2299 | State.regs[dstreg] = 0x80000000; | |
2300 | else | |
2301 | State.regs[dstreg] = tmp; | |
2302 | } | |
2303 | /* 16bit saturation */ | |
2304 | else if (IMM8 == 0x10) | |
2305 | { | |
24a39d88 | 2306 | signed64 tmp; |
c2d11a7d JM |
2307 | |
2308 | tmp = State.regs[REG_MCRH]; | |
2309 | tmp <<= 32; | |
2310 | tmp += State.regs[REG_MCRL]; | |
2311 | ||
2312 | if (tmp > 0x7fff) | |
2313 | State.regs[dstreg] = 0x7fff; | |
2314 | else if (tmp < 0xffffffffffff8000LL) | |
2315 | State.regs[dstreg] = 0x8000; | |
2316 | else | |
2317 | State.regs[dstreg] = tmp; | |
2318 | } | |
2319 | /* 8 bit saturation */ | |
2320 | else if (IMM8 == 0x8) | |
2321 | { | |
24a39d88 | 2322 | signed64 tmp; |
c2d11a7d JM |
2323 | |
2324 | tmp = State.regs[REG_MCRH]; | |
2325 | tmp <<= 32; | |
2326 | tmp += State.regs[REG_MCRL]; | |
2327 | ||
2328 | if (tmp > 0x7f) | |
2329 | State.regs[dstreg] = 0x7f; | |
2330 | else if (tmp < 0xffffffffffffff80LL) | |
2331 | State.regs[dstreg] = 0x80; | |
2332 | else | |
2333 | State.regs[dstreg] = tmp; | |
2334 | } | |
2335 | /* 9 bit saturation */ | |
2336 | else if (IMM8 == 0x9) | |
2337 | { | |
24a39d88 | 2338 | signed64 tmp; |
c2d11a7d JM |
2339 | |
2340 | tmp = State.regs[REG_MCRH]; | |
2341 | tmp <<= 32; | |
2342 | tmp += State.regs[REG_MCRL]; | |
2343 | ||
2344 | if (tmp > 0x80) | |
2345 | State.regs[dstreg] = 0x80; | |
2346 | else if (tmp < 0xffffffffffffff81LL) | |
2347 | State.regs[dstreg] = 0x81; | |
2348 | else | |
2349 | State.regs[dstreg] = tmp; | |
2350 | } | |
2351 | /* 9 bit saturation */ | |
2352 | else if (IMM8 == 0x30) | |
2353 | { | |
24a39d88 | 2354 | signed64 tmp; |
c2d11a7d JM |
2355 | |
2356 | tmp = State.regs[REG_MCRH]; | |
2357 | tmp <<= 32; | |
2358 | tmp += State.regs[REG_MCRL]; | |
2359 | ||
2360 | if (tmp > 0x7fffffffffffLL) | |
2361 | tmp = 0x7fffffffffffLL; | |
2362 | else if (tmp < 0xffff800000000000LL) | |
2363 | tmp = 0xffff800000000000LL; | |
2364 | ||
2365 | tmp >>= 16; | |
2366 | State.regs[dstreg] = tmp; | |
2367 | } | |
2368 | } | |
2369 | ||
2370 | // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd | |
2371 | 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add | |
2372 | "add" | |
2373 | *am33 | |
2374 | { | |
2375 | int z, c, n, v; | |
24a39d88 | 2376 | unsigned32 sum, source1, source2; |
c2d11a7d JM |
2377 | int srcreg1, srcreg2, dstreg; |
2378 | ||
2379 | PC = cia; | |
2380 | srcreg1 = translate_rreg (SD_, RM2); | |
2381 | srcreg2 = translate_rreg (SD_, RN0); | |
2382 | dstreg = translate_rreg (SD_, RD0); | |
2383 | ||
2384 | source1 = State.regs[srcreg1]; | |
2385 | source2 = State.regs[srcreg2]; | |
2386 | sum = source1 + source2; | |
2387 | State.regs[dstreg] = sum; | |
2388 | ||
2389 | z = (sum == 0); | |
2390 | n = (sum & 0x80000000); | |
2391 | c = (sum < source1) || (sum < source2); | |
2392 | v = ((source1 & 0x80000000) == (source2 & 0x80000000) | |
2393 | && (source1 & 0x80000000) != (sum & 0x80000000)); | |
2394 | ||
2395 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2396 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
2397 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
2398 | } | |
2399 | ||
2400 | // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd | |
2401 | 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc | |
2402 | "addc" | |
2403 | *am33 | |
2404 | { | |
2405 | int z, c, n, v; | |
24a39d88 | 2406 | unsigned32 sum, source1, source2; |
c2d11a7d JM |
2407 | int srcreg1, srcreg2, dstreg; |
2408 | ||
2409 | PC = cia; | |
2410 | srcreg1 = translate_rreg (SD_, RM2); | |
2411 | srcreg2 = translate_rreg (SD_, RN0); | |
2412 | dstreg = translate_rreg (SD_, RD0); | |
2413 | ||
2414 | source1 = State.regs[srcreg1]; | |
2415 | source2 = State.regs[srcreg2]; | |
2416 | sum = source1 + source2 + ((PSW & PSW_C) != 0); | |
2417 | State.regs[dstreg] = sum; | |
2418 | ||
2419 | z = ((PSW & PSW_Z) != 0) && (sum == 0); | |
2420 | n = (sum & 0x80000000); | |
2421 | c = (sum < source1) || (sum < source2); | |
2422 | v = ((source1 & 0x80000000) == (source2 & 0x80000000) | |
2423 | && (source1 & 0x80000000) != (sum & 0x80000000)); | |
2424 | ||
2425 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2426 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
2427 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
2428 | } | |
2429 | ||
2430 | // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd | |
2431 | 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub | |
2432 | "sub" | |
2433 | *am33 | |
2434 | { | |
2435 | int z, c, n, v; | |
24a39d88 | 2436 | unsigned32 difference, source1, source2; |
c2d11a7d JM |
2437 | int srcreg1, srcreg2, dstreg; |
2438 | ||
2439 | PC = cia; | |
2440 | srcreg1 = translate_rreg (SD_, RM2); | |
2441 | srcreg2 = translate_rreg (SD_, RN0); | |
2442 | dstreg = translate_rreg (SD_, RD0); | |
2443 | ||
2444 | source1 = State.regs[srcreg1]; | |
2445 | source2 = State.regs[srcreg2]; | |
2446 | difference = source2 - source1; | |
2447 | State.regs[dstreg] = difference; | |
2448 | ||
2449 | z = (difference == 0); | |
2450 | n = (difference & 0x80000000); | |
2451 | c = (source1 > source1); | |
2452 | v = ((source1 & 0x80000000) == (source2 & 0x80000000) | |
2453 | && (source1 & 0x80000000) != (difference & 0x80000000)); | |
2454 | ||
2455 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2456 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
2457 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
2458 | } | |
2459 | ||
2460 | // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd | |
2461 | 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc | |
2462 | "subc" | |
2463 | *am33 | |
2464 | { | |
2465 | int z, c, n, v; | |
24a39d88 | 2466 | unsigned32 difference, source1, source2; |
c2d11a7d JM |
2467 | int srcreg1, srcreg2, dstreg; |
2468 | ||
2469 | PC = cia; | |
2470 | srcreg1 = translate_rreg (SD_, RM2); | |
2471 | srcreg2 = translate_rreg (SD_, RN0); | |
2472 | dstreg = translate_rreg (SD_, RD0); | |
2473 | ||
2474 | source1 = State.regs[srcreg1]; | |
2475 | source2 = State.regs[srcreg2]; | |
2476 | difference = source2 - source1 - ((PSW & PSW_C) != 0); | |
2477 | State.regs[dstreg] = difference; | |
2478 | ||
2479 | z = ((PSW & PSW_Z) != 0) && (difference == 0); | |
2480 | n = (difference & 0x80000000); | |
2481 | c = (source1 > source2); | |
2482 | v = ((source1 & 0x80000000) == (source2 & 0x80000000) | |
2483 | && (source1 & 0x80000000) != (difference & 0x80000000)); | |
2484 | ||
2485 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2486 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
2487 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
2488 | } | |
2489 | ||
2490 | // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd | |
2491 | 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and | |
2492 | "and" | |
2493 | *am33 | |
2494 | { | |
2495 | int z, n; | |
2496 | int srcreg1, srcreg2, dstreg; | |
2497 | ||
2498 | PC = cia; | |
2499 | srcreg1 = translate_rreg (SD_, RM2); | |
2500 | srcreg2 = translate_rreg (SD_, RN0); | |
2501 | dstreg = translate_rreg (SD_, RD0); | |
2502 | ||
2503 | State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2]; | |
2504 | ||
2505 | z = (State.regs[dstreg] == 0); | |
2506 | n = (State.regs[dstreg] & 0x80000000); | |
2507 | ||
2508 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2509 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); | |
2510 | } | |
2511 | ||
2512 | // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd | |
2513 | 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or | |
2514 | "or" | |
2515 | *am33 | |
2516 | { | |
2517 | int z, n; | |
2518 | int srcreg1, srcreg2, dstreg; | |
2519 | ||
2520 | PC = cia; | |
2521 | srcreg1 = translate_rreg (SD_, RM2); | |
2522 | srcreg2 = translate_rreg (SD_, RN0); | |
2523 | dstreg = translate_rreg (SD_, RD0); | |
2524 | ||
2525 | State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2]; | |
2526 | ||
2527 | z = (State.regs[dstreg] == 0); | |
2528 | n = (State.regs[dstreg] & 0x80000000); | |
2529 | ||
2530 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2531 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); | |
2532 | } | |
2533 | ||
2534 | // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd | |
2535 | 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor | |
2536 | "xor" | |
2537 | *am33 | |
2538 | { | |
2539 | int z, n; | |
2540 | int srcreg1, srcreg2, dstreg; | |
2541 | ||
2542 | PC = cia; | |
2543 | srcreg1 = translate_rreg (SD_, RM2); | |
2544 | srcreg2 = translate_rreg (SD_, RN0); | |
2545 | dstreg = translate_rreg (SD_, RD0); | |
2546 | ||
2547 | State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2]; | |
2548 | ||
2549 | z = (State.regs[dstreg] == 0); | |
2550 | n = (State.regs[dstreg] & 0x80000000); | |
2551 | ||
2552 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2553 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); | |
2554 | } | |
2555 | ||
2556 | // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd | |
2557 | 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr | |
2558 | "asr" | |
2559 | *am33 | |
2560 | { | |
2561 | int z, c, n; | |
24a39d88 | 2562 | signed32 temp; |
c2d11a7d JM |
2563 | int srcreg1, srcreg2, dstreg; |
2564 | ||
2565 | PC = cia; | |
2566 | srcreg1 = translate_rreg (SD_, RM2); | |
2567 | srcreg2 = translate_rreg (SD_, RN0); | |
2568 | dstreg = translate_rreg (SD_, RD0); | |
2569 | ||
2570 | temp = State.regs[srcreg2]; | |
2571 | c = temp & 1; | |
2572 | temp >>= State.regs[srcreg1]; | |
2573 | State.regs[dstreg] = temp; | |
2574 | ||
2575 | z = (State.regs[dstreg] == 0); | |
2576 | n = (State.regs[dstreg] & 0x80000000); | |
2577 | ||
2578 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
2579 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); | |
2580 | } | |
2581 | ||
2582 | // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd | |
2583 | 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr | |
2584 | "lsr" | |
2585 | *am33 | |
2586 | { | |
2587 | int z, c, n; | |
2588 | int srcreg1, srcreg2, dstreg; | |
2589 | ||
2590 | PC = cia; | |
2591 | srcreg1 = translate_rreg (SD_, RM2); | |
2592 | srcreg2 = translate_rreg (SD_, RN0); | |
2593 | dstreg = translate_rreg (SD_, RD0); | |
2594 | ||
2595 | c = State.regs[srcreg2] & 1; | |
2596 | State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1]; | |
2597 | ||
2598 | z = (State.regs[dstreg] == 0); | |
2599 | n = (State.regs[dstreg] & 0x80000000); | |
2600 | ||
2601 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
2602 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); | |
2603 | } | |
2604 | ||
2605 | // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd | |
2606 | 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl | |
2607 | "asl" | |
2608 | *am33 | |
2609 | { | |
2610 | int z, n; | |
2611 | int srcreg1, srcreg2, dstreg; | |
2612 | ||
2613 | PC = cia; | |
2614 | srcreg1 = translate_rreg (SD_, RM2); | |
2615 | srcreg2 = translate_rreg (SD_, RN0); | |
2616 | dstreg = translate_rreg (SD_, RD0); | |
2617 | ||
2618 | State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1]; | |
2619 | ||
2620 | z = (State.regs[dstreg] == 0); | |
2621 | n = (State.regs[dstreg] & 0x80000000); | |
2622 | ||
2623 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
2624 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); | |
2625 | } | |
2626 | ||
2627 | // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2 | |
2628 | 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul | |
2629 | "mul" | |
2630 | *am33 | |
2631 | { | |
2632 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 | 2633 | signed64 temp; |
c2d11a7d JM |
2634 | int n, z; |
2635 | ||
2636 | PC = cia; | |
2637 | srcreg1 = translate_rreg (SD_, RM2); | |
2638 | srcreg2 = translate_rreg (SD_, RN0); | |
2639 | dstreg1 = translate_rreg (SD_, RD0); | |
2640 | dstreg2 = translate_rreg (SD_, RD2); | |
2641 | ||
2642 | temp = ((signed64)(signed32)State.regs[srcreg1] | |
2643 | * (signed64)(signed32)State.regs[srcreg2]); | |
2644 | State.regs[dstreg2] = temp & 0xffffffff; | |
2645 | State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32; | |
2646 | ||
2647 | z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0); | |
2648 | n = (State.regs[dstreg1] & 0x80000000); | |
2649 | ||
2650 | PSW &= ~(PSW_Z | PSW_N); | |
2651 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); | |
2652 | } | |
2653 | ||
2654 | // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2 | |
2655 | 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu | |
2656 | "mulu" | |
2657 | *am33 | |
2658 | { | |
2659 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 | 2660 | signed64 temp; |
c2d11a7d JM |
2661 | int n, z; |
2662 | ||
2663 | PC = cia; | |
2664 | srcreg1 = translate_rreg (SD_, RM2); | |
2665 | srcreg2 = translate_rreg (SD_, RN0); | |
2666 | dstreg1 = translate_rreg (SD_, RD0); | |
2667 | dstreg2 = translate_rreg (SD_, RD2); | |
2668 | ||
2669 | temp = ((unsigned64)State.regs[srcreg1] | |
2670 | * (unsigned64)State.regs[srcreg2]); | |
2671 | State.regs[dstreg2] = temp & 0xffffffff; | |
2672 | State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32; | |
2673 | ||
2674 | z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0); | |
2675 | n = (State.regs[dstreg1] & 0x80000000); | |
2676 | ||
2677 | PSW &= ~(PSW_Z | PSW_N); | |
2678 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); | |
2679 | } | |
2680 | ||
2681 | // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn | |
2682 | 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov | |
2683 | "mov" | |
2684 | *am33 | |
2685 | { | |
2686 | int dstreg; | |
2687 | ||
2688 | PC = cia; | |
2689 | dstreg = translate_rreg (SD_, RN2); | |
2690 | State.regs[dstreg] = load_word (IMM8); | |
2691 | } | |
2692 | ||
2693 | // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8) | |
2694 | 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov | |
2695 | "mov" | |
2696 | *am33 | |
2697 | { | |
2698 | int srcreg; | |
2699 | ||
2700 | PC = cia; | |
2701 | srcreg = translate_rreg (SD_, RM2); | |
2702 | store_word (IMM8, State.regs[srcreg]); | |
2703 | } | |
2704 | ||
2705 | // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn | |
2706 | 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu | |
2707 | "movbu" | |
2708 | *am33 | |
2709 | { | |
2710 | int dstreg; | |
2711 | ||
2712 | PC = cia; | |
2713 | dstreg = translate_rreg (SD_, RN2); | |
2714 | State.regs[dstreg] = load_byte (IMM8); | |
2715 | } | |
2716 | ||
2717 | // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8) | |
2718 | 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu | |
2719 | "movbu" | |
2720 | *am33 | |
2721 | { | |
2722 | int srcreg; | |
2723 | ||
2724 | PC = cia; | |
2725 | srcreg = translate_rreg (SD_, RM2); | |
2726 | store_byte (IMM8, State.regs[srcreg]); | |
2727 | } | |
2728 | ||
2729 | // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn | |
2730 | 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu | |
2731 | "movhu" | |
2732 | *am33 | |
2733 | { | |
2734 | int dstreg; | |
2735 | ||
2736 | PC = cia; | |
2737 | dstreg = translate_rreg (SD_, RN2); | |
2738 | State.regs[dstreg] = load_half (IMM8); | |
2739 | } | |
2740 | ||
2741 | // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8) | |
2742 | 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu | |
2743 | "movhu" | |
2744 | *am33 | |
2745 | { | |
2746 | int srcreg; | |
2747 | ||
2748 | PC = cia; | |
2749 | srcreg = translate_rreg (SD_, RM2); | |
2750 | store_half (IMM8, State.regs[srcreg]); | |
2751 | } | |
2752 | ||
2753 | // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn | |
2754 | 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov | |
2755 | "mov" | |
2756 | *am33 | |
2757 | { | |
2758 | int srcreg1, srcreg2, dstreg; | |
2759 | ||
2760 | PC = cia; | |
2761 | srcreg1 = translate_rreg (SD_, RM0); | |
5425ca99 | 2762 | srcreg2 = translate_rreg (SD_, RI0); |
c2d11a7d JM |
2763 | dstreg = translate_rreg (SD_, RN0); |
2764 | State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]); | |
2765 | } | |
2766 | ||
2767 | // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm) | |
2768 | 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov | |
2769 | "mov" | |
2770 | *am33 | |
2771 | { | |
2772 | int srcreg, dstreg1, dstreg2; | |
2773 | ||
2774 | PC = cia; | |
2775 | srcreg = translate_rreg (SD_, RM0); | |
2776 | dstreg1 = translate_rreg (SD_, RI0); | |
2777 | dstreg2 = translate_rreg (SD_, RN0); | |
2778 | store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]); | |
2779 | } | |
2780 | ||
2781 | // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn | |
2782 | 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu | |
2783 | "movbu" | |
2784 | *am33 | |
2785 | { | |
2786 | int srcreg1, srcreg2, dstreg; | |
2787 | ||
2788 | PC = cia; | |
2789 | srcreg1 = translate_rreg (SD_, RM0); | |
5425ca99 | 2790 | srcreg2 = translate_rreg (SD_, RI0); |
c2d11a7d JM |
2791 | dstreg = translate_rreg (SD_, RN0); |
2792 | State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]); | |
2793 | } | |
2794 | ||
2795 | // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm) | |
2796 | 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu | |
2797 | "movbu" | |
2798 | *am33 | |
2799 | { | |
2800 | int srcreg, dstreg1, dstreg2; | |
2801 | ||
2802 | PC = cia; | |
2803 | srcreg = translate_rreg (SD_, RM0); | |
2804 | dstreg1 = translate_rreg (SD_, RI0); | |
2805 | dstreg2 = translate_rreg (SD_, RN0); | |
2806 | store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]); | |
2807 | } | |
2808 | ||
2809 | // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn | |
2810 | 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu | |
2811 | "movhu" | |
2812 | *am33 | |
2813 | { | |
2814 | int srcreg1, srcreg2, dstreg; | |
2815 | ||
2816 | PC = cia; | |
2817 | srcreg1 = translate_rreg (SD_, RM0); | |
5425ca99 | 2818 | srcreg2 = translate_rreg (SD_, RI0); |
c2d11a7d JM |
2819 | dstreg = translate_rreg (SD_, RN0); |
2820 | State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]); | |
2821 | } | |
2822 | ||
2823 | // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm) | |
2824 | 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu | |
2825 | "movhu" | |
2826 | *am33 | |
2827 | { | |
2828 | int srcreg, dstreg1, dstreg2; | |
2829 | ||
2830 | PC = cia; | |
2831 | srcreg = translate_rreg (SD_, RM0); | |
2832 | dstreg1 = translate_rreg (SD_, RI0); | |
2833 | dstreg2 = translate_rreg (SD_, RN0); | |
2834 | store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]); | |
2835 | } | |
2836 | ||
2837 | // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2 | |
2838 | 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac | |
2839 | "mac" | |
2840 | *am33 | |
2841 | { | |
2842 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 AO |
2843 | signed64 temp; |
2844 | unsigned32 sum; | |
c2d11a7d JM |
2845 | int c, v; |
2846 | ||
2847 | PC = cia; | |
2848 | srcreg1 = translate_rreg (SD_, RM2); | |
2849 | srcreg2 = translate_rreg (SD_, RN0); | |
2850 | dstreg1 = translate_rreg (SD_, RD0); | |
2851 | dstreg2 = translate_rreg (SD_, RD2); | |
2852 | ||
2853 | temp = ((signed64)(signed32)State.regs[srcreg1] | |
2854 | * (signed64)(signed32)State.regs[srcreg2]); | |
2855 | ||
2856 | sum = State.regs[dstreg2] + (temp & 0xffffffff); | |
2857 | c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff)); | |
2858 | State.regs[dstreg2] = sum; | |
2859 | temp >>= 32; | |
2860 | temp &= 0xffffffff; | |
2861 | sum = State.regs[dstreg1] + temp + c; | |
2862 | v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) | |
2863 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
2864 | State.regs[dstreg1] = sum; | |
2865 | if (v) | |
2866 | { | |
2867 | State.regs[REG_MCVF] = 1; | |
2868 | PSW &= ~(PSW_V); | |
2869 | PSW |= (( v ? PSW_V : 0)); | |
2870 | } | |
2871 | } | |
2872 | ||
2873 | // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2 | |
2874 | 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu | |
2875 | "macu" | |
2876 | *am33 | |
2877 | { | |
2878 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 AO |
2879 | signed64 temp; |
2880 | unsigned32 sum; | |
c2d11a7d JM |
2881 | int c, v; |
2882 | ||
2883 | PC = cia; | |
2884 | srcreg1 = translate_rreg (SD_, RM2); | |
2885 | srcreg2 = translate_rreg (SD_, RN0); | |
2886 | dstreg1 = translate_rreg (SD_, RD0); | |
2887 | dstreg2 = translate_rreg (SD_, RD2); | |
2888 | ||
2889 | temp = ((unsigned64)State.regs[srcreg1] | |
2890 | * (unsigned64)State.regs[srcreg2]); | |
2891 | ||
2892 | sum = State.regs[dstreg2] + (temp & 0xffffffff); | |
2893 | c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff)); | |
2894 | State.regs[dstreg2] = sum; | |
2895 | temp >>= 32; | |
2896 | temp &= 0xffffffff; | |
2897 | sum = State.regs[dstreg1] + temp + c; | |
2898 | v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) | |
2899 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
2900 | State.regs[dstreg1] = sum; | |
2901 | if (v) | |
2902 | { | |
2903 | State.regs[REG_MCVF] = 1; | |
2904 | PSW &= ~(PSW_V); | |
2905 | PSW |= (( v ? PSW_V : 0)); | |
2906 | } | |
2907 | } | |
2908 | ||
2909 | // 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1 | |
2910 | 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb | |
2911 | "macb" | |
2912 | *am33 | |
2913 | { | |
2914 | int srcreg1, srcreg2, dstreg; | |
24a39d88 | 2915 | signed32 temp, sum; |
c2d11a7d JM |
2916 | int v; |
2917 | ||
2918 | PC = cia; | |
2919 | srcreg1 = translate_rreg (SD_, RM2); | |
2920 | srcreg2 = translate_rreg (SD_, RN0); | |
2921 | dstreg = translate_rreg (SD_, RD0); | |
2922 | ||
2923 | temp = ((signed32)(State.regs[srcreg2] & 0xff) | |
2924 | * (signed32)(State.regs[srcreg1] & 0xff)); | |
2925 | sum = State.regs[dstreg] + temp; | |
2926 | v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) | |
2927 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
2928 | State.regs[dstreg] = sum; | |
2929 | if (v) | |
2930 | { | |
2931 | State.regs[REG_MCVF] = 1; | |
2932 | PSW &= ~(PSW_V); | |
2933 | PSW |= ((v ? PSW_V : 0)); | |
2934 | } | |
2935 | } | |
2936 | ||
2937 | // 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1 | |
2938 | 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu | |
2939 | "macbu" | |
2940 | *am33 | |
2941 | { | |
2942 | int srcreg1, srcreg2, dstreg; | |
24a39d88 | 2943 | signed32 temp, sum; |
c2d11a7d JM |
2944 | int v; |
2945 | ||
2946 | PC = cia; | |
2947 | srcreg1 = translate_rreg (SD_, RM2); | |
2948 | srcreg2 = translate_rreg (SD_, RN0); | |
2949 | dstreg = translate_rreg (SD_, RD0); | |
2950 | ||
2951 | temp = ((unsigned32)(State.regs[srcreg2] & 0xff) | |
2952 | * (unsigned32)(State.regs[srcreg1] & 0xff)); | |
2953 | sum = State.regs[dstreg] + temp; | |
2954 | v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) | |
2955 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
2956 | State.regs[dstreg] = sum; | |
2957 | if (v) | |
2958 | { | |
2959 | State.regs[REG_MCVF] = 1; | |
2960 | PSW &= ~(PSW_V); | |
2961 | PSW |= ((v ? PSW_V : 0)); | |
2962 | } | |
2963 | } | |
2964 | ||
2965 | // 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2 | |
2966 | 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach | |
2967 | "mach" | |
2968 | *am33 | |
2969 | { | |
2970 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 | 2971 | signed64 temp, sum; |
c2d11a7d JM |
2972 | int v; |
2973 | ||
2974 | PC = cia; | |
2975 | srcreg1 = translate_rreg (SD_, RM2); | |
2976 | srcreg2 = translate_rreg (SD_, RN0); | |
2977 | dstreg1 = translate_rreg (SD_, RD0); | |
2978 | dstreg2 = translate_rreg (SD_, RD0); | |
2979 | ||
2980 | temp = ((signed32)(State.regs[srcreg2] & 0xffff) | |
2981 | * (signed32)(State.regs[srcreg1] & 0xffff)); | |
2982 | State.regs[dstreg2] += (temp & 0xffffffff); | |
2983 | sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff); | |
2984 | v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) | |
2985 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
2986 | State.regs[dstreg1] = sum; | |
2987 | if (v) | |
2988 | { | |
2989 | State.regs[REG_MCVF] = 1; | |
2990 | PSW &= ~(PSW_V); | |
2991 | PSW |= ((v ? PSW_V : 0)); | |
2992 | } | |
2993 | } | |
2994 | ||
2995 | // 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2 | |
2996 | 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu | |
2997 | "machu" | |
2998 | *am33 | |
2999 | { | |
3000 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 | 3001 | signed64 temp, sum; |
c2d11a7d JM |
3002 | int v; |
3003 | ||
3004 | PC = cia; | |
3005 | srcreg1 = translate_rreg (SD_, RM2); | |
3006 | srcreg2 = translate_rreg (SD_, RN0); | |
3007 | dstreg1 = translate_rreg (SD_, RD0); | |
3008 | dstreg2 = translate_rreg (SD_, RD0); | |
3009 | ||
3010 | temp = ((unsigned32)(State.regs[srcreg2] & 0xffff) | |
3011 | * (unsigned32)(State.regs[srcreg1] & 0xffff)); | |
3012 | State.regs[dstreg2] += (temp & 0xffffffff); | |
3013 | sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff); | |
3014 | v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) | |
3015 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
3016 | State.regs[dstreg1] = sum; | |
3017 | if (v) | |
3018 | { | |
3019 | State.regs[REG_MCVF] = 1; | |
3020 | PSW &= ~(PSW_V); | |
3021 | PSW |= ((v ? PSW_V : 0)); | |
3022 | } | |
3023 | } | |
3024 | ||
3025 | // 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1 | |
3026 | 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach | |
3027 | "dmach" | |
3028 | *am33 | |
3029 | { | |
3030 | int srcreg1, srcreg2, dstreg; | |
24a39d88 | 3031 | signed32 temp, temp2, sum; |
c2d11a7d JM |
3032 | int v; |
3033 | ||
3034 | PC = cia; | |
3035 | srcreg1 = translate_rreg (SD_, RM2); | |
3036 | srcreg2 = translate_rreg (SD_, RN0); | |
3037 | dstreg = translate_rreg (SD_, RD0); | |
3038 | ||
3039 | temp = ((signed32)(State.regs[srcreg2] & 0xffff) | |
3040 | * (signed32)(State.regs[srcreg1] & 0xffff)); | |
3041 | temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff) | |
3042 | * (signed32)((State.regs[srcreg2] >> 16) & 0xffff)); | |
3043 | sum = temp + temp2 + State.regs[dstreg]; | |
3044 | v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) | |
3045 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
3046 | State.regs[dstreg] = sum; | |
3047 | if (v) | |
3048 | { | |
3049 | State.regs[REG_MCVF] = 1; | |
3050 | PSW &= ~(PSW_V); | |
3051 | PSW |= ((v ? PSW_V : 0)); | |
3052 | } | |
3053 | } | |
3054 | ||
3055 | // 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1 | |
3056 | 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu | |
3057 | "dmachu" | |
3058 | *am33 | |
3059 | { | |
3060 | int srcreg1, srcreg2, dstreg; | |
24a39d88 | 3061 | signed32 temp, temp2, sum; |
c2d11a7d JM |
3062 | int v; |
3063 | ||
3064 | PC = cia; | |
3065 | srcreg1 = translate_rreg (SD_, RM2); | |
3066 | srcreg2 = translate_rreg (SD_, RN0); | |
3067 | dstreg = translate_rreg (SD_, RD0); | |
3068 | ||
3069 | temp = ((unsigned32)(State.regs[srcreg2] & 0xffff) | |
3070 | * (unsigned32)(State.regs[srcreg1] & 0xffff)); | |
3071 | temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff) | |
3072 | * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff)); | |
3073 | sum = temp + temp2 + State.regs[dstreg]; | |
3074 | v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) | |
3075 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
3076 | State.regs[dstreg] = sum; | |
3077 | if (v) | |
3078 | { | |
3079 | State.regs[REG_MCVF] = 1; | |
3080 | PSW &= ~(PSW_V); | |
3081 | PSW |= ((v ? PSW_V : 0)); | |
3082 | } | |
3083 | } | |
3084 | ||
3085 | // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2 | |
3086 | 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh | |
3087 | "dmulh" | |
3088 | *am33 | |
3089 | { | |
3090 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 | 3091 | signed64 temp; |
c2d11a7d JM |
3092 | |
3093 | PC = cia; | |
3094 | srcreg1 = translate_rreg (SD_, RM2); | |
3095 | srcreg2 = translate_rreg (SD_, RN0); | |
3096 | dstreg1 = translate_rreg (SD_, RD0); | |
3097 | dstreg2 = translate_rreg (SD_, RD2); | |
3098 | ||
3099 | temp = ((signed32)(State.regs[srcreg1] & 0xffff) | |
3100 | * (signed32)(State.regs[srcreg1] & 0xffff)); | |
3101 | State.regs[dstreg2] = temp; | |
3102 | temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff) | |
3103 | * (signed32)((State.regs[srcreg1] >>16) & 0xffff)); | |
3104 | State.regs[dstreg1] = temp; | |
3105 | } | |
3106 | ||
3107 | // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2 | |
3108 | 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu | |
3109 | "dmulhu" | |
3110 | *am33 | |
3111 | { | |
3112 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 | 3113 | signed64 temp; |
c2d11a7d JM |
3114 | |
3115 | PC = cia; | |
3116 | srcreg1 = translate_rreg (SD_, RM2); | |
3117 | srcreg2 = translate_rreg (SD_, RN0); | |
3118 | dstreg1 = translate_rreg (SD_, RD0); | |
3119 | dstreg2 = translate_rreg (SD_, RD2); | |
3120 | ||
3121 | temp = ((unsigned32)(State.regs[srcreg1] & 0xffff) | |
3122 | * (unsigned32)(State.regs[srcreg1] & 0xffff)); | |
3123 | State.regs[dstreg2] = temp; | |
3124 | temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff) | |
3125 | * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff)); | |
3126 | State.regs[dstreg1] = temp; | |
3127 | } | |
3128 | ||
3129 | // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn | |
3130 | 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24 | |
3131 | "sat24" | |
3132 | *am33 | |
3133 | { | |
3134 | int srcreg, dstreg; | |
3135 | int value, n, z; | |
3136 | ||
3137 | PC = cia; | |
3138 | srcreg = translate_rreg (SD_, RM2); | |
3139 | dstreg = translate_rreg (SD_, RN0); | |
3140 | ||
3141 | value = State.regs[srcreg]; | |
3142 | ||
3143 | if (value >= 0x7fffff) | |
3144 | State.regs[dstreg] = 0x7fffff; | |
3145 | else if (value <= 0xff800000) | |
3146 | State.regs[dstreg] = 0xff800000; | |
3147 | else | |
3148 | State.regs[dstreg] = value; | |
3149 | ||
3150 | n = (State.regs[dstreg] & 0x800000) != 0; | |
3151 | z = (State.regs[dstreg] == 0); | |
3152 | PSW &= ~(PSW_Z | PSW_N); | |
3153 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3154 | } | |
3155 | ||
3156 | // 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1 | |
3157 | 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch | |
3158 | "bsch" | |
3159 | *am33 | |
3160 | { | |
3161 | int temp, c, i; | |
3162 | int srcreg1, srcreg2, dstreg; | |
3163 | int start; | |
3164 | ||
3165 | PC = cia; | |
3166 | srcreg1 = translate_rreg (SD_, RM2); | |
3167 | srcreg2 = translate_rreg (SD_, RN0); | |
3168 | dstreg = translate_rreg (SD_, RD0); | |
3169 | ||
3170 | temp = State.regs[srcreg1]; | |
3171 | start = (State.regs[srcreg2] & 0x1f) - 1; | |
3172 | if (start == -1) | |
3173 | start = 31; | |
5425ca99 AO |
3174 | |
3175 | c = 0; | |
c2d11a7d JM |
3176 | for (i = start; i >= 0; i--) |
3177 | { | |
3178 | if (temp & (1 << i)) | |
3179 | { | |
3180 | c = 1; | |
3181 | State.regs[dstreg] = i; | |
3182 | break; | |
3183 | } | |
3184 | } | |
3185 | ||
3186 | if (i < 0) | |
3187 | { | |
3188 | c = 0; | |
3189 | State.regs[dstreg] = 0; | |
3190 | } | |
3191 | PSW &= ~(PSW_C); | |
3192 | PSW |= (c ? PSW_C : 0); | |
3193 | } | |
3194 | ||
3195 | // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn | |
3196 | 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov | |
3197 | "mov" | |
3198 | *am33 | |
3199 | { | |
3200 | int dstreg; | |
3201 | ||
3202 | PC = cia; | |
3203 | dstreg = translate_rreg (SD_, RN0); | |
3204 | State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); | |
3205 | } | |
3206 | ||
3207 | // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn | |
3208 | 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu | |
3209 | "movu" | |
3210 | *am33 | |
3211 | { | |
3212 | int dstreg; | |
3213 | ||
3214 | PC = cia; | |
3215 | dstreg = translate_rreg (SD_, RN0); | |
3216 | State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff; | |
3217 | } | |
3218 | ||
3219 | // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn | |
3220 | 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add | |
3221 | "add" | |
3222 | *am33 | |
3223 | { | |
3224 | int dstreg; | |
3225 | ||
3226 | PC = cia; | |
3227 | dstreg = translate_rreg (SD_, RN0); | |
3228 | genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg); | |
3229 | } | |
3230 | ||
3231 | // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn | |
3232 | 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc | |
3233 | "addc" | |
3234 | *am33 | |
3235 | { | |
3236 | int dstreg, z, n, c, v; | |
24a39d88 | 3237 | unsigned32 sum, imm, reg2; |
c2d11a7d JM |
3238 | |
3239 | PC = cia; | |
3240 | dstreg = translate_rreg (SD_, RN0); | |
3241 | ||
3242 | imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); | |
3243 | reg2 = State.regs[dstreg]; | |
3244 | sum = imm + reg2 + ((PSW & PSW_C) != 0); | |
3245 | State.regs[dstreg] = sum; | |
3246 | ||
3247 | z = ((PSW & PSW_Z) != 0) && (sum == 0); | |
3248 | n = (sum & 0x80000000); | |
3249 | c = (sum < imm) || (sum < reg2); | |
3250 | v = ((reg2 & 0x80000000) == (imm & 0x80000000) | |
3251 | && (reg2 & 0x80000000) != (sum & 0x80000000)); | |
3252 | ||
3253 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3254 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
3255 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
3256 | } | |
3257 | ||
3258 | // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn | |
3259 | 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub | |
3260 | "sub" | |
3261 | *am33 | |
3262 | { | |
3263 | int dstreg; | |
3264 | ||
3265 | PC = cia; | |
3266 | dstreg = translate_rreg (SD_, RN0); | |
3267 | genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg); | |
3268 | } | |
3269 | ||
3270 | // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn | |
3271 | 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc | |
3272 | "subc" | |
3273 | *am33 | |
3274 | { | |
3275 | int dstreg, z, n, c, v; | |
24a39d88 | 3276 | unsigned32 difference, imm, reg2; |
c2d11a7d JM |
3277 | |
3278 | PC = cia; | |
3279 | dstreg = translate_rreg (SD_, RN0); | |
3280 | ||
3281 | imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); | |
3282 | reg2 = State.regs[dstreg]; | |
3283 | difference = reg2 - imm - ((PSW & PSW_C) != 0); | |
3284 | State.regs[dstreg] = difference; | |
3285 | ||
3286 | z = ((PSW & PSW_Z) != 0) && (difference == 0); | |
3287 | n = (difference & 0x80000000); | |
3288 | c = (imm > reg2); | |
3289 | v = ((reg2 & 0x80000000) == (imm & 0x80000000) | |
3290 | && (reg2 & 0x80000000) != (difference & 0x80000000)); | |
3291 | ||
3292 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3293 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
3294 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
3295 | } | |
3296 | ||
3297 | // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn | |
3298 | 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp | |
3299 | "cmp" | |
3300 | *am33 | |
3301 | { | |
3302 | int srcreg; | |
3303 | ||
3304 | PC = cia; | |
3305 | srcreg = translate_rreg (SD_, RN0); | |
3306 | genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]); | |
3307 | } | |
3308 | ||
3309 | // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn | |
3310 | 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov | |
3311 | "mov" | |
3312 | *am33 | |
3313 | { | |
3314 | int dstreg; | |
3315 | ||
3316 | PC = cia; | |
3317 | dstreg = translate_xreg (SD_, XRN0); | |
3318 | ||
3319 | State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff; | |
3320 | } | |
3321 | ||
3322 | // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn | |
3323 | 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and | |
3324 | "and" | |
3325 | *am33 | |
3326 | { | |
3327 | int dstreg; | |
3328 | int z,n; | |
3329 | ||
3330 | PC = cia; | |
3331 | dstreg = translate_rreg (SD_, RN0); | |
3332 | ||
3333 | State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff); | |
3334 | z = (State.regs[dstreg] == 0); | |
3335 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
3336 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3337 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3338 | } | |
3339 | ||
3340 | // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn | |
3341 | 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or | |
3342 | "or" | |
3343 | *am33 | |
3344 | { | |
3345 | int dstreg; | |
3346 | int z,n; | |
3347 | ||
3348 | PC = cia; | |
3349 | dstreg = translate_rreg (SD_, RN0); | |
3350 | ||
3351 | State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff); | |
3352 | z = (State.regs[dstreg] == 0); | |
3353 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
3354 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3355 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3356 | } | |
3357 | ||
3358 | // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn | |
3359 | 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor | |
3360 | "xor" | |
3361 | *am33 | |
3362 | { | |
3363 | int dstreg; | |
3364 | int z,n; | |
3365 | ||
3366 | PC = cia; | |
3367 | dstreg = translate_rreg (SD_, RN0); | |
3368 | ||
3369 | State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff); | |
3370 | z = (State.regs[dstreg] == 0); | |
3371 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
3372 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3373 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3374 | } | |
3375 | ||
3376 | // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn | |
3377 | 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr | |
3378 | "asr" | |
3379 | *am33 | |
3380 | { | |
3381 | int dstreg; | |
24a39d88 | 3382 | signed32 temp; |
c2d11a7d JM |
3383 | int c, z, n; |
3384 | ||
3385 | PC = cia; | |
3386 | dstreg = translate_rreg (SD_, RN0); | |
3387 | ||
3388 | temp = State.regs[dstreg]; | |
3389 | c = temp & 1; | |
3390 | temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C)); | |
3391 | State.regs[dstreg] = temp; | |
3392 | z = (State.regs[dstreg] == 0); | |
3393 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
3394 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
3395 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
3396 | } | |
3397 | ||
3398 | ||
3399 | // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn | |
3400 | 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr | |
3401 | "lsr" | |
3402 | *am33 | |
3403 | { | |
3404 | int dstreg; | |
3405 | int z, n, c; | |
3406 | ||
3407 | PC = cia; | |
3408 | dstreg = translate_rreg (SD_, RN0); | |
3409 | ||
3410 | c = State.regs[dstreg] & 1; | |
3411 | State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C)); | |
3412 | z = (State.regs[dstreg] == 0); | |
3413 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
3414 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
3415 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
3416 | } | |
3417 | ||
3418 | // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn | |
3419 | 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl | |
3420 | "asl" | |
3421 | *am33 | |
3422 | { | |
5425ca99 | 3423 | int dstreg; |
c2d11a7d JM |
3424 | int z, n; |
3425 | ||
3426 | PC = cia; | |
3427 | dstreg = translate_rreg (SD_, RN0); | |
3428 | ||
3429 | State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C)); | |
3430 | z = (State.regs[dstreg] == 0); | |
3431 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
3432 | PSW &= ~(PSW_Z | PSW_N); | |
3433 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3434 | } | |
3435 | ||
3436 | // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn | |
3437 | 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul | |
3438 | "mul" | |
3439 | *am33 | |
3440 | { | |
3441 | int dstreg; | |
24a39d88 | 3442 | unsigned64 temp; |
c2d11a7d JM |
3443 | int z, n; |
3444 | ||
3445 | PC = cia; | |
3446 | dstreg = translate_rreg (SD_, RN0); | |
3447 | ||
3448 | temp = ((signed64)(signed32)State.regs[dstreg] | |
3449 | * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))); | |
3450 | State.regs[dstreg] = temp & 0xffffffff; | |
3451 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; | |
3452 | z = (State.regs[dstreg] == 0); | |
3453 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
3454 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3455 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3456 | } | |
3457 | ||
3458 | // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn | |
3459 | 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu | |
3460 | "mulu" | |
3461 | *am33 | |
3462 | { | |
3463 | int dstreg; | |
24a39d88 | 3464 | unsigned64 temp; |
c2d11a7d JM |
3465 | int z, n; |
3466 | ||
3467 | PC = cia; | |
3468 | dstreg = translate_rreg (SD_, RN0); | |
3469 | ||
3470 | temp = ((unsigned64)State.regs[dstreg] | |
3471 | * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))); | |
3472 | State.regs[dstreg] = temp & 0xffffffff; | |
3473 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; | |
3474 | z = (State.regs[dstreg] == 0); | |
3475 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
3476 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3477 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3478 | } | |
3479 | ||
3480 | // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn | |
3481 | 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst | |
3482 | "btst" | |
3483 | *am33 | |
3484 | { | |
3485 | int srcreg; | |
3486 | ||
3487 | PC = cia; | |
3488 | srcreg = translate_rreg (SD_, RN0); | |
3489 | genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); | |
3490 | } | |
3491 | ||
3492 | // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn | |
3493 | 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov | |
3494 | "mov" | |
3495 | *am33 | |
3496 | { | |
3497 | int srcreg, dstreg; | |
3498 | ||
3499 | PC = cia; | |
3500 | srcreg = translate_rreg (SD_, RM0); | |
3501 | dstreg = translate_rreg (SD_, RN2); | |
3502 | State.regs[dstreg] = load_word (State.regs[srcreg] | |
3503 | + EXTEND24 (FETCH24 (IMM24A, | |
3504 | IMM24B, IMM24C))); | |
3505 | } | |
3506 | ||
3507 | // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn) | |
3508 | 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov | |
3509 | "mov" | |
3510 | *am33 | |
3511 | { | |
3512 | int srcreg, dstreg; | |
3513 | ||
3514 | PC = cia; | |
3515 | srcreg = translate_rreg (SD_, RM2); | |
3516 | dstreg = translate_rreg (SD_, RN0); | |
3517 | store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), | |
3518 | State.regs[srcreg]); | |
3519 | } | |
3520 | ||
3521 | // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn | |
3522 | 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu | |
3523 | "movbu" | |
3524 | *am33 | |
3525 | { | |
3526 | int srcreg, dstreg; | |
3527 | ||
3528 | PC = cia; | |
3529 | srcreg = translate_rreg (SD_, RM0); | |
3530 | dstreg = translate_rreg (SD_, RN2); | |
3531 | State.regs[dstreg] = load_byte (State.regs[srcreg] | |
3532 | + EXTEND24 (FETCH24 (IMM24A, | |
3533 | IMM24B, IMM24C))); | |
3534 | } | |
3535 | ||
3536 | // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn) | |
3537 | 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu | |
3538 | "movbu" | |
3539 | *am33 | |
3540 | { | |
3541 | int srcreg, dstreg; | |
3542 | ||
3543 | PC = cia; | |
3544 | srcreg = translate_rreg (SD_, RM2); | |
3545 | dstreg = translate_rreg (SD_, RN0); | |
3546 | store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), | |
3547 | State.regs[srcreg]); | |
3548 | } | |
3549 | ||
3550 | // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn | |
3551 | 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu | |
3552 | "movhu" | |
3553 | *am33 | |
3554 | { | |
3555 | int srcreg, dstreg; | |
3556 | ||
3557 | PC = cia; | |
3558 | srcreg = translate_rreg (SD_, RM0); | |
3559 | dstreg = translate_rreg (SD_, RN2); | |
3560 | State.regs[dstreg] = load_half (State.regs[srcreg] | |
3561 | + EXTEND24 (FETCH24 (IMM24A, | |
3562 | IMM24B, IMM24C))); | |
3563 | } | |
3564 | ||
3565 | // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn) | |
3566 | 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu | |
3567 | "movhu" | |
3568 | *am33 | |
3569 | { | |
3570 | int srcreg, dstreg; | |
3571 | ||
3572 | PC = cia; | |
3573 | srcreg = translate_rreg (SD_, RM2); | |
3574 | dstreg = translate_rreg (SD_, RN0); | |
3575 | store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), | |
3576 | State.regs[srcreg]); | |
3577 | } | |
3578 | ||
3579 | // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn | |
3580 | 8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov | |
3581 | "mov" | |
3582 | *am33 | |
3583 | { | |
3584 | int srcreg, dstreg; | |
3585 | ||
3586 | PC = cia; | |
3587 | srcreg = translate_rreg (SD_, RM0); | |
3588 | dstreg = translate_rreg (SD_, RN2); | |
3589 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
3590 | State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); | |
3591 | } | |
3592 | ||
3593 | // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+) | |
3594 | 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov | |
3595 | "mov" | |
3596 | *am33 | |
3597 | { | |
3598 | int srcreg, dstreg; | |
3599 | ||
3600 | PC = cia; | |
3601 | srcreg = translate_rreg (SD_, RM2); | |
3602 | dstreg = translate_rreg (SD_, RN0); | |
3603 | store_word (State.regs[dstreg], State.regs[srcreg]); | |
3604 | State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); | |
3605 | } | |
3606 | ||
3607 | ||
3608 | // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn | |
3609 | 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov | |
3610 | "mov" | |
3611 | *am33 | |
3612 | { | |
3613 | int dstreg; | |
3614 | ||
3615 | PC = cia; | |
3616 | dstreg = translate_rreg (SD_, RN2); | |
3617 | State.regs[dstreg] = load_word (State.regs[REG_SP] | |
d8e7020f | 3618 | + FETCH24 (IMM24A, IMM24B, IMM24C)); |
c2d11a7d JM |
3619 | } |
3620 | ||
3621 | // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp) | |
3622 | 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov | |
3623 | "mov" | |
3624 | *am33 | |
3625 | { | |
3626 | int srcreg; | |
3627 | ||
3628 | PC = cia; | |
3629 | srcreg = translate_rreg (SD_, RM2); | |
d8e7020f | 3630 | store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C), |
c2d11a7d JM |
3631 | State.regs[srcreg]); |
3632 | } | |
3633 | ||
e33c0364 | 3634 | // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,sp),Rn |
c2d11a7d JM |
3635 | 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu |
3636 | "movbu" | |
3637 | *am33 | |
3638 | { | |
3639 | int dstreg; | |
3640 | ||
3641 | PC = cia; | |
3642 | dstreg = translate_rreg (SD_, RN2); | |
3643 | State.regs[dstreg] = load_byte (State.regs[REG_SP] | |
e33c0364 | 3644 | + FETCH24 (IMM24A, IMM24B, IMM24C)); |
c2d11a7d JM |
3645 | } |
3646 | ||
3647 | // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp) | |
3648 | 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu | |
3649 | "movbu" | |
3650 | *am33 | |
3651 | { | |
3652 | int srcreg; | |
3653 | ||
3654 | PC = cia; | |
3655 | srcreg = translate_rreg (SD_, RM2); | |
d8e7020f | 3656 | store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C), |
c2d11a7d JM |
3657 | State.regs[srcreg]); |
3658 | } | |
3659 | ||
3660 | // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn | |
3661 | 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu | |
3662 | "movhu" | |
3663 | *am33 | |
3664 | { | |
3665 | int dstreg; | |
3666 | ||
3667 | PC = cia; | |
3668 | dstreg = translate_rreg (SD_, RN2); | |
3669 | State.regs[dstreg] = load_half (State.regs[REG_SP] | |
d8e7020f | 3670 | + FETCH24 (IMM24A, IMM24B, IMM24C)); |
c2d11a7d JM |
3671 | } |
3672 | ||
3673 | // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp) | |
3674 | 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu | |
3675 | "movhu" | |
3676 | *am33 | |
3677 | { | |
3678 | int srcreg; | |
3679 | ||
3680 | PC = cia; | |
3681 | srcreg = translate_rreg (SD_, RM2); | |
d8e7020f | 3682 | store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C), |
c2d11a7d JM |
3683 | State.regs[srcreg]); |
3684 | } | |
3685 | ||
3686 | // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn | |
3687 | 8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu | |
3688 | "movhu" | |
3689 | *am33 | |
3690 | { | |
3691 | int srcreg, dstreg; | |
3692 | ||
3693 | PC = cia; | |
3694 | srcreg = translate_rreg (SD_, RM0); | |
3695 | dstreg = translate_rreg (SD_, RN2); | |
3696 | State.regs[dstreg] = load_half (State.regs[srcreg]); | |
3697 | State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); | |
3698 | } | |
3699 | ||
3700 | // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+) | |
3701 | 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu | |
3702 | "movhu" | |
3703 | *am33 | |
3704 | { | |
3705 | int srcreg, dstreg; | |
3706 | ||
3707 | PC = cia; | |
3708 | srcreg = translate_rreg (SD_, RM2); | |
3709 | dstreg = translate_rreg (SD_, RN0); | |
3710 | store_half (State.regs[dstreg], State.regs[srcreg]); | |
3711 | State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); | |
3712 | } | |
3713 | ||
3714 | // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn | |
3715 | 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac | |
3716 | "mac" | |
3717 | *am33 | |
3718 | { | |
3719 | int srcreg; | |
24a39d88 | 3720 | signed64 temp, sum; |
c2d11a7d JM |
3721 | int c, v; |
3722 | ||
3723 | PC = cia; | |
3724 | srcreg = translate_rreg (SD_, RN2); | |
3725 | ||
3726 | temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)) | |
3727 | * (signed64)State.regs[srcreg]); | |
3728 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
3729 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
3730 | State.regs[REG_MCRL] = sum; | |
3731 | temp >>= 32; | |
3732 | temp &= 0xffffffff; | |
3733 | sum = State.regs[REG_MCRH] + temp + c; | |
3734 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
3735 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
3736 | State.regs[REG_MCRH] = sum; | |
3737 | if (v) | |
3738 | State.regs[REG_MCVF] = 1; | |
3739 | } | |
3740 | ||
3741 | // 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn | |
3742 | 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu | |
3743 | "macu" | |
3744 | *am33 | |
3745 | { | |
3746 | int srcreg; | |
24a39d88 | 3747 | signed64 temp, sum; |
c2d11a7d JM |
3748 | int c, v; |
3749 | ||
3750 | PC = cia; | |
3751 | srcreg = translate_rreg (SD_, RN2); | |
3752 | ||
3753 | temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C)) | |
3754 | * (unsigned64)State.regs[srcreg]); | |
3755 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
3756 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
3757 | State.regs[REG_MCRL] = sum; | |
3758 | temp >>= 32; | |
3759 | temp &= 0xffffffff; | |
3760 | sum = State.regs[REG_MCRH] + temp + c; | |
3761 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
3762 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
3763 | State.regs[REG_MCRH] = sum; | |
3764 | if (v) | |
3765 | State.regs[REG_MCVF] = 1; | |
3766 | } | |
3767 | ||
3768 | // 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn | |
3769 | 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb | |
3770 | "macb" | |
3771 | *am33 | |
3772 | { | |
3773 | int srcreg; | |
24a39d88 | 3774 | signed64 temp, sum; |
c2d11a7d JM |
3775 | int c, v; |
3776 | ||
3777 | PC = cia; | |
3778 | srcreg = translate_rreg (SD_, RN2); | |
3779 | ||
3780 | temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)) | |
3781 | * (signed64)State.regs[srcreg] & 0xff); | |
3782 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
3783 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
3784 | State.regs[REG_MCRL] = sum; | |
3785 | temp >>= 32; | |
3786 | temp &= 0xffffffff; | |
3787 | sum = State.regs[REG_MCRH] + temp + c; | |
3788 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
3789 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
3790 | State.regs[REG_MCRH] = sum; | |
3791 | if (v) | |
3792 | State.regs[REG_MCVF] = 1; | |
3793 | } | |
3794 | ||
3795 | // 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn | |
3796 | 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu | |
3797 | "macbu" | |
3798 | *am33 | |
3799 | { | |
3800 | int srcreg; | |
24a39d88 | 3801 | signed64 temp, sum; |
c2d11a7d JM |
3802 | int c, v; |
3803 | ||
3804 | PC = cia; | |
3805 | srcreg = translate_rreg (SD_, RN2); | |
3806 | ||
3807 | temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C)) | |
3808 | * (unsigned64)State.regs[srcreg] & 0xff); | |
3809 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
3810 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
3811 | State.regs[REG_MCRL] = sum; | |
3812 | temp >>= 32; | |
3813 | temp &= 0xffffffff; | |
3814 | sum = State.regs[REG_MCRH] + temp + c; | |
3815 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
3816 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
3817 | State.regs[REG_MCRH] = sum; | |
3818 | if (v) | |
3819 | State.regs[REG_MCVF] = 1; | |
3820 | } | |
3821 | ||
3822 | // 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn | |
3823 | 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach | |
3824 | "mach" | |
3825 | *am33 | |
3826 | { | |
3827 | int srcreg; | |
24a39d88 | 3828 | signed64 temp, sum; |
c2d11a7d JM |
3829 | int c, v; |
3830 | ||
3831 | PC = cia; | |
3832 | srcreg = translate_rreg (SD_, RN2); | |
3833 | ||
3834 | temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C)) | |
3835 | * (signed64)State.regs[srcreg] & 0xffff); | |
3836 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
3837 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
3838 | State.regs[REG_MCRL] = sum; | |
3839 | temp >>= 32; | |
3840 | temp &= 0xffffffff; | |
3841 | sum = State.regs[REG_MCRH] + temp + c; | |
3842 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
3843 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
3844 | State.regs[REG_MCRH] = sum; | |
3845 | if (v) | |
3846 | State.regs[REG_MCVF] = 1; | |
3847 | } | |
3848 | ||
3849 | // 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn | |
3850 | 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu | |
3851 | "machu" | |
3852 | *am33 | |
3853 | { | |
3854 | int srcreg; | |
24a39d88 | 3855 | signed64 temp, sum; |
c2d11a7d JM |
3856 | int c, v; |
3857 | ||
3858 | PC = cia; | |
3859 | srcreg = translate_rreg (SD_, RN2); | |
3860 | ||
3861 | temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff) | |
3862 | * (unsigned64)State.regs[srcreg] & 0xffff); | |
3863 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
3864 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
3865 | State.regs[REG_MCRL] = sum; | |
3866 | temp >>= 32; | |
3867 | temp &= 0xffffffff; | |
3868 | sum = State.regs[REG_MCRH] + temp + c; | |
3869 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
3870 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
3871 | State.regs[REG_MCRH] = sum; | |
3872 | if (v) | |
3873 | State.regs[REG_MCVF] = 1; | |
3874 | } | |
3875 | ||
3876 | // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn | |
3877 | 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov | |
3878 | "mov" | |
3879 | *am33 | |
3880 | { | |
3881 | int dstreg; | |
3882 | ||
3883 | PC = cia; | |
3884 | dstreg = translate_rreg (SD_, RN2); | |
3885 | State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C)); | |
3886 | } | |
3887 | ||
3888 | // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24) | |
3889 | 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov | |
3890 | "mov" | |
3891 | *am33 | |
3892 | { | |
3893 | int srcreg; | |
3894 | ||
3895 | PC = cia; | |
3896 | srcreg = translate_rreg (SD_, RM2); | |
3897 | store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); | |
3898 | } | |
3899 | ||
3900 | ||
3901 | // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn | |
3902 | 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu | |
3903 | "movbu" | |
3904 | *am33 | |
3905 | { | |
3906 | int dstreg; | |
3907 | ||
3908 | PC = cia; | |
3909 | dstreg = translate_rreg (SD_, RN2); | |
3910 | State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C)); | |
3911 | } | |
3912 | ||
3913 | // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24) | |
3914 | 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu | |
3915 | "movbu" | |
3916 | *am33 | |
3917 | { | |
3918 | int srcreg; | |
3919 | ||
3920 | PC = cia; | |
3921 | srcreg = translate_rreg (SD_, RM2); | |
3922 | store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); | |
3923 | } | |
3924 | ||
3925 | ||
3926 | // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn | |
3927 | 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu | |
3928 | "movhu" | |
3929 | *am33 | |
3930 | { | |
3931 | int dstreg; | |
3932 | ||
3933 | PC = cia; | |
3934 | dstreg = translate_rreg (SD_, RN2); | |
3935 | State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C)); | |
3936 | } | |
3937 | ||
3938 | // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24) | |
3939 | 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu | |
3940 | "movhu" | |
3941 | *am33 | |
3942 | { | |
3943 | int srcreg; | |
3944 | ||
3945 | PC = cia; | |
3946 | srcreg = translate_rreg (SD_, RM2); | |
3947 | store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); | |
3948 | } | |
3949 | ||
3950 | ||
3951 | // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn | |
3952 | 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov | |
3953 | "mov" | |
3954 | *am33 | |
3955 | { | |
3956 | int dstreg; | |
3957 | ||
3958 | PC = cia; | |
3959 | dstreg = translate_rreg (SD_, RN0); | |
3960 | State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); | |
3961 | } | |
3962 | ||
3963 | // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn | |
3964 | 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu | |
3965 | "movu" | |
3966 | *am33 | |
3967 | { | |
3968 | int dstreg; | |
3969 | ||
3970 | PC = cia; | |
3971 | dstreg = translate_rreg (SD_, RN0); | |
3972 | State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); | |
3973 | } | |
3974 | ||
3975 | // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn | |
3976 | 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add | |
3977 | "add" | |
3978 | *am33 | |
3979 | { | |
3980 | int dstreg; | |
3981 | ||
3982 | PC = cia; | |
3983 | dstreg = translate_rreg (SD_, RN0); | |
3984 | genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg); | |
3985 | } | |
3986 | ||
3987 | // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn | |
3988 | 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc | |
3989 | "addc" | |
3990 | *am33 | |
3991 | { | |
3992 | int dstreg; | |
24a39d88 | 3993 | unsigned32 imm, reg2, sum; |
c2d11a7d JM |
3994 | int z, n, c, v; |
3995 | ||
3996 | PC = cia; | |
3997 | dstreg = translate_rreg (SD_, RN0); | |
3998 | ||
3999 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4000 | reg2 = State.regs[dstreg]; | |
4001 | sum = imm + reg2 + ((PSW & PSW_C) != 0); | |
4002 | State.regs[dstreg] = sum; | |
4003 | ||
4004 | z = ((PSW & PSW_Z) != 0) && (sum == 0); | |
4005 | n = (sum & 0x80000000); | |
4006 | c = (sum < imm) || (sum < reg2); | |
4007 | v = ((reg2 & 0x80000000) == (imm & 0x80000000) | |
4008 | && (reg2 & 0x80000000) != (sum & 0x80000000)); | |
4009 | ||
4010 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
4011 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
4012 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
4013 | } | |
4014 | ||
4015 | // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn | |
4016 | 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub | |
4017 | "sub" | |
4018 | *am33 | |
4019 | { | |
4020 | int dstreg; | |
4021 | ||
4022 | PC = cia; | |
4023 | dstreg = translate_rreg (SD_, RN0); | |
4024 | genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg); | |
4025 | } | |
4026 | ||
4027 | // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn | |
4028 | 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc | |
4029 | "subc" | |
4030 | *am33 | |
4031 | { | |
4032 | int dstreg; | |
24a39d88 | 4033 | unsigned32 imm, reg2, difference; |
c2d11a7d JM |
4034 | int z, n, c, v; |
4035 | ||
4036 | PC = cia; | |
4037 | dstreg = translate_rreg (SD_, RN0); | |
4038 | ||
4039 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4040 | reg2 = State.regs[dstreg]; | |
4041 | difference = reg2 - imm - ((PSW & PSW_C) != 0); | |
4042 | State.regs[dstreg] = difference; | |
4043 | ||
4044 | z = ((PSW & PSW_Z) != 0) && (difference == 0); | |
4045 | n = (difference & 0x80000000); | |
4046 | c = (imm > reg2); | |
4047 | v = ((reg2 & 0x80000000) == (imm & 0x80000000) | |
4048 | && (reg2 & 0x80000000) != (difference & 0x80000000)); | |
4049 | ||
4050 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
4051 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
4052 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
4053 | } | |
4054 | ||
4055 | // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn | |
4056 | 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp | |
4057 | "cmp" | |
4058 | *am33 | |
4059 | { | |
4060 | int srcreg; | |
4061 | ||
4062 | PC = cia; | |
4063 | srcreg = translate_rreg (SD_, RN0); | |
4064 | genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); | |
4065 | } | |
4066 | ||
4067 | // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn | |
4068 | 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov | |
4069 | "mov" | |
4070 | *am33 | |
4071 | { | |
4072 | int dstreg; | |
4073 | ||
4074 | PC = cia; | |
4075 | dstreg = translate_xreg (SD_, XRN0); | |
4076 | ||
4077 | State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); | |
4078 | } | |
4079 | ||
4080 | // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn | |
4081 | 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and | |
4082 | "and" | |
4083 | *am33 | |
4084 | { | |
4085 | int dstreg; | |
4086 | int z,n; | |
4087 | ||
4088 | PC = cia; | |
4089 | dstreg = translate_rreg (SD_, RN0); | |
4090 | ||
4091 | State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4092 | z = (State.regs[dstreg] == 0); | |
4093 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
4094 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
4095 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
4096 | } | |
4097 | ||
4098 | // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn | |
4099 | 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or | |
4100 | "or" | |
4101 | *am33 | |
4102 | { | |
4103 | int dstreg; | |
4104 | int z,n; | |
4105 | ||
4106 | PC = cia; | |
4107 | dstreg = translate_rreg (SD_, RN0); | |
4108 | ||
4109 | State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4110 | z = (State.regs[dstreg] == 0); | |
4111 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
4112 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
4113 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
4114 | } | |
4115 | ||
4116 | // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn | |
4117 | 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor | |
4118 | "xor" | |
4119 | *am33 | |
4120 | { | |
4121 | int dstreg; | |
4122 | int z,n; | |
4123 | ||
4124 | PC = cia; | |
4125 | dstreg = translate_rreg (SD_, RN0); | |
4126 | ||
4127 | State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4128 | z = (State.regs[dstreg] == 0); | |
4129 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
4130 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
4131 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
4132 | } | |
4133 | ||
4134 | // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn | |
4135 | 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr | |
4136 | "asr" | |
4137 | *am33 | |
4138 | { | |
4139 | int dstreg; | |
24a39d88 | 4140 | signed32 temp; |
c2d11a7d JM |
4141 | int c, z, n; |
4142 | ||
4143 | PC = cia; | |
4144 | dstreg = translate_rreg (SD_, RN0); | |
4145 | ||
4146 | temp = State.regs[dstreg]; | |
4147 | c = temp & 1; | |
4148 | temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4149 | State.regs[dstreg] = temp; | |
4150 | z = (State.regs[dstreg] == 0); | |
4151 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
4152 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
4153 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
4154 | } | |
4155 | ||
4156 | // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn | |
4157 | 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr | |
4158 | "lsr" | |
4159 | *am33 | |
4160 | { | |
4161 | int dstreg; | |
4162 | int z, n, c; | |
4163 | ||
4164 | PC = cia; | |
4165 | dstreg = translate_rreg (SD_, RN0); | |
4166 | ||
4167 | c = State.regs[dstreg] & 1; | |
4168 | State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4169 | z = (State.regs[dstreg] == 0); | |
4170 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
4171 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
4172 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
4173 | } | |
4174 | ||
4175 | // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn | |
4176 | 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl | |
4177 | "asl" | |
4178 | *am33 | |
4179 | { | |
5425ca99 | 4180 | int dstreg; |
c2d11a7d JM |
4181 | int z, n; |
4182 | ||
4183 | PC = cia; | |
4184 | dstreg = translate_rreg (SD_, RN0); | |
4185 | ||
4186 | State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4187 | z = (State.regs[dstreg] == 0); | |
4188 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
4189 | PSW &= ~(PSW_Z | PSW_N); | |
4190 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
4191 | } | |
4192 | ||
4193 | // 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn | |
4194 | 8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul | |
4195 | "mul" | |
4196 | *am33 | |
4197 | { | |
4198 | int dstreg; | |
24a39d88 | 4199 | unsigned64 temp; |
c2d11a7d JM |
4200 | int z, n; |
4201 | ||
4202 | PC = cia; | |
4203 | dstreg = translate_rreg (SD_, RN0); | |
4204 | ||
4205 | temp = ((signed64)(signed32)State.regs[dstreg] | |
4206 | * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D))); | |
4207 | State.regs[dstreg] = temp & 0xffffffff; | |
4208 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; | |
4209 | z = (State.regs[dstreg] == 0); | |
4210 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
4211 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
4212 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
4213 | } | |
4214 | ||
4215 | // 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn | |
4216 | 8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu | |
4217 | "mulu" | |
4218 | *am33 | |
4219 | { | |
4220 | int dstreg; | |
24a39d88 | 4221 | unsigned64 temp; |
c2d11a7d JM |
4222 | int z, n; |
4223 | ||
4224 | PC = cia; | |
4225 | dstreg = translate_rreg (SD_, RN0); | |
4226 | ||
4227 | temp = ((unsigned64)State.regs[dstreg] | |
4228 | * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D))); | |
4229 | State.regs[dstreg] = temp & 0xffffffff; | |
4230 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; | |
4231 | z = (State.regs[dstreg] == 0); | |
4232 | n = (State.regs[dstreg] & 0x80000000) != 0; | |
4233 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
4234 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
4235 | } | |
4236 | ||
4237 | // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn | |
4238 | 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst | |
4239 | "btst" | |
4240 | *am33 | |
4241 | { | |
4242 | int srcreg; | |
4243 | ||
4244 | PC = cia; | |
4245 | srcreg = translate_rreg (SD_, RN0); | |
4246 | genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); | |
4247 | } | |
4248 | ||
4249 | // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn | |
4250 | 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov | |
4251 | "mov" | |
4252 | *am33 | |
4253 | { | |
4254 | int srcreg, dstreg; | |
4255 | ||
4256 | PC = cia; | |
4257 | srcreg = translate_rreg (SD_, RM0); | |
4258 | dstreg = translate_rreg (SD_, RN2); | |
4259 | State.regs[dstreg] = load_word (State.regs[srcreg] | |
4260 | + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4261 | } | |
4262 | ||
4263 | // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn) | |
4264 | 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov | |
4265 | "mov" | |
4266 | *am33 | |
4267 | { | |
4268 | int srcreg, dstreg; | |
4269 | ||
4270 | PC = cia; | |
4271 | srcreg = translate_rreg (SD_, RM2); | |
4272 | dstreg = translate_rreg (SD_, RN0); | |
4273 | store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), | |
4274 | State.regs[srcreg]); | |
4275 | } | |
4276 | ||
4277 | // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn | |
4278 | 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu | |
4279 | "movbu" | |
4280 | *am33 | |
4281 | { | |
4282 | int srcreg, dstreg; | |
4283 | ||
4284 | PC = cia; | |
4285 | srcreg = translate_rreg (SD_, RM0); | |
4286 | dstreg = translate_rreg (SD_, RN2); | |
4287 | State.regs[dstreg] = load_byte (State.regs[srcreg] | |
4288 | + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4289 | } | |
4290 | ||
4291 | // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn) | |
4292 | 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu | |
4293 | "movbu" | |
4294 | *am33 | |
4295 | { | |
4296 | int srcreg, dstreg; | |
4297 | ||
4298 | PC = cia; | |
4299 | srcreg = translate_rreg (SD_, RM2); | |
4300 | dstreg = translate_rreg (SD_, RN0); | |
4301 | store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), | |
4302 | State.regs[srcreg]); | |
4303 | } | |
4304 | ||
4305 | // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn | |
4306 | 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu | |
4307 | "movhu" | |
4308 | *am33 | |
4309 | { | |
4310 | int srcreg, dstreg; | |
4311 | ||
4312 | PC = cia; | |
4313 | srcreg = translate_rreg (SD_, RM0); | |
4314 | dstreg = translate_rreg (SD_, RN2); | |
4315 | State.regs[dstreg] = load_half (State.regs[srcreg] | |
4316 | + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4317 | } | |
4318 | ||
4319 | // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn) | |
4320 | 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu | |
4321 | "movhu" | |
4322 | *am33 | |
4323 | { | |
4324 | int srcreg, dstreg; | |
4325 | ||
4326 | PC = cia; | |
4327 | srcreg = translate_rreg (SD_, RM2); | |
4328 | dstreg = translate_rreg (SD_, RN0); | |
4329 | store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), | |
4330 | State.regs[srcreg]); | |
4331 | } | |
4332 | ||
4333 | // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn | |
4334 | 8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov | |
4335 | "mov" | |
4336 | *am33 | |
4337 | { | |
4338 | int srcreg, dstreg; | |
4339 | ||
4340 | PC = cia; | |
4341 | srcreg = translate_rreg (SD_, RM0); | |
4342 | dstreg = translate_rreg (SD_, RN2); | |
4343 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
4344 | State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4345 | } | |
4346 | ||
4347 | // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+) | |
4348 | 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov | |
4349 | "mov" | |
4350 | *am33 | |
4351 | { | |
4352 | int srcreg, dstreg; | |
4353 | ||
4354 | PC = cia; | |
4355 | srcreg = translate_rreg (SD_, RM2); | |
4356 | dstreg = translate_rreg (SD_, RN0); | |
4357 | store_word (State.regs[dstreg], State.regs[srcreg]); | |
4358 | State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4359 | } | |
4360 | ||
4361 | ||
4362 | // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn | |
4363 | 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov | |
4364 | "mov" | |
4365 | *am33 | |
4366 | { | |
4367 | int dstreg; | |
4368 | ||
4369 | PC = cia; | |
4370 | dstreg = translate_rreg (SD_, RN2); | |
4371 | State.regs[dstreg] = load_word (State.regs[REG_SP] | |
4372 | + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4373 | } | |
4374 | ||
4375 | // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp) | |
4376 | 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov | |
4377 | "mov" | |
4378 | *am33 | |
4379 | { | |
4380 | int srcreg; | |
4381 | ||
4382 | PC = cia; | |
4383 | srcreg = translate_rreg (SD_, RM2); | |
4384 | store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), | |
4385 | State.regs[srcreg]); | |
4386 | } | |
4387 | ||
4388 | // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn | |
4389 | 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu | |
4390 | "movbu" | |
4391 | *am33 | |
4392 | { | |
4393 | int dstreg; | |
4394 | ||
4395 | PC = cia; | |
4396 | dstreg = translate_rreg (SD_, RN2); | |
4397 | State.regs[dstreg] = load_byte (State.regs[REG_SP] | |
4398 | + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4399 | } | |
4400 | ||
4401 | // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp) | |
4402 | 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu | |
4403 | "movbu" | |
4404 | *am33 | |
4405 | { | |
4406 | int srcreg; | |
4407 | ||
4408 | PC = cia; | |
4409 | srcreg = translate_rreg (SD_, RM2); | |
4410 | store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), | |
4411 | State.regs[srcreg]); | |
4412 | } | |
4413 | ||
4414 | // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn | |
4415 | 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu | |
4416 | "movhu" | |
4417 | *am33 | |
4418 | { | |
4419 | int dstreg; | |
4420 | ||
4421 | PC = cia; | |
4422 | dstreg = translate_rreg (SD_, RN2); | |
4423 | State.regs[dstreg] = load_half (State.regs[REG_SP] | |
4424 | + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4425 | } | |
4426 | ||
4427 | // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp) | |
4428 | 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu | |
4429 | "movhu" | |
4430 | *am33 | |
4431 | { | |
4432 | int srcreg; | |
4433 | ||
4434 | PC = cia; | |
4435 | srcreg = translate_rreg (SD_, RM2); | |
4436 | store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), | |
4437 | State.regs[srcreg]); | |
4438 | } | |
4439 | ||
4440 | ||
4441 | // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn | |
4442 | 8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu | |
4443 | "movhu" | |
4444 | *am33 | |
4445 | { | |
4446 | int srcreg, dstreg; | |
4447 | ||
4448 | PC = cia; | |
4449 | srcreg = translate_rreg (SD_, RM0); | |
4450 | dstreg = translate_rreg (SD_, RN2); | |
4451 | State.regs[dstreg] = load_half (State.regs[srcreg]); | |
4452 | State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4453 | } | |
4454 | ||
4455 | // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+) | |
4456 | 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu | |
4457 | "movhu" | |
4458 | *am33 | |
4459 | { | |
4460 | int srcreg, dstreg; | |
4461 | ||
4462 | PC = cia; | |
4463 | srcreg = translate_rreg (SD_, RM2); | |
4464 | dstreg = translate_rreg (SD_, RN0); | |
4465 | store_half (State.regs[dstreg], State.regs[srcreg]); | |
4466 | State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4467 | } | |
4468 | ||
4469 | ||
4470 | // 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn | |
4471 | 8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac | |
4472 | "mac" | |
4473 | *am33 | |
4474 | { | |
4475 | int srcreg, imm; | |
24a39d88 | 4476 | signed64 temp, sum; |
c2d11a7d JM |
4477 | int c, v; |
4478 | ||
4479 | PC = cia; | |
4480 | srcreg = translate_rreg (SD_, RN0); | |
4481 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4482 | ||
4483 | temp = ((signed64)(signed32)State.regs[srcreg] | |
4484 | * (signed64)(signed32)imm); | |
4485 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
4486 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
4487 | State.regs[REG_MCRL] = sum; | |
4488 | temp >>= 32; | |
4489 | temp &= 0xffffffff; | |
4490 | sum = State.regs[REG_MCRH] + temp + c; | |
4491 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
4492 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
4493 | State.regs[REG_MCRH] = sum; | |
4494 | if (v) | |
4495 | State.regs[REG_MCVF] = 1; | |
4496 | } | |
4497 | ||
4498 | // 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn | |
4499 | 8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu | |
4500 | "macu" | |
4501 | *am33 | |
4502 | { | |
4503 | int srcreg, imm; | |
24a39d88 | 4504 | signed64 temp, sum; |
c2d11a7d JM |
4505 | int c, v; |
4506 | ||
4507 | PC = cia; | |
4508 | srcreg = translate_rreg (SD_, RN0); | |
4509 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4510 | ||
4511 | temp = ((unsigned64)State.regs[srcreg] | |
4512 | * (unsigned64)imm); | |
4513 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); | |
4514 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); | |
4515 | State.regs[REG_MCRL] = sum; | |
4516 | temp >>= 32; | |
4517 | temp &= 0xffffffff; | |
4518 | sum = State.regs[REG_MCRH] + temp + c; | |
4519 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) | |
4520 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
4521 | State.regs[REG_MCRH] = sum; | |
4522 | if (v) | |
4523 | State.regs[REG_MCVF] = 1; | |
4524 | } | |
4525 | ||
4526 | // 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn | |
4527 | 8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb | |
4528 | "macb" | |
4529 | *am33 | |
4530 | { | |
4531 | int srcreg, imm; | |
24a39d88 | 4532 | signed32 temp, sum; |
c2d11a7d JM |
4533 | int v; |
4534 | ||
4535 | PC = cia; | |
4536 | srcreg = translate_rreg (SD_, RN0); | |
4537 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4538 | ||
4539 | temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff) | |
4540 | * (signed32)(signed8)(imm & 0xff)); | |
4541 | sum = State.regs[REG_MCRL] + temp; | |
4542 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) | |
4543 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
4544 | State.regs[REG_MCRL] = sum; | |
4545 | if (v) | |
4546 | State.regs[REG_MCVF] = 1; | |
4547 | } | |
4548 | ||
4549 | // 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn | |
4550 | 8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu | |
4551 | "macbu" | |
4552 | *am33 | |
4553 | { | |
4554 | int srcreg, imm; | |
24a39d88 | 4555 | signed32 temp, sum; |
c2d11a7d JM |
4556 | int v; |
4557 | ||
4558 | PC = cia; | |
4559 | srcreg = translate_rreg (SD_, RN0); | |
4560 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4561 | ||
4562 | temp = ((unsigned32)(State.regs[srcreg] & 0xff) | |
4563 | * (unsigned32)(imm & 0xff)); | |
4564 | sum = State.regs[REG_MCRL] + temp; | |
4565 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) | |
4566 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
4567 | State.regs[REG_MCRL] = sum; | |
4568 | if (v) | |
4569 | State.regs[REG_MCVF] = 1; | |
4570 | } | |
4571 | ||
4572 | // 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn | |
4573 | 8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach | |
4574 | "mach" | |
4575 | *am33 | |
4576 | { | |
4577 | int srcreg, imm; | |
24a39d88 | 4578 | signed32 temp, sum; |
c2d11a7d JM |
4579 | int v; |
4580 | ||
4581 | PC = cia; | |
4582 | srcreg = translate_rreg (SD_, RN0); | |
4583 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4584 | ||
4585 | temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff) | |
4586 | * (signed32)(signed16)(imm & 0xffff)); | |
4587 | sum = State.regs[REG_MCRL] + temp; | |
4588 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) | |
4589 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
4590 | State.regs[REG_MCRL] = sum; | |
4591 | if (v) | |
4592 | State.regs[REG_MCVF] = 1; | |
4593 | } | |
4594 | ||
4595 | // 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn | |
4596 | 8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu | |
4597 | "machu" | |
4598 | *am33 | |
4599 | { | |
4600 | int srcreg, imm; | |
24a39d88 | 4601 | signed32 temp, sum; |
c2d11a7d JM |
4602 | int v; |
4603 | ||
4604 | PC = cia; | |
4605 | srcreg = translate_rreg (SD_, RN0); | |
4606 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4607 | ||
4608 | temp = ((unsigned32)(State.regs[srcreg] & 0xffff) | |
4609 | * (unsigned32)(imm & 0xffff)); | |
4610 | sum = State.regs[REG_MCRL] + temp; | |
4611 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) | |
4612 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
4613 | State.regs[REG_MCRL] = sum; | |
4614 | if (v) | |
4615 | State.regs[REG_MCVF] = 1; | |
4616 | } | |
4617 | ||
4618 | // 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn | |
4619 | 8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach | |
4620 | "dmach" | |
4621 | *am33 | |
4622 | { | |
4623 | int srcreg, imm; | |
24a39d88 | 4624 | signed32 temp, temp2, sum; |
c2d11a7d JM |
4625 | int v; |
4626 | ||
4627 | PC = cia; | |
4628 | srcreg = translate_rreg (SD_, RN0); | |
4629 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4630 | ||
4631 | temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff) | |
4632 | * (signed32)(signed16)(imm & 0xffff)); | |
4633 | temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff) | |
4634 | * (signed32)(signed16)((imm >> 16) & 0xffff)); | |
4635 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
4636 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) | |
4637 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
4638 | State.regs[REG_MCRL] = sum; | |
4639 | if (v) | |
4640 | State.regs[REG_MCVF] = 1; | |
4641 | } | |
4642 | ||
4643 | // 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn | |
4644 | 8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu | |
4645 | "dmachu" | |
4646 | *am33 | |
4647 | { | |
4648 | int srcreg, imm; | |
24a39d88 | 4649 | signed32 temp, temp2, sum; |
c2d11a7d JM |
4650 | int v; |
4651 | ||
4652 | PC = cia; | |
4653 | srcreg = translate_rreg (SD_, RN0); | |
4654 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4655 | ||
4656 | temp = ((unsigned32)(State.regs[srcreg] & 0xffff) | |
4657 | * (unsigned32)(imm & 0xffff)); | |
4658 | temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff) | |
4659 | * (unsigned32)((imm >> 16) & 0xffff)); | |
4660 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
4661 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) | |
4662 | && (temp & 0x80000000) != (sum & 0x80000000)); | |
4663 | State.regs[REG_MCRL] = sum; | |
4664 | if (v) | |
4665 | State.regs[REG_MCVF] = 1; | |
4666 | } | |
4667 | ||
4668 | // 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn | |
4669 | 8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh | |
4670 | "dmulh" | |
4671 | *am33 | |
4672 | { | |
4673 | int imm, dstreg; | |
24a39d88 | 4674 | signed32 temp; |
c2d11a7d JM |
4675 | |
4676 | PC = cia; | |
4677 | dstreg = translate_rreg (SD_, RN0); | |
4678 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4679 | ||
4680 | temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff) | |
4681 | * (signed32)(signed16)(imm & 0xffff)); | |
4682 | State.regs[REG_MDRQ] = temp; | |
4683 | temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff) | |
4684 | * (signed32)(signed16)((imm>>16) & 0xffff)); | |
4685 | State.regs[dstreg] = temp; | |
4686 | } | |
4687 | ||
4688 | // 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn | |
4689 | 8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu | |
4690 | "dmulhu" | |
4691 | *am33 | |
4692 | { | |
4693 | int imm, dstreg; | |
24a39d88 | 4694 | signed32 temp; |
c2d11a7d JM |
4695 | |
4696 | PC = cia; | |
4697 | dstreg = translate_rreg (SD_, RN0); | |
4698 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); | |
4699 | ||
4700 | temp = ((unsigned32)(State.regs[dstreg] & 0xffff) | |
4701 | * (unsigned32)(imm & 0xffff)); | |
4702 | State.regs[REG_MDRQ] = temp; | |
4703 | temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff) | |
4704 | * (unsigned32)((imm >>16) & 0xffff)); | |
4705 | State.regs[dstreg] = temp; | |
4706 | } | |
4707 | ||
4708 | // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn | |
4709 | 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov | |
4710 | "mov" | |
4711 | *am33 | |
4712 | { | |
4713 | int dstreg; | |
4714 | ||
4715 | PC = cia; | |
4716 | dstreg = translate_rreg (SD_, RN2); | |
4717 | State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4718 | } | |
4719 | ||
4720 | // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32) | |
4721 | 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov | |
4722 | "mov" | |
4723 | *am33 | |
4724 | { | |
4725 | int srcreg; | |
4726 | ||
4727 | PC = cia; | |
4728 | srcreg = translate_rreg (SD_, RM2); | |
4729 | store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); | |
4730 | } | |
4731 | ||
4732 | // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn | |
4733 | 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu | |
4734 | "movbu" | |
4735 | *am33 | |
4736 | { | |
4737 | int dstreg; | |
4738 | ||
4739 | PC = cia; | |
4740 | dstreg = translate_rreg (SD_, RN2); | |
4741 | State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4742 | } | |
4743 | ||
4744 | // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32) | |
4745 | 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu | |
4746 | "movbu" | |
4747 | *am33 | |
4748 | { | |
4749 | int srcreg; | |
4750 | ||
4751 | PC = cia; | |
4752 | srcreg = translate_rreg (SD_, RM2); | |
4753 | store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); | |
4754 | } | |
4755 | ||
4756 | // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn | |
4757 | 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu | |
4758 | "movhu" | |
4759 | *am33 | |
4760 | { | |
4761 | int dstreg; | |
4762 | ||
4763 | PC = cia; | |
4764 | dstreg = translate_rreg (SD_, RN2); | |
4765 | State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); | |
4766 | } | |
4767 | ||
4768 | // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32) | |
4769 | 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu | |
4770 | "movhu" | |
4771 | *am33 | |
4772 | { | |
4773 | int srcreg; | |
4774 | ||
4775 | PC = cia; | |
4776 | srcreg = translate_rreg (SD_, RM2); | |
4777 | store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); | |
4778 | } | |
4779 | ||
4780 | // 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2 | |
4781 | 8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add | |
4782 | "add_add" | |
4783 | *am33 | |
4784 | { | |
4785 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
4786 | int result1; | |
4787 | ||
4788 | PC = cia; | |
4789 | srcreg1 = translate_rreg (SD_, RM1); | |
4790 | srcreg2 = translate_rreg (SD_, RM2); | |
4791 | dstreg1 = translate_rreg (SD_, RN1); | |
4792 | dstreg2 = translate_rreg (SD_, RN2); | |
4793 | ||
4794 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; | |
4795 | State.regs[dstreg2] += State.regs[srcreg2]; | |
4796 | State.regs[dstreg1] = result1; | |
4797 | } | |
4798 | ||
4799 | // 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2 | |
4800 | 8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add | |
4801 | "add_add" | |
4802 | *am33 | |
4803 | { | |
4804 | int srcreg1, dstreg1, dstreg2; | |
4805 | int result1; | |
4806 | ||
4807 | PC = cia; | |
4808 | srcreg1 = translate_rreg (SD_, RM1); | |
4809 | dstreg1 = translate_rreg (SD_, RN1); | |
4810 | dstreg2 = translate_rreg (SD_, RN2); | |
4811 | ||
4812 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; | |
4813 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
4814 | State.regs[dstreg1] = result1; | |
4815 | } | |
4816 | ||
4817 | // 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2 | |
4818 | 8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub | |
4819 | "add_sub" | |
4820 | *am33 | |
4821 | { | |
4822 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
4823 | int result1; | |
4824 | ||
4825 | PC = cia; | |
4826 | srcreg1 = translate_rreg (SD_, RM1); | |
4827 | srcreg2 = translate_rreg (SD_, RM2); | |
4828 | dstreg1 = translate_rreg (SD_, RN1); | |
4829 | dstreg2 = translate_rreg (SD_, RN2); | |
4830 | ||
4831 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; | |
4832 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
4833 | State.regs[dstreg1] = result1; | |
4834 | } | |
4835 | ||
4836 | // 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2 | |
4837 | 8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub | |
4838 | "add_sub" | |
4839 | *am33 | |
4840 | { | |
4841 | int srcreg1, dstreg1, dstreg2; | |
4842 | int result1; | |
4843 | ||
4844 | PC = cia; | |
4845 | srcreg1 = translate_rreg (SD_, RM1); | |
4846 | dstreg1 = translate_rreg (SD_, RN1); | |
4847 | dstreg2 = translate_rreg (SD_, RN2); | |
4848 | ||
4849 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; | |
4850 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
4851 | State.regs[dstreg1] = result1; | |
4852 | } | |
4853 | ||
4854 | // 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2 | |
4855 | 8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp | |
4856 | "add_cmp" | |
4857 | *am33 | |
4858 | { | |
4859 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
4860 | ||
4861 | PC = cia; | |
4862 | srcreg1 = translate_rreg (SD_, RM1); | |
4863 | srcreg2 = translate_rreg (SD_, RM2); | |
4864 | dstreg1 = translate_rreg (SD_, RN1); | |
4865 | dstreg2 = translate_rreg (SD_, RN2); | |
4866 | ||
4867 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); | |
4868 | State.regs[dstreg1] += State.regs[srcreg1]; | |
4869 | } | |
4870 | ||
4871 | // 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2 | |
4872 | 8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp | |
4873 | "add_cmp" | |
4874 | *am33 | |
4875 | { | |
4876 | int srcreg1, dstreg1, dstreg2; | |
4877 | ||
4878 | PC = cia; | |
4879 | srcreg1 = translate_rreg (SD_, RM1); | |
4880 | dstreg1 = translate_rreg (SD_, RN1); | |
4881 | dstreg2 = translate_rreg (SD_, RN2); | |
4882 | ||
4883 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); | |
4884 | State.regs[dstreg1] += State.regs[srcreg1]; | |
4885 | } | |
4886 | ||
4887 | // 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2 | |
4888 | 8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov | |
4889 | "add_mov" | |
4890 | *am33 | |
4891 | { | |
4892 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
4893 | int result1; | |
4894 | ||
4895 | PC = cia; | |
4896 | srcreg1 = translate_rreg (SD_, RM1); | |
4897 | srcreg2 = translate_rreg (SD_, RM2); | |
4898 | dstreg1 = translate_rreg (SD_, RN1); | |
4899 | dstreg2 = translate_rreg (SD_, RN2); | |
4900 | ||
4901 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; | |
4902 | State.regs[dstreg2] = State.regs[srcreg2]; | |
4903 | State.regs[dstreg1] = result1; | |
4904 | } | |
4905 | ||
4906 | // 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2 | |
4907 | 8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov | |
4908 | "add_mov" | |
4909 | *am33 | |
4910 | { | |
4911 | int srcreg1, dstreg1, dstreg2; | |
4912 | int result1; | |
4913 | ||
4914 | PC = cia; | |
4915 | srcreg1 = translate_rreg (SD_, RM1); | |
4916 | dstreg1 = translate_rreg (SD_, RN1); | |
4917 | dstreg2 = translate_rreg (SD_, RN2); | |
4918 | ||
4919 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; | |
4920 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
4921 | State.regs[dstreg1] = result1; | |
4922 | } | |
4923 | ||
4924 | // 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2 | |
4925 | 8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr | |
4926 | "add_asr" | |
4927 | *am33 | |
4928 | { | |
4929 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
4930 | int result1; | |
4931 | signed int temp; | |
4932 | ||
4933 | PC = cia; | |
4934 | srcreg1 = translate_rreg (SD_, RM1); | |
4935 | srcreg2 = translate_rreg (SD_, RM2); | |
4936 | dstreg1 = translate_rreg (SD_, RN1); | |
4937 | dstreg2 = translate_rreg (SD_, RN2); | |
4938 | ||
4939 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; | |
4940 | temp = State.regs[dstreg2]; | |
4941 | temp >>= State.regs[srcreg2]; | |
4942 | State.regs[dstreg2] = temp; | |
4943 | State.regs[dstreg1] = result1; | |
4944 | } | |
4945 | ||
4946 | // 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2 | |
4947 | 8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr | |
4948 | "add_asr" | |
4949 | *am33 | |
4950 | { | |
4951 | int srcreg1, dstreg1, dstreg2; | |
4952 | int result1; | |
4953 | signed int temp; | |
4954 | ||
4955 | PC = cia; | |
4956 | srcreg1 = translate_rreg (SD_, RM1); | |
4957 | dstreg1 = translate_rreg (SD_, RN1); | |
4958 | dstreg2 = translate_rreg (SD_, RN2); | |
4959 | ||
4960 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; | |
4961 | temp = State.regs[dstreg2]; | |
4962 | temp >>= IMM4; | |
4963 | State.regs[dstreg2] = temp; | |
4964 | State.regs[dstreg1] = result1; | |
4965 | } | |
4966 | ||
4967 | // 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2 | |
4968 | 8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr | |
4969 | "add_lsr" | |
4970 | *am33 | |
4971 | { | |
4972 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
4973 | int result1; | |
4974 | ||
4975 | PC = cia; | |
4976 | srcreg1 = translate_rreg (SD_, RM1); | |
4977 | srcreg2 = translate_rreg (SD_, RM2); | |
4978 | dstreg1 = translate_rreg (SD_, RN1); | |
4979 | dstreg2 = translate_rreg (SD_, RN2); | |
4980 | ||
4981 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; | |
4982 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
4983 | State.regs[dstreg1] = result1; | |
4984 | } | |
4985 | ||
4986 | // 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2 | |
4987 | 8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr | |
4988 | "add_lsr" | |
4989 | *am33 | |
4990 | { | |
4991 | int srcreg1, dstreg1, dstreg2; | |
4992 | int result1; | |
c2d11a7d JM |
4993 | |
4994 | PC = cia; | |
4995 | srcreg1 = translate_rreg (SD_, RM1); | |
4996 | dstreg1 = translate_rreg (SD_, RN1); | |
4997 | dstreg2 = translate_rreg (SD_, RN2); | |
4998 | ||
4999 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; | |
5000 | State.regs[dstreg2] >>= IMM4; | |
5001 | State.regs[dstreg1] = result1; | |
5002 | } | |
5003 | ||
5004 | ||
5005 | // 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2 | |
5006 | 8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl | |
5007 | "add_asl" | |
5008 | *am33 | |
5009 | { | |
5010 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5011 | int result1; | |
5012 | ||
5013 | PC = cia; | |
5014 | srcreg1 = translate_rreg (SD_, RM1); | |
5015 | srcreg2 = translate_rreg (SD_, RM2); | |
5016 | dstreg1 = translate_rreg (SD_, RN1); | |
5017 | dstreg2 = translate_rreg (SD_, RN2); | |
5018 | ||
5019 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; | |
5020 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
5021 | State.regs[dstreg1] = result1; | |
5022 | } | |
5023 | ||
5024 | // 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2 | |
5025 | 8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl | |
5026 | "add_asl" | |
5027 | *am33 | |
5028 | { | |
5029 | int srcreg1, dstreg1, dstreg2; | |
5030 | int result1; | |
c2d11a7d JM |
5031 | |
5032 | PC = cia; | |
5033 | srcreg1 = translate_rreg (SD_, RM1); | |
5034 | dstreg1 = translate_rreg (SD_, RN1); | |
5035 | dstreg2 = translate_rreg (SD_, RN2); | |
5036 | ||
5037 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; | |
5038 | State.regs[dstreg2] <<= IMM4; | |
5039 | State.regs[dstreg1] = result1; | |
5040 | } | |
5041 | ||
5042 | // 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2 | |
5043 | 8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add | |
5044 | "cmp_add" | |
5045 | *am33 | |
5046 | { | |
5047 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5048 | ||
5049 | PC = cia; | |
5050 | srcreg1 = translate_rreg (SD_, RM1); | |
5051 | srcreg2 = translate_rreg (SD_, RM2); | |
5052 | dstreg1 = translate_rreg (SD_, RN1); | |
5053 | dstreg2 = translate_rreg (SD_, RN2); | |
5054 | ||
5055 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); | |
5056 | State.regs[dstreg2] += State.regs[srcreg2]; | |
5057 | } | |
5058 | ||
5059 | // 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2 | |
5060 | 8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add | |
5061 | "cmp_add" | |
5062 | *am33 | |
5063 | { | |
5064 | int srcreg1, dstreg1, dstreg2; | |
5065 | ||
5066 | PC = cia; | |
5067 | srcreg1 = translate_rreg (SD_, RM1); | |
5068 | dstreg1 = translate_rreg (SD_, RN1); | |
5069 | dstreg2 = translate_rreg (SD_, RN2); | |
5070 | ||
5071 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); | |
5072 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
5073 | } | |
5074 | ||
5075 | // 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2 | |
5076 | 8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub | |
5077 | "cmp_sub" | |
5078 | *am33 | |
5079 | { | |
5080 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5081 | ||
5082 | PC = cia; | |
5083 | srcreg1 = translate_rreg (SD_, RM1); | |
5084 | srcreg2 = translate_rreg (SD_, RM2); | |
5085 | dstreg1 = translate_rreg (SD_, RN1); | |
5086 | dstreg2 = translate_rreg (SD_, RN2); | |
5087 | ||
5088 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); | |
5089 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
5090 | } | |
5091 | ||
5092 | // 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2 | |
5093 | 8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub | |
5094 | "cmp_sub" | |
5095 | *am33 | |
5096 | { | |
5097 | int srcreg1, dstreg1, dstreg2; | |
5098 | ||
5099 | PC = cia; | |
5100 | srcreg1 = translate_rreg (SD_, RM1); | |
5101 | dstreg1 = translate_rreg (SD_, RN1); | |
5102 | dstreg2 = translate_rreg (SD_, RN2); | |
5103 | ||
5104 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); | |
5105 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
5106 | } | |
5107 | ||
5108 | // 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2 | |
5109 | 8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov | |
5110 | "cmp_mov" | |
5111 | *am33 | |
5112 | { | |
5113 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5114 | ||
5115 | PC = cia; | |
5116 | srcreg1 = translate_rreg (SD_, RM1); | |
5117 | srcreg2 = translate_rreg (SD_, RM2); | |
5118 | dstreg1 = translate_rreg (SD_, RN1); | |
5119 | dstreg2 = translate_rreg (SD_, RN2); | |
5120 | ||
5121 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); | |
5122 | State.regs[dstreg2] = State.regs[srcreg2]; | |
5123 | } | |
5124 | ||
5125 | // 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2 | |
5126 | 8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov | |
5127 | "cmp_mov" | |
5128 | *am33 | |
5129 | { | |
5130 | int srcreg1, dstreg1, dstreg2; | |
5131 | ||
5132 | PC = cia; | |
5133 | srcreg1 = translate_rreg (SD_, RM1); | |
5134 | dstreg1 = translate_rreg (SD_, RN1); | |
5135 | dstreg2 = translate_rreg (SD_, RN2); | |
5136 | ||
5137 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); | |
5138 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
5139 | } | |
5140 | ||
5141 | // 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2 | |
5142 | 8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr | |
5143 | "cmp_asr" | |
5144 | *am33 | |
5145 | { | |
5146 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5147 | signed int temp; | |
5148 | ||
5149 | PC = cia; | |
5150 | srcreg1 = translate_rreg (SD_, RM1); | |
5151 | srcreg2 = translate_rreg (SD_, RM2); | |
5152 | dstreg1 = translate_rreg (SD_, RN1); | |
5153 | dstreg2 = translate_rreg (SD_, RN2); | |
5154 | ||
5155 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); | |
5156 | temp = State.regs[dstreg2]; | |
5157 | temp >>= State.regs[srcreg2]; | |
5158 | State.regs[dstreg2] = temp; | |
5159 | } | |
5160 | ||
5161 | // 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2 | |
5162 | 8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr | |
5163 | "cmp_asr" | |
5164 | *am33 | |
5165 | { | |
5166 | int srcreg1, dstreg1, dstreg2; | |
5167 | signed int temp; | |
5168 | ||
5169 | PC = cia; | |
5170 | srcreg1 = translate_rreg (SD_, RM1); | |
5171 | dstreg1 = translate_rreg (SD_, RN1); | |
5172 | dstreg2 = translate_rreg (SD_, RN2); | |
5173 | ||
5174 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); | |
5175 | temp = State.regs[dstreg2]; | |
5176 | temp >>= IMM4; | |
5177 | State.regs[dstreg2] = temp; | |
5178 | } | |
5179 | ||
5180 | // 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2 | |
5181 | 8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr | |
5182 | "cmp_lsr" | |
5183 | *am33 | |
5184 | { | |
5185 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5186 | ||
5187 | PC = cia; | |
5188 | srcreg1 = translate_rreg (SD_, RM1); | |
5189 | srcreg2 = translate_rreg (SD_, RM2); | |
5190 | dstreg1 = translate_rreg (SD_, RN1); | |
5191 | dstreg2 = translate_rreg (SD_, RN2); | |
5192 | ||
5193 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); | |
5194 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
5195 | } | |
5196 | ||
5197 | // 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2 | |
5198 | 8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr | |
5199 | "cmp_lsr" | |
5200 | *am33 | |
5201 | { | |
5202 | int srcreg1, dstreg1, dstreg2; | |
c2d11a7d JM |
5203 | |
5204 | PC = cia; | |
5205 | srcreg1 = translate_rreg (SD_, RM1); | |
5206 | dstreg1 = translate_rreg (SD_, RN1); | |
5207 | dstreg2 = translate_rreg (SD_, RN2); | |
5208 | ||
5209 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); | |
5210 | State.regs[dstreg2] >>= IMM4; | |
5211 | } | |
5212 | ||
5213 | ||
5214 | // 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2 | |
5215 | 8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl | |
5216 | "cmp_asl" | |
5217 | *am33 | |
5218 | { | |
5219 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5220 | ||
5221 | PC = cia; | |
5222 | srcreg1 = translate_rreg (SD_, RM1); | |
5223 | srcreg2 = translate_rreg (SD_, RM2); | |
5224 | dstreg1 = translate_rreg (SD_, RN1); | |
5225 | dstreg2 = translate_rreg (SD_, RN2); | |
5226 | ||
5227 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); | |
5228 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
5229 | } | |
5230 | ||
5231 | // 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2 | |
5232 | 8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl | |
5233 | "cmp_asl" | |
5234 | *am33 | |
5235 | { | |
5236 | int srcreg1, dstreg1, dstreg2; | |
c2d11a7d JM |
5237 | |
5238 | PC = cia; | |
5239 | srcreg1 = translate_rreg (SD_, RM1); | |
5240 | dstreg1 = translate_rreg (SD_, RN1); | |
5241 | dstreg2 = translate_rreg (SD_, RN2); | |
5242 | ||
5243 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); | |
5244 | State.regs[dstreg2] <<= IMM4; | |
5245 | } | |
5246 | ||
5247 | // 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2 | |
5248 | 8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add | |
5249 | "sub_add" | |
5250 | *am33 | |
5251 | { | |
5252 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5253 | int result1; | |
5254 | ||
5255 | PC = cia; | |
5256 | srcreg1 = translate_rreg (SD_, RM1); | |
5257 | srcreg2 = translate_rreg (SD_, RM2); | |
5258 | dstreg1 = translate_rreg (SD_, RN1); | |
5259 | dstreg2 = translate_rreg (SD_, RN2); | |
5260 | ||
5261 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; | |
5262 | State.regs[dstreg2] += State.regs[srcreg2]; | |
5263 | State.regs[dstreg1] = result1; | |
5264 | } | |
5265 | ||
5266 | // 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2 | |
5267 | 8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add | |
5268 | "sub_add" | |
5269 | *am33 | |
5270 | { | |
5271 | int srcreg1, dstreg1, dstreg2; | |
5272 | int result1; | |
5273 | ||
5274 | PC = cia; | |
5275 | srcreg1 = translate_rreg (SD_, RM1); | |
5276 | dstreg1 = translate_rreg (SD_, RN1); | |
5277 | dstreg2 = translate_rreg (SD_, RN2); | |
5278 | ||
5279 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; | |
5280 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
5281 | State.regs[dstreg1] = result1; | |
5282 | } | |
5283 | ||
5284 | // 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2 | |
5285 | 8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub | |
5286 | "sub_sub" | |
5287 | *am33 | |
5288 | { | |
5289 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5290 | int result1; | |
5291 | ||
5292 | PC = cia; | |
5293 | srcreg1 = translate_rreg (SD_, RM1); | |
5294 | srcreg2 = translate_rreg (SD_, RM2); | |
5295 | dstreg1 = translate_rreg (SD_, RN1); | |
5296 | dstreg2 = translate_rreg (SD_, RN2); | |
5297 | ||
5298 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; | |
5299 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
5300 | State.regs[dstreg1] = result1; | |
5301 | } | |
5302 | ||
5303 | // 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2 | |
5304 | 8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub | |
5305 | "sub_sub" | |
5306 | *am33 | |
5307 | { | |
5308 | int srcreg1, dstreg1, dstreg2; | |
5309 | int result1; | |
5310 | ||
5311 | PC = cia; | |
5312 | srcreg1 = translate_rreg (SD_, RM1); | |
5313 | dstreg1 = translate_rreg (SD_, RN1); | |
5314 | dstreg2 = translate_rreg (SD_, RN2); | |
5315 | ||
5316 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; | |
5317 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
5318 | State.regs[dstreg1] = result1; | |
5319 | } | |
5320 | ||
5321 | // 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2 | |
5322 | 8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp | |
5323 | "sub_cmp" | |
5324 | *am33 | |
5325 | { | |
5326 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5327 | ||
5328 | PC = cia; | |
5329 | srcreg1 = translate_rreg (SD_, RM1); | |
5330 | srcreg2 = translate_rreg (SD_, RM2); | |
5331 | dstreg1 = translate_rreg (SD_, RN1); | |
5332 | dstreg2 = translate_rreg (SD_, RN2); | |
5333 | ||
5334 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); | |
5335 | State.regs[dstreg1] -= State.regs[srcreg1]; | |
5336 | } | |
5337 | ||
5338 | // 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2 | |
5339 | 8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp | |
5340 | "sub_cmp" | |
5341 | *am33 | |
5342 | { | |
5343 | int srcreg1, dstreg1, dstreg2; | |
c2d11a7d JM |
5344 | |
5345 | PC = cia; | |
5346 | srcreg1 = translate_rreg (SD_, RM1); | |
5347 | dstreg1 = translate_rreg (SD_, RN1); | |
5348 | dstreg2 = translate_rreg (SD_, RN2); | |
5349 | ||
5350 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); | |
5351 | State.regs[dstreg1] -= State.regs[srcreg1]; | |
5352 | } | |
5353 | ||
5354 | // 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2 | |
5355 | 8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov | |
5356 | "sub_mov" | |
5357 | *am33 | |
5358 | { | |
5359 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5360 | int result1; | |
5361 | ||
5362 | PC = cia; | |
5363 | srcreg1 = translate_rreg (SD_, RM1); | |
5364 | srcreg2 = translate_rreg (SD_, RM2); | |
5365 | dstreg1 = translate_rreg (SD_, RN1); | |
5366 | dstreg2 = translate_rreg (SD_, RN2); | |
5367 | ||
5368 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; | |
5369 | State.regs[dstreg2] = State.regs[srcreg2]; | |
5370 | State.regs[dstreg1] = result1; | |
5371 | } | |
5372 | ||
5373 | // 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2 | |
5374 | 8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov | |
5375 | "sub_mov" | |
5376 | *am33 | |
5377 | { | |
5378 | int srcreg1, dstreg1, dstreg2; | |
5379 | int result1; | |
5380 | ||
5381 | PC = cia; | |
5382 | srcreg1 = translate_rreg (SD_, RM1); | |
5383 | dstreg1 = translate_rreg (SD_, RN1); | |
5384 | dstreg2 = translate_rreg (SD_, RN2); | |
5385 | ||
5386 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; | |
5387 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
5388 | State.regs[dstreg1] = result1; | |
5389 | } | |
5390 | ||
5391 | // 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2 | |
5392 | 8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr | |
5393 | "sub_asr" | |
5394 | *am33 | |
5395 | { | |
5396 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5397 | int result1; | |
5398 | signed int temp; | |
5399 | ||
5400 | PC = cia; | |
5401 | srcreg1 = translate_rreg (SD_, RM1); | |
5402 | srcreg2 = translate_rreg (SD_, RM2); | |
5403 | dstreg1 = translate_rreg (SD_, RN1); | |
5404 | dstreg2 = translate_rreg (SD_, RN2); | |
5405 | ||
5406 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; | |
5407 | temp = State.regs[dstreg2]; | |
5408 | temp >>= State.regs[srcreg2]; | |
5409 | State.regs[dstreg2] = temp; | |
5410 | State.regs[dstreg1] = result1; | |
5411 | } | |
5412 | ||
5413 | // 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2 | |
5414 | 8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr | |
5415 | "sub_asr" | |
5416 | *am33 | |
5417 | { | |
5418 | int srcreg1, dstreg1, dstreg2; | |
5419 | int result1; | |
5420 | signed int temp; | |
5421 | ||
5422 | PC = cia; | |
5423 | srcreg1 = translate_rreg (SD_, RM1); | |
5424 | dstreg1 = translate_rreg (SD_, RN1); | |
5425 | dstreg2 = translate_rreg (SD_, RN2); | |
5426 | ||
5427 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; | |
5428 | temp = State.regs[dstreg2]; | |
5429 | temp >>= IMM4; | |
5430 | State.regs[dstreg2] = temp; | |
5431 | State.regs[dstreg1] = result1; | |
5432 | } | |
5433 | ||
5434 | // 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2 | |
5435 | 8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr | |
5436 | "sub_lsr" | |
5437 | *am33 | |
5438 | { | |
5439 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5440 | int result1; | |
5441 | ||
5442 | PC = cia; | |
5443 | srcreg1 = translate_rreg (SD_, RM1); | |
5444 | srcreg2 = translate_rreg (SD_, RM2); | |
5445 | dstreg1 = translate_rreg (SD_, RN1); | |
5446 | dstreg2 = translate_rreg (SD_, RN2); | |
5447 | ||
5448 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; | |
5449 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
5450 | State.regs[dstreg1] = result1; | |
5451 | } | |
5452 | ||
5453 | // 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2 | |
5454 | 8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr | |
5455 | "sub_lsr" | |
5456 | *am33 | |
5457 | { | |
5458 | int srcreg1, dstreg1, dstreg2; | |
5459 | int result1; | |
c2d11a7d JM |
5460 | |
5461 | PC = cia; | |
5462 | srcreg1 = translate_rreg (SD_, RM1); | |
5463 | dstreg1 = translate_rreg (SD_, RN1); | |
5464 | dstreg2 = translate_rreg (SD_, RN2); | |
5465 | ||
5466 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; | |
5467 | State.regs[dstreg2] >>= IMM4; | |
5468 | State.regs[dstreg1] = result1; | |
5469 | } | |
5470 | ||
5471 | ||
5472 | // 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2 | |
5473 | 8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl | |
5474 | "sub_asl" | |
5475 | *am33 | |
5476 | { | |
5477 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5478 | int result1; | |
5479 | ||
5480 | PC = cia; | |
5481 | srcreg1 = translate_rreg (SD_, RM1); | |
5482 | srcreg2 = translate_rreg (SD_, RM2); | |
5483 | dstreg1 = translate_rreg (SD_, RN1); | |
5484 | dstreg2 = translate_rreg (SD_, RN2); | |
5485 | ||
5486 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; | |
5487 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
5488 | State.regs[dstreg1] = result1; | |
5489 | } | |
5490 | ||
5491 | // 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2 | |
5492 | 8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl | |
5493 | "sub_asl" | |
5494 | *am33 | |
5495 | { | |
5496 | int srcreg1, dstreg1, dstreg2; | |
5497 | int result1; | |
c2d11a7d JM |
5498 | |
5499 | PC = cia; | |
5500 | srcreg1 = translate_rreg (SD_, RM1); | |
5501 | dstreg1 = translate_rreg (SD_, RN1); | |
5502 | dstreg2 = translate_rreg (SD_, RN2); | |
5503 | ||
5504 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; | |
5505 | State.regs[dstreg2] <<= IMM4; | |
5506 | State.regs[dstreg1] = result1; | |
5507 | } | |
5508 | ||
5509 | // 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2 | |
5510 | 8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add | |
5511 | "mov_add" | |
5512 | *am33 | |
5513 | { | |
5514 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5515 | int result1; | |
5516 | ||
5517 | PC = cia; | |
5518 | srcreg1 = translate_rreg (SD_, RM1); | |
5519 | srcreg2 = translate_rreg (SD_, RM2); | |
5520 | dstreg1 = translate_rreg (SD_, RN1); | |
5521 | dstreg2 = translate_rreg (SD_, RN2); | |
5522 | ||
5523 | result1 = State.regs[srcreg1]; | |
5524 | State.regs[dstreg2] += State.regs[srcreg2]; | |
5525 | State.regs[dstreg1] = result1; | |
5526 | } | |
5527 | ||
5528 | // 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2 | |
5529 | 8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add | |
5530 | "mov_add" | |
5531 | *am33 | |
5532 | { | |
5533 | int srcreg1, dstreg1, dstreg2; | |
5534 | int result1; | |
5535 | ||
5536 | PC = cia; | |
5537 | srcreg1 = translate_rreg (SD_, RM1); | |
5538 | dstreg1 = translate_rreg (SD_, RN1); | |
5539 | dstreg2 = translate_rreg (SD_, RN2); | |
5540 | ||
5541 | result1 = State.regs[srcreg1]; | |
5542 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
5543 | State.regs[dstreg1] = result1; | |
5544 | } | |
5545 | ||
5546 | // 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2 | |
5547 | 8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub | |
5548 | "mov_sub" | |
5549 | *am33 | |
5550 | { | |
5551 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5552 | int result1; | |
5553 | ||
5554 | PC = cia; | |
5555 | srcreg1 = translate_rreg (SD_, RM1); | |
5556 | srcreg2 = translate_rreg (SD_, RM2); | |
5557 | dstreg1 = translate_rreg (SD_, RN1); | |
5558 | dstreg2 = translate_rreg (SD_, RN2); | |
5559 | ||
5560 | result1 = State.regs[srcreg1]; | |
5561 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
5562 | State.regs[dstreg1] = result1; | |
5563 | } | |
5564 | ||
5565 | // 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2 | |
5566 | 8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub | |
5567 | "mov_sub" | |
5568 | *am33 | |
5569 | { | |
5570 | int srcreg1, dstreg1, dstreg2; | |
5571 | int result1; | |
5572 | ||
5573 | PC = cia; | |
5574 | srcreg1 = translate_rreg (SD_, RM1); | |
5575 | dstreg1 = translate_rreg (SD_, RN1); | |
5576 | dstreg2 = translate_rreg (SD_, RN2); | |
5577 | ||
5578 | result1 = State.regs[srcreg1]; | |
5579 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
5580 | State.regs[dstreg1] = result1; | |
5581 | } | |
5582 | ||
5583 | // 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2 | |
5584 | 8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp | |
5585 | "mov_cmp" | |
5586 | *am33 | |
5587 | { | |
5588 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5589 | ||
5590 | PC = cia; | |
5591 | srcreg1 = translate_rreg (SD_, RM1); | |
5592 | srcreg2 = translate_rreg (SD_, RM2); | |
5593 | dstreg1 = translate_rreg (SD_, RN1); | |
5594 | dstreg2 = translate_rreg (SD_, RN2); | |
5595 | ||
5596 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); | |
5597 | State.regs[dstreg1] = State.regs[srcreg1]; | |
5598 | } | |
5599 | ||
5600 | // 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2 | |
5601 | 8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp | |
5602 | "mov_cmp" | |
5603 | *am33 | |
5604 | { | |
5605 | int srcreg1, dstreg1, dstreg2; | |
5606 | ||
5607 | PC = cia; | |
5608 | srcreg1 = translate_rreg (SD_, RM1); | |
5609 | dstreg1 = translate_rreg (SD_, RN1); | |
5610 | dstreg2 = translate_rreg (SD_, RN2); | |
5611 | ||
5612 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); | |
5613 | State.regs[dstreg1] = State.regs[srcreg1]; | |
5614 | } | |
5615 | ||
5616 | // 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2 | |
5617 | 8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov | |
5618 | "mov_mov" | |
5619 | *am33 | |
5620 | { | |
5621 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5622 | int result1; | |
5623 | ||
5624 | PC = cia; | |
5625 | srcreg1 = translate_rreg (SD_, RM1); | |
5626 | srcreg2 = translate_rreg (SD_, RM2); | |
5627 | dstreg1 = translate_rreg (SD_, RN1); | |
5628 | dstreg2 = translate_rreg (SD_, RN2); | |
5629 | ||
5630 | result1 = State.regs[srcreg1]; | |
5631 | State.regs[dstreg2] = State.regs[srcreg2]; | |
5632 | State.regs[dstreg1] = result1; | |
5633 | } | |
5634 | ||
5635 | // 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2 | |
5636 | 8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov | |
5637 | "mov_mov" | |
5638 | *am33 | |
5639 | { | |
5640 | int srcreg1, dstreg1, dstreg2; | |
5641 | int result1; | |
5642 | ||
5643 | PC = cia; | |
5644 | srcreg1 = translate_rreg (SD_, RM1); | |
5645 | dstreg1 = translate_rreg (SD_, RN1); | |
5646 | dstreg2 = translate_rreg (SD_, RN2); | |
5647 | ||
5648 | result1 = State.regs[srcreg1]; | |
5649 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
5650 | State.regs[dstreg1] = result1; | |
5651 | } | |
5652 | ||
5653 | // 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2 | |
5654 | 8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr | |
5655 | "mov_asr" | |
5656 | *am33 | |
5657 | { | |
5658 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5659 | int result1; | |
5660 | signed int temp; | |
5661 | ||
5662 | PC = cia; | |
5663 | srcreg1 = translate_rreg (SD_, RM1); | |
5664 | srcreg2 = translate_rreg (SD_, RM2); | |
5665 | dstreg1 = translate_rreg (SD_, RN1); | |
5666 | dstreg2 = translate_rreg (SD_, RN2); | |
5667 | ||
5668 | result1 = State.regs[srcreg1]; | |
5669 | temp = State.regs[dstreg2]; | |
5670 | temp >>= State.regs[srcreg2]; | |
5671 | State.regs[dstreg2] = temp; | |
5672 | State.regs[dstreg1] = result1; | |
5673 | } | |
5674 | ||
5675 | // 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2 | |
5676 | 8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr | |
5677 | "mov_asr" | |
5678 | *am33 | |
5679 | { | |
5680 | int srcreg1, dstreg1, dstreg2; | |
5681 | int result1; | |
5682 | signed int temp; | |
5683 | ||
5684 | PC = cia; | |
5685 | srcreg1 = translate_rreg (SD_, RM1); | |
5686 | dstreg1 = translate_rreg (SD_, RN1); | |
5687 | dstreg2 = translate_rreg (SD_, RN2); | |
5688 | ||
5689 | result1 = State.regs[srcreg1]; | |
5690 | temp = State.regs[dstreg2]; | |
5691 | temp >>= IMM4; | |
5692 | State.regs[dstreg2] = temp; | |
5693 | State.regs[dstreg1] = result1; | |
5694 | } | |
5695 | ||
5696 | // 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2 | |
5697 | 8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr | |
5698 | "mov_lsr" | |
5699 | *am33 | |
5700 | { | |
5701 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5702 | int result1; | |
5703 | ||
5704 | PC = cia; | |
5705 | srcreg1 = translate_rreg (SD_, RM1); | |
5706 | srcreg2 = translate_rreg (SD_, RM2); | |
5707 | dstreg1 = translate_rreg (SD_, RN1); | |
5708 | dstreg2 = translate_rreg (SD_, RN2); | |
5709 | ||
5710 | result1 = State.regs[srcreg1]; | |
5711 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
5712 | State.regs[dstreg1] = result1; | |
5713 | } | |
5714 | ||
5715 | // 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2 | |
5716 | 8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr | |
5717 | "mov_lsr" | |
5718 | *am33 | |
5719 | { | |
5720 | int srcreg1, dstreg1, dstreg2; | |
5721 | int result1; | |
c2d11a7d JM |
5722 | |
5723 | PC = cia; | |
5724 | srcreg1 = translate_rreg (SD_, RM1); | |
5725 | dstreg1 = translate_rreg (SD_, RN1); | |
5726 | dstreg2 = translate_rreg (SD_, RN2); | |
5727 | ||
5728 | result1 = State.regs[srcreg1]; | |
5729 | State.regs[dstreg2] >>= IMM4; | |
5730 | State.regs[dstreg1] = result1; | |
5731 | } | |
5732 | ||
5733 | ||
5734 | // 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2 | |
5735 | 8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl | |
5736 | "mov_asl" | |
5737 | *am33 | |
5738 | { | |
5739 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
5740 | int result1; | |
5741 | ||
5742 | PC = cia; | |
5743 | srcreg1 = translate_rreg (SD_, RM1); | |
5744 | srcreg2 = translate_rreg (SD_, RM2); | |
5745 | dstreg1 = translate_rreg (SD_, RN1); | |
5746 | dstreg2 = translate_rreg (SD_, RN2); | |
5747 | ||
5748 | result1 = State.regs[srcreg1]; | |
5749 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
5750 | State.regs[dstreg1] = result1; | |
5751 | } | |
5752 | ||
5753 | // 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2 | |
5754 | 8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl | |
5755 | "mov_asl" | |
5756 | *am33 | |
5757 | { | |
5758 | int srcreg1, dstreg1, dstreg2; | |
5759 | int result1; | |
c2d11a7d JM |
5760 | |
5761 | PC = cia; | |
5762 | srcreg1 = translate_rreg (SD_, RM1); | |
5763 | dstreg1 = translate_rreg (SD_, RN1); | |
5764 | dstreg2 = translate_rreg (SD_, RN2); | |
5765 | ||
5766 | result1 = State.regs[srcreg1]; | |
5767 | State.regs[dstreg2] <<= IMM4; | |
5768 | State.regs[dstreg1] = result1; | |
5769 | } | |
5770 | ||
5771 | // 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2 | |
5772 | 8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add | |
5773 | "add_add" | |
5774 | *am33 | |
5775 | { | |
5776 | int srcreg2, dstreg1, dstreg2; | |
5777 | int result1; | |
5778 | ||
5779 | PC = cia; | |
5780 | srcreg2 = translate_rreg (SD_, RM2); | |
5781 | dstreg1 = translate_rreg (SD_, RN1); | |
5782 | dstreg2 = translate_rreg (SD_, RN2); | |
5783 | ||
5784 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); | |
5785 | State.regs[dstreg2] += State.regs[srcreg2]; | |
5786 | State.regs[dstreg1] = result1; | |
5787 | } | |
5788 | ||
5789 | // 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2 | |
5790 | 8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add | |
5791 | "add_add" | |
5792 | *am33 | |
5793 | { | |
5794 | int dstreg1, dstreg2; | |
5795 | int result1; | |
5796 | ||
5797 | PC = cia; | |
5798 | dstreg1 = translate_rreg (SD_, RN1); | |
5799 | dstreg2 = translate_rreg (SD_, RN2); | |
5800 | ||
5801 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); | |
5802 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
5803 | State.regs[dstreg1] = result1; | |
5804 | } | |
5805 | ||
5806 | // 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2 | |
5807 | 8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub | |
5808 | "add_sub" | |
5809 | *am33 | |
5810 | { | |
5811 | int srcreg2, dstreg1, dstreg2; | |
5812 | int result1; | |
5813 | ||
5814 | PC = cia; | |
5815 | srcreg2 = translate_rreg (SD_, RM2); | |
5816 | dstreg1 = translate_rreg (SD_, RN1); | |
5817 | dstreg2 = translate_rreg (SD_, RN2); | |
5818 | ||
5819 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); | |
5820 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
5821 | State.regs[dstreg1] = result1; | |
5822 | } | |
5823 | ||
5824 | // 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2 | |
5825 | 8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub | |
5826 | "add_sub" | |
5827 | *am33 | |
5828 | { | |
5829 | int dstreg1, dstreg2; | |
5830 | int result1; | |
5831 | ||
5832 | PC = cia; | |
5833 | dstreg1 = translate_rreg (SD_, RN1); | |
5834 | dstreg2 = translate_rreg (SD_, RN2); | |
5835 | ||
5836 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); | |
5837 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
5838 | State.regs[dstreg1] = result1; | |
5839 | } | |
5840 | ||
5841 | // 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2 | |
5842 | 8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp | |
5843 | "add_cmp" | |
5844 | *am33 | |
5845 | { | |
5846 | int srcreg2, dstreg1, dstreg2; | |
5847 | ||
5848 | PC = cia; | |
5849 | srcreg2 = translate_rreg (SD_, RM2); | |
5850 | dstreg1 = translate_rreg (SD_, RN1); | |
5851 | dstreg2 = translate_rreg (SD_, RN2); | |
5852 | ||
5853 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); | |
5854 | State.regs[dstreg1] += EXTEND4 (IMM4A); | |
5855 | } | |
5856 | ||
5857 | // 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2 | |
5858 | 8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp | |
5859 | "add_cmp" | |
5860 | *am33 | |
5861 | { | |
5862 | int dstreg1, dstreg2; | |
5863 | ||
5864 | PC = cia; | |
5865 | dstreg1 = translate_rreg (SD_, RN1); | |
5866 | dstreg2 = translate_rreg (SD_, RN2); | |
5867 | ||
5868 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); | |
5869 | State.regs[dstreg1] += EXTEND4 (IMM4A); | |
5870 | } | |
5871 | ||
5872 | // 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2 | |
5873 | 8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov | |
5874 | "add_mov" | |
5875 | *am33 | |
5876 | { | |
5877 | int srcreg2, dstreg1, dstreg2; | |
5878 | int result1; | |
5879 | ||
5880 | PC = cia; | |
5881 | srcreg2 = translate_rreg (SD_, RM2); | |
5882 | dstreg1 = translate_rreg (SD_, RN1); | |
5883 | dstreg2 = translate_rreg (SD_, RN2); | |
5884 | ||
5885 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); | |
5886 | State.regs[dstreg2] = State.regs[srcreg2]; | |
5887 | State.regs[dstreg1] = result1; | |
5888 | } | |
5889 | ||
5890 | // 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2 | |
5891 | 8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov | |
5892 | "add_mov" | |
5893 | *am33 | |
5894 | { | |
5895 | int dstreg1, dstreg2; | |
5896 | int result1; | |
5897 | ||
5898 | PC = cia; | |
5899 | dstreg1 = translate_rreg (SD_, RN1); | |
5900 | dstreg2 = translate_rreg (SD_, RN2); | |
5901 | ||
5902 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); | |
5903 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
5904 | State.regs[dstreg1] = result1; | |
5905 | } | |
5906 | ||
5907 | // 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2 | |
5908 | 8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr | |
5909 | "add_asr" | |
5910 | *am33 | |
5911 | { | |
5912 | int srcreg2, dstreg1, dstreg2; | |
5913 | int result1; | |
5914 | signed int temp; | |
5915 | ||
5916 | PC = cia; | |
5917 | srcreg2 = translate_rreg (SD_, RM2); | |
5918 | dstreg1 = translate_rreg (SD_, RN1); | |
5919 | dstreg2 = translate_rreg (SD_, RN2); | |
5920 | ||
5921 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); | |
5922 | temp = State.regs[dstreg2]; | |
5923 | temp >>= State.regs[srcreg2]; | |
5924 | State.regs[dstreg2] = temp; | |
5925 | State.regs[dstreg1] = result1; | |
5926 | } | |
5927 | ||
5928 | // 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2 | |
5929 | 8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr | |
5930 | "add_asr" | |
5931 | *am33 | |
5932 | { | |
5933 | int dstreg1, dstreg2; | |
5934 | int result1; | |
5935 | signed int temp; | |
5936 | ||
5937 | PC = cia; | |
5938 | dstreg1 = translate_rreg (SD_, RN1); | |
5939 | dstreg2 = translate_rreg (SD_, RN2); | |
5940 | ||
5941 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); | |
5942 | temp = State.regs[dstreg2]; | |
5943 | temp >>= IMM4; | |
5944 | State.regs[dstreg2] = temp; | |
5945 | State.regs[dstreg1] = result1; | |
5946 | } | |
5947 | ||
5948 | // 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2 | |
5949 | 8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr | |
5950 | "add_lsr" | |
5951 | *am33 | |
5952 | { | |
5953 | int srcreg2, dstreg1, dstreg2; | |
5954 | int result1; | |
5955 | ||
5956 | PC = cia; | |
5957 | srcreg2 = translate_rreg (SD_, RM2); | |
5958 | dstreg1 = translate_rreg (SD_, RN1); | |
5959 | dstreg2 = translate_rreg (SD_, RN2); | |
5960 | ||
5961 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); | |
5962 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
5963 | State.regs[dstreg1] = result1; | |
5964 | } | |
5965 | ||
5966 | // 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2 | |
5967 | 8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr | |
5968 | "add_lsr" | |
5969 | *am33 | |
5970 | { | |
5971 | int dstreg1, dstreg2; | |
5972 | int result1; | |
c2d11a7d JM |
5973 | |
5974 | PC = cia; | |
5975 | dstreg1 = translate_rreg (SD_, RN1); | |
5976 | dstreg2 = translate_rreg (SD_, RN2); | |
5977 | ||
5978 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); | |
5979 | State.regs[dstreg2] >>= IMM4; | |
5980 | State.regs[dstreg1] = result1; | |
5981 | } | |
5982 | ||
5983 | ||
5984 | // 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2 | |
5985 | 8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl | |
5986 | "add_asl" | |
5987 | *am33 | |
5988 | { | |
5989 | int srcreg2, dstreg1, dstreg2; | |
5990 | int result1; | |
5991 | ||
5992 | PC = cia; | |
5993 | srcreg2 = translate_rreg (SD_, RM2); | |
5994 | dstreg1 = translate_rreg (SD_, RN1); | |
5995 | dstreg2 = translate_rreg (SD_, RN2); | |
5996 | ||
5997 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); | |
5998 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
5999 | State.regs[dstreg1] = result1; | |
6000 | } | |
6001 | ||
6002 | // 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2 | |
6003 | 8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl | |
6004 | "add_asl" | |
6005 | *am33 | |
6006 | { | |
6007 | int dstreg1, dstreg2; | |
6008 | int result1; | |
c2d11a7d JM |
6009 | |
6010 | PC = cia; | |
6011 | dstreg1 = translate_rreg (SD_, RN1); | |
6012 | dstreg2 = translate_rreg (SD_, RN2); | |
6013 | ||
6014 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); | |
6015 | State.regs[dstreg2] <<= IMM4; | |
6016 | State.regs[dstreg1] = result1; | |
6017 | } | |
6018 | ||
6019 | // 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2 | |
6020 | 8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add | |
6021 | "cmp_add" | |
6022 | *am33 | |
6023 | { | |
6024 | int srcreg2, dstreg1, dstreg2; | |
6025 | ||
6026 | PC = cia; | |
6027 | srcreg2 = translate_rreg (SD_, RM2); | |
6028 | dstreg1 = translate_rreg (SD_, RN1); | |
6029 | dstreg2 = translate_rreg (SD_, RN2); | |
6030 | ||
6031 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); | |
6032 | State.regs[dstreg2] += State.regs[srcreg2]; | |
6033 | } | |
6034 | ||
6035 | // 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2 | |
6036 | 8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add | |
6037 | "cmp_add" | |
6038 | *am33 | |
6039 | { | |
6040 | int dstreg1, dstreg2; | |
6041 | ||
6042 | PC = cia; | |
6043 | dstreg1 = translate_rreg (SD_, RN1); | |
6044 | dstreg2 = translate_rreg (SD_, RN2); | |
6045 | ||
6046 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); | |
6047 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
6048 | } | |
6049 | ||
6050 | // 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2 | |
6051 | 8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub | |
6052 | "cmp_sub" | |
6053 | *am33 | |
6054 | { | |
6055 | int srcreg2, dstreg1, dstreg2; | |
6056 | ||
6057 | PC = cia; | |
6058 | srcreg2 = translate_rreg (SD_, RM2); | |
6059 | dstreg1 = translate_rreg (SD_, RN1); | |
6060 | dstreg2 = translate_rreg (SD_, RN2); | |
6061 | ||
6062 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); | |
6063 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
6064 | } | |
6065 | ||
6066 | // 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2 | |
6067 | 8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub | |
6068 | "cmp_sub" | |
6069 | *am33 | |
6070 | { | |
6071 | int dstreg1, dstreg2; | |
6072 | ||
6073 | PC = cia; | |
6074 | dstreg1 = translate_rreg (SD_, RN1); | |
6075 | dstreg2 = translate_rreg (SD_, RN2); | |
6076 | ||
6077 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); | |
6078 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
6079 | } | |
6080 | ||
6081 | // 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2 | |
6082 | 8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov | |
6083 | "cmp_mov" | |
6084 | *am33 | |
6085 | { | |
6086 | int srcreg2, dstreg1, dstreg2; | |
6087 | ||
6088 | PC = cia; | |
6089 | srcreg2 = translate_rreg (SD_, RM2); | |
6090 | dstreg1 = translate_rreg (SD_, RN1); | |
6091 | dstreg2 = translate_rreg (SD_, RN2); | |
6092 | ||
6093 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); | |
6094 | State.regs[dstreg2] = State.regs[srcreg2]; | |
6095 | } | |
6096 | ||
6097 | // 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2 | |
6098 | 8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov | |
6099 | "cmp_mov" | |
6100 | *am33 | |
6101 | { | |
6102 | int dstreg1, dstreg2; | |
6103 | ||
6104 | PC = cia; | |
6105 | dstreg1 = translate_rreg (SD_, RN1); | |
6106 | dstreg2 = translate_rreg (SD_, RN2); | |
6107 | ||
6108 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); | |
6109 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
6110 | } | |
6111 | ||
6112 | // 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2 | |
6113 | 8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr | |
6114 | "cmp_asr" | |
6115 | *am33 | |
6116 | { | |
6117 | int srcreg2, dstreg1, dstreg2; | |
6118 | signed int temp; | |
6119 | ||
6120 | PC = cia; | |
6121 | srcreg2 = translate_rreg (SD_, RM2); | |
6122 | dstreg1 = translate_rreg (SD_, RN1); | |
6123 | dstreg2 = translate_rreg (SD_, RN2); | |
6124 | ||
6125 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); | |
6126 | temp = State.regs[dstreg2]; | |
6127 | temp >>= State.regs[srcreg2]; | |
6128 | State.regs[dstreg2] = temp; | |
6129 | } | |
6130 | ||
6131 | // 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2 | |
6132 | 8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr | |
6133 | "cmp_asr" | |
6134 | *am33 | |
6135 | { | |
6136 | int dstreg1, dstreg2; | |
6137 | signed int temp; | |
6138 | ||
6139 | PC = cia; | |
6140 | dstreg1 = translate_rreg (SD_, RN1); | |
6141 | dstreg2 = translate_rreg (SD_, RN2); | |
6142 | ||
6143 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); | |
6144 | temp = State.regs[dstreg2]; | |
6145 | temp >>= IMM4; | |
6146 | State.regs[dstreg2] = temp; | |
6147 | } | |
6148 | ||
6149 | // 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2 | |
6150 | 8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr | |
6151 | "cmp_lsr" | |
6152 | *am33 | |
6153 | { | |
6154 | int srcreg2, dstreg1, dstreg2; | |
6155 | ||
6156 | PC = cia; | |
6157 | srcreg2 = translate_rreg (SD_, RM2); | |
6158 | dstreg1 = translate_rreg (SD_, RN1); | |
6159 | dstreg2 = translate_rreg (SD_, RN2); | |
6160 | ||
6161 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); | |
6162 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
6163 | } | |
6164 | ||
6165 | // 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2 | |
6166 | 8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr | |
6167 | "cmp_lsr" | |
6168 | *am33 | |
6169 | { | |
6170 | int dstreg1, dstreg2; | |
c2d11a7d JM |
6171 | |
6172 | PC = cia; | |
6173 | dstreg1 = translate_rreg (SD_, RN1); | |
6174 | dstreg2 = translate_rreg (SD_, RN2); | |
6175 | ||
6176 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); | |
6177 | State.regs[dstreg2] >>= IMM4; | |
6178 | } | |
6179 | ||
6180 | ||
6181 | // 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2 | |
6182 | 8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl | |
6183 | "cmp_asl" | |
6184 | *am33 | |
6185 | { | |
6186 | int srcreg2, dstreg1, dstreg2; | |
6187 | ||
6188 | PC = cia; | |
6189 | srcreg2 = translate_rreg (SD_, RM2); | |
6190 | dstreg1 = translate_rreg (SD_, RN1); | |
6191 | dstreg2 = translate_rreg (SD_, RN2); | |
6192 | ||
6193 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); | |
6194 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
6195 | } | |
6196 | ||
6197 | // 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2 | |
6198 | 8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl | |
6199 | "cmp_asl" | |
6200 | *am33 | |
6201 | { | |
6202 | int dstreg1, dstreg2; | |
c2d11a7d JM |
6203 | |
6204 | PC = cia; | |
6205 | dstreg1 = translate_rreg (SD_, RN1); | |
6206 | dstreg2 = translate_rreg (SD_, RN2); | |
6207 | ||
6208 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); | |
6209 | State.regs[dstreg2] <<= IMM4; | |
6210 | } | |
6211 | ||
6212 | // 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2 | |
6213 | 8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add | |
6214 | "sub_add" | |
6215 | *am33 | |
6216 | { | |
6217 | int srcreg2, dstreg1, dstreg2; | |
6218 | int result1; | |
6219 | ||
6220 | PC = cia; | |
6221 | srcreg2 = translate_rreg (SD_, RM2); | |
6222 | dstreg1 = translate_rreg (SD_, RN1); | |
6223 | dstreg2 = translate_rreg (SD_, RN2); | |
6224 | ||
6225 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); | |
6226 | State.regs[dstreg2] += State.regs[srcreg2]; | |
6227 | State.regs[dstreg1] = result1; | |
6228 | } | |
6229 | ||
6230 | // 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2 | |
6231 | 8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add | |
6232 | "sub_add" | |
6233 | *am33 | |
6234 | { | |
6235 | int dstreg1, dstreg2; | |
6236 | int result1; | |
6237 | ||
6238 | PC = cia; | |
6239 | dstreg1 = translate_rreg (SD_, RN1); | |
6240 | dstreg2 = translate_rreg (SD_, RN2); | |
6241 | ||
6242 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); | |
6243 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
6244 | State.regs[dstreg1] = result1; | |
6245 | } | |
6246 | ||
6247 | // 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2 | |
6248 | 8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub | |
6249 | "sub_sub" | |
6250 | *am33 | |
6251 | { | |
6252 | int srcreg2, dstreg1, dstreg2; | |
6253 | int result1; | |
6254 | ||
6255 | PC = cia; | |
6256 | srcreg2 = translate_rreg (SD_, RM2); | |
6257 | dstreg1 = translate_rreg (SD_, RN1); | |
6258 | dstreg2 = translate_rreg (SD_, RN2); | |
6259 | ||
6260 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); | |
6261 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
6262 | State.regs[dstreg1] = result1; | |
6263 | } | |
6264 | ||
6265 | // 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2 | |
6266 | 8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub | |
6267 | "sub_sub" | |
6268 | *am33 | |
6269 | { | |
6270 | int dstreg1, dstreg2; | |
6271 | int result1; | |
6272 | ||
6273 | PC = cia; | |
6274 | dstreg1 = translate_rreg (SD_, RN1); | |
6275 | dstreg2 = translate_rreg (SD_, RN2); | |
6276 | ||
6277 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); | |
6278 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
6279 | State.regs[dstreg1] = result1; | |
6280 | } | |
6281 | ||
6282 | // 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2 | |
6283 | 8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp | |
6284 | "sub_cmp" | |
6285 | *am33 | |
6286 | { | |
6287 | int srcreg2, dstreg1, dstreg2; | |
c2d11a7d JM |
6288 | |
6289 | PC = cia; | |
6290 | srcreg2 = translate_rreg (SD_, RM2); | |
6291 | dstreg1 = translate_rreg (SD_, RN1); | |
6292 | dstreg2 = translate_rreg (SD_, RN2); | |
6293 | ||
6294 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); | |
6295 | State.regs[dstreg1] -= EXTEND4 (IMM4A); | |
6296 | } | |
6297 | ||
6298 | // 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2 | |
6299 | 8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp | |
6300 | "sub_cmp" | |
6301 | *am33 | |
6302 | { | |
6303 | int dstreg1, dstreg2; | |
c2d11a7d JM |
6304 | |
6305 | PC = cia; | |
6306 | dstreg1 = translate_rreg (SD_, RN1); | |
6307 | dstreg2 = translate_rreg (SD_, RN2); | |
6308 | ||
6309 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); | |
6310 | State.regs[dstreg1] -= EXTEND4 (IMM4A); | |
6311 | } | |
6312 | ||
6313 | // 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2 | |
6314 | 8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov | |
6315 | "sub_mov" | |
6316 | *am33 | |
6317 | { | |
6318 | int srcreg2, dstreg1, dstreg2; | |
6319 | int result1; | |
6320 | ||
6321 | PC = cia; | |
6322 | srcreg2 = translate_rreg (SD_, RM2); | |
6323 | dstreg1 = translate_rreg (SD_, RN1); | |
6324 | dstreg2 = translate_rreg (SD_, RN2); | |
6325 | ||
6326 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); | |
6327 | State.regs[dstreg2] = State.regs[srcreg2]; | |
6328 | State.regs[dstreg1] = result1; | |
6329 | } | |
6330 | ||
6331 | // 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2 | |
6332 | 8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov | |
6333 | "sub_mov" | |
6334 | *am33 | |
6335 | { | |
6336 | int dstreg1, dstreg2; | |
6337 | int result1; | |
6338 | ||
6339 | PC = cia; | |
6340 | dstreg1 = translate_rreg (SD_, RN1); | |
6341 | dstreg2 = translate_rreg (SD_, RN2); | |
6342 | ||
6343 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); | |
6344 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
6345 | State.regs[dstreg1] = result1; | |
6346 | } | |
6347 | ||
6348 | // 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2 | |
6349 | 8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr | |
6350 | "sub_asr" | |
6351 | *am33 | |
6352 | { | |
6353 | int srcreg2, dstreg1, dstreg2; | |
6354 | int result1; | |
6355 | signed int temp; | |
6356 | ||
6357 | PC = cia; | |
6358 | srcreg2 = translate_rreg (SD_, RM2); | |
6359 | dstreg1 = translate_rreg (SD_, RN1); | |
6360 | dstreg2 = translate_rreg (SD_, RN2); | |
6361 | ||
6362 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); | |
6363 | temp = State.regs[dstreg2]; | |
6364 | temp >>= State.regs[srcreg2]; | |
6365 | State.regs[dstreg2] = temp; | |
6366 | State.regs[dstreg1] = result1; | |
6367 | } | |
6368 | ||
6369 | // 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2 | |
6370 | 8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr | |
6371 | "sub_asr" | |
6372 | *am33 | |
6373 | { | |
6374 | int dstreg1, dstreg2; | |
6375 | int result1; | |
6376 | signed int temp; | |
6377 | ||
6378 | PC = cia; | |
6379 | dstreg1 = translate_rreg (SD_, RN1); | |
6380 | dstreg2 = translate_rreg (SD_, RN2); | |
6381 | ||
6382 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); | |
6383 | temp = State.regs[dstreg2]; | |
6384 | temp >>= IMM4; | |
6385 | State.regs[dstreg2] = temp; | |
6386 | State.regs[dstreg1] = result1; | |
6387 | } | |
6388 | ||
6389 | // 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2 | |
6390 | 8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr | |
6391 | "sub_lsr" | |
6392 | *am33 | |
6393 | { | |
6394 | int srcreg2, dstreg1, dstreg2; | |
6395 | int result1; | |
6396 | ||
6397 | PC = cia; | |
6398 | srcreg2 = translate_rreg (SD_, RM2); | |
6399 | dstreg1 = translate_rreg (SD_, RN1); | |
6400 | dstreg2 = translate_rreg (SD_, RN2); | |
6401 | ||
6402 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); | |
6403 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
6404 | State.regs[dstreg1] = result1; | |
6405 | } | |
6406 | ||
6407 | // 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2 | |
6408 | 8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr | |
6409 | "sub_lsr" | |
6410 | *am33 | |
6411 | { | |
6412 | int dstreg1, dstreg2; | |
6413 | int result1; | |
c2d11a7d JM |
6414 | |
6415 | PC = cia; | |
6416 | dstreg1 = translate_rreg (SD_, RN1); | |
6417 | dstreg2 = translate_rreg (SD_, RN2); | |
6418 | ||
6419 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); | |
6420 | State.regs[dstreg2] >>= IMM4; | |
6421 | State.regs[dstreg1] = result1; | |
6422 | } | |
6423 | ||
6424 | ||
6425 | // 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2 | |
6426 | 8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl | |
6427 | "sub_asl" | |
6428 | *am33 | |
6429 | { | |
6430 | int srcreg2, dstreg1, dstreg2; | |
6431 | int result1; | |
6432 | ||
6433 | PC = cia; | |
6434 | srcreg2 = translate_rreg (SD_, RM2); | |
6435 | dstreg1 = translate_rreg (SD_, RN1); | |
6436 | dstreg2 = translate_rreg (SD_, RN2); | |
6437 | ||
6438 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); | |
6439 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
6440 | State.regs[dstreg1] = result1; | |
6441 | } | |
6442 | ||
6443 | // 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2 | |
6444 | 8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl | |
6445 | "sub_asl" | |
6446 | *am33 | |
6447 | { | |
6448 | int dstreg1, dstreg2; | |
6449 | int result1; | |
c2d11a7d JM |
6450 | |
6451 | PC = cia; | |
6452 | dstreg1 = translate_rreg (SD_, RN1); | |
6453 | dstreg2 = translate_rreg (SD_, RN2); | |
6454 | ||
6455 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); | |
6456 | State.regs[dstreg2] <<= IMM4; | |
6457 | State.regs[dstreg1] = result1; | |
6458 | } | |
6459 | ||
6460 | // 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2 | |
6461 | 8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add | |
6462 | "mov_add" | |
6463 | *am33 | |
6464 | { | |
6465 | int srcreg2, dstreg1, dstreg2; | |
6466 | int result1; | |
6467 | ||
6468 | PC = cia; | |
6469 | srcreg2 = translate_rreg (SD_, RM2); | |
6470 | dstreg1 = translate_rreg (SD_, RN1); | |
6471 | dstreg2 = translate_rreg (SD_, RN2); | |
6472 | ||
6473 | result1 = EXTEND4 (IMM4A); | |
6474 | State.regs[dstreg2] += State.regs[srcreg2]; | |
6475 | State.regs[dstreg1] = result1; | |
6476 | } | |
6477 | ||
6478 | // 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2 | |
6479 | 8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add | |
6480 | "mov_add" | |
6481 | *am33 | |
6482 | { | |
6483 | int dstreg1, dstreg2; | |
6484 | int result1; | |
6485 | ||
6486 | PC = cia; | |
6487 | dstreg1 = translate_rreg (SD_, RN1); | |
6488 | dstreg2 = translate_rreg (SD_, RN2); | |
6489 | ||
6490 | result1 = EXTEND4 (IMM4A); | |
6491 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
6492 | State.regs[dstreg1] = result1; | |
6493 | } | |
6494 | ||
6495 | // 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2 | |
6496 | 8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub | |
6497 | "mov_sub" | |
6498 | *am33 | |
6499 | { | |
6500 | int srcreg2, dstreg1, dstreg2; | |
6501 | int result1; | |
6502 | ||
6503 | PC = cia; | |
6504 | srcreg2 = translate_rreg (SD_, RM2); | |
6505 | dstreg1 = translate_rreg (SD_, RN1); | |
6506 | dstreg2 = translate_rreg (SD_, RN2); | |
6507 | ||
6508 | result1 = EXTEND4 (IMM4A); | |
6509 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
6510 | State.regs[dstreg1] = result1; | |
6511 | } | |
6512 | ||
6513 | // 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2 | |
6514 | 8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub | |
6515 | "mov_sub" | |
6516 | *am33 | |
6517 | { | |
6518 | int dstreg1, dstreg2; | |
6519 | int result1; | |
6520 | ||
6521 | PC = cia; | |
6522 | dstreg1 = translate_rreg (SD_, RN1); | |
6523 | dstreg2 = translate_rreg (SD_, RN2); | |
6524 | ||
6525 | result1 = EXTEND4 (IMM4A); | |
6526 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
6527 | State.regs[dstreg1] = result1; | |
6528 | } | |
6529 | ||
6530 | // 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2 | |
6531 | 8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp | |
6532 | "mov_cmp" | |
6533 | *am33 | |
6534 | { | |
6535 | int srcreg2, dstreg1, dstreg2; | |
6536 | ||
6537 | PC = cia; | |
6538 | srcreg2 = translate_rreg (SD_, RM2); | |
6539 | dstreg1 = translate_rreg (SD_, RN1); | |
6540 | dstreg2 = translate_rreg (SD_, RN2); | |
6541 | ||
6542 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); | |
6543 | State.regs[dstreg1] = EXTEND4 (IMM4A); | |
6544 | } | |
6545 | ||
6546 | // 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2 | |
6547 | 8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp | |
6548 | "mov_cmp" | |
6549 | *am33 | |
6550 | { | |
6551 | int dstreg1, dstreg2; | |
6552 | ||
6553 | PC = cia; | |
6554 | dstreg1 = translate_rreg (SD_, RN1); | |
6555 | dstreg2 = translate_rreg (SD_, RN2); | |
6556 | ||
6557 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); | |
6558 | State.regs[dstreg1] = EXTEND4 (IMM4A); | |
6559 | } | |
6560 | ||
6561 | // 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2 | |
6562 | 8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov | |
6563 | "mov_mov" | |
6564 | *am33 | |
6565 | { | |
6566 | int srcreg2, dstreg1, dstreg2; | |
6567 | int result1; | |
6568 | ||
6569 | PC = cia; | |
6570 | srcreg2 = translate_rreg (SD_, RM2); | |
6571 | dstreg1 = translate_rreg (SD_, RN1); | |
6572 | dstreg2 = translate_rreg (SD_, RN2); | |
6573 | ||
6574 | result1 = EXTEND4 (IMM4A); | |
6575 | State.regs[dstreg2] = State.regs[srcreg2]; | |
6576 | State.regs[dstreg1] = result1; | |
6577 | } | |
6578 | ||
6579 | // 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2 | |
6580 | 8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov | |
6581 | "mov_mov" | |
6582 | *am33 | |
6583 | { | |
6584 | int dstreg1, dstreg2; | |
6585 | int result1; | |
6586 | ||
6587 | PC = cia; | |
6588 | dstreg1 = translate_rreg (SD_, RN1); | |
6589 | dstreg2 = translate_rreg (SD_, RN2); | |
6590 | ||
6591 | result1 = EXTEND4 (IMM4A); | |
6592 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
6593 | State.regs[dstreg1] = result1; | |
6594 | } | |
6595 | ||
6596 | // 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2 | |
6597 | 8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr | |
6598 | "mov_asr" | |
6599 | *am33 | |
6600 | { | |
6601 | int srcreg2, dstreg1, dstreg2; | |
6602 | int result1; | |
6603 | signed int temp; | |
6604 | ||
6605 | PC = cia; | |
6606 | srcreg2 = translate_rreg (SD_, RM2); | |
6607 | dstreg1 = translate_rreg (SD_, RN1); | |
6608 | dstreg2 = translate_rreg (SD_, RN2); | |
6609 | ||
6610 | result1 = EXTEND4 (IMM4A); | |
6611 | temp = State.regs[dstreg2]; | |
6612 | temp >>= State.regs[srcreg2]; | |
6613 | State.regs[dstreg2] = temp; | |
6614 | State.regs[dstreg1] = result1; | |
6615 | } | |
6616 | ||
6617 | // 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2 | |
6618 | 8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr | |
6619 | "mov_asr" | |
6620 | *am33 | |
6621 | { | |
6622 | int dstreg1, dstreg2; | |
6623 | int result1; | |
6624 | signed int temp; | |
6625 | ||
6626 | PC = cia; | |
6627 | dstreg1 = translate_rreg (SD_, RN1); | |
6628 | dstreg2 = translate_rreg (SD_, RN2); | |
6629 | ||
6630 | result1 = EXTEND4 (IMM4A); | |
6631 | temp = State.regs[dstreg2]; | |
6632 | temp >>= IMM4; | |
6633 | State.regs[dstreg2] = temp; | |
6634 | State.regs[dstreg1] = result1; | |
6635 | } | |
6636 | ||
6637 | // 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2 | |
6638 | 8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr | |
6639 | "mov_lsr" | |
6640 | *am33 | |
6641 | { | |
6642 | int srcreg2, dstreg1, dstreg2; | |
6643 | int result1; | |
6644 | ||
6645 | PC = cia; | |
6646 | srcreg2 = translate_rreg (SD_, RM2); | |
6647 | dstreg1 = translate_rreg (SD_, RN1); | |
6648 | dstreg2 = translate_rreg (SD_, RN2); | |
6649 | ||
6650 | result1 = EXTEND4 (IMM4A); | |
6651 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
6652 | State.regs[dstreg1] = result1; | |
6653 | } | |
6654 | ||
6655 | // 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2 | |
6656 | 8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr | |
6657 | "mov_lsr" | |
6658 | *am33 | |
6659 | { | |
6660 | int dstreg1, dstreg2; | |
6661 | int result1; | |
c2d11a7d JM |
6662 | |
6663 | PC = cia; | |
6664 | dstreg1 = translate_rreg (SD_, RN1); | |
6665 | dstreg2 = translate_rreg (SD_, RN2); | |
6666 | ||
6667 | result1 = EXTEND4 (IMM4A); | |
6668 | State.regs[dstreg2] >>= IMM4; | |
6669 | State.regs[dstreg1] = result1; | |
6670 | } | |
6671 | ||
6672 | ||
6673 | // 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2 | |
6674 | 8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl | |
6675 | "mov_asl" | |
6676 | *am33 | |
6677 | { | |
6678 | int srcreg2, dstreg1, dstreg2; | |
6679 | int result1; | |
6680 | ||
6681 | PC = cia; | |
6682 | srcreg2 = translate_rreg (SD_, RM2); | |
6683 | dstreg1 = translate_rreg (SD_, RN1); | |
6684 | dstreg2 = translate_rreg (SD_, RN2); | |
6685 | ||
6686 | result1 = EXTEND4 (IMM4A); | |
6687 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
6688 | State.regs[dstreg1] = result1; | |
6689 | } | |
6690 | ||
6691 | // 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2 | |
6692 | 8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl | |
6693 | "mov_asl" | |
6694 | *am33 | |
6695 | { | |
6696 | int dstreg1, dstreg2; | |
6697 | int result1; | |
c2d11a7d JM |
6698 | |
6699 | PC = cia; | |
6700 | dstreg1 = translate_rreg (SD_, RN1); | |
6701 | dstreg2 = translate_rreg (SD_, RN2); | |
6702 | ||
6703 | result1 = EXTEND4 (IMM4A); | |
6704 | State.regs[dstreg2] <<= IMM4; | |
6705 | State.regs[dstreg1] = result1; | |
6706 | } | |
6707 | ||
6708 | // 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2 | |
6709 | 8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add | |
6710 | "and_add" | |
6711 | *am33 | |
6712 | { | |
6713 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
6714 | int result1; | |
6715 | ||
6716 | PC = cia; | |
6717 | srcreg1 = translate_rreg (SD_, RM1); | |
6718 | srcreg2 = translate_rreg (SD_, RM2); | |
6719 | dstreg1 = translate_rreg (SD_, RN1); | |
6720 | dstreg2 = translate_rreg (SD_, RN2); | |
6721 | ||
6722 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; | |
6723 | State.regs[dstreg2] += State.regs[srcreg2]; | |
6724 | State.regs[dstreg1] = result1; | |
6725 | } | |
6726 | ||
6727 | // 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2 | |
6728 | 8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add | |
6729 | "and_add" | |
6730 | *am33 | |
6731 | { | |
6732 | int srcreg1, dstreg1, dstreg2; | |
6733 | int result1; | |
6734 | ||
6735 | PC = cia; | |
6736 | srcreg1 = translate_rreg (SD_, RM1); | |
6737 | dstreg1 = translate_rreg (SD_, RN1); | |
6738 | dstreg2 = translate_rreg (SD_, RN2); | |
6739 | ||
6740 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; | |
6741 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
6742 | State.regs[dstreg1] = result1; | |
6743 | } | |
6744 | ||
6745 | // 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2 | |
6746 | 8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub | |
6747 | "and_sub" | |
6748 | *am33 | |
6749 | { | |
6750 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
6751 | int result1; | |
6752 | ||
6753 | PC = cia; | |
6754 | srcreg1 = translate_rreg (SD_, RM1); | |
6755 | srcreg2 = translate_rreg (SD_, RM2); | |
6756 | dstreg1 = translate_rreg (SD_, RN1); | |
6757 | dstreg2 = translate_rreg (SD_, RN2); | |
6758 | ||
6759 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; | |
6760 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
6761 | State.regs[dstreg1] = result1; | |
6762 | } | |
6763 | ||
6764 | // 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2 | |
6765 | 8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub | |
6766 | "and_sub" | |
6767 | *am33 | |
6768 | { | |
6769 | int srcreg1, dstreg1, dstreg2; | |
6770 | int result1; | |
6771 | ||
6772 | PC = cia; | |
6773 | srcreg1 = translate_rreg (SD_, RM1); | |
6774 | dstreg1 = translate_rreg (SD_, RN1); | |
6775 | dstreg2 = translate_rreg (SD_, RN2); | |
6776 | ||
6777 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; | |
6778 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
6779 | State.regs[dstreg1] = result1; | |
6780 | } | |
6781 | ||
6782 | // 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2 | |
6783 | 8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp | |
6784 | "and_cmp" | |
6785 | *am33 | |
6786 | { | |
6787 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
6788 | ||
6789 | PC = cia; | |
6790 | srcreg1 = translate_rreg (SD_, RM1); | |
6791 | srcreg2 = translate_rreg (SD_, RM2); | |
6792 | dstreg1 = translate_rreg (SD_, RN1); | |
6793 | dstreg2 = translate_rreg (SD_, RN2); | |
6794 | ||
6795 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); | |
6796 | State.regs[dstreg1] &= State.regs[srcreg1]; | |
6797 | } | |
6798 | ||
6799 | // 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2 | |
6800 | 8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp | |
6801 | "and_cmp" | |
6802 | *am33 | |
6803 | { | |
6804 | int srcreg1, dstreg1, dstreg2; | |
6805 | ||
6806 | PC = cia; | |
6807 | srcreg1 = translate_rreg (SD_, RM1); | |
6808 | dstreg1 = translate_rreg (SD_, RN1); | |
6809 | dstreg2 = translate_rreg (SD_, RN2); | |
6810 | ||
6811 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); | |
6812 | State.regs[dstreg1] &= State.regs[srcreg1]; | |
6813 | } | |
6814 | ||
6815 | // 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2 | |
6816 | 8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov | |
6817 | "and_mov" | |
6818 | *am33 | |
6819 | { | |
6820 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
6821 | int result1; | |
6822 | ||
6823 | PC = cia; | |
6824 | srcreg1 = translate_rreg (SD_, RM1); | |
6825 | srcreg2 = translate_rreg (SD_, RM2); | |
6826 | dstreg1 = translate_rreg (SD_, RN1); | |
6827 | dstreg2 = translate_rreg (SD_, RN2); | |
6828 | ||
6829 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; | |
6830 | State.regs[dstreg2] = State.regs[srcreg2]; | |
6831 | State.regs[dstreg1] = result1; | |
6832 | } | |
6833 | ||
6834 | // 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2 | |
6835 | 8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov | |
6836 | "and_mov" | |
6837 | *am33 | |
6838 | { | |
6839 | int srcreg1, dstreg1, dstreg2; | |
6840 | int result1; | |
6841 | ||
6842 | PC = cia; | |
6843 | srcreg1 = translate_rreg (SD_, RM1); | |
6844 | dstreg1 = translate_rreg (SD_, RN1); | |
6845 | dstreg2 = translate_rreg (SD_, RN2); | |
6846 | ||
6847 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; | |
6848 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
6849 | State.regs[dstreg1] = result1; | |
6850 | } | |
6851 | ||
6852 | // 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2 | |
6853 | 8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr | |
6854 | "and_asr" | |
6855 | *am33 | |
6856 | { | |
6857 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
6858 | int result1; | |
6859 | signed int temp; | |
6860 | ||
6861 | PC = cia; | |
6862 | srcreg1 = translate_rreg (SD_, RM1); | |
6863 | srcreg2 = translate_rreg (SD_, RM2); | |
6864 | dstreg1 = translate_rreg (SD_, RN1); | |
6865 | dstreg2 = translate_rreg (SD_, RN2); | |
6866 | ||
6867 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; | |
6868 | temp = State.regs[dstreg2]; | |
6869 | temp >>= State.regs[srcreg2]; | |
6870 | State.regs[dstreg2] = temp; | |
6871 | State.regs[dstreg1] = result1; | |
6872 | } | |
6873 | ||
6874 | // 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2 | |
6875 | 8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr | |
6876 | "and_asr" | |
6877 | *am33 | |
6878 | { | |
6879 | int srcreg1, dstreg1, dstreg2; | |
6880 | int result1; | |
6881 | signed int temp; | |
6882 | ||
6883 | PC = cia; | |
6884 | srcreg1 = translate_rreg (SD_, RM1); | |
6885 | dstreg1 = translate_rreg (SD_, RN1); | |
6886 | dstreg2 = translate_rreg (SD_, RN2); | |
6887 | ||
6888 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; | |
6889 | temp = State.regs[dstreg2]; | |
6890 | temp >>= IMM4; | |
6891 | State.regs[dstreg2] = temp; | |
6892 | State.regs[dstreg1] = result1; | |
6893 | } | |
6894 | ||
6895 | // 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2 | |
6896 | 8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr | |
6897 | "and_lsr" | |
6898 | *am33 | |
6899 | { | |
6900 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
6901 | int result1; | |
6902 | ||
6903 | PC = cia; | |
6904 | srcreg1 = translate_rreg (SD_, RM1); | |
6905 | srcreg2 = translate_rreg (SD_, RM2); | |
6906 | dstreg1 = translate_rreg (SD_, RN1); | |
6907 | dstreg2 = translate_rreg (SD_, RN2); | |
6908 | ||
6909 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; | |
6910 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
6911 | State.regs[dstreg1] = result1; | |
6912 | } | |
6913 | ||
6914 | // 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2 | |
6915 | 8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr | |
6916 | "and_lsr" | |
6917 | *am33 | |
6918 | { | |
6919 | int srcreg1, dstreg1, dstreg2; | |
6920 | int result1; | |
c2d11a7d JM |
6921 | |
6922 | PC = cia; | |
6923 | srcreg1 = translate_rreg (SD_, RM1); | |
6924 | dstreg1 = translate_rreg (SD_, RN1); | |
6925 | dstreg2 = translate_rreg (SD_, RN2); | |
6926 | ||
6927 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; | |
6928 | State.regs[dstreg2] >>= IMM4; | |
6929 | State.regs[dstreg1] = result1; | |
6930 | } | |
6931 | ||
6932 | ||
6933 | // 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2 | |
6934 | 8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl | |
6935 | "and_asl" | |
6936 | *am33 | |
6937 | { | |
6938 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
6939 | int result1; | |
6940 | ||
6941 | PC = cia; | |
6942 | srcreg1 = translate_rreg (SD_, RM1); | |
6943 | srcreg2 = translate_rreg (SD_, RM2); | |
6944 | dstreg1 = translate_rreg (SD_, RN1); | |
6945 | dstreg2 = translate_rreg (SD_, RN2); | |
6946 | ||
6947 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; | |
6948 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
6949 | State.regs[dstreg1] = result1; | |
6950 | } | |
6951 | ||
6952 | // 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2 | |
6953 | 8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl | |
6954 | "and_asl" | |
6955 | *am33 | |
6956 | { | |
6957 | int srcreg1, dstreg1, dstreg2; | |
6958 | int result1; | |
c2d11a7d JM |
6959 | |
6960 | PC = cia; | |
6961 | srcreg1 = translate_rreg (SD_, RM1); | |
6962 | dstreg1 = translate_rreg (SD_, RN1); | |
6963 | dstreg2 = translate_rreg (SD_, RN2); | |
6964 | ||
6965 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; | |
6966 | State.regs[dstreg2] <<= IMM4; | |
6967 | State.regs[dstreg1] = result1; | |
6968 | } | |
6969 | ||
6970 | // 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2 | |
6971 | 8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add | |
6972 | "dmach_add" | |
6973 | *am33 | |
6974 | { | |
6975 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 | 6976 | signed32 temp, temp2, sum; |
c2d11a7d JM |
6977 | |
6978 | PC = cia; | |
6979 | srcreg1 = translate_rreg (SD_, RM1); | |
6980 | srcreg2 = translate_rreg (SD_, RM2); | |
6981 | dstreg1 = translate_rreg (SD_, RN1); | |
6982 | dstreg2 = translate_rreg (SD_, RN2); | |
6983 | ||
6984 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
6985 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
6986 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
6987 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
6988 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
6989 | ||
6990 | State.regs[dstreg2] += State.regs[srcreg2]; | |
6991 | State.regs[dstreg1] = sum; | |
6992 | } | |
6993 | ||
6994 | // 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2 | |
6995 | 8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add | |
6996 | "dmach_add" | |
6997 | *am33 | |
6998 | { | |
6999 | int srcreg1, dstreg1, dstreg2; | |
24a39d88 | 7000 | signed32 temp, temp2, sum; |
c2d11a7d JM |
7001 | |
7002 | PC = cia; | |
7003 | srcreg1 = translate_rreg (SD_, RM1); | |
7004 | dstreg1 = translate_rreg (SD_, RN1); | |
7005 | dstreg2 = translate_rreg (SD_, RN2); | |
7006 | ||
7007 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
7008 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
7009 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
7010 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
7011 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
7012 | ||
7013 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
7014 | State.regs[dstreg1] = sum; | |
7015 | } | |
7016 | ||
7017 | // 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2 | |
7018 | 8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub | |
7019 | "dmach_sub" | |
7020 | *am33 | |
7021 | { | |
7022 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 | 7023 | signed32 temp, temp2, sum; |
c2d11a7d JM |
7024 | |
7025 | PC = cia; | |
7026 | srcreg1 = translate_rreg (SD_, RM1); | |
7027 | srcreg2 = translate_rreg (SD_, RM2); | |
7028 | dstreg1 = translate_rreg (SD_, RN1); | |
7029 | dstreg2 = translate_rreg (SD_, RN2); | |
7030 | ||
7031 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
7032 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
7033 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
7034 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
7035 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
7036 | ||
7037 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
7038 | State.regs[dstreg1] = sum; | |
7039 | } | |
7040 | ||
7041 | // 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2 | |
7042 | 8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub | |
7043 | "dmach_sub" | |
7044 | *am33 | |
7045 | { | |
7046 | int srcreg1, dstreg1, dstreg2; | |
24a39d88 | 7047 | signed32 temp, temp2, sum; |
c2d11a7d JM |
7048 | |
7049 | PC = cia; | |
7050 | srcreg1 = translate_rreg (SD_, RM1); | |
7051 | dstreg1 = translate_rreg (SD_, RN1); | |
7052 | dstreg2 = translate_rreg (SD_, RN2); | |
7053 | ||
7054 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
7055 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
7056 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
7057 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
7058 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
7059 | ||
7060 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
7061 | State.regs[dstreg1] = sum; | |
7062 | } | |
7063 | ||
7064 | // 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2 | |
7065 | 8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp | |
7066 | "dmach_cmp" | |
7067 | *am33 | |
7068 | { | |
7069 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 | 7070 | signed32 temp, temp2, sum; |
c2d11a7d JM |
7071 | |
7072 | PC = cia; | |
7073 | srcreg1 = translate_rreg (SD_, RM1); | |
7074 | srcreg2 = translate_rreg (SD_, RM2); | |
7075 | dstreg1 = translate_rreg (SD_, RN1); | |
7076 | dstreg2 = translate_rreg (SD_, RN2); | |
7077 | ||
7078 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
7079 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
7080 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
7081 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
7082 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
7083 | ||
7084 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); | |
7085 | State.regs[dstreg1] = sum; | |
7086 | } | |
7087 | ||
7088 | // 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2 | |
7089 | 8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp | |
7090 | "dmach_cmp" | |
7091 | *am33 | |
7092 | { | |
7093 | int srcreg1, dstreg1, dstreg2; | |
24a39d88 | 7094 | signed32 temp, temp2, sum; |
c2d11a7d JM |
7095 | |
7096 | PC = cia; | |
7097 | srcreg1 = translate_rreg (SD_, RM1); | |
7098 | dstreg1 = translate_rreg (SD_, RN1); | |
7099 | dstreg2 = translate_rreg (SD_, RN2); | |
7100 | ||
7101 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
7102 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
7103 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
7104 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
7105 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
7106 | ||
7107 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); | |
7108 | State.regs[dstreg1] = sum; | |
7109 | } | |
7110 | ||
7111 | // 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2 | |
7112 | 8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov | |
7113 | "dmach_mov" | |
7114 | *am33 | |
7115 | { | |
7116 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 | 7117 | signed32 temp, temp2, sum; |
c2d11a7d JM |
7118 | |
7119 | PC = cia; | |
7120 | srcreg1 = translate_rreg (SD_, RM1); | |
7121 | srcreg2 = translate_rreg (SD_, RM2); | |
7122 | dstreg1 = translate_rreg (SD_, RN1); | |
7123 | dstreg2 = translate_rreg (SD_, RN2); | |
7124 | ||
7125 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
7126 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
7127 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
7128 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
7129 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
7130 | ||
7131 | State.regs[dstreg2] = State.regs[srcreg2]; | |
7132 | State.regs[dstreg1] = sum; | |
7133 | } | |
7134 | ||
7135 | // 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2 | |
7136 | 8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov | |
7137 | "dmach_mov" | |
7138 | *am33 | |
7139 | { | |
7140 | int srcreg1, dstreg1, dstreg2; | |
24a39d88 | 7141 | signed32 temp, temp2, sum; |
c2d11a7d JM |
7142 | |
7143 | PC = cia; | |
7144 | srcreg1 = translate_rreg (SD_, RM1); | |
7145 | dstreg1 = translate_rreg (SD_, RN1); | |
7146 | dstreg2 = translate_rreg (SD_, RN2); | |
7147 | ||
7148 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
7149 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
7150 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
7151 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
7152 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
7153 | ||
7154 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
7155 | State.regs[dstreg1] = sum; | |
7156 | } | |
7157 | ||
7158 | // 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2 | |
7159 | 8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr | |
7160 | "dmach_asr" | |
7161 | *am33 | |
7162 | { | |
7163 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 | 7164 | signed32 temp, temp2, sum; |
c2d11a7d JM |
7165 | |
7166 | PC = cia; | |
7167 | srcreg1 = translate_rreg (SD_, RM1); | |
7168 | srcreg2 = translate_rreg (SD_, RM2); | |
7169 | dstreg1 = translate_rreg (SD_, RN1); | |
7170 | dstreg2 = translate_rreg (SD_, RN2); | |
7171 | ||
7172 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
7173 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
7174 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
7175 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
7176 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
7177 | ||
7178 | temp = State.regs[dstreg2]; | |
7179 | temp >>= State.regs[srcreg2]; | |
7180 | State.regs[dstreg2] = temp; | |
7181 | State.regs[dstreg1] = sum; | |
7182 | } | |
7183 | ||
7184 | // 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2 | |
7185 | 8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr | |
7186 | "dmach_asr" | |
7187 | *am33 | |
7188 | { | |
7189 | int srcreg1, dstreg1, dstreg2; | |
24a39d88 | 7190 | signed32 temp, temp2, sum; |
c2d11a7d JM |
7191 | |
7192 | PC = cia; | |
7193 | srcreg1 = translate_rreg (SD_, RM1); | |
7194 | dstreg1 = translate_rreg (SD_, RN1); | |
7195 | dstreg2 = translate_rreg (SD_, RN2); | |
7196 | ||
7197 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
7198 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
7199 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
7200 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
7201 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
7202 | ||
7203 | temp = State.regs[dstreg2]; | |
7204 | temp >>= IMM4; | |
7205 | State.regs[dstreg2] = temp; | |
7206 | State.regs[dstreg1] = sum; | |
7207 | } | |
7208 | ||
7209 | // 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2 | |
7210 | 8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr | |
7211 | "dmach_lsr" | |
7212 | *am33 | |
7213 | { | |
7214 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 | 7215 | signed32 temp, temp2, sum; |
c2d11a7d JM |
7216 | |
7217 | PC = cia; | |
7218 | srcreg1 = translate_rreg (SD_, RM1); | |
7219 | srcreg2 = translate_rreg (SD_, RM2); | |
7220 | dstreg1 = translate_rreg (SD_, RN1); | |
7221 | dstreg2 = translate_rreg (SD_, RN2); | |
7222 | ||
7223 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
7224 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
7225 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
7226 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
7227 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
7228 | ||
7229 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
7230 | State.regs[dstreg1] = sum; | |
7231 | } | |
7232 | ||
7233 | // 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2 | |
7234 | 8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr | |
7235 | "dmach_lsr" | |
7236 | *am33 | |
7237 | { | |
7238 | int srcreg1, dstreg1, dstreg2; | |
24a39d88 | 7239 | signed32 temp, temp2, sum; |
c2d11a7d JM |
7240 | |
7241 | PC = cia; | |
7242 | srcreg1 = translate_rreg (SD_, RM1); | |
7243 | dstreg1 = translate_rreg (SD_, RN1); | |
7244 | dstreg2 = translate_rreg (SD_, RN2); | |
7245 | ||
7246 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
7247 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
7248 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
7249 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
7250 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
7251 | ||
7252 | State.regs[dstreg2] >>= IMM4; | |
7253 | State.regs[dstreg1] = sum; | |
7254 | } | |
7255 | ||
7256 | ||
7257 | // 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2 | |
7258 | 8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl | |
7259 | "dmach_asl" | |
7260 | *am33 | |
7261 | { | |
7262 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
24a39d88 | 7263 | signed32 temp, temp2, sum; |
c2d11a7d JM |
7264 | |
7265 | PC = cia; | |
7266 | srcreg1 = translate_rreg (SD_, RM1); | |
7267 | srcreg2 = translate_rreg (SD_, RM2); | |
7268 | dstreg1 = translate_rreg (SD_, RN1); | |
7269 | dstreg2 = translate_rreg (SD_, RN2); | |
7270 | ||
7271 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
7272 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
7273 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
7274 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
7275 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
7276 | ||
7277 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
7278 | State.regs[dstreg1] = sum; | |
7279 | } | |
7280 | ||
7281 | // 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2 | |
7282 | 8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl | |
7283 | "dmach_asl" | |
7284 | *am33 | |
7285 | { | |
7286 | int srcreg1, dstreg1, dstreg2; | |
24a39d88 | 7287 | signed32 temp, temp2, sum; |
c2d11a7d JM |
7288 | |
7289 | PC = cia; | |
7290 | srcreg1 = translate_rreg (SD_, RM1); | |
7291 | dstreg1 = translate_rreg (SD_, RN1); | |
7292 | dstreg2 = translate_rreg (SD_, RN2); | |
7293 | ||
7294 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) | |
7295 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); | |
7296 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) | |
7297 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); | |
7298 | sum = temp + temp2 + State.regs[REG_MCRL]; | |
7299 | ||
7300 | State.regs[dstreg2] <<= IMM4; | |
7301 | State.regs[dstreg1] = sum; | |
7302 | } | |
7303 | ||
7304 | // 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2 | |
7305 | 8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add | |
7306 | "xor_add" | |
7307 | *am33 | |
7308 | { | |
7309 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7310 | int result1; | |
7311 | ||
7312 | PC = cia; | |
7313 | srcreg1 = translate_rreg (SD_, RM1); | |
7314 | srcreg2 = translate_rreg (SD_, RM2); | |
7315 | dstreg1 = translate_rreg (SD_, RN1); | |
7316 | dstreg2 = translate_rreg (SD_, RN2); | |
7317 | ||
7318 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; | |
7319 | State.regs[dstreg2] += State.regs[srcreg2]; | |
7320 | State.regs[dstreg1] = result1; | |
7321 | } | |
7322 | ||
7323 | // 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2 | |
7324 | 8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add | |
7325 | "xor_add" | |
7326 | *am33 | |
7327 | { | |
7328 | int srcreg1, dstreg1, dstreg2; | |
7329 | int result1; | |
7330 | ||
7331 | PC = cia; | |
7332 | srcreg1 = translate_rreg (SD_, RM1); | |
7333 | dstreg1 = translate_rreg (SD_, RN1); | |
7334 | dstreg2 = translate_rreg (SD_, RN2); | |
7335 | ||
7336 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; | |
7337 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
7338 | State.regs[dstreg1] = result1; | |
7339 | } | |
7340 | ||
7341 | // 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2 | |
7342 | 8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub | |
7343 | "xor_sub" | |
7344 | *am33 | |
7345 | { | |
7346 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7347 | int result1; | |
7348 | ||
7349 | PC = cia; | |
7350 | srcreg1 = translate_rreg (SD_, RM1); | |
7351 | srcreg2 = translate_rreg (SD_, RM2); | |
7352 | dstreg1 = translate_rreg (SD_, RN1); | |
7353 | dstreg2 = translate_rreg (SD_, RN2); | |
7354 | ||
7355 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; | |
7356 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
7357 | State.regs[dstreg1] = result1; | |
7358 | } | |
7359 | ||
7360 | // 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2 | |
7361 | 8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub | |
7362 | "xor_sub" | |
7363 | *am33 | |
7364 | { | |
7365 | int srcreg1, dstreg1, dstreg2; | |
7366 | int result1; | |
7367 | ||
7368 | PC = cia; | |
7369 | srcreg1 = translate_rreg (SD_, RM1); | |
7370 | dstreg1 = translate_rreg (SD_, RN1); | |
7371 | dstreg2 = translate_rreg (SD_, RN2); | |
7372 | ||
7373 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; | |
7374 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
7375 | State.regs[dstreg1] = result1; | |
7376 | } | |
7377 | ||
7378 | // 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2 | |
7379 | 8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp | |
7380 | "xor_cmp" | |
7381 | *am33 | |
7382 | { | |
7383 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7384 | ||
7385 | PC = cia; | |
7386 | srcreg1 = translate_rreg (SD_, RM1); | |
7387 | srcreg2 = translate_rreg (SD_, RM2); | |
7388 | dstreg1 = translate_rreg (SD_, RN1); | |
7389 | dstreg2 = translate_rreg (SD_, RN2); | |
7390 | ||
7391 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); | |
7392 | State.regs[dstreg1] ^= State.regs[srcreg1]; | |
7393 | } | |
7394 | ||
7395 | // 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2 | |
7396 | 8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp | |
7397 | "xor_cmp" | |
7398 | *am33 | |
7399 | { | |
7400 | int srcreg1, dstreg1, dstreg2; | |
7401 | ||
7402 | PC = cia; | |
7403 | srcreg1 = translate_rreg (SD_, RM1); | |
7404 | dstreg1 = translate_rreg (SD_, RN1); | |
7405 | dstreg2 = translate_rreg (SD_, RN2); | |
7406 | ||
7407 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); | |
7408 | State.regs[dstreg1] ^= State.regs[srcreg1]; | |
7409 | } | |
7410 | ||
7411 | // 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2 | |
7412 | 8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov | |
7413 | "xor_mov" | |
7414 | *am33 | |
7415 | { | |
7416 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7417 | int result1; | |
7418 | ||
7419 | PC = cia; | |
7420 | srcreg1 = translate_rreg (SD_, RM1); | |
7421 | srcreg2 = translate_rreg (SD_, RM2); | |
7422 | dstreg1 = translate_rreg (SD_, RN1); | |
7423 | dstreg2 = translate_rreg (SD_, RN2); | |
7424 | ||
7425 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; | |
7426 | State.regs[dstreg2] = State.regs[srcreg2]; | |
7427 | State.regs[dstreg1] = result1; | |
7428 | } | |
7429 | ||
7430 | // 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2 | |
7431 | 8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov | |
7432 | "xor_mov" | |
7433 | *am33 | |
7434 | { | |
7435 | int srcreg1, dstreg1, dstreg2; | |
7436 | int result1; | |
7437 | ||
7438 | PC = cia; | |
7439 | srcreg1 = translate_rreg (SD_, RM1); | |
7440 | dstreg1 = translate_rreg (SD_, RN1); | |
7441 | dstreg2 = translate_rreg (SD_, RN2); | |
7442 | ||
7443 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; | |
7444 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
7445 | State.regs[dstreg1] = result1; | |
7446 | } | |
7447 | ||
7448 | // 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2 | |
7449 | 8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr | |
7450 | "xor_asr" | |
7451 | *am33 | |
7452 | { | |
7453 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7454 | int result1; | |
7455 | signed int temp; | |
7456 | ||
7457 | PC = cia; | |
7458 | srcreg1 = translate_rreg (SD_, RM1); | |
7459 | srcreg2 = translate_rreg (SD_, RM2); | |
7460 | dstreg1 = translate_rreg (SD_, RN1); | |
7461 | dstreg2 = translate_rreg (SD_, RN2); | |
7462 | ||
7463 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; | |
7464 | temp = State.regs[dstreg2]; | |
7465 | temp >>= State.regs[srcreg2]; | |
7466 | State.regs[dstreg2] = temp; | |
7467 | State.regs[dstreg1] = result1; | |
7468 | } | |
7469 | ||
7470 | // 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2 | |
7471 | 8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr | |
7472 | "xor_asr" | |
7473 | *am33 | |
7474 | { | |
7475 | int srcreg1, dstreg1, dstreg2; | |
7476 | int result1; | |
7477 | signed int temp; | |
7478 | ||
7479 | PC = cia; | |
7480 | srcreg1 = translate_rreg (SD_, RM1); | |
7481 | dstreg1 = translate_rreg (SD_, RN1); | |
7482 | dstreg2 = translate_rreg (SD_, RN2); | |
7483 | ||
7484 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; | |
7485 | temp = State.regs[dstreg2]; | |
7486 | temp >>= IMM4; | |
7487 | State.regs[dstreg2] = temp; | |
7488 | State.regs[dstreg1] = result1; | |
7489 | } | |
7490 | ||
7491 | // 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2 | |
7492 | 8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr | |
7493 | "xor_lsr" | |
7494 | *am33 | |
7495 | { | |
7496 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7497 | int result1; | |
7498 | ||
7499 | PC = cia; | |
7500 | srcreg1 = translate_rreg (SD_, RM1); | |
7501 | srcreg2 = translate_rreg (SD_, RM2); | |
7502 | dstreg1 = translate_rreg (SD_, RN1); | |
7503 | dstreg2 = translate_rreg (SD_, RN2); | |
7504 | ||
7505 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; | |
7506 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
7507 | State.regs[dstreg1] = result1; | |
7508 | } | |
7509 | ||
7510 | // 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2 | |
7511 | 8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr | |
7512 | "xor_lsr" | |
7513 | *am33 | |
7514 | { | |
7515 | int srcreg1, dstreg1, dstreg2; | |
7516 | int result1; | |
c2d11a7d JM |
7517 | |
7518 | PC = cia; | |
7519 | srcreg1 = translate_rreg (SD_, RM1); | |
7520 | dstreg1 = translate_rreg (SD_, RN1); | |
7521 | dstreg2 = translate_rreg (SD_, RN2); | |
7522 | ||
7523 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; | |
7524 | State.regs[dstreg2] >>= IMM4; | |
7525 | State.regs[dstreg1] = result1; | |
7526 | } | |
7527 | ||
7528 | ||
7529 | // 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2 | |
7530 | 8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl | |
7531 | "xor_asl" | |
7532 | *am33 | |
7533 | { | |
7534 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7535 | int result1; | |
7536 | ||
7537 | PC = cia; | |
7538 | srcreg1 = translate_rreg (SD_, RM1); | |
7539 | srcreg2 = translate_rreg (SD_, RM2); | |
7540 | dstreg1 = translate_rreg (SD_, RN1); | |
7541 | dstreg2 = translate_rreg (SD_, RN2); | |
7542 | ||
7543 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; | |
7544 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
7545 | State.regs[dstreg1] = result1; | |
7546 | } | |
7547 | ||
7548 | // 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2 | |
7549 | 8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl | |
7550 | "xor_asl" | |
7551 | *am33 | |
7552 | { | |
7553 | int srcreg1, dstreg1, dstreg2; | |
7554 | int result1; | |
c2d11a7d JM |
7555 | |
7556 | PC = cia; | |
7557 | srcreg1 = translate_rreg (SD_, RM1); | |
7558 | dstreg1 = translate_rreg (SD_, RN1); | |
7559 | dstreg2 = translate_rreg (SD_, RN2); | |
7560 | ||
7561 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; | |
7562 | State.regs[dstreg2] <<= IMM4; | |
7563 | State.regs[dstreg1] = result1; | |
7564 | } | |
7565 | ||
7566 | // 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2 | |
7567 | 8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add | |
7568 | "swhw_add" | |
7569 | *am33 | |
7570 | { | |
7571 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7572 | int result1; | |
7573 | ||
7574 | PC = cia; | |
7575 | srcreg1 = translate_rreg (SD_, RM1); | |
7576 | srcreg2 = translate_rreg (SD_, RM2); | |
7577 | dstreg1 = translate_rreg (SD_, RN1); | |
7578 | dstreg2 = translate_rreg (SD_, RN2); | |
7579 | ||
7580 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; | |
7581 | State.regs[dstreg2] += State.regs[srcreg2]; | |
7582 | State.regs[dstreg1] = result1; | |
7583 | } | |
7584 | ||
7585 | // 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2 | |
7586 | 8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add | |
7587 | "swhw_add" | |
7588 | *am33 | |
7589 | { | |
7590 | int srcreg1, dstreg1, dstreg2; | |
7591 | int result1; | |
7592 | ||
7593 | PC = cia; | |
7594 | srcreg1 = translate_rreg (SD_, RM1); | |
7595 | dstreg1 = translate_rreg (SD_, RN1); | |
7596 | dstreg2 = translate_rreg (SD_, RN2); | |
7597 | ||
7598 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) | |
7599 | | ((State.regs[srcreg1] >> 16) & 0xffff)); | |
7600 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
7601 | State.regs[dstreg1] = result1; | |
7602 | } | |
7603 | ||
7604 | // 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2 | |
7605 | 8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub | |
7606 | "swhw_sub" | |
7607 | *am33 | |
7608 | { | |
7609 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7610 | int result1; | |
7611 | ||
7612 | PC = cia; | |
7613 | srcreg1 = translate_rreg (SD_, RM1); | |
7614 | srcreg2 = translate_rreg (SD_, RM2); | |
7615 | dstreg1 = translate_rreg (SD_, RN1); | |
7616 | dstreg2 = translate_rreg (SD_, RN2); | |
7617 | ||
7618 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) | |
7619 | | ((State.regs[srcreg1] >> 16) & 0xffff)); | |
7620 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
7621 | State.regs[dstreg1] = result1; | |
7622 | } | |
7623 | ||
7624 | // 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2 | |
7625 | 8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub | |
7626 | "swhw_sub" | |
7627 | *am33 | |
7628 | { | |
7629 | int srcreg1, dstreg1, dstreg2; | |
7630 | int result1; | |
7631 | ||
7632 | PC = cia; | |
7633 | srcreg1 = translate_rreg (SD_, RM1); | |
7634 | dstreg1 = translate_rreg (SD_, RN1); | |
7635 | dstreg2 = translate_rreg (SD_, RN2); | |
7636 | ||
7637 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) | |
7638 | | ((State.regs[srcreg1] >> 16) & 0xffff)); | |
7639 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
7640 | State.regs[dstreg1] = result1; | |
7641 | } | |
7642 | ||
7643 | // 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2 | |
7644 | 8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp | |
7645 | "swhw_cmp" | |
7646 | *am33 | |
7647 | { | |
7648 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7649 | ||
7650 | PC = cia; | |
7651 | srcreg1 = translate_rreg (SD_, RM1); | |
7652 | srcreg2 = translate_rreg (SD_, RM2); | |
7653 | dstreg1 = translate_rreg (SD_, RN1); | |
7654 | dstreg2 = translate_rreg (SD_, RN2); | |
7655 | ||
7656 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); | |
7657 | State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16) | |
7658 | | ((State.regs[srcreg1] >> 16) & 0xffff)); | |
7659 | } | |
7660 | ||
7661 | // 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2 | |
7662 | 8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp | |
7663 | "swhw_cmp" | |
7664 | *am33 | |
7665 | { | |
7666 | int srcreg1, dstreg1, dstreg2; | |
7667 | ||
7668 | PC = cia; | |
7669 | srcreg1 = translate_rreg (SD_, RM1); | |
7670 | dstreg1 = translate_rreg (SD_, RN1); | |
7671 | dstreg2 = translate_rreg (SD_, RN2); | |
7672 | ||
7673 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); | |
7674 | State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16) | |
7675 | | ((State.regs[srcreg1] >> 16) & 0xffff)); | |
7676 | } | |
7677 | ||
7678 | // 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2 | |
7679 | 8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov | |
7680 | "swhw_mov" | |
7681 | *am33 | |
7682 | { | |
7683 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7684 | int result1; | |
7685 | ||
7686 | PC = cia; | |
7687 | srcreg1 = translate_rreg (SD_, RM1); | |
7688 | srcreg2 = translate_rreg (SD_, RM2); | |
7689 | dstreg1 = translate_rreg (SD_, RN1); | |
7690 | dstreg2 = translate_rreg (SD_, RN2); | |
7691 | ||
7692 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) | |
7693 | | ((State.regs[srcreg1] >> 16) & 0xffff)); | |
7694 | State.regs[dstreg2] = State.regs[srcreg2]; | |
7695 | State.regs[dstreg1] = result1; | |
7696 | } | |
7697 | ||
7698 | // 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2 | |
7699 | 8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov | |
7700 | "swhw_mov" | |
7701 | *am33 | |
7702 | { | |
7703 | int srcreg1, dstreg1, dstreg2; | |
7704 | int result1; | |
7705 | ||
7706 | PC = cia; | |
7707 | srcreg1 = translate_rreg (SD_, RM1); | |
7708 | dstreg1 = translate_rreg (SD_, RN1); | |
7709 | dstreg2 = translate_rreg (SD_, RN2); | |
7710 | ||
7711 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) | |
7712 | | ((State.regs[srcreg1] >> 16) & 0xffff)); | |
7713 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
7714 | State.regs[dstreg1] = result1; | |
7715 | } | |
7716 | ||
7717 | // 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2 | |
7718 | 8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr | |
7719 | "swhw_asr" | |
7720 | *am33 | |
7721 | { | |
7722 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7723 | int result1; | |
7724 | signed int temp; | |
7725 | ||
7726 | PC = cia; | |
7727 | srcreg1 = translate_rreg (SD_, RM1); | |
7728 | srcreg2 = translate_rreg (SD_, RM2); | |
7729 | dstreg1 = translate_rreg (SD_, RN1); | |
7730 | dstreg2 = translate_rreg (SD_, RN2); | |
7731 | ||
7732 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) | |
7733 | | ((State.regs[srcreg1] >> 16) & 0xffff)); | |
7734 | temp = State.regs[dstreg2]; | |
7735 | temp >>= State.regs[srcreg2]; | |
7736 | State.regs[dstreg2] = temp; | |
7737 | State.regs[dstreg1] = result1; | |
7738 | } | |
7739 | ||
7740 | // 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2 | |
7741 | 8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr | |
7742 | "swhw_asr" | |
7743 | *am33 | |
7744 | { | |
7745 | int srcreg1, dstreg1, dstreg2; | |
7746 | int result1; | |
7747 | signed int temp; | |
7748 | ||
7749 | PC = cia; | |
7750 | srcreg1 = translate_rreg (SD_, RM1); | |
7751 | dstreg1 = translate_rreg (SD_, RN1); | |
7752 | dstreg2 = translate_rreg (SD_, RN2); | |
7753 | ||
7754 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) | |
7755 | | ((State.regs[srcreg1] >> 16) & 0xffff)); | |
7756 | temp = State.regs[dstreg2]; | |
7757 | temp >>= IMM4; | |
7758 | State.regs[dstreg2] = temp; | |
7759 | State.regs[dstreg1] = result1; | |
7760 | } | |
7761 | ||
7762 | // 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2 | |
7763 | 8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr | |
7764 | "swhw_lsr" | |
7765 | *am33 | |
7766 | { | |
7767 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7768 | int result1; | |
7769 | ||
7770 | PC = cia; | |
7771 | srcreg1 = translate_rreg (SD_, RM1); | |
7772 | srcreg2 = translate_rreg (SD_, RM2); | |
7773 | dstreg1 = translate_rreg (SD_, RN1); | |
7774 | dstreg2 = translate_rreg (SD_, RN2); | |
7775 | ||
7776 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) | |
7777 | | ((State.regs[srcreg1] >> 16) & 0xffff)); | |
7778 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
7779 | State.regs[dstreg1] = result1; | |
7780 | } | |
7781 | ||
7782 | // 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2 | |
7783 | 8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr | |
7784 | "swhw_lsr" | |
7785 | *am33 | |
7786 | { | |
7787 | int srcreg1, dstreg1, dstreg2; | |
7788 | int result1; | |
c2d11a7d JM |
7789 | |
7790 | PC = cia; | |
7791 | srcreg1 = translate_rreg (SD_, RM1); | |
7792 | dstreg1 = translate_rreg (SD_, RN1); | |
7793 | dstreg2 = translate_rreg (SD_, RN2); | |
7794 | ||
7795 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) | |
7796 | | ((State.regs[srcreg1] >> 16) & 0xffff)); | |
7797 | State.regs[dstreg2] >>= IMM4; | |
7798 | State.regs[dstreg1] = result1; | |
7799 | } | |
7800 | ||
7801 | ||
7802 | // 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2 | |
7803 | 8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl | |
7804 | "swhw_asl" | |
7805 | *am33 | |
7806 | { | |
7807 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7808 | int result1; | |
7809 | ||
7810 | PC = cia; | |
7811 | srcreg1 = translate_rreg (SD_, RM1); | |
7812 | srcreg2 = translate_rreg (SD_, RM2); | |
7813 | dstreg1 = translate_rreg (SD_, RN1); | |
7814 | dstreg2 = translate_rreg (SD_, RN2); | |
7815 | ||
7816 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) | |
7817 | | ((State.regs[srcreg1] >> 16) & 0xffff)); | |
7818 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
7819 | State.regs[dstreg1] = result1; | |
7820 | } | |
7821 | ||
7822 | // 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2 | |
7823 | 8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl | |
7824 | "swhw_asl" | |
7825 | *am33 | |
7826 | { | |
7827 | int srcreg1, dstreg1, dstreg2; | |
7828 | int result1; | |
c2d11a7d JM |
7829 | |
7830 | PC = cia; | |
7831 | srcreg1 = translate_rreg (SD_, RM1); | |
7832 | dstreg1 = translate_rreg (SD_, RN1); | |
7833 | dstreg2 = translate_rreg (SD_, RN2); | |
7834 | ||
7835 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) | |
7836 | | ((State.regs[srcreg1] >> 16) & 0xffff)); | |
7837 | State.regs[dstreg2] <<= IMM4; | |
7838 | State.regs[dstreg1] = result1; | |
7839 | } | |
7840 | ||
7841 | // 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2 | |
7842 | 8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add | |
7843 | "or_add" | |
7844 | *am33 | |
7845 | { | |
7846 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7847 | int result1; | |
7848 | ||
7849 | PC = cia; | |
7850 | srcreg1 = translate_rreg (SD_, RM1); | |
7851 | srcreg2 = translate_rreg (SD_, RM2); | |
7852 | dstreg1 = translate_rreg (SD_, RN1); | |
7853 | dstreg2 = translate_rreg (SD_, RN2); | |
7854 | ||
7855 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; | |
7856 | State.regs[dstreg2] += State.regs[srcreg2]; | |
7857 | State.regs[dstreg1] = result1; | |
7858 | } | |
7859 | ||
7860 | // 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2 | |
7861 | 8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add | |
7862 | "or_add" | |
7863 | *am33 | |
7864 | { | |
7865 | int srcreg1, dstreg1, dstreg2; | |
7866 | int result1; | |
7867 | ||
7868 | PC = cia; | |
7869 | srcreg1 = translate_rreg (SD_, RM1); | |
7870 | dstreg1 = translate_rreg (SD_, RN1); | |
7871 | dstreg2 = translate_rreg (SD_, RN2); | |
7872 | ||
7873 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; | |
7874 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
7875 | State.regs[dstreg1] = result1; | |
7876 | } | |
7877 | ||
7878 | // 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2 | |
7879 | 8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub | |
7880 | "or_sub" | |
7881 | *am33 | |
7882 | { | |
7883 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7884 | int result1; | |
7885 | ||
7886 | PC = cia; | |
7887 | srcreg1 = translate_rreg (SD_, RM1); | |
7888 | srcreg2 = translate_rreg (SD_, RM2); | |
7889 | dstreg1 = translate_rreg (SD_, RN1); | |
7890 | dstreg2 = translate_rreg (SD_, RN2); | |
7891 | ||
7892 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; | |
7893 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
7894 | State.regs[dstreg1] = result1; | |
7895 | } | |
7896 | ||
7897 | // 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2 | |
7898 | 8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub | |
7899 | "or_sub" | |
7900 | *am33 | |
7901 | { | |
7902 | int srcreg1, dstreg1, dstreg2; | |
7903 | int result1; | |
7904 | ||
7905 | PC = cia; | |
7906 | srcreg1 = translate_rreg (SD_, RM1); | |
7907 | dstreg1 = translate_rreg (SD_, RN1); | |
7908 | dstreg2 = translate_rreg (SD_, RN2); | |
7909 | ||
7910 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; | |
7911 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
7912 | State.regs[dstreg1] = result1; | |
7913 | } | |
7914 | ||
7915 | // 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2 | |
7916 | 8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp | |
7917 | "or_cmp" | |
7918 | *am33 | |
7919 | { | |
7920 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7921 | ||
7922 | PC = cia; | |
7923 | srcreg1 = translate_rreg (SD_, RM1); | |
7924 | srcreg2 = translate_rreg (SD_, RM2); | |
7925 | dstreg1 = translate_rreg (SD_, RN1); | |
7926 | dstreg2 = translate_rreg (SD_, RN2); | |
7927 | ||
7928 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); | |
7929 | State.regs[dstreg1] |= State.regs[srcreg1]; | |
7930 | } | |
7931 | ||
7932 | // 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2 | |
7933 | 8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp | |
7934 | "or_cmp" | |
7935 | *am33 | |
7936 | { | |
7937 | int srcreg1, dstreg1, dstreg2; | |
7938 | ||
7939 | PC = cia; | |
7940 | srcreg1 = translate_rreg (SD_, RM1); | |
7941 | dstreg1 = translate_rreg (SD_, RN1); | |
7942 | dstreg2 = translate_rreg (SD_, RN2); | |
7943 | ||
7944 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); | |
7945 | State.regs[dstreg1] |= State.regs[srcreg1]; | |
7946 | } | |
7947 | ||
7948 | // 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2 | |
7949 | 8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov | |
7950 | "or_mov" | |
7951 | *am33 | |
7952 | { | |
7953 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7954 | int result1; | |
7955 | ||
7956 | PC = cia; | |
7957 | srcreg1 = translate_rreg (SD_, RM1); | |
7958 | srcreg2 = translate_rreg (SD_, RM2); | |
7959 | dstreg1 = translate_rreg (SD_, RN1); | |
7960 | dstreg2 = translate_rreg (SD_, RN2); | |
7961 | ||
7962 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; | |
7963 | State.regs[dstreg2] = State.regs[srcreg2]; | |
7964 | State.regs[dstreg1] = result1; | |
7965 | } | |
7966 | ||
7967 | // 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2 | |
7968 | 8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov | |
7969 | "or_mov" | |
7970 | *am33 | |
7971 | { | |
7972 | int srcreg1, dstreg1, dstreg2; | |
7973 | int result1; | |
7974 | ||
7975 | PC = cia; | |
7976 | srcreg1 = translate_rreg (SD_, RM1); | |
7977 | dstreg1 = translate_rreg (SD_, RN1); | |
7978 | dstreg2 = translate_rreg (SD_, RN2); | |
7979 | ||
7980 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; | |
7981 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
7982 | State.regs[dstreg1] = result1; | |
7983 | } | |
7984 | ||
7985 | // 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2 | |
7986 | 8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr | |
7987 | "or_asr" | |
7988 | *am33 | |
7989 | { | |
7990 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
7991 | int result1; | |
7992 | signed int temp; | |
7993 | ||
7994 | PC = cia; | |
7995 | srcreg1 = translate_rreg (SD_, RM1); | |
7996 | srcreg2 = translate_rreg (SD_, RM2); | |
7997 | dstreg1 = translate_rreg (SD_, RN1); | |
7998 | dstreg2 = translate_rreg (SD_, RN2); | |
7999 | ||
8000 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; | |
8001 | temp = State.regs[dstreg2]; | |
8002 | temp >>= State.regs[srcreg2]; | |
8003 | State.regs[dstreg2] = temp; | |
8004 | State.regs[dstreg1] = result1; | |
8005 | } | |
8006 | ||
8007 | // 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2 | |
8008 | 8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr | |
8009 | "or_asr" | |
8010 | *am33 | |
8011 | { | |
8012 | int srcreg1, dstreg1, dstreg2; | |
8013 | int result1; | |
8014 | signed int temp; | |
8015 | ||
8016 | PC = cia; | |
8017 | srcreg1 = translate_rreg (SD_, RM1); | |
8018 | dstreg1 = translate_rreg (SD_, RN1); | |
8019 | dstreg2 = translate_rreg (SD_, RN2); | |
8020 | ||
8021 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; | |
8022 | temp = State.regs[dstreg2]; | |
8023 | temp >>= IMM4; | |
8024 | State.regs[dstreg2] = temp; | |
8025 | State.regs[dstreg1] = result1; | |
8026 | } | |
8027 | ||
8028 | // 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2 | |
8029 | 8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr | |
8030 | "or_lsr" | |
8031 | *am33 | |
8032 | { | |
8033 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
8034 | int result1; | |
8035 | ||
8036 | PC = cia; | |
8037 | srcreg1 = translate_rreg (SD_, RM1); | |
8038 | srcreg2 = translate_rreg (SD_, RM2); | |
8039 | dstreg1 = translate_rreg (SD_, RN1); | |
8040 | dstreg2 = translate_rreg (SD_, RN2); | |
8041 | ||
8042 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; | |
8043 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
8044 | State.regs[dstreg1] = result1; | |
8045 | } | |
8046 | ||
8047 | // 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2 | |
8048 | 8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr | |
8049 | "or_lsr" | |
8050 | *am33 | |
8051 | { | |
8052 | int srcreg1, dstreg1, dstreg2; | |
8053 | int result1; | |
c2d11a7d JM |
8054 | |
8055 | PC = cia; | |
8056 | srcreg1 = translate_rreg (SD_, RM1); | |
8057 | dstreg1 = translate_rreg (SD_, RN1); | |
8058 | dstreg2 = translate_rreg (SD_, RN2); | |
8059 | ||
8060 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; | |
8061 | State.regs[dstreg2] >>= IMM4; | |
8062 | State.regs[dstreg1] = result1; | |
8063 | } | |
8064 | ||
8065 | ||
8066 | // 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2 | |
8067 | 8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl | |
8068 | "or_asl" | |
8069 | *am33 | |
8070 | { | |
8071 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
8072 | int result1; | |
8073 | ||
8074 | PC = cia; | |
8075 | srcreg1 = translate_rreg (SD_, RM1); | |
8076 | srcreg2 = translate_rreg (SD_, RM2); | |
8077 | dstreg1 = translate_rreg (SD_, RN1); | |
8078 | dstreg2 = translate_rreg (SD_, RN2); | |
8079 | ||
8080 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; | |
8081 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
8082 | State.regs[dstreg1] = result1; | |
8083 | } | |
8084 | ||
8085 | // 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2 | |
8086 | 8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl | |
8087 | "or_asl" | |
8088 | *am33 | |
8089 | { | |
8090 | int srcreg1, dstreg1, dstreg2; | |
8091 | int result1; | |
c2d11a7d JM |
8092 | |
8093 | PC = cia; | |
8094 | srcreg1 = translate_rreg (SD_, RM1); | |
8095 | dstreg1 = translate_rreg (SD_, RN1); | |
8096 | dstreg2 = translate_rreg (SD_, RN2); | |
8097 | ||
8098 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; | |
8099 | State.regs[dstreg2] <<= IMM4; | |
8100 | State.regs[dstreg1] = result1; | |
8101 | } | |
8102 | ||
8103 | // 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2 | |
8104 | 8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add | |
8105 | "sat16_add" | |
8106 | *am33 | |
8107 | { | |
8108 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
8109 | int result1; | |
8110 | ||
8111 | PC = cia; | |
8112 | srcreg1 = translate_rreg (SD_, RM1); | |
8113 | srcreg2 = translate_rreg (SD_, RM2); | |
8114 | dstreg1 = translate_rreg (SD_, RN1); | |
8115 | dstreg2 = translate_rreg (SD_, RN2); | |
8116 | ||
8117 | if (State.regs[srcreg1] >= 0x7fff) | |
8118 | result1 = 0x7fff; | |
8119 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8120 | result1 = 0xffff8000; | |
8121 | else | |
8122 | result1 = State.regs[srcreg1]; | |
8123 | ||
8124 | State.regs[dstreg2] += State.regs[srcreg2]; | |
8125 | State.regs[dstreg1] = result1; | |
8126 | } | |
8127 | ||
8128 | // 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2 | |
8129 | 8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add | |
8130 | "sat16_add" | |
8131 | *am33 | |
8132 | { | |
8133 | int srcreg1, dstreg1, dstreg2; | |
8134 | int result1; | |
8135 | ||
8136 | PC = cia; | |
8137 | srcreg1 = translate_rreg (SD_, RM1); | |
8138 | dstreg1 = translate_rreg (SD_, RN1); | |
8139 | dstreg2 = translate_rreg (SD_, RN2); | |
8140 | ||
8141 | if (State.regs[srcreg1] >= 0x7fff) | |
8142 | result1 = 0x7fff; | |
8143 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8144 | result1 = 0xffff8000; | |
8145 | else | |
8146 | result1 = State.regs[srcreg1]; | |
8147 | ||
8148 | State.regs[dstreg2] += EXTEND4 (IMM4); | |
8149 | State.regs[dstreg1] = result1; | |
8150 | } | |
8151 | ||
8152 | // 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2 | |
8153 | 8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub | |
8154 | "sat16_sub" | |
8155 | *am33 | |
8156 | { | |
8157 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
8158 | int result1; | |
8159 | ||
8160 | PC = cia; | |
8161 | srcreg1 = translate_rreg (SD_, RM1); | |
8162 | srcreg2 = translate_rreg (SD_, RM2); | |
8163 | dstreg1 = translate_rreg (SD_, RN1); | |
8164 | dstreg2 = translate_rreg (SD_, RN2); | |
8165 | ||
8166 | if (State.regs[srcreg1] >= 0x7fff) | |
8167 | result1 = 0x7fff; | |
8168 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8169 | result1 = 0xffff8000; | |
8170 | else | |
8171 | result1 = State.regs[srcreg1]; | |
8172 | ||
8173 | State.regs[dstreg2] -= State.regs[srcreg2]; | |
8174 | State.regs[dstreg1] = result1; | |
8175 | } | |
8176 | ||
8177 | // 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2 | |
8178 | 8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub | |
8179 | "sat16_sub" | |
8180 | *am33 | |
8181 | { | |
8182 | int srcreg1, dstreg1, dstreg2; | |
8183 | int result1; | |
8184 | ||
8185 | PC = cia; | |
8186 | srcreg1 = translate_rreg (SD_, RM1); | |
8187 | dstreg1 = translate_rreg (SD_, RN1); | |
8188 | dstreg2 = translate_rreg (SD_, RN2); | |
8189 | ||
8190 | if (State.regs[srcreg1] >= 0x7fff) | |
8191 | result1 = 0x7fff; | |
8192 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8193 | result1 = 0xffff8000; | |
8194 | else | |
8195 | result1 = State.regs[srcreg1]; | |
8196 | ||
8197 | State.regs[dstreg2] -= EXTEND4 (IMM4); | |
8198 | State.regs[dstreg1] = result1; | |
8199 | } | |
8200 | ||
8201 | // 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2 | |
8202 | 8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp | |
8203 | "sat16_cmp" | |
8204 | *am33 | |
8205 | { | |
8206 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
c2d11a7d JM |
8207 | |
8208 | PC = cia; | |
8209 | srcreg1 = translate_rreg (SD_, RM1); | |
8210 | srcreg2 = translate_rreg (SD_, RM2); | |
8211 | dstreg1 = translate_rreg (SD_, RN1); | |
8212 | dstreg2 = translate_rreg (SD_, RN2); | |
8213 | ||
5425ca99 | 8214 | genericCmp (State.regs[dstreg2], State.regs[dstreg1]); |
c2d11a7d JM |
8215 | if (State.regs[srcreg1] >= 0x7fff) |
8216 | State.regs[dstreg1] = 0x7fff; | |
8217 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8218 | State.regs[dstreg1] = 0xffff8000; | |
8219 | else | |
8220 | State.regs[dstreg1] = State.regs[srcreg1]; | |
8221 | } | |
8222 | ||
8223 | // 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2 | |
8224 | 8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp | |
8225 | "sat16_cmp" | |
8226 | *am33 | |
8227 | { | |
8228 | int srcreg1, dstreg1, dstreg2; | |
8229 | ||
8230 | PC = cia; | |
8231 | srcreg1 = translate_rreg (SD_, RM1); | |
8232 | dstreg1 = translate_rreg (SD_, RN1); | |
8233 | dstreg2 = translate_rreg (SD_, RN2); | |
8234 | ||
8235 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); | |
8236 | if (State.regs[srcreg1] >= 0x7fff) | |
8237 | State.regs[dstreg1] = 0x7fff; | |
8238 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8239 | State.regs[dstreg1] = 0xffff8000; | |
8240 | else | |
8241 | State.regs[dstreg1] = State.regs[srcreg1]; | |
8242 | } | |
8243 | ||
8244 | // 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2 | |
8245 | 8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov | |
8246 | "sat16_mov" | |
8247 | *am33 | |
8248 | { | |
8249 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
8250 | int result1; | |
8251 | ||
8252 | PC = cia; | |
8253 | srcreg1 = translate_rreg (SD_, RM1); | |
8254 | srcreg2 = translate_rreg (SD_, RM2); | |
8255 | dstreg1 = translate_rreg (SD_, RN1); | |
8256 | dstreg2 = translate_rreg (SD_, RN2); | |
8257 | ||
8258 | if (State.regs[srcreg1] >= 0x7fff) | |
8259 | result1 = 0x7fff; | |
8260 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8261 | result1 = 0xffff8000; | |
8262 | else | |
8263 | result1 = State.regs[srcreg1]; | |
8264 | ||
8265 | State.regs[dstreg2] = State.regs[srcreg2]; | |
8266 | State.regs[dstreg1] = result1; | |
8267 | } | |
8268 | ||
8269 | // 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2 | |
8270 | 8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov | |
8271 | "sat16_mov" | |
8272 | *am33 | |
8273 | { | |
8274 | int srcreg1, dstreg1, dstreg2; | |
8275 | int result1; | |
8276 | ||
8277 | PC = cia; | |
8278 | srcreg1 = translate_rreg (SD_, RM1); | |
8279 | dstreg1 = translate_rreg (SD_, RN1); | |
8280 | dstreg2 = translate_rreg (SD_, RN2); | |
8281 | ||
8282 | if (State.regs[srcreg1] >= 0x7fff) | |
8283 | result1 = 0x7fff; | |
8284 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8285 | result1 = 0xffff8000; | |
8286 | else | |
8287 | result1 = State.regs[srcreg1]; | |
8288 | ||
8289 | State.regs[dstreg2] = EXTEND4 (IMM4); | |
8290 | State.regs[dstreg1] = result1; | |
8291 | } | |
8292 | ||
8293 | // 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2 | |
8294 | 8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr | |
8295 | "sat16_asr" | |
8296 | *am33 | |
8297 | { | |
8298 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
8299 | int result1; | |
8300 | signed int temp; | |
8301 | ||
8302 | PC = cia; | |
8303 | srcreg1 = translate_rreg (SD_, RM1); | |
8304 | srcreg2 = translate_rreg (SD_, RM2); | |
8305 | dstreg1 = translate_rreg (SD_, RN1); | |
8306 | dstreg2 = translate_rreg (SD_, RN2); | |
8307 | ||
8308 | if (State.regs[srcreg1] >= 0x7fff) | |
8309 | result1 = 0x7fff; | |
8310 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8311 | result1 = 0xffff8000; | |
8312 | else | |
8313 | result1 = State.regs[srcreg1]; | |
8314 | ||
8315 | temp = State.regs[dstreg2]; | |
8316 | temp >>= State.regs[srcreg2]; | |
8317 | State.regs[dstreg2] = temp; | |
8318 | State.regs[dstreg1] = result1; | |
8319 | } | |
8320 | ||
8321 | // 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2 | |
8322 | 8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr | |
8323 | "sat16_asr" | |
8324 | *am33 | |
8325 | { | |
8326 | int srcreg1, dstreg1, dstreg2; | |
8327 | int result1; | |
8328 | signed int temp; | |
8329 | ||
8330 | PC = cia; | |
8331 | srcreg1 = translate_rreg (SD_, RM1); | |
8332 | dstreg1 = translate_rreg (SD_, RN1); | |
8333 | dstreg2 = translate_rreg (SD_, RN2); | |
8334 | ||
8335 | if (State.regs[srcreg1] >= 0x7fff) | |
8336 | result1 = 0x7fff; | |
8337 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8338 | result1 = 0xffff8000; | |
8339 | else | |
8340 | result1 = State.regs[srcreg1]; | |
8341 | ||
8342 | temp = State.regs[dstreg2]; | |
8343 | temp >>= IMM4; | |
8344 | State.regs[dstreg2] = temp; | |
8345 | State.regs[dstreg1] = result1; | |
8346 | } | |
8347 | ||
8348 | // 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2 | |
8349 | 8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr | |
8350 | "sat16_lsr" | |
8351 | *am33 | |
8352 | { | |
8353 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
8354 | int result1; | |
8355 | ||
8356 | PC = cia; | |
8357 | srcreg1 = translate_rreg (SD_, RM1); | |
8358 | srcreg2 = translate_rreg (SD_, RM2); | |
8359 | dstreg1 = translate_rreg (SD_, RN1); | |
8360 | dstreg2 = translate_rreg (SD_, RN2); | |
8361 | ||
8362 | if (State.regs[srcreg1] >= 0x7fff) | |
8363 | result1 = 0x7fff; | |
8364 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8365 | result1 = 0xffff8000; | |
8366 | else | |
8367 | result1 = State.regs[srcreg1]; | |
8368 | ||
8369 | State.regs[dstreg2] >>= State.regs[srcreg2]; | |
8370 | State.regs[dstreg1] = result1; | |
8371 | } | |
8372 | ||
8373 | // 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2 | |
8374 | 8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr | |
8375 | "sat16_lsr" | |
8376 | *am33 | |
8377 | { | |
8378 | int srcreg1, dstreg1, dstreg2; | |
8379 | int result1; | |
c2d11a7d JM |
8380 | |
8381 | PC = cia; | |
8382 | srcreg1 = translate_rreg (SD_, RM1); | |
8383 | dstreg1 = translate_rreg (SD_, RN1); | |
8384 | dstreg2 = translate_rreg (SD_, RN2); | |
8385 | ||
8386 | if (State.regs[srcreg1] >= 0x7fff) | |
8387 | result1 = 0x7fff; | |
8388 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8389 | result1 = 0xffff8000; | |
8390 | else | |
8391 | result1 = State.regs[srcreg1]; | |
8392 | ||
8393 | State.regs[dstreg2] >>= IMM4; | |
8394 | State.regs[dstreg1] = result1; | |
8395 | } | |
8396 | ||
8397 | ||
8398 | // 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2 | |
8399 | 8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl | |
8400 | "sat16_asl" | |
8401 | *am33 | |
8402 | { | |
8403 | int srcreg1, srcreg2, dstreg1, dstreg2; | |
8404 | int result1; | |
8405 | ||
8406 | PC = cia; | |
8407 | srcreg1 = translate_rreg (SD_, RM1); | |
8408 | srcreg2 = translate_rreg (SD_, RM2); | |
8409 | dstreg1 = translate_rreg (SD_, RN1); | |
8410 | dstreg2 = translate_rreg (SD_, RN2); | |
8411 | ||
8412 | if (State.regs[srcreg1] >= 0x7fff) | |
8413 | result1 = 0x7fff; | |
8414 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8415 | result1 = 0xffff8000; | |
8416 | else | |
8417 | result1 = State.regs[srcreg1]; | |
8418 | ||
8419 | State.regs[dstreg2] <<= State.regs[srcreg2]; | |
8420 | State.regs[dstreg1] = result1; | |
8421 | } | |
8422 | ||
8423 | // 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2 | |
8424 | 8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl | |
8425 | "sat16_asl" | |
8426 | *am33 | |
8427 | { | |
8428 | int srcreg1, dstreg1, dstreg2; | |
8429 | int result1; | |
c2d11a7d JM |
8430 | |
8431 | PC = cia; | |
8432 | srcreg1 = translate_rreg (SD_, RM1); | |
8433 | dstreg1 = translate_rreg (SD_, RN1); | |
8434 | dstreg2 = translate_rreg (SD_, RN2); | |
8435 | ||
8436 | if (State.regs[srcreg1] >= 0x7fff) | |
8437 | result1 = 0x7fff; | |
8438 | else if (State.regs[srcreg1] <= 0xffff8000) | |
8439 | result1 = 0xffff8000; | |
8440 | else | |
8441 | result1 = State.regs[srcreg1]; | |
8442 | ||
8443 | State.regs[dstreg2] <<= IMM4; | |
8444 | State.regs[dstreg1] = result1; | |
8445 | } | |
8446 | ||
8447 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn | |
8448 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt | |
8449 | "mov_llt" | |
8450 | *am33 | |
8451 | { | |
8452 | int srcreg, dstreg; | |
c2d11a7d JM |
8453 | |
8454 | PC = cia; | |
8455 | srcreg = translate_rreg (SD_, RM); | |
8456 | dstreg = translate_rreg (SD_, RN); | |
8457 | ||
8458 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
8459 | State.regs[srcreg] += EXTEND4 (IMM4); | |
8460 | ||
8461 | if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)) | |
8462 | { | |
8463 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
8464 | nia = PC; | |
8465 | } | |
c2d11a7d JM |
8466 | } |
8467 | ||
8468 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn | |
8469 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt | |
8470 | "mov_lgt" | |
8471 | *am33 | |
8472 | { | |
8473 | int srcreg, dstreg; | |
8474 | ||
8475 | PC = cia; | |
8476 | srcreg = translate_rreg (SD_, RM); | |
8477 | dstreg = translate_rreg (SD_, RN); | |
8478 | ||
8479 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
8480 | State.regs[srcreg] += EXTEND4 (IMM4); | |
8481 | ||
8482 | if (!((PSW & PSW_Z) | |
8483 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))) | |
8484 | { | |
8485 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
8486 | nia = PC; | |
8487 | } | |
8488 | } | |
8489 | ||
8490 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn | |
8491 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge | |
8492 | "mov_lge" | |
8493 | *am33 | |
8494 | { | |
8495 | int srcreg, dstreg; | |
8496 | ||
8497 | PC = cia; | |
8498 | srcreg = translate_rreg (SD_, RM); | |
8499 | dstreg = translate_rreg (SD_, RN); | |
8500 | ||
8501 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
8502 | State.regs[srcreg] += EXTEND4 (IMM4); | |
8503 | ||
8504 | if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) | |
8505 | { | |
8506 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
8507 | nia = PC; | |
8508 | } | |
8509 | } | |
8510 | ||
8511 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn | |
8512 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle | |
8513 | "mov_lle" | |
8514 | *am33 | |
8515 | { | |
8516 | int srcreg, dstreg; | |
8517 | ||
8518 | PC = cia; | |
8519 | srcreg = translate_rreg (SD_, RM); | |
8520 | dstreg = translate_rreg (SD_, RN); | |
8521 | ||
8522 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
8523 | State.regs[srcreg] += EXTEND4 (IMM4); | |
8524 | ||
8525 | if ((PSW & PSW_Z) | |
8526 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) | |
8527 | { | |
8528 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
8529 | nia = PC; | |
8530 | } | |
8531 | } | |
8532 | ||
8533 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn | |
8534 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs | |
8535 | "mov_lcs" | |
8536 | *am33 | |
8537 | { | |
8538 | int srcreg, dstreg; | |
8539 | ||
8540 | PC = cia; | |
8541 | srcreg = translate_rreg (SD_, RM); | |
8542 | dstreg = translate_rreg (SD_, RN); | |
8543 | ||
8544 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
8545 | State.regs[srcreg] += EXTEND4 (IMM4); | |
8546 | ||
8547 | if (PSW & PSW_C) | |
8548 | { | |
8549 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
8550 | nia = PC; | |
8551 | } | |
8552 | } | |
8553 | ||
8554 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn | |
8555 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi | |
8556 | "mov_lhi" | |
8557 | *am33 | |
8558 | { | |
8559 | int srcreg, dstreg; | |
8560 | ||
8561 | PC = cia; | |
8562 | srcreg = translate_rreg (SD_, RM); | |
8563 | dstreg = translate_rreg (SD_, RN); | |
8564 | ||
8565 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
8566 | State.regs[srcreg] += EXTEND4 (IMM4); | |
8567 | ||
8568 | if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)) | |
8569 | { | |
8570 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
8571 | nia = PC; | |
8572 | } | |
8573 | } | |
8574 | ||
8575 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn | |
8576 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc | |
8577 | "mov_lcc" | |
8578 | *am33 | |
8579 | { | |
8580 | int srcreg, dstreg; | |
8581 | ||
8582 | PC = cia; | |
8583 | srcreg = translate_rreg (SD_, RM); | |
8584 | dstreg = translate_rreg (SD_, RN); | |
8585 | ||
8586 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
8587 | State.regs[srcreg] += EXTEND4 (IMM4); | |
8588 | ||
8589 | if (!(PSW & PSW_C)) | |
8590 | { | |
8591 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
8592 | nia = PC; | |
8593 | } | |
8594 | } | |
8595 | ||
8596 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn | |
8597 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls | |
8598 | "mov_lls" | |
8599 | *am33 | |
8600 | { | |
8601 | int srcreg, dstreg; | |
8602 | ||
8603 | PC = cia; | |
8604 | srcreg = translate_rreg (SD_, RM); | |
8605 | dstreg = translate_rreg (SD_, RN); | |
8606 | ||
8607 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
8608 | State.regs[srcreg] += EXTEND4 (IMM4); | |
8609 | ||
8610 | if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0) | |
8611 | { | |
8612 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
8613 | nia = PC; | |
8614 | } | |
8615 | } | |
8616 | ||
8617 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn | |
8618 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq | |
8619 | "mov_leq" | |
8620 | *am33 | |
8621 | { | |
8622 | int srcreg, dstreg; | |
8623 | ||
8624 | PC = cia; | |
8625 | srcreg = translate_rreg (SD_, RM); | |
8626 | dstreg = translate_rreg (SD_, RN); | |
8627 | ||
8628 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
8629 | State.regs[srcreg] += EXTEND4 (IMM4); | |
8630 | ||
8631 | if (PSW & PSW_Z) | |
8632 | { | |
8633 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
8634 | nia = PC; | |
8635 | } | |
8636 | } | |
8637 | ||
8638 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn | |
8639 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne | |
8640 | "mov_lne" | |
8641 | *am33 | |
8642 | { | |
8643 | int srcreg, dstreg; | |
8644 | ||
8645 | PC = cia; | |
8646 | srcreg = translate_rreg (SD_, RM); | |
8647 | dstreg = translate_rreg (SD_, RN); | |
8648 | ||
8649 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
8650 | State.regs[srcreg] += EXTEND4 (IMM4); | |
8651 | ||
8652 | if (!(PSW & PSW_Z)) | |
8653 | { | |
8654 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
8655 | nia = PC; | |
8656 | } | |
8657 | } | |
8658 | ||
8659 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn | |
8660 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra | |
8661 | "mov_lra" | |
8662 | *am33 | |
8663 | { | |
8664 | int srcreg, dstreg; | |
8665 | ||
8666 | PC = cia; | |
8667 | srcreg = translate_rreg (SD_, RM); | |
8668 | dstreg = translate_rreg (SD_, RN); | |
8669 | ||
8670 | State.regs[dstreg] = load_word (State.regs[srcreg]); | |
8671 | State.regs[srcreg] += EXTEND4 (IMM4); | |
8672 | ||
8673 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
8674 | nia = PC; | |
8675 | } | |
ceec3559 | 8676 |