Commit | Line | Data |
---|---|---|
05ccbdfd | 1 | #include <signal.h> |
6274d39b JJ |
2 | |
3 | #if WITH_COMMON | |
4 | #include "sim-main.h" | |
e855e576 | 5 | #include "sim-options.h" |
6d133cc9 | 6 | /* start-sanitize-am30 */ |
6100784a | 7 | #include "sim-hw.h" |
6d133cc9 | 8 | /* end-sanitize-am30 */ |
6274d39b JJ |
9 | #else |
10 | #include "mn10300_sim.h" | |
11 | #endif | |
12 | ||
05ccbdfd JL |
13 | #include "sysdep.h" |
14 | #include "bfd.h" | |
6274d39b JJ |
15 | #include "sim-assert.h" |
16 | ||
17 | ||
18 | #ifdef HAVE_STDLIB_H | |
19 | #include <stdlib.h> | |
20 | #endif | |
21 | ||
22 | #ifdef HAVE_STRING_H | |
23 | #include <string.h> | |
24 | #else | |
25 | #ifdef HAVE_STRINGS_H | |
26 | #include <strings.h> | |
27 | #endif | |
28 | #endif | |
29 | ||
30 | #include "bfd.h" | |
31 | ||
32 | #ifndef INLINE | |
33 | #ifdef __GNUC__ | |
34 | #define INLINE inline | |
35 | #else | |
36 | #define INLINE | |
37 | #endif | |
38 | #endif | |
05ccbdfd | 39 | |
05ccbdfd | 40 | |
05ccbdfd JL |
41 | host_callback *mn10300_callback; |
42 | int mn10300_debug; | |
43 | ||
6adf5185 JJ |
44 | |
45 | /* simulation target board. NULL=default configuration */ | |
46 | static char* board = NULL; | |
47 | ||
48 | static DECLARE_OPTION_HANDLER (mn10300_option_handler); | |
49 | ||
50 | enum { | |
51 | OPTION_BOARD = OPTION_START, | |
52 | }; | |
53 | ||
54 | static SIM_RC | |
55 | mn10300_option_handler (sd, cpu, opt, arg, is_command) | |
56 | SIM_DESC sd; | |
57 | sim_cpu *cpu; | |
58 | int opt; | |
59 | char *arg; | |
60 | int is_command; | |
61 | { | |
62 | int cpu_nr; | |
63 | switch (opt) | |
64 | { | |
65 | case OPTION_BOARD: | |
66 | { | |
67 | if (arg) | |
68 | { | |
69 | board = zalloc(strlen(arg) + 1); | |
70 | strcpy(board, arg); | |
71 | } | |
72 | return SIM_RC_OK; | |
73 | } | |
74 | } | |
75 | ||
76 | return SIM_RC_OK; | |
77 | } | |
78 | ||
79 | static const OPTION mn10300_options[] = | |
80 | { | |
81 | /* start-sanitize-am30 */ | |
82 | #define BOARD_AM32 "am32" | |
83 | { {"board", required_argument, NULL, OPTION_BOARD}, | |
84 | '\0', "none" /* rely on compile-time string concatenation for other options */ | |
85 | "|" BOARD_AM32 | |
86 | , "Customize simulation for a particular board.", mn10300_option_handler }, | |
87 | /* end-sanitize-am30 */ | |
88 | ||
89 | { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } | |
90 | }; | |
91 | ||
6274d39b JJ |
92 | #if WITH_COMMON |
93 | #else | |
baa83bcc | 94 | static void dispatch PARAMS ((uint32, uint32, int)); |
05ccbdfd JL |
95 | static long hash PARAMS ((long)); |
96 | static void init_system PARAMS ((void)); | |
e855e576 AC |
97 | |
98 | static SIM_OPEN_KIND sim_kind; | |
99 | static char *myname; | |
baa83bcc | 100 | #define MAX_HASH 127 |
05ccbdfd JL |
101 | |
102 | struct hash_entry | |
103 | { | |
104 | struct hash_entry *next; | |
105 | long opcode; | |
106 | long mask; | |
107 | struct simops *ops; | |
baa83bcc JL |
108 | #ifdef HASH_STAT |
109 | unsigned long count; | |
110 | #endif | |
05ccbdfd JL |
111 | }; |
112 | ||
234a9a49 | 113 | static int max_mem = 0; |
05ccbdfd JL |
114 | struct hash_entry hash_table[MAX_HASH+1]; |
115 | ||
116 | ||
d2523010 JL |
117 | /* This probably doesn't do a very good job at bucket filling, but |
118 | it's simple... */ | |
05ccbdfd JL |
119 | static INLINE long |
120 | hash(insn) | |
121 | long insn; | |
122 | { | |
baa83bcc JL |
123 | /* These are one byte insns, we special case these since, in theory, |
124 | they should be the most heavily used. */ | |
d2523010 JL |
125 | if ((insn & 0xffffff00) == 0) |
126 | { | |
baa83bcc JL |
127 | switch (insn & 0xf0) |
128 | { | |
129 | case 0x00: | |
130 | return 0x70; | |
131 | ||
132 | case 0x40: | |
133 | return 0x71; | |
134 | ||
135 | case 0x10: | |
136 | return 0x72; | |
137 | ||
138 | case 0x30: | |
139 | return 0x73; | |
140 | ||
141 | case 0x50: | |
142 | return 0x74; | |
143 | ||
144 | case 0x60: | |
145 | return 0x75; | |
146 | ||
147 | case 0x70: | |
148 | return 0x76; | |
149 | ||
150 | case 0x80: | |
151 | return 0x77; | |
152 | ||
153 | case 0x90: | |
154 | return 0x78; | |
155 | ||
156 | case 0xa0: | |
157 | return 0x79; | |
158 | ||
159 | case 0xb0: | |
160 | return 0x7a; | |
161 | ||
162 | case 0xe0: | |
163 | return 0x7b; | |
164 | ||
165 | default: | |
166 | return 0x7c; | |
167 | } | |
d2523010 JL |
168 | } |
169 | ||
170 | /* These are two byte insns */ | |
171 | if ((insn & 0xffff0000) == 0) | |
172 | { | |
173 | if ((insn & 0xf000) == 0x2000 | |
174 | || (insn & 0xf000) == 0x5000) | |
baa83bcc | 175 | return ((insn & 0xfc00) >> 8) & 0x7f; |
d2523010 JL |
176 | |
177 | if ((insn & 0xf000) == 0x4000) | |
baa83bcc | 178 | return ((insn & 0xf300) >> 8) & 0x7f; |
d2523010 JL |
179 | |
180 | if ((insn & 0xf000) == 0x8000 | |
181 | || (insn & 0xf000) == 0x9000 | |
182 | || (insn & 0xf000) == 0xa000 | |
183 | || (insn & 0xf000) == 0xb000) | |
baa83bcc JL |
184 | return ((insn & 0xf000) >> 8) & 0x7f; |
185 | ||
186 | if ((insn & 0xff00) == 0xf000 | |
187 | || (insn & 0xff00) == 0xf100 | |
188 | || (insn & 0xff00) == 0xf200 | |
189 | || (insn & 0xff00) == 0xf500 | |
190 | || (insn & 0xff00) == 0xf600) | |
191 | return ((insn & 0xfff0) >> 4) & 0x7f; | |
192 | ||
193 | if ((insn & 0xf000) == 0xc000) | |
194 | return ((insn & 0xff00) >> 8) & 0x7f; | |
195 | ||
196 | return ((insn & 0xffc0) >> 6) & 0x7f; | |
d2523010 JL |
197 | } |
198 | ||
199 | /* These are three byte insns. */ | |
200 | if ((insn & 0xff000000) == 0) | |
201 | { | |
202 | if ((insn & 0xf00000) == 0x000000) | |
baa83bcc | 203 | return ((insn & 0xf30000) >> 16) & 0x7f; |
d2523010 JL |
204 | |
205 | if ((insn & 0xf00000) == 0x200000 | |
206 | || (insn & 0xf00000) == 0x300000) | |
baa83bcc JL |
207 | return ((insn & 0xfc0000) >> 16) & 0x7f; |
208 | ||
209 | if ((insn & 0xff0000) == 0xf80000) | |
210 | return ((insn & 0xfff000) >> 12) & 0x7f; | |
d2523010 | 211 | |
baa83bcc JL |
212 | if ((insn & 0xff0000) == 0xf90000) |
213 | return ((insn & 0xfffc00) >> 10) & 0x7f; | |
214 | ||
215 | return ((insn & 0xff0000) >> 16) & 0x7f; | |
d2523010 JL |
216 | } |
217 | ||
218 | /* These are four byte or larger insns. */ | |
baa83bcc JL |
219 | if ((insn & 0xf0000000) == 0xf0000000) |
220 | return ((insn & 0xfff00000) >> 20) & 0x7f; | |
221 | ||
222 | return ((insn & 0xff000000) >> 24) & 0x7f; | |
05ccbdfd JL |
223 | } |
224 | ||
4df7aeb3 | 225 | static INLINE void |
baa83bcc JL |
226 | dispatch (insn, extension, length) |
227 | uint32 insn; | |
228 | uint32 extension; | |
d2523010 | 229 | int length; |
05ccbdfd JL |
230 | { |
231 | struct hash_entry *h; | |
232 | ||
baa83bcc | 233 | h = &hash_table[hash(insn)]; |
05ccbdfd | 234 | |
baa83bcc JL |
235 | while ((insn & h->mask) != h->opcode |
236 | || (length != h->ops->length)) | |
05ccbdfd | 237 | { |
baa83bcc | 238 | if (!h->next) |
05ccbdfd | 239 | { |
baa83bcc JL |
240 | (*mn10300_callback->printf_filtered) (mn10300_callback, |
241 | "ERROR looking up hash for 0x%x, PC=0x%x\n", insn, PC); | |
05ccbdfd JL |
242 | exit(1); |
243 | } | |
244 | h = h->next; | |
245 | } | |
baa83bcc JL |
246 | |
247 | ||
248 | #ifdef HASH_STAT | |
249 | h->count++; | |
250 | #endif | |
251 | ||
252 | /* Now call the right function. */ | |
253 | (h->ops->func)(insn, extension); | |
254 | PC += length; | |
05ccbdfd JL |
255 | } |
256 | ||
05ccbdfd JL |
257 | void |
258 | sim_size (power) | |
259 | int power; | |
260 | ||
261 | { | |
262 | if (State.mem) | |
263 | free (State.mem); | |
264 | ||
234a9a49 | 265 | max_mem = 1 << power; |
05ccbdfd JL |
266 | State.mem = (uint8 *) calloc (1, 1 << power); |
267 | if (!State.mem) | |
268 | { | |
269 | (*mn10300_callback->printf_filtered) (mn10300_callback, "Allocation of main memory failed.\n"); | |
270 | exit (1); | |
271 | } | |
272 | } | |
273 | ||
274 | static void | |
275 | init_system () | |
276 | { | |
277 | if (!State.mem) | |
6cc6987e | 278 | sim_size(19); |
05ccbdfd JL |
279 | } |
280 | ||
281 | int | |
6cc6987e DE |
282 | sim_write (sd, addr, buffer, size) |
283 | SIM_DESC sd; | |
05ccbdfd JL |
284 | SIM_ADDR addr; |
285 | unsigned char *buffer; | |
286 | int size; | |
287 | { | |
288 | int i; | |
289 | ||
290 | init_system (); | |
291 | ||
292 | for (i = 0; i < size; i++) | |
003c91be | 293 | store_byte (addr + i, buffer[i]); |
05ccbdfd JL |
294 | |
295 | return size; | |
296 | } | |
297 | ||
b07a1e78 JL |
298 | /* Compare two opcode table entries for qsort. */ |
299 | static int | |
300 | compare_simops (arg1, arg2) | |
301 | const PTR arg1; | |
302 | const PTR arg2; | |
303 | { | |
304 | unsigned long code1 = ((struct simops *)arg1)->opcode; | |
305 | unsigned long code2 = ((struct simops *)arg2)->opcode; | |
306 | ||
307 | if (code1 < code2) | |
308 | return -1; | |
309 | if (code2 < code1) | |
310 | return 1; | |
311 | return 0; | |
312 | } | |
313 | ||
6cc6987e | 314 | SIM_DESC |
247fccde | 315 | sim_open (kind, cb, abfd, argv) |
6cc6987e | 316 | SIM_OPEN_KIND kind; |
003c91be | 317 | host_callback *cb; |
247fccde | 318 | struct _bfd *abfd; |
6cc6987e | 319 | char **argv; |
05ccbdfd JL |
320 | { |
321 | struct simops *s; | |
322 | struct hash_entry *h; | |
6cc6987e | 323 | char **p; |
b07a1e78 JL |
324 | int i; |
325 | ||
003c91be JL |
326 | mn10300_callback = cb; |
327 | ||
b07a1e78 JL |
328 | /* Sort the opcode array from smallest opcode to largest. |
329 | This will generally improve simulator performance as the smaller | |
330 | opcodes are generally preferred to the larger opcodes. */ | |
331 | for (i = 0, s = Simops; s->func; s++, i++) | |
332 | ; | |
333 | qsort (Simops, i, sizeof (Simops[0]), compare_simops); | |
6cc6987e DE |
334 | |
335 | sim_kind = kind; | |
336 | myname = argv[0]; | |
337 | ||
338 | for (p = argv + 1; *p; ++p) | |
05ccbdfd | 339 | { |
6cc6987e DE |
340 | if (strcmp (*p, "-E") == 0) |
341 | ++p; /* ignore endian spec */ | |
342 | else | |
05ccbdfd | 343 | #ifdef DEBUG |
6cc6987e | 344 | if (strcmp (*p, "-t") == 0) |
05ccbdfd JL |
345 | mn10300_debug = DEBUG; |
346 | else | |
347 | #endif | |
6cc6987e | 348 | (*mn10300_callback->printf_filtered) (mn10300_callback, "ERROR: unsupported option(s): %s\n",*p); |
05ccbdfd JL |
349 | } |
350 | ||
baa83bcc | 351 | /* put all the opcodes in the hash table */ |
05ccbdfd JL |
352 | for (s = Simops; s->func; s++) |
353 | { | |
354 | h = &hash_table[hash(s->opcode)]; | |
baa83bcc | 355 | |
05ccbdfd JL |
356 | /* go to the last entry in the chain */ |
357 | while (h->next) | |
baa83bcc JL |
358 | { |
359 | /* Don't insert the same opcode more than once. */ | |
360 | if (h->opcode == s->opcode | |
361 | && h->mask == s->mask | |
362 | && h->ops == s) | |
247fccde | 363 | break; |
baa83bcc JL |
364 | else |
365 | h = h->next; | |
366 | } | |
367 | ||
368 | /* Don't insert the same opcode more than once. */ | |
369 | if (h->opcode == s->opcode | |
370 | && h->mask == s->mask | |
371 | && h->ops == s) | |
372 | continue; | |
05ccbdfd JL |
373 | |
374 | if (h->ops) | |
375 | { | |
376 | h->next = calloc(1,sizeof(struct hash_entry)); | |
377 | h = h->next; | |
378 | } | |
379 | h->ops = s; | |
380 | h->mask = s->mask; | |
381 | h->opcode = s->opcode; | |
baa83bcc JL |
382 | #if HASH_STAT |
383 | h->count = 0; | |
384 | #endif | |
05ccbdfd | 385 | } |
6cc6987e | 386 | |
baa83bcc | 387 | |
6cc6987e DE |
388 | /* fudge our descriptor for now */ |
389 | return (SIM_DESC) 1; | |
05ccbdfd JL |
390 | } |
391 | ||
392 | ||
393 | void | |
6cc6987e DE |
394 | sim_close (sd, quitting) |
395 | SIM_DESC sd; | |
05ccbdfd JL |
396 | int quitting; |
397 | { | |
398 | /* nothing to do */ | |
399 | } | |
400 | ||
401 | void | |
402 | sim_set_profile (n) | |
403 | int n; | |
404 | { | |
405 | (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile %d\n", n); | |
406 | } | |
407 | ||
408 | void | |
409 | sim_set_profile_size (n) | |
410 | int n; | |
411 | { | |
412 | (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile_size %d\n", n); | |
413 | } | |
414 | ||
baa83bcc JL |
415 | int |
416 | sim_stop (sd) | |
417 | SIM_DESC sd; | |
418 | { | |
419 | return 0; | |
420 | } | |
421 | ||
05ccbdfd | 422 | void |
6cc6987e DE |
423 | sim_resume (sd, step, siggnal) |
424 | SIM_DESC sd; | |
05ccbdfd JL |
425 | int step, siggnal; |
426 | { | |
7c52bf32 | 427 | uint32 inst; |
05ccbdfd | 428 | reg_t oldpc; |
d2523010 | 429 | struct hash_entry *h; |
05ccbdfd JL |
430 | |
431 | if (step) | |
432 | State.exception = SIGTRAP; | |
433 | else | |
434 | State.exception = 0; | |
435 | ||
247fccde AC |
436 | State.exited = 0; |
437 | ||
05ccbdfd JL |
438 | do |
439 | { | |
d2523010 JL |
440 | unsigned long insn, extension; |
441 | ||
05ccbdfd | 442 | /* Fetch the current instruction. */ |
baa83bcc | 443 | inst = load_mem_big (PC, 2); |
05ccbdfd | 444 | oldpc = PC; |
05ccbdfd | 445 | |
baa83bcc JL |
446 | /* Using a giant case statement may seem like a waste because of the |
447 | code/rodata size the table itself will consume. However, using | |
448 | a giant case statement speeds up the simulator by 10-15% by avoiding | |
449 | cascading if/else statements or cascading case statements. */ | |
d2523010 | 450 | |
baa83bcc | 451 | switch ((inst >> 8) & 0xff) |
d2523010 | 452 | { |
baa83bcc JL |
453 | /* All the single byte insns except 0x80, 0x90, 0xa0, 0xb0 |
454 | which must be handled specially. */ | |
455 | case 0x00: | |
456 | case 0x04: | |
457 | case 0x08: | |
458 | case 0x0c: | |
09e142d5 | 459 | case 0x10: |
baa83bcc JL |
460 | case 0x11: |
461 | case 0x12: | |
462 | case 0x13: | |
463 | case 0x14: | |
464 | case 0x15: | |
465 | case 0x16: | |
466 | case 0x17: | |
467 | case 0x18: | |
468 | case 0x19: | |
469 | case 0x1a: | |
470 | case 0x1b: | |
471 | case 0x1c: | |
472 | case 0x1d: | |
473 | case 0x1e: | |
474 | case 0x1f: | |
475 | case 0x3c: | |
476 | case 0x3d: | |
477 | case 0x3e: | |
478 | case 0x3f: | |
479 | case 0x40: | |
480 | case 0x41: | |
481 | case 0x44: | |
482 | case 0x45: | |
483 | case 0x48: | |
484 | case 0x49: | |
485 | case 0x4c: | |
486 | case 0x4d: | |
487 | case 0x50: | |
488 | case 0x51: | |
489 | case 0x52: | |
490 | case 0x53: | |
491 | case 0x54: | |
492 | case 0x55: | |
493 | case 0x56: | |
494 | case 0x57: | |
495 | case 0x60: | |
496 | case 0x61: | |
497 | case 0x62: | |
498 | case 0x63: | |
499 | case 0x64: | |
500 | case 0x65: | |
501 | case 0x66: | |
502 | case 0x67: | |
503 | case 0x68: | |
504 | case 0x69: | |
505 | case 0x6a: | |
506 | case 0x6b: | |
507 | case 0x6c: | |
508 | case 0x6d: | |
509 | case 0x6e: | |
510 | case 0x6f: | |
511 | case 0x70: | |
512 | case 0x71: | |
513 | case 0x72: | |
514 | case 0x73: | |
515 | case 0x74: | |
516 | case 0x75: | |
517 | case 0x76: | |
518 | case 0x77: | |
519 | case 0x78: | |
520 | case 0x79: | |
521 | case 0x7a: | |
522 | case 0x7b: | |
523 | case 0x7c: | |
524 | case 0x7d: | |
525 | case 0x7e: | |
526 | case 0x7f: | |
527 | case 0xcb: | |
528 | case 0xd0: | |
529 | case 0xd1: | |
530 | case 0xd2: | |
531 | case 0xd3: | |
532 | case 0xd4: | |
533 | case 0xd5: | |
534 | case 0xd6: | |
535 | case 0xd7: | |
536 | case 0xd8: | |
537 | case 0xd9: | |
538 | case 0xda: | |
539 | case 0xdb: | |
540 | case 0xe0: | |
541 | case 0xe1: | |
542 | case 0xe2: | |
543 | case 0xe3: | |
544 | case 0xe4: | |
545 | case 0xe5: | |
546 | case 0xe6: | |
547 | case 0xe7: | |
548 | case 0xe8: | |
549 | case 0xe9: | |
550 | case 0xea: | |
551 | case 0xeb: | |
552 | case 0xec: | |
553 | case 0xed: | |
554 | case 0xee: | |
555 | case 0xef: | |
556 | case 0xff: | |
557 | insn = (inst >> 8) & 0xff; | |
558 | extension = 0; | |
559 | dispatch (insn, extension, 1); | |
560 | break; | |
561 | ||
562 | /* Special cases where dm == dn is used to encode a different | |
563 | instruction. */ | |
564 | case 0x80: | |
565 | case 0x85: | |
566 | case 0x8a: | |
567 | case 0x8f: | |
568 | case 0x90: | |
569 | case 0x95: | |
570 | case 0x9a: | |
571 | case 0x9f: | |
572 | case 0xa0: | |
573 | case 0xa5: | |
574 | case 0xaa: | |
575 | case 0xaf: | |
576 | case 0xb0: | |
577 | case 0xb5: | |
578 | case 0xba: | |
579 | case 0xbf: | |
580 | insn = inst; | |
581 | extension = 0; | |
582 | dispatch (insn, extension, 2); | |
583 | break; | |
584 | ||
585 | case 0x81: | |
586 | case 0x82: | |
587 | case 0x83: | |
588 | case 0x84: | |
589 | case 0x86: | |
590 | case 0x87: | |
591 | case 0x88: | |
592 | case 0x89: | |
593 | case 0x8b: | |
594 | case 0x8c: | |
595 | case 0x8d: | |
596 | case 0x8e: | |
597 | case 0x91: | |
598 | case 0x92: | |
599 | case 0x93: | |
600 | case 0x94: | |
601 | case 0x96: | |
602 | case 0x97: | |
603 | case 0x98: | |
604 | case 0x99: | |
605 | case 0x9b: | |
606 | case 0x9c: | |
607 | case 0x9d: | |
608 | case 0x9e: | |
609 | case 0xa1: | |
610 | case 0xa2: | |
611 | case 0xa3: | |
612 | case 0xa4: | |
613 | case 0xa6: | |
614 | case 0xa7: | |
615 | case 0xa8: | |
616 | case 0xa9: | |
617 | case 0xab: | |
618 | case 0xac: | |
619 | case 0xad: | |
620 | case 0xae: | |
621 | case 0xb1: | |
622 | case 0xb2: | |
623 | case 0xb3: | |
624 | case 0xb4: | |
625 | case 0xb6: | |
626 | case 0xb7: | |
627 | case 0xb8: | |
628 | case 0xb9: | |
629 | case 0xbb: | |
630 | case 0xbc: | |
631 | case 0xbd: | |
632 | case 0xbe: | |
633 | insn = (inst >> 8) & 0xff; | |
634 | extension = 0; | |
635 | dispatch (insn, extension, 1); | |
636 | break; | |
637 | ||
638 | /* The two byte instructions. */ | |
639 | case 0x20: | |
640 | case 0x21: | |
641 | case 0x22: | |
642 | case 0x23: | |
643 | case 0x28: | |
644 | case 0x29: | |
645 | case 0x2a: | |
646 | case 0x2b: | |
647 | case 0x42: | |
648 | case 0x43: | |
649 | case 0x46: | |
650 | case 0x47: | |
651 | case 0x4a: | |
652 | case 0x4b: | |
653 | case 0x4e: | |
654 | case 0x4f: | |
655 | case 0x58: | |
656 | case 0x59: | |
657 | case 0x5a: | |
658 | case 0x5b: | |
659 | case 0x5c: | |
660 | case 0x5d: | |
661 | case 0x5e: | |
662 | case 0x5f: | |
663 | case 0xc0: | |
664 | case 0xc1: | |
665 | case 0xc2: | |
666 | case 0xc3: | |
667 | case 0xc4: | |
668 | case 0xc5: | |
669 | case 0xc6: | |
670 | case 0xc7: | |
671 | case 0xc8: | |
672 | case 0xc9: | |
673 | case 0xca: | |
674 | case 0xce: | |
675 | case 0xcf: | |
676 | case 0xf0: | |
677 | case 0xf1: | |
678 | case 0xf2: | |
679 | case 0xf3: | |
680 | case 0xf4: | |
681 | case 0xf5: | |
682 | case 0xf6: | |
683 | insn = inst; | |
684 | extension = 0; | |
685 | dispatch (insn, extension, 2); | |
686 | break; | |
687 | ||
688 | /* The three byte insns with a 16bit operand in little endian | |
689 | format. */ | |
690 | case 0x01: | |
691 | case 0x02: | |
692 | case 0x03: | |
693 | case 0x05: | |
694 | case 0x06: | |
695 | case 0x07: | |
696 | case 0x09: | |
697 | case 0x0a: | |
698 | case 0x0b: | |
699 | case 0x0d: | |
700 | case 0x0e: | |
701 | case 0x0f: | |
702 | case 0x24: | |
703 | case 0x25: | |
704 | case 0x26: | |
705 | case 0x27: | |
706 | case 0x2c: | |
707 | case 0x2d: | |
708 | case 0x2e: | |
709 | case 0x2f: | |
710 | case 0x30: | |
711 | case 0x31: | |
712 | case 0x32: | |
713 | case 0x33: | |
714 | case 0x34: | |
715 | case 0x35: | |
716 | case 0x36: | |
717 | case 0x37: | |
718 | case 0x38: | |
719 | case 0x39: | |
720 | case 0x3a: | |
721 | case 0x3b: | |
722 | case 0xcc: | |
003c91be | 723 | insn = load_byte (PC); |
baa83bcc | 724 | insn <<= 16; |
003c91be | 725 | insn |= load_half (PC + 1); |
baa83bcc JL |
726 | extension = 0; |
727 | dispatch (insn, extension, 3); | |
728 | break; | |
729 | ||
730 | /* The three byte insns without 16bit operand. */ | |
731 | case 0xde: | |
732 | case 0xdf: | |
733 | case 0xf8: | |
734 | case 0xf9: | |
735 | insn = load_mem_big (PC, 3); | |
736 | extension = 0; | |
737 | dispatch (insn, extension, 3); | |
738 | break; | |
739 | ||
740 | /* Four byte insns. */ | |
741 | case 0xfa: | |
742 | case 0xfb: | |
743 | if ((inst & 0xfffc) == 0xfaf0 | |
744 | || (inst & 0xfffc) == 0xfaf4 | |
745 | || (inst & 0xfffc) == 0xfaf8) | |
746 | insn = load_mem_big (PC, 4); | |
747 | else | |
748 | { | |
749 | insn = inst; | |
750 | insn <<= 16; | |
003c91be | 751 | insn |= load_half (PC + 2); |
baa83bcc JL |
752 | extension = 0; |
753 | } | |
754 | dispatch (insn, extension, 4); | |
755 | break; | |
756 | ||
757 | /* Five byte insns. */ | |
758 | case 0xcd: | |
003c91be | 759 | insn = load_byte (PC); |
baa83bcc | 760 | insn <<= 24; |
003c91be JL |
761 | insn |= (load_half (PC + 1) << 8); |
762 | insn |= load_byte (PC + 3); | |
763 | extension = load_byte (PC + 4); | |
baa83bcc JL |
764 | dispatch (insn, extension, 5); |
765 | break; | |
766 | ||
767 | case 0xdc: | |
003c91be | 768 | insn = load_byte (PC); |
baa83bcc | 769 | insn <<= 24; |
003c91be | 770 | extension = load_word (PC + 1); |
baa83bcc JL |
771 | insn |= (extension & 0xffffff00) >> 8; |
772 | extension &= 0xff; | |
773 | dispatch (insn, extension, 5); | |
774 | break; | |
775 | ||
776 | /* Six byte insns. */ | |
777 | case 0xfc: | |
778 | case 0xfd: | |
779 | insn = (inst << 16); | |
003c91be | 780 | extension = load_word (PC + 2); |
baa83bcc JL |
781 | insn |= ((extension & 0xffff0000) >> 16); |
782 | extension &= 0xffff; | |
783 | dispatch (insn, extension, 6); | |
784 | break; | |
785 | ||
786 | case 0xdd: | |
003c91be JL |
787 | insn = load_byte (PC) << 24; |
788 | extension = load_word (PC + 1); | |
baa83bcc JL |
789 | insn |= ((extension >> 8) & 0xffffff); |
790 | extension = (extension & 0xff) << 16; | |
003c91be JL |
791 | extension |= load_byte (PC + 5) << 8; |
792 | extension |= load_byte (PC + 6); | |
baa83bcc JL |
793 | dispatch (insn, extension, 7); |
794 | break; | |
795 | ||
796 | case 0xfe: | |
797 | insn = inst << 16; | |
003c91be | 798 | extension = load_word (PC + 2); |
baa83bcc JL |
799 | insn |= ((extension >> 16) & 0xffff); |
800 | extension <<= 8; | |
801 | extension &= 0xffff00; | |
003c91be | 802 | extension |= load_byte (PC + 6); |
baa83bcc JL |
803 | dispatch (insn, extension, 7); |
804 | break; | |
805 | ||
806 | default: | |
807 | abort (); | |
05ccbdfd JL |
808 | } |
809 | } | |
810 | while (!State.exception); | |
baa83bcc JL |
811 | |
812 | #ifdef HASH_STAT | |
813 | { | |
814 | int i; | |
815 | for (i = 0; i < MAX_HASH; i++) | |
816 | { | |
817 | struct hash_entry *h; | |
818 | h = &hash_table[i]; | |
819 | ||
820 | printf("hash 0x%x:\n", i); | |
821 | ||
822 | while (h) | |
823 | { | |
824 | printf("h->opcode = 0x%x, count = 0x%x\n", h->opcode, h->count); | |
825 | h = h->next; | |
826 | } | |
827 | ||
828 | printf("\n\n"); | |
829 | } | |
830 | fflush (stdout); | |
831 | } | |
832 | #endif | |
833 | ||
05ccbdfd JL |
834 | } |
835 | ||
836 | int | |
6cc6987e DE |
837 | sim_trace (sd) |
838 | SIM_DESC sd; | |
05ccbdfd JL |
839 | { |
840 | #ifdef DEBUG | |
841 | mn10300_debug = DEBUG; | |
842 | #endif | |
6cc6987e | 843 | sim_resume (sd, 0, 0); |
05ccbdfd JL |
844 | return 1; |
845 | } | |
846 | ||
847 | void | |
6cc6987e DE |
848 | sim_info (sd, verbose) |
849 | SIM_DESC sd; | |
05ccbdfd JL |
850 | int verbose; |
851 | { | |
852 | (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_info\n"); | |
853 | } | |
854 | ||
6cc6987e | 855 | SIM_RC |
6274d39b | 856 | sim_create_inferior (sd, abfd, argv, env) |
6cc6987e | 857 | SIM_DESC sd; |
6274d39b | 858 | struct _bfd *abfd; |
05ccbdfd JL |
859 | char **argv; |
860 | char **env; | |
861 | { | |
6274d39b JJ |
862 | if (abfd != NULL) |
863 | PC = bfd_get_start_address (abfd); | |
864 | else | |
865 | PC = 0; | |
6cc6987e | 866 | return SIM_RC_OK; |
05ccbdfd JL |
867 | } |
868 | ||
05ccbdfd | 869 | void |
003c91be | 870 | sim_set_callbacks (p) |
05ccbdfd JL |
871 | host_callback *p; |
872 | { | |
873 | mn10300_callback = p; | |
874 | } | |
875 | ||
876 | /* All the code for exiting, signals, etc needs to be revamped. | |
877 | ||
878 | This is enough to get c-torture limping though. */ | |
879 | ||
880 | void | |
6cc6987e DE |
881 | sim_stop_reason (sd, reason, sigrc) |
882 | SIM_DESC sd; | |
05ccbdfd JL |
883 | enum sim_stop *reason; |
884 | int *sigrc; | |
885 | { | |
247fccde AC |
886 | if (State.exited) |
887 | *reason = sim_exited; | |
888 | else | |
889 | *reason = sim_stopped; | |
05ccbdfd JL |
890 | if (State.exception == SIGQUIT) |
891 | *sigrc = 0; | |
892 | else | |
893 | *sigrc = State.exception; | |
894 | } | |
895 | ||
05ccbdfd | 896 | int |
6cc6987e DE |
897 | sim_read (sd, addr, buffer, size) |
898 | SIM_DESC sd; | |
05ccbdfd JL |
899 | SIM_ADDR addr; |
900 | unsigned char *buffer; | |
901 | int size; | |
902 | { | |
903 | int i; | |
904 | for (i = 0; i < size; i++) | |
003c91be | 905 | buffer[i] = load_byte (addr + i); |
05ccbdfd JL |
906 | |
907 | return size; | |
908 | } | |
909 | ||
910 | void | |
6cc6987e DE |
911 | sim_do_command (sd, cmd) |
912 | SIM_DESC sd; | |
05ccbdfd JL |
913 | char *cmd; |
914 | { | |
915 | (*mn10300_callback->printf_filtered) (mn10300_callback, "\"%s\" is not a valid mn10300 simulator command.\n", cmd); | |
916 | } | |
917 | ||
6cc6987e DE |
918 | SIM_RC |
919 | sim_load (sd, prog, abfd, from_tty) | |
920 | SIM_DESC sd; | |
05ccbdfd | 921 | char *prog; |
6cc6987e | 922 | bfd *abfd; |
05ccbdfd JL |
923 | int from_tty; |
924 | { | |
6cc6987e DE |
925 | extern bfd *sim_load_file (); /* ??? Don't know where this should live. */ |
926 | bfd *prog_bfd; | |
927 | ||
928 | prog_bfd = sim_load_file (sd, myname, mn10300_callback, prog, abfd, | |
6274d39b JJ |
929 | sim_kind == SIM_OPEN_DEBUG, |
930 | 0, sim_write); | |
6cc6987e DE |
931 | if (prog_bfd == NULL) |
932 | return SIM_RC_FAIL; | |
6cc6987e DE |
933 | if (abfd == NULL) |
934 | bfd_close (prog_bfd); | |
935 | return SIM_RC_OK; | |
05ccbdfd | 936 | } |
6274d39b JJ |
937 | #endif /* not WITH_COMMON */ |
938 | ||
939 | ||
940 | #if WITH_COMMON | |
941 | ||
942 | /* For compatibility */ | |
943 | SIM_DESC simulator; | |
944 | ||
6274d39b JJ |
945 | /* These default values correspond to expected usage for the chip. */ |
946 | ||
947 | SIM_DESC | |
948 | sim_open (kind, cb, abfd, argv) | |
949 | SIM_OPEN_KIND kind; | |
950 | host_callback *cb; | |
951 | struct _bfd *abfd; | |
952 | char **argv; | |
953 | { | |
954 | SIM_DESC sd = sim_state_alloc (kind, cb); | |
6274d39b JJ |
955 | mn10300_callback = cb; |
956 | ||
957 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
958 | ||
959 | /* for compatibility */ | |
960 | simulator = sd; | |
961 | ||
6100784a AC |
962 | /* FIXME: should be better way of setting up interrupts. For |
963 | moment, only support watchpoints causing a breakpoint (gdb | |
964 | halt). */ | |
6274d39b JJ |
965 | STATE_WATCHPOINTS (sd)->pc = &(PC); |
966 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
6100784a AC |
967 | STATE_WATCHPOINTS (sd)->interrupt_handler = NULL; |
968 | STATE_WATCHPOINTS (sd)->interrupt_names = NULL; | |
6274d39b JJ |
969 | |
970 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
971 | return 0; | |
6adf5185 | 972 | sim_add_option_table (sd, NULL, mn10300_options); |
6274d39b JJ |
973 | |
974 | /* Allocate core managed memory */ | |
6274d39b | 975 | sim_do_command (sd, "memory region 0,0x100000"); |
6100784a | 976 | sim_do_command (sd, "memory region 0x40000000,0x100000"); |
6274d39b JJ |
977 | |
978 | /* getopt will print the error message so we just have to exit if this fails. | |
979 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
980 | print_filtered. */ | |
981 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
982 | { | |
983 | /* Uninstall the modules to avoid memory leaks, | |
984 | file descriptor leaks, etc. */ | |
985 | sim_module_uninstall (sd); | |
986 | return 0; | |
987 | } | |
988 | ||
6d133cc9 | 989 | /* start-sanitize-am30 */ |
6adf5185 JJ |
990 | if ( NULL != board |
991 | && (strcmp(board, BOARD_AM32) == 0 ) ) | |
992 | { | |
993 | /* device support for mn1030002 */ | |
994 | /* interrupt controller */ | |
995 | ||
996 | sim_hw_parse (sd, "/mn103int@0x34000100/reg 0x34000100 0x7C 0x34000200 0x8 0x3400280 0x8"); | |
997 | ||
998 | /* DEBUG: NMI input's */ | |
999 | sim_hw_parse (sd, "/glue@0x30000000/reg 0x30000000 12"); | |
1000 | sim_hw_parse (sd, "/glue@0x30000000 > int0 nmirq /mn103int"); | |
1001 | sim_hw_parse (sd, "/glue@0x30000000 > int1 watchdog /mn103int"); | |
1002 | sim_hw_parse (sd, "/glue@0x30000000 > int2 syserr /mn103int"); | |
1003 | ||
1004 | /* DEBUG: ACK input */ | |
1005 | sim_hw_parse (sd, "/glue@0x30002000/reg 0x30002000 4"); | |
1006 | sim_hw_parse (sd, "/glue@0x30002000 > int ack /mn103int"); | |
1007 | ||
1008 | /* DEBUG: LEVEL output */ | |
1009 | sim_hw_parse (sd, "/glue@0x30004000/reg 0x30004000 8"); | |
1010 | sim_hw_parse (sd, "/mn103int > nmi int0 /glue@0x30004000"); | |
1011 | sim_hw_parse (sd, "/mn103int > level int1 /glue@0x30004000"); | |
1012 | ||
1013 | /* DEBUG: A bunch of interrupt inputs */ | |
1014 | sim_hw_parse (sd, "/glue@0x30006000/reg 0x30006000 32"); | |
1015 | sim_hw_parse (sd, "/glue@0x30006000 > int0 irq-0 /mn103int"); | |
1016 | sim_hw_parse (sd, "/glue@0x30006000 > int1 irq-1 /mn103int"); | |
1017 | sim_hw_parse (sd, "/glue@0x30006000 > int2 irq-2 /mn103int"); | |
1018 | sim_hw_parse (sd, "/glue@0x30006000 > int3 irq-3 /mn103int"); | |
1019 | sim_hw_parse (sd, "/glue@0x30006000 > int4 irq-4 /mn103int"); | |
1020 | sim_hw_parse (sd, "/glue@0x30006000 > int5 irq-5 /mn103int"); | |
1021 | sim_hw_parse (sd, "/glue@0x30006000 > int6 irq-6 /mn103int"); | |
1022 | sim_hw_parse (sd, "/glue@0x30006000 > int7 irq-7 /mn103int"); | |
1023 | ||
1024 | /* processor interrupt device */ | |
1025 | ||
1026 | /* the device */ | |
1027 | sim_hw_parse (sd, "/mn103cpu@0x20000000"); | |
1028 | sim_hw_parse (sd, "/mn103cpu@0x20000000/reg 0x20000000 0x42"); | |
1029 | ||
1030 | /* DEBUG: ACK output wired upto a glue device */ | |
1031 | sim_hw_parse (sd, "/glue@0x20002000"); | |
1032 | sim_hw_parse (sd, "/glue@0x20002000/reg 0x20002000 4"); | |
1033 | sim_hw_parse (sd, "/mn103cpu > ack int0 /glue@0x20002000"); | |
1034 | ||
1035 | /* DEBUG: RESET/NMI/LEVEL wired up to a glue device */ | |
1036 | sim_hw_parse (sd, "/glue@0x20004000"); | |
1037 | sim_hw_parse (sd, "/glue@0x20004000/reg 0x20004000 12"); | |
1038 | sim_hw_parse (sd, "/glue@0x20004000 > int0 reset /mn103cpu"); | |
1039 | sim_hw_parse (sd, "/glue@0x20004000 > int1 nmi /mn103cpu"); | |
1040 | sim_hw_parse (sd, "/glue@0x20004000 > int2 level /mn103cpu"); | |
1041 | ||
1042 | /* REAL: The processor wired up to the real interrupt controller */ | |
1043 | sim_hw_parse (sd, "/mn103cpu > ack ack /mn103int"); | |
1044 | sim_hw_parse (sd, "/mn103int > level level /mn103cpu"); | |
1045 | sim_hw_parse (sd, "/mn103int > nmi nmi /mn103cpu"); | |
1046 | ||
1047 | ||
1048 | /* PAL */ | |
1049 | ||
1050 | /* the device */ | |
1051 | sim_hw_parse (sd, "/pal@0x31000000"); | |
1052 | sim_hw_parse (sd, "/pal@0x31000000/reg 0x31000000 64"); | |
1053 | sim_hw_parse (sd, "/pal@0x31000000/poll? true"); | |
1054 | ||
1055 | /* DEBUG: PAL wired up to a glue device */ | |
1056 | sim_hw_parse (sd, "/glue@0x31002000"); | |
1057 | sim_hw_parse (sd, "/glue@0x31002000/reg 0x31002000 16"); | |
1058 | sim_hw_parse (sd, "/pal@0x31000000 > countdown int0 /glue@0x31002000"); | |
1059 | sim_hw_parse (sd, "/pal@0x31000000 > timer int1 /glue@0x31002000"); | |
1060 | sim_hw_parse (sd, "/pal@0x31000000 > int int2 /glue@0x31002000"); | |
1061 | sim_hw_parse (sd, "/glue@0x31002000 > int0 int3 /glue@0x31002000"); | |
1062 | sim_hw_parse (sd, "/glue@0x31002000 > int1 int3 /glue@0x31002000"); | |
1063 | sim_hw_parse (sd, "/glue@0x31002000 > int2 int3 /glue@0x31002000"); | |
1064 | ||
1065 | /* REAL: The PAL wired up to the real interrupt controller */ | |
1066 | sim_hw_parse (sd, "/pal@0x31000000 > countdown irq-0 /mn103int"); | |
1067 | sim_hw_parse (sd, "/pal@0x31000000 > timer irq-1 /mn103int"); | |
1068 | sim_hw_parse (sd, "/pal@0x31000000 > int irq-2 /mn103int"); | |
1069 | ||
1070 | /* 8 and 16 bit timers */ | |
1071 | sim_hw_parse (sd, "/mn103tim@0x34001000/reg 0x34001000 36 0x34001080 100"); | |
1072 | ||
1073 | /* Hook timer interrupts up to interrupt controller */ | |
1074 | sim_hw_parse (sd, "/mn103tim > timer-0-underflow timer-0-underflow /mn103int"); | |
1075 | sim_hw_parse (sd, "/mn103tim > timer-1-underflow timer-1-underflow /mn103int"); | |
1076 | sim_hw_parse (sd, "/mn103tim > timer-2-underflow timer-2-underflow /mn103int"); | |
1077 | sim_hw_parse (sd, "/mn103tim > timer-3-underflow timer-3-underflow /mn103int"); | |
1078 | sim_hw_parse (sd, "/mn103tim > timer-4-underflow timer-4-underflow /mn103int"); | |
1079 | sim_hw_parse (sd, "/mn103tim > timer-5-underflow timer-5-underflow /mn103int"); | |
1080 | sim_hw_parse (sd, "/mn103tim > timer-6-underflow timer-6-underflow /mn103int"); | |
1081 | sim_hw_parse (sd, "/mn103tim > timer-6-compare-a timer-6-compare-a /mn103int"); | |
1082 | sim_hw_parse (sd, "/mn103tim > timer-6-compare-b timer-6-compare-b /mn103int"); | |
1083 | ||
1084 | ||
1085 | /* Serial devices 0,1,2 */ | |
1086 | sim_hw_parse (sd, "/mn103ser@0x34000800/reg 0x34000800 48"); | |
1087 | ||
1088 | /* Hook serial interrupts up to interrupt controller */ | |
1089 | sim_hw_parse (sd, "/mn103ser > serial-0-receive serial-0-receive /mn103int"); | |
1090 | sim_hw_parse (sd, "/mn103ser > serial-0-transmit serial-0-transmit /mn103int"); | |
1091 | sim_hw_parse (sd, "/mn103ser > serial-1-receive serial-0-receive /mn103int"); | |
1092 | sim_hw_parse (sd, "/mn103ser > serial-1-transmit serial-0-transmit /mn103int"); | |
1093 | sim_hw_parse (sd, "/mn103ser > serial-2-receive serial-0-receive /mn103int"); | |
1094 | sim_hw_parse (sd, "/mn103ser > serial-2-transmit serial-0-transmit /mn103int"); | |
1095 | } | |
1096 | ||
6d133cc9 | 1097 | /* end-sanitize-am30 */ |
6100784a | 1098 | |
6274d39b JJ |
1099 | /* check for/establish the a reference program image */ |
1100 | if (sim_analyze_program (sd, | |
1101 | (STATE_PROG_ARGV (sd) != NULL | |
1102 | ? *STATE_PROG_ARGV (sd) | |
1103 | : NULL), | |
1104 | abfd) != SIM_RC_OK) | |
1105 | { | |
1106 | sim_module_uninstall (sd); | |
1107 | return 0; | |
1108 | } | |
1109 | ||
1110 | /* establish any remaining configuration options */ | |
1111 | if (sim_config (sd) != SIM_RC_OK) | |
1112 | { | |
1113 | sim_module_uninstall (sd); | |
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
1118 | { | |
1119 | /* Uninstall the modules to avoid memory leaks, | |
1120 | file descriptor leaks, etc. */ | |
1121 | sim_module_uninstall (sd); | |
1122 | return 0; | |
1123 | } | |
1124 | ||
1125 | ||
1126 | /* set machine specific configuration */ | |
1127 | /* STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT */ | |
1128 | /* | PSW_CY | PSW_OV | PSW_S | PSW_Z); */ | |
1129 | ||
1130 | return sd; | |
1131 | } | |
1132 | ||
1133 | ||
1134 | void | |
1135 | sim_close (sd, quitting) | |
1136 | SIM_DESC sd; | |
1137 | int quitting; | |
1138 | { | |
1139 | sim_module_uninstall (sd); | |
1140 | } | |
1141 | ||
1142 | ||
1143 | SIM_RC | |
1144 | sim_create_inferior (sd, prog_bfd, argv, env) | |
1145 | SIM_DESC sd; | |
1146 | struct _bfd *prog_bfd; | |
1147 | char **argv; | |
1148 | char **env; | |
1149 | { | |
1150 | memset (&State, 0, sizeof (State)); | |
1151 | if (prog_bfd != NULL) { | |
1152 | PC = bfd_get_start_address (prog_bfd); | |
1153 | } else { | |
1154 | PC = 0; | |
1155 | } | |
1156 | CIA_SET (STATE_CPU (sd, 0), (unsigned64) PC); | |
1157 | ||
1158 | return SIM_RC_OK; | |
1159 | } | |
1160 | ||
1161 | void | |
1162 | sim_do_command (sd, cmd) | |
1163 | SIM_DESC sd; | |
1164 | char *cmd; | |
1165 | { | |
1166 | char *mm_cmd = "memory-map"; | |
1167 | char *int_cmd = "interrupt"; | |
1168 | ||
1169 | if (sim_args_command (sd, cmd) != SIM_RC_OK) | |
1170 | { | |
1171 | if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0)) | |
1172 | sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n"); | |
1173 | else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0) | |
1174 | sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n"); | |
1175 | else | |
1176 | sim_io_eprintf (sd, "Unknown command `%s'\n", cmd); | |
1177 | } | |
1178 | } | |
1179 | #endif /* WITH_COMMON */ | |
1180 | ||
1181 | /* FIXME These would more efficient to use than load_mem/store_mem, | |
1182 | but need to be changed to use the memory map. */ | |
1183 | ||
1184 | uint8 | |
1185 | get_byte (x) | |
1186 | uint8 *x; | |
1187 | { | |
1188 | return *x; | |
1189 | } | |
1190 | ||
1191 | uint16 | |
1192 | get_half (x) | |
1193 | uint8 *x; | |
1194 | { | |
1195 | uint8 *a = x; | |
1196 | return (a[1] << 8) + (a[0]); | |
1197 | } | |
1198 | ||
1199 | uint32 | |
1200 | get_word (x) | |
1201 | uint8 *x; | |
1202 | { | |
1203 | uint8 *a = x; | |
1204 | return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]); | |
1205 | } | |
1206 | ||
1207 | void | |
1208 | put_byte (addr, data) | |
1209 | uint8 *addr; | |
1210 | uint8 data; | |
1211 | { | |
1212 | uint8 *a = addr; | |
1213 | a[0] = data; | |
1214 | } | |
1215 | ||
1216 | void | |
1217 | put_half (addr, data) | |
1218 | uint8 *addr; | |
1219 | uint16 data; | |
1220 | { | |
1221 | uint8 *a = addr; | |
1222 | a[0] = data & 0xff; | |
1223 | a[1] = (data >> 8) & 0xff; | |
1224 | } | |
1225 | ||
1226 | void | |
1227 | put_word (addr, data) | |
1228 | uint8 *addr; | |
1229 | uint32 data; | |
1230 | { | |
1231 | uint8 *a = addr; | |
1232 | a[0] = data & 0xff; | |
1233 | a[1] = (data >> 8) & 0xff; | |
1234 | a[2] = (data >> 16) & 0xff; | |
1235 | a[3] = (data >> 24) & 0xff; | |
1236 | } | |
1237 | ||
1238 | int | |
1239 | sim_fetch_register (sd, rn, memory, length) | |
1240 | SIM_DESC sd; | |
1241 | int rn; | |
1242 | unsigned char *memory; | |
1243 | int length; | |
1244 | { | |
1245 | put_word (memory, State.regs[rn]); | |
1246 | return -1; | |
1247 | } | |
1248 | ||
1249 | int | |
1250 | sim_store_register (sd, rn, memory, length) | |
1251 | SIM_DESC sd; | |
1252 | int rn; | |
1253 | unsigned char *memory; | |
1254 | int length; | |
1255 | { | |
1256 | State.regs[rn] = get_word (memory); | |
1257 | return -1; | |
1258 | } |