Commit | Line | Data |
---|---|---|
05ccbdfd | 1 | #include <signal.h> |
6274d39b JJ |
2 | |
3 | #if WITH_COMMON | |
4 | #include "sim-main.h" | |
5 | #else | |
6 | #include "mn10300_sim.h" | |
7 | #endif | |
8 | ||
05ccbdfd JL |
9 | #include "sysdep.h" |
10 | #include "bfd.h" | |
6274d39b JJ |
11 | #include "sim-assert.h" |
12 | ||
13 | ||
14 | #ifdef HAVE_STDLIB_H | |
15 | #include <stdlib.h> | |
16 | #endif | |
17 | ||
18 | #ifdef HAVE_STRING_H | |
19 | #include <string.h> | |
20 | #else | |
21 | #ifdef HAVE_STRINGS_H | |
22 | #include <strings.h> | |
23 | #endif | |
24 | #endif | |
25 | ||
26 | #include "bfd.h" | |
27 | ||
28 | #ifndef INLINE | |
29 | #ifdef __GNUC__ | |
30 | #define INLINE inline | |
31 | #else | |
32 | #define INLINE | |
33 | #endif | |
34 | #endif | |
05ccbdfd | 35 | |
05ccbdfd | 36 | |
05ccbdfd JL |
37 | host_callback *mn10300_callback; |
38 | int mn10300_debug; | |
6cc6987e DE |
39 | static SIM_OPEN_KIND sim_kind; |
40 | static char *myname; | |
05ccbdfd | 41 | |
6274d39b JJ |
42 | #if WITH_COMMON |
43 | #else | |
baa83bcc | 44 | static void dispatch PARAMS ((uint32, uint32, int)); |
05ccbdfd JL |
45 | static long hash PARAMS ((long)); |
46 | static void init_system PARAMS ((void)); | |
baa83bcc | 47 | #define MAX_HASH 127 |
05ccbdfd JL |
48 | |
49 | struct hash_entry | |
50 | { | |
51 | struct hash_entry *next; | |
52 | long opcode; | |
53 | long mask; | |
54 | struct simops *ops; | |
baa83bcc JL |
55 | #ifdef HASH_STAT |
56 | unsigned long count; | |
57 | #endif | |
05ccbdfd JL |
58 | }; |
59 | ||
234a9a49 | 60 | static int max_mem = 0; |
05ccbdfd JL |
61 | struct hash_entry hash_table[MAX_HASH+1]; |
62 | ||
63 | ||
d2523010 JL |
64 | /* This probably doesn't do a very good job at bucket filling, but |
65 | it's simple... */ | |
05ccbdfd JL |
66 | static INLINE long |
67 | hash(insn) | |
68 | long insn; | |
69 | { | |
baa83bcc JL |
70 | /* These are one byte insns, we special case these since, in theory, |
71 | they should be the most heavily used. */ | |
d2523010 JL |
72 | if ((insn & 0xffffff00) == 0) |
73 | { | |
baa83bcc JL |
74 | switch (insn & 0xf0) |
75 | { | |
76 | case 0x00: | |
77 | return 0x70; | |
78 | ||
79 | case 0x40: | |
80 | return 0x71; | |
81 | ||
82 | case 0x10: | |
83 | return 0x72; | |
84 | ||
85 | case 0x30: | |
86 | return 0x73; | |
87 | ||
88 | case 0x50: | |
89 | return 0x74; | |
90 | ||
91 | case 0x60: | |
92 | return 0x75; | |
93 | ||
94 | case 0x70: | |
95 | return 0x76; | |
96 | ||
97 | case 0x80: | |
98 | return 0x77; | |
99 | ||
100 | case 0x90: | |
101 | return 0x78; | |
102 | ||
103 | case 0xa0: | |
104 | return 0x79; | |
105 | ||
106 | case 0xb0: | |
107 | return 0x7a; | |
108 | ||
109 | case 0xe0: | |
110 | return 0x7b; | |
111 | ||
112 | default: | |
113 | return 0x7c; | |
114 | } | |
d2523010 JL |
115 | } |
116 | ||
117 | /* These are two byte insns */ | |
118 | if ((insn & 0xffff0000) == 0) | |
119 | { | |
120 | if ((insn & 0xf000) == 0x2000 | |
121 | || (insn & 0xf000) == 0x5000) | |
baa83bcc | 122 | return ((insn & 0xfc00) >> 8) & 0x7f; |
d2523010 JL |
123 | |
124 | if ((insn & 0xf000) == 0x4000) | |
baa83bcc | 125 | return ((insn & 0xf300) >> 8) & 0x7f; |
d2523010 JL |
126 | |
127 | if ((insn & 0xf000) == 0x8000 | |
128 | || (insn & 0xf000) == 0x9000 | |
129 | || (insn & 0xf000) == 0xa000 | |
130 | || (insn & 0xf000) == 0xb000) | |
baa83bcc JL |
131 | return ((insn & 0xf000) >> 8) & 0x7f; |
132 | ||
133 | if ((insn & 0xff00) == 0xf000 | |
134 | || (insn & 0xff00) == 0xf100 | |
135 | || (insn & 0xff00) == 0xf200 | |
136 | || (insn & 0xff00) == 0xf500 | |
137 | || (insn & 0xff00) == 0xf600) | |
138 | return ((insn & 0xfff0) >> 4) & 0x7f; | |
139 | ||
140 | if ((insn & 0xf000) == 0xc000) | |
141 | return ((insn & 0xff00) >> 8) & 0x7f; | |
142 | ||
143 | return ((insn & 0xffc0) >> 6) & 0x7f; | |
d2523010 JL |
144 | } |
145 | ||
146 | /* These are three byte insns. */ | |
147 | if ((insn & 0xff000000) == 0) | |
148 | { | |
149 | if ((insn & 0xf00000) == 0x000000) | |
baa83bcc | 150 | return ((insn & 0xf30000) >> 16) & 0x7f; |
d2523010 JL |
151 | |
152 | if ((insn & 0xf00000) == 0x200000 | |
153 | || (insn & 0xf00000) == 0x300000) | |
baa83bcc JL |
154 | return ((insn & 0xfc0000) >> 16) & 0x7f; |
155 | ||
156 | if ((insn & 0xff0000) == 0xf80000) | |
157 | return ((insn & 0xfff000) >> 12) & 0x7f; | |
d2523010 | 158 | |
baa83bcc JL |
159 | if ((insn & 0xff0000) == 0xf90000) |
160 | return ((insn & 0xfffc00) >> 10) & 0x7f; | |
161 | ||
162 | return ((insn & 0xff0000) >> 16) & 0x7f; | |
d2523010 JL |
163 | } |
164 | ||
165 | /* These are four byte or larger insns. */ | |
baa83bcc JL |
166 | if ((insn & 0xf0000000) == 0xf0000000) |
167 | return ((insn & 0xfff00000) >> 20) & 0x7f; | |
168 | ||
169 | return ((insn & 0xff000000) >> 24) & 0x7f; | |
05ccbdfd JL |
170 | } |
171 | ||
4df7aeb3 | 172 | static INLINE void |
baa83bcc JL |
173 | dispatch (insn, extension, length) |
174 | uint32 insn; | |
175 | uint32 extension; | |
d2523010 | 176 | int length; |
05ccbdfd JL |
177 | { |
178 | struct hash_entry *h; | |
179 | ||
baa83bcc | 180 | h = &hash_table[hash(insn)]; |
05ccbdfd | 181 | |
baa83bcc JL |
182 | while ((insn & h->mask) != h->opcode |
183 | || (length != h->ops->length)) | |
05ccbdfd | 184 | { |
baa83bcc | 185 | if (!h->next) |
05ccbdfd | 186 | { |
baa83bcc JL |
187 | (*mn10300_callback->printf_filtered) (mn10300_callback, |
188 | "ERROR looking up hash for 0x%x, PC=0x%x\n", insn, PC); | |
05ccbdfd JL |
189 | exit(1); |
190 | } | |
191 | h = h->next; | |
192 | } | |
baa83bcc JL |
193 | |
194 | ||
195 | #ifdef HASH_STAT | |
196 | h->count++; | |
197 | #endif | |
198 | ||
199 | /* Now call the right function. */ | |
200 | (h->ops->func)(insn, extension); | |
201 | PC += length; | |
05ccbdfd JL |
202 | } |
203 | ||
05ccbdfd JL |
204 | void |
205 | sim_size (power) | |
206 | int power; | |
207 | ||
208 | { | |
209 | if (State.mem) | |
210 | free (State.mem); | |
211 | ||
234a9a49 | 212 | max_mem = 1 << power; |
05ccbdfd JL |
213 | State.mem = (uint8 *) calloc (1, 1 << power); |
214 | if (!State.mem) | |
215 | { | |
216 | (*mn10300_callback->printf_filtered) (mn10300_callback, "Allocation of main memory failed.\n"); | |
217 | exit (1); | |
218 | } | |
219 | } | |
220 | ||
221 | static void | |
222 | init_system () | |
223 | { | |
224 | if (!State.mem) | |
6cc6987e | 225 | sim_size(19); |
05ccbdfd JL |
226 | } |
227 | ||
228 | int | |
6cc6987e DE |
229 | sim_write (sd, addr, buffer, size) |
230 | SIM_DESC sd; | |
05ccbdfd JL |
231 | SIM_ADDR addr; |
232 | unsigned char *buffer; | |
233 | int size; | |
234 | { | |
235 | int i; | |
236 | ||
237 | init_system (); | |
238 | ||
239 | for (i = 0; i < size; i++) | |
003c91be | 240 | store_byte (addr + i, buffer[i]); |
05ccbdfd JL |
241 | |
242 | return size; | |
243 | } | |
244 | ||
b07a1e78 JL |
245 | /* Compare two opcode table entries for qsort. */ |
246 | static int | |
247 | compare_simops (arg1, arg2) | |
248 | const PTR arg1; | |
249 | const PTR arg2; | |
250 | { | |
251 | unsigned long code1 = ((struct simops *)arg1)->opcode; | |
252 | unsigned long code2 = ((struct simops *)arg2)->opcode; | |
253 | ||
254 | if (code1 < code2) | |
255 | return -1; | |
256 | if (code2 < code1) | |
257 | return 1; | |
258 | return 0; | |
259 | } | |
260 | ||
6274d39b | 261 | |
6cc6987e | 262 | SIM_DESC |
247fccde | 263 | sim_open (kind, cb, abfd, argv) |
6cc6987e | 264 | SIM_OPEN_KIND kind; |
003c91be | 265 | host_callback *cb; |
247fccde | 266 | struct _bfd *abfd; |
6cc6987e | 267 | char **argv; |
05ccbdfd JL |
268 | { |
269 | struct simops *s; | |
270 | struct hash_entry *h; | |
6cc6987e | 271 | char **p; |
b07a1e78 JL |
272 | int i; |
273 | ||
003c91be JL |
274 | mn10300_callback = cb; |
275 | ||
b07a1e78 JL |
276 | /* Sort the opcode array from smallest opcode to largest. |
277 | This will generally improve simulator performance as the smaller | |
278 | opcodes are generally preferred to the larger opcodes. */ | |
279 | for (i = 0, s = Simops; s->func; s++, i++) | |
280 | ; | |
281 | qsort (Simops, i, sizeof (Simops[0]), compare_simops); | |
6cc6987e DE |
282 | |
283 | sim_kind = kind; | |
284 | myname = argv[0]; | |
285 | ||
286 | for (p = argv + 1; *p; ++p) | |
05ccbdfd | 287 | { |
6cc6987e DE |
288 | if (strcmp (*p, "-E") == 0) |
289 | ++p; /* ignore endian spec */ | |
290 | else | |
05ccbdfd | 291 | #ifdef DEBUG |
6cc6987e | 292 | if (strcmp (*p, "-t") == 0) |
05ccbdfd JL |
293 | mn10300_debug = DEBUG; |
294 | else | |
295 | #endif | |
6cc6987e | 296 | (*mn10300_callback->printf_filtered) (mn10300_callback, "ERROR: unsupported option(s): %s\n",*p); |
05ccbdfd JL |
297 | } |
298 | ||
baa83bcc | 299 | /* put all the opcodes in the hash table */ |
05ccbdfd JL |
300 | for (s = Simops; s->func; s++) |
301 | { | |
302 | h = &hash_table[hash(s->opcode)]; | |
baa83bcc | 303 | |
05ccbdfd JL |
304 | /* go to the last entry in the chain */ |
305 | while (h->next) | |
baa83bcc JL |
306 | { |
307 | /* Don't insert the same opcode more than once. */ | |
308 | if (h->opcode == s->opcode | |
309 | && h->mask == s->mask | |
310 | && h->ops == s) | |
247fccde | 311 | break; |
baa83bcc JL |
312 | else |
313 | h = h->next; | |
314 | } | |
315 | ||
316 | /* Don't insert the same opcode more than once. */ | |
317 | if (h->opcode == s->opcode | |
318 | && h->mask == s->mask | |
319 | && h->ops == s) | |
320 | continue; | |
05ccbdfd JL |
321 | |
322 | if (h->ops) | |
323 | { | |
324 | h->next = calloc(1,sizeof(struct hash_entry)); | |
325 | h = h->next; | |
326 | } | |
327 | h->ops = s; | |
328 | h->mask = s->mask; | |
329 | h->opcode = s->opcode; | |
baa83bcc JL |
330 | #if HASH_STAT |
331 | h->count = 0; | |
332 | #endif | |
05ccbdfd | 333 | } |
6cc6987e | 334 | |
baa83bcc | 335 | |
6cc6987e DE |
336 | /* fudge our descriptor for now */ |
337 | return (SIM_DESC) 1; | |
05ccbdfd JL |
338 | } |
339 | ||
340 | ||
341 | void | |
6cc6987e DE |
342 | sim_close (sd, quitting) |
343 | SIM_DESC sd; | |
05ccbdfd JL |
344 | int quitting; |
345 | { | |
346 | /* nothing to do */ | |
347 | } | |
348 | ||
349 | void | |
350 | sim_set_profile (n) | |
351 | int n; | |
352 | { | |
353 | (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile %d\n", n); | |
354 | } | |
355 | ||
356 | void | |
357 | sim_set_profile_size (n) | |
358 | int n; | |
359 | { | |
360 | (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile_size %d\n", n); | |
361 | } | |
362 | ||
baa83bcc JL |
363 | int |
364 | sim_stop (sd) | |
365 | SIM_DESC sd; | |
366 | { | |
367 | return 0; | |
368 | } | |
369 | ||
05ccbdfd | 370 | void |
6cc6987e DE |
371 | sim_resume (sd, step, siggnal) |
372 | SIM_DESC sd; | |
05ccbdfd JL |
373 | int step, siggnal; |
374 | { | |
7c52bf32 | 375 | uint32 inst; |
05ccbdfd | 376 | reg_t oldpc; |
d2523010 | 377 | struct hash_entry *h; |
05ccbdfd JL |
378 | |
379 | if (step) | |
380 | State.exception = SIGTRAP; | |
381 | else | |
382 | State.exception = 0; | |
383 | ||
247fccde AC |
384 | State.exited = 0; |
385 | ||
05ccbdfd JL |
386 | do |
387 | { | |
d2523010 JL |
388 | unsigned long insn, extension; |
389 | ||
05ccbdfd | 390 | /* Fetch the current instruction. */ |
baa83bcc | 391 | inst = load_mem_big (PC, 2); |
05ccbdfd | 392 | oldpc = PC; |
05ccbdfd | 393 | |
baa83bcc JL |
394 | /* Using a giant case statement may seem like a waste because of the |
395 | code/rodata size the table itself will consume. However, using | |
396 | a giant case statement speeds up the simulator by 10-15% by avoiding | |
397 | cascading if/else statements or cascading case statements. */ | |
d2523010 | 398 | |
baa83bcc | 399 | switch ((inst >> 8) & 0xff) |
d2523010 | 400 | { |
baa83bcc JL |
401 | /* All the single byte insns except 0x80, 0x90, 0xa0, 0xb0 |
402 | which must be handled specially. */ | |
403 | case 0x00: | |
404 | case 0x04: | |
405 | case 0x08: | |
406 | case 0x0c: | |
09e142d5 | 407 | case 0x10: |
baa83bcc JL |
408 | case 0x11: |
409 | case 0x12: | |
410 | case 0x13: | |
411 | case 0x14: | |
412 | case 0x15: | |
413 | case 0x16: | |
414 | case 0x17: | |
415 | case 0x18: | |
416 | case 0x19: | |
417 | case 0x1a: | |
418 | case 0x1b: | |
419 | case 0x1c: | |
420 | case 0x1d: | |
421 | case 0x1e: | |
422 | case 0x1f: | |
423 | case 0x3c: | |
424 | case 0x3d: | |
425 | case 0x3e: | |
426 | case 0x3f: | |
427 | case 0x40: | |
428 | case 0x41: | |
429 | case 0x44: | |
430 | case 0x45: | |
431 | case 0x48: | |
432 | case 0x49: | |
433 | case 0x4c: | |
434 | case 0x4d: | |
435 | case 0x50: | |
436 | case 0x51: | |
437 | case 0x52: | |
438 | case 0x53: | |
439 | case 0x54: | |
440 | case 0x55: | |
441 | case 0x56: | |
442 | case 0x57: | |
443 | case 0x60: | |
444 | case 0x61: | |
445 | case 0x62: | |
446 | case 0x63: | |
447 | case 0x64: | |
448 | case 0x65: | |
449 | case 0x66: | |
450 | case 0x67: | |
451 | case 0x68: | |
452 | case 0x69: | |
453 | case 0x6a: | |
454 | case 0x6b: | |
455 | case 0x6c: | |
456 | case 0x6d: | |
457 | case 0x6e: | |
458 | case 0x6f: | |
459 | case 0x70: | |
460 | case 0x71: | |
461 | case 0x72: | |
462 | case 0x73: | |
463 | case 0x74: | |
464 | case 0x75: | |
465 | case 0x76: | |
466 | case 0x77: | |
467 | case 0x78: | |
468 | case 0x79: | |
469 | case 0x7a: | |
470 | case 0x7b: | |
471 | case 0x7c: | |
472 | case 0x7d: | |
473 | case 0x7e: | |
474 | case 0x7f: | |
475 | case 0xcb: | |
476 | case 0xd0: | |
477 | case 0xd1: | |
478 | case 0xd2: | |
479 | case 0xd3: | |
480 | case 0xd4: | |
481 | case 0xd5: | |
482 | case 0xd6: | |
483 | case 0xd7: | |
484 | case 0xd8: | |
485 | case 0xd9: | |
486 | case 0xda: | |
487 | case 0xdb: | |
488 | case 0xe0: | |
489 | case 0xe1: | |
490 | case 0xe2: | |
491 | case 0xe3: | |
492 | case 0xe4: | |
493 | case 0xe5: | |
494 | case 0xe6: | |
495 | case 0xe7: | |
496 | case 0xe8: | |
497 | case 0xe9: | |
498 | case 0xea: | |
499 | case 0xeb: | |
500 | case 0xec: | |
501 | case 0xed: | |
502 | case 0xee: | |
503 | case 0xef: | |
504 | case 0xff: | |
505 | insn = (inst >> 8) & 0xff; | |
506 | extension = 0; | |
507 | dispatch (insn, extension, 1); | |
508 | break; | |
509 | ||
510 | /* Special cases where dm == dn is used to encode a different | |
511 | instruction. */ | |
512 | case 0x80: | |
513 | case 0x85: | |
514 | case 0x8a: | |
515 | case 0x8f: | |
516 | case 0x90: | |
517 | case 0x95: | |
518 | case 0x9a: | |
519 | case 0x9f: | |
520 | case 0xa0: | |
521 | case 0xa5: | |
522 | case 0xaa: | |
523 | case 0xaf: | |
524 | case 0xb0: | |
525 | case 0xb5: | |
526 | case 0xba: | |
527 | case 0xbf: | |
528 | insn = inst; | |
529 | extension = 0; | |
530 | dispatch (insn, extension, 2); | |
531 | break; | |
532 | ||
533 | case 0x81: | |
534 | case 0x82: | |
535 | case 0x83: | |
536 | case 0x84: | |
537 | case 0x86: | |
538 | case 0x87: | |
539 | case 0x88: | |
540 | case 0x89: | |
541 | case 0x8b: | |
542 | case 0x8c: | |
543 | case 0x8d: | |
544 | case 0x8e: | |
545 | case 0x91: | |
546 | case 0x92: | |
547 | case 0x93: | |
548 | case 0x94: | |
549 | case 0x96: | |
550 | case 0x97: | |
551 | case 0x98: | |
552 | case 0x99: | |
553 | case 0x9b: | |
554 | case 0x9c: | |
555 | case 0x9d: | |
556 | case 0x9e: | |
557 | case 0xa1: | |
558 | case 0xa2: | |
559 | case 0xa3: | |
560 | case 0xa4: | |
561 | case 0xa6: | |
562 | case 0xa7: | |
563 | case 0xa8: | |
564 | case 0xa9: | |
565 | case 0xab: | |
566 | case 0xac: | |
567 | case 0xad: | |
568 | case 0xae: | |
569 | case 0xb1: | |
570 | case 0xb2: | |
571 | case 0xb3: | |
572 | case 0xb4: | |
573 | case 0xb6: | |
574 | case 0xb7: | |
575 | case 0xb8: | |
576 | case 0xb9: | |
577 | case 0xbb: | |
578 | case 0xbc: | |
579 | case 0xbd: | |
580 | case 0xbe: | |
581 | insn = (inst >> 8) & 0xff; | |
582 | extension = 0; | |
583 | dispatch (insn, extension, 1); | |
584 | break; | |
585 | ||
586 | /* The two byte instructions. */ | |
587 | case 0x20: | |
588 | case 0x21: | |
589 | case 0x22: | |
590 | case 0x23: | |
591 | case 0x28: | |
592 | case 0x29: | |
593 | case 0x2a: | |
594 | case 0x2b: | |
595 | case 0x42: | |
596 | case 0x43: | |
597 | case 0x46: | |
598 | case 0x47: | |
599 | case 0x4a: | |
600 | case 0x4b: | |
601 | case 0x4e: | |
602 | case 0x4f: | |
603 | case 0x58: | |
604 | case 0x59: | |
605 | case 0x5a: | |
606 | case 0x5b: | |
607 | case 0x5c: | |
608 | case 0x5d: | |
609 | case 0x5e: | |
610 | case 0x5f: | |
611 | case 0xc0: | |
612 | case 0xc1: | |
613 | case 0xc2: | |
614 | case 0xc3: | |
615 | case 0xc4: | |
616 | case 0xc5: | |
617 | case 0xc6: | |
618 | case 0xc7: | |
619 | case 0xc8: | |
620 | case 0xc9: | |
621 | case 0xca: | |
622 | case 0xce: | |
623 | case 0xcf: | |
624 | case 0xf0: | |
625 | case 0xf1: | |
626 | case 0xf2: | |
627 | case 0xf3: | |
628 | case 0xf4: | |
629 | case 0xf5: | |
630 | case 0xf6: | |
631 | insn = inst; | |
632 | extension = 0; | |
633 | dispatch (insn, extension, 2); | |
634 | break; | |
635 | ||
636 | /* The three byte insns with a 16bit operand in little endian | |
637 | format. */ | |
638 | case 0x01: | |
639 | case 0x02: | |
640 | case 0x03: | |
641 | case 0x05: | |
642 | case 0x06: | |
643 | case 0x07: | |
644 | case 0x09: | |
645 | case 0x0a: | |
646 | case 0x0b: | |
647 | case 0x0d: | |
648 | case 0x0e: | |
649 | case 0x0f: | |
650 | case 0x24: | |
651 | case 0x25: | |
652 | case 0x26: | |
653 | case 0x27: | |
654 | case 0x2c: | |
655 | case 0x2d: | |
656 | case 0x2e: | |
657 | case 0x2f: | |
658 | case 0x30: | |
659 | case 0x31: | |
660 | case 0x32: | |
661 | case 0x33: | |
662 | case 0x34: | |
663 | case 0x35: | |
664 | case 0x36: | |
665 | case 0x37: | |
666 | case 0x38: | |
667 | case 0x39: | |
668 | case 0x3a: | |
669 | case 0x3b: | |
670 | case 0xcc: | |
003c91be | 671 | insn = load_byte (PC); |
baa83bcc | 672 | insn <<= 16; |
003c91be | 673 | insn |= load_half (PC + 1); |
baa83bcc JL |
674 | extension = 0; |
675 | dispatch (insn, extension, 3); | |
676 | break; | |
677 | ||
678 | /* The three byte insns without 16bit operand. */ | |
679 | case 0xde: | |
680 | case 0xdf: | |
681 | case 0xf8: | |
682 | case 0xf9: | |
683 | insn = load_mem_big (PC, 3); | |
684 | extension = 0; | |
685 | dispatch (insn, extension, 3); | |
686 | break; | |
687 | ||
688 | /* Four byte insns. */ | |
689 | case 0xfa: | |
690 | case 0xfb: | |
691 | if ((inst & 0xfffc) == 0xfaf0 | |
692 | || (inst & 0xfffc) == 0xfaf4 | |
693 | || (inst & 0xfffc) == 0xfaf8) | |
694 | insn = load_mem_big (PC, 4); | |
695 | else | |
696 | { | |
697 | insn = inst; | |
698 | insn <<= 16; | |
003c91be | 699 | insn |= load_half (PC + 2); |
baa83bcc JL |
700 | extension = 0; |
701 | } | |
702 | dispatch (insn, extension, 4); | |
703 | break; | |
704 | ||
705 | /* Five byte insns. */ | |
706 | case 0xcd: | |
003c91be | 707 | insn = load_byte (PC); |
baa83bcc | 708 | insn <<= 24; |
003c91be JL |
709 | insn |= (load_half (PC + 1) << 8); |
710 | insn |= load_byte (PC + 3); | |
711 | extension = load_byte (PC + 4); | |
baa83bcc JL |
712 | dispatch (insn, extension, 5); |
713 | break; | |
714 | ||
715 | case 0xdc: | |
003c91be | 716 | insn = load_byte (PC); |
baa83bcc | 717 | insn <<= 24; |
003c91be | 718 | extension = load_word (PC + 1); |
baa83bcc JL |
719 | insn |= (extension & 0xffffff00) >> 8; |
720 | extension &= 0xff; | |
721 | dispatch (insn, extension, 5); | |
722 | break; | |
723 | ||
724 | /* Six byte insns. */ | |
725 | case 0xfc: | |
726 | case 0xfd: | |
727 | insn = (inst << 16); | |
003c91be | 728 | extension = load_word (PC + 2); |
baa83bcc JL |
729 | insn |= ((extension & 0xffff0000) >> 16); |
730 | extension &= 0xffff; | |
731 | dispatch (insn, extension, 6); | |
732 | break; | |
733 | ||
734 | case 0xdd: | |
003c91be JL |
735 | insn = load_byte (PC) << 24; |
736 | extension = load_word (PC + 1); | |
baa83bcc JL |
737 | insn |= ((extension >> 8) & 0xffffff); |
738 | extension = (extension & 0xff) << 16; | |
003c91be JL |
739 | extension |= load_byte (PC + 5) << 8; |
740 | extension |= load_byte (PC + 6); | |
baa83bcc JL |
741 | dispatch (insn, extension, 7); |
742 | break; | |
743 | ||
744 | case 0xfe: | |
745 | insn = inst << 16; | |
003c91be | 746 | extension = load_word (PC + 2); |
baa83bcc JL |
747 | insn |= ((extension >> 16) & 0xffff); |
748 | extension <<= 8; | |
749 | extension &= 0xffff00; | |
003c91be | 750 | extension |= load_byte (PC + 6); |
baa83bcc JL |
751 | dispatch (insn, extension, 7); |
752 | break; | |
753 | ||
754 | default: | |
755 | abort (); | |
05ccbdfd JL |
756 | } |
757 | } | |
758 | while (!State.exception); | |
baa83bcc JL |
759 | |
760 | #ifdef HASH_STAT | |
761 | { | |
762 | int i; | |
763 | for (i = 0; i < MAX_HASH; i++) | |
764 | { | |
765 | struct hash_entry *h; | |
766 | h = &hash_table[i]; | |
767 | ||
768 | printf("hash 0x%x:\n", i); | |
769 | ||
770 | while (h) | |
771 | { | |
772 | printf("h->opcode = 0x%x, count = 0x%x\n", h->opcode, h->count); | |
773 | h = h->next; | |
774 | } | |
775 | ||
776 | printf("\n\n"); | |
777 | } | |
778 | fflush (stdout); | |
779 | } | |
780 | #endif | |
781 | ||
05ccbdfd JL |
782 | } |
783 | ||
784 | int | |
6cc6987e DE |
785 | sim_trace (sd) |
786 | SIM_DESC sd; | |
05ccbdfd JL |
787 | { |
788 | #ifdef DEBUG | |
789 | mn10300_debug = DEBUG; | |
790 | #endif | |
6cc6987e | 791 | sim_resume (sd, 0, 0); |
05ccbdfd JL |
792 | return 1; |
793 | } | |
794 | ||
795 | void | |
6cc6987e DE |
796 | sim_info (sd, verbose) |
797 | SIM_DESC sd; | |
05ccbdfd JL |
798 | int verbose; |
799 | { | |
800 | (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_info\n"); | |
801 | } | |
802 | ||
6cc6987e | 803 | SIM_RC |
6274d39b | 804 | sim_create_inferior (sd, abfd, argv, env) |
6cc6987e | 805 | SIM_DESC sd; |
6274d39b | 806 | struct _bfd *abfd; |
05ccbdfd JL |
807 | char **argv; |
808 | char **env; | |
809 | { | |
6274d39b JJ |
810 | if (abfd != NULL) |
811 | PC = bfd_get_start_address (abfd); | |
812 | else | |
813 | PC = 0; | |
6cc6987e | 814 | return SIM_RC_OK; |
05ccbdfd JL |
815 | } |
816 | ||
05ccbdfd | 817 | void |
003c91be | 818 | sim_set_callbacks (p) |
05ccbdfd JL |
819 | host_callback *p; |
820 | { | |
821 | mn10300_callback = p; | |
822 | } | |
823 | ||
824 | /* All the code for exiting, signals, etc needs to be revamped. | |
825 | ||
826 | This is enough to get c-torture limping though. */ | |
827 | ||
828 | void | |
6cc6987e DE |
829 | sim_stop_reason (sd, reason, sigrc) |
830 | SIM_DESC sd; | |
05ccbdfd JL |
831 | enum sim_stop *reason; |
832 | int *sigrc; | |
833 | { | |
247fccde AC |
834 | if (State.exited) |
835 | *reason = sim_exited; | |
836 | else | |
837 | *reason = sim_stopped; | |
05ccbdfd JL |
838 | if (State.exception == SIGQUIT) |
839 | *sigrc = 0; | |
840 | else | |
841 | *sigrc = State.exception; | |
842 | } | |
843 | ||
05ccbdfd | 844 | int |
6cc6987e DE |
845 | sim_read (sd, addr, buffer, size) |
846 | SIM_DESC sd; | |
05ccbdfd JL |
847 | SIM_ADDR addr; |
848 | unsigned char *buffer; | |
849 | int size; | |
850 | { | |
851 | int i; | |
852 | for (i = 0; i < size; i++) | |
003c91be | 853 | buffer[i] = load_byte (addr + i); |
05ccbdfd JL |
854 | |
855 | return size; | |
856 | } | |
857 | ||
858 | void | |
6cc6987e DE |
859 | sim_do_command (sd, cmd) |
860 | SIM_DESC sd; | |
05ccbdfd JL |
861 | char *cmd; |
862 | { | |
863 | (*mn10300_callback->printf_filtered) (mn10300_callback, "\"%s\" is not a valid mn10300 simulator command.\n", cmd); | |
864 | } | |
865 | ||
6cc6987e DE |
866 | SIM_RC |
867 | sim_load (sd, prog, abfd, from_tty) | |
868 | SIM_DESC sd; | |
05ccbdfd | 869 | char *prog; |
6cc6987e | 870 | bfd *abfd; |
05ccbdfd JL |
871 | int from_tty; |
872 | { | |
6cc6987e DE |
873 | extern bfd *sim_load_file (); /* ??? Don't know where this should live. */ |
874 | bfd *prog_bfd; | |
875 | ||
876 | prog_bfd = sim_load_file (sd, myname, mn10300_callback, prog, abfd, | |
6274d39b JJ |
877 | sim_kind == SIM_OPEN_DEBUG, |
878 | 0, sim_write); | |
6cc6987e DE |
879 | if (prog_bfd == NULL) |
880 | return SIM_RC_FAIL; | |
6cc6987e DE |
881 | if (abfd == NULL) |
882 | bfd_close (prog_bfd); | |
883 | return SIM_RC_OK; | |
05ccbdfd | 884 | } |
6274d39b JJ |
885 | #endif /* not WITH_COMMON */ |
886 | ||
887 | ||
888 | #if WITH_COMMON | |
889 | ||
890 | /* For compatibility */ | |
891 | SIM_DESC simulator; | |
892 | ||
893 | /* mn10300 interrupt model */ | |
894 | ||
895 | enum interrupt_type | |
896 | { | |
897 | int_reset, | |
898 | int_nmi, | |
899 | int_intov1, | |
900 | int_intp10, | |
901 | int_intp11, | |
902 | int_intp12, | |
903 | int_intp13, | |
904 | int_intcm4, | |
905 | num_int_types | |
906 | }; | |
907 | ||
908 | char *interrupt_names[] = { | |
909 | "reset", | |
910 | "nmi", | |
911 | "intov1", | |
912 | "intp10", | |
913 | "intp11", | |
914 | "intp12", | |
915 | "intp13", | |
916 | "intcm4", | |
917 | NULL | |
918 | }; | |
919 | ||
920 | ||
921 | static void | |
922 | do_interrupt (sd, data) | |
923 | SIM_DESC sd; | |
924 | void *data; | |
925 | { | |
926 | #if 0 | |
927 | char **interrupt_name = (char**)data; | |
928 | enum interrupt_type inttype; | |
929 | inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names); | |
930 | ||
931 | /* For a hardware reset, drop everything and jump to the start | |
932 | address */ | |
933 | if (inttype == int_reset) | |
934 | { | |
935 | PC = 0; | |
936 | PSW = 0x20; | |
937 | ECR = 0; | |
938 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); | |
939 | } | |
940 | ||
941 | /* Deliver an NMI when allowed */ | |
942 | if (inttype == int_nmi) | |
943 | { | |
944 | if (PSW & PSW_NP) | |
945 | { | |
946 | /* We're already working on an NMI, so this one must wait | |
947 | around until the previous one is done. The processor | |
948 | ignores subsequent NMIs, so we don't need to count them. | |
949 | Just keep re-scheduling a single NMI until it manages to | |
950 | be delivered */ | |
951 | if (STATE_CPU (sd, 0)->pending_nmi != NULL) | |
952 | sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi); | |
953 | STATE_CPU (sd, 0)->pending_nmi = | |
954 | sim_events_schedule (sd, 1, do_interrupt, data); | |
955 | return; | |
956 | } | |
957 | else | |
958 | { | |
959 | /* NMI can be delivered. Do not deschedule pending_nmi as | |
960 | that, if still in the event queue, is a second NMI that | |
961 | needs to be delivered later. */ | |
962 | FEPC = PC; | |
963 | FEPSW = PSW; | |
964 | /* Set the FECC part of the ECR. */ | |
965 | ECR &= 0x0000ffff; | |
966 | ECR |= 0x10; | |
967 | PSW |= PSW_NP; | |
968 | PSW &= ~PSW_EP; | |
969 | PSW |= PSW_ID; | |
970 | PC = 0x10; | |
971 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); | |
972 | } | |
973 | } | |
974 | ||
975 | /* deliver maskable interrupt when allowed */ | |
976 | if (inttype > int_nmi && inttype < num_int_types) | |
977 | { | |
978 | if ((PSW & PSW_NP) || (PSW & PSW_ID)) | |
979 | { | |
980 | /* Can't deliver this interrupt, reschedule it for later */ | |
981 | sim_events_schedule (sd, 1, do_interrupt, data); | |
982 | return; | |
983 | } | |
984 | else | |
985 | { | |
986 | /* save context */ | |
987 | EIPC = PC; | |
988 | EIPSW = PSW; | |
989 | /* Disable further interrupts. */ | |
990 | PSW |= PSW_ID; | |
991 | /* Indicate that we're doing interrupt not exception processing. */ | |
992 | PSW &= ~PSW_EP; | |
993 | /* Clear the EICC part of the ECR, will set below. */ | |
994 | ECR &= 0xffff0000; | |
995 | switch (inttype) | |
996 | { | |
997 | case int_intov1: | |
998 | PC = 0x80; | |
999 | ECR |= 0x80; | |
1000 | break; | |
1001 | case int_intp10: | |
1002 | PC = 0x90; | |
1003 | ECR |= 0x90; | |
1004 | break; | |
1005 | case int_intp11: | |
1006 | PC = 0xa0; | |
1007 | ECR |= 0xa0; | |
1008 | break; | |
1009 | case int_intp12: | |
1010 | PC = 0xb0; | |
1011 | ECR |= 0xb0; | |
1012 | break; | |
1013 | case int_intp13: | |
1014 | PC = 0xc0; | |
1015 | ECR |= 0xc0; | |
1016 | break; | |
1017 | case int_intcm4: | |
1018 | PC = 0xd0; | |
1019 | ECR |= 0xd0; | |
1020 | break; | |
1021 | default: | |
1022 | /* Should never be possible. */ | |
1023 | sim_engine_abort (sd, NULL, NULL_CIA, | |
1024 | "do_interrupt - internal error - bad switch"); | |
1025 | break; | |
1026 | } | |
1027 | } | |
1028 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); | |
1029 | } | |
1030 | ||
1031 | /* some other interrupt? */ | |
1032 | sim_engine_abort (sd, NULL, NULL_CIA, | |
1033 | "do_interrupt - internal error - interrupt %d unknown", | |
1034 | inttype); | |
1035 | #endif /* 0 */ | |
1036 | } | |
1037 | ||
1038 | /* These default values correspond to expected usage for the chip. */ | |
1039 | ||
1040 | SIM_DESC | |
1041 | sim_open (kind, cb, abfd, argv) | |
1042 | SIM_OPEN_KIND kind; | |
1043 | host_callback *cb; | |
1044 | struct _bfd *abfd; | |
1045 | char **argv; | |
1046 | { | |
1047 | SIM_DESC sd = sim_state_alloc (kind, cb); | |
1048 | int mach; | |
1049 | mn10300_callback = cb; | |
1050 | ||
1051 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
1052 | ||
1053 | /* for compatibility */ | |
1054 | simulator = sd; | |
1055 | ||
1056 | /* FIXME: should be better way of setting up interrupts */ | |
1057 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
1058 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
1059 | STATE_WATCHPOINTS (sd)->interrupt_handler = do_interrupt; | |
1060 | STATE_WATCHPOINTS (sd)->interrupt_names = interrupt_names; | |
1061 | ||
1062 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
1063 | return 0; | |
1064 | ||
1065 | /* Allocate core managed memory */ | |
1066 | ||
1067 | /* "Mirror" the ROM addresses below 1MB. */ | |
1068 | sim_do_command (sd, "memory region 0,0x100000"); | |
1069 | ||
1070 | /* getopt will print the error message so we just have to exit if this fails. | |
1071 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
1072 | print_filtered. */ | |
1073 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
1074 | { | |
1075 | /* Uninstall the modules to avoid memory leaks, | |
1076 | file descriptor leaks, etc. */ | |
1077 | sim_module_uninstall (sd); | |
1078 | return 0; | |
1079 | } | |
1080 | ||
1081 | /* check for/establish the a reference program image */ | |
1082 | if (sim_analyze_program (sd, | |
1083 | (STATE_PROG_ARGV (sd) != NULL | |
1084 | ? *STATE_PROG_ARGV (sd) | |
1085 | : NULL), | |
1086 | abfd) != SIM_RC_OK) | |
1087 | { | |
1088 | sim_module_uninstall (sd); | |
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | /* establish any remaining configuration options */ | |
1093 | if (sim_config (sd) != SIM_RC_OK) | |
1094 | { | |
1095 | sim_module_uninstall (sd); | |
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
1100 | { | |
1101 | /* Uninstall the modules to avoid memory leaks, | |
1102 | file descriptor leaks, etc. */ | |
1103 | sim_module_uninstall (sd); | |
1104 | return 0; | |
1105 | } | |
1106 | ||
1107 | ||
1108 | /* set machine specific configuration */ | |
1109 | /* STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT */ | |
1110 | /* | PSW_CY | PSW_OV | PSW_S | PSW_Z); */ | |
1111 | ||
1112 | return sd; | |
1113 | } | |
1114 | ||
1115 | ||
1116 | void | |
1117 | sim_close (sd, quitting) | |
1118 | SIM_DESC sd; | |
1119 | int quitting; | |
1120 | { | |
1121 | sim_module_uninstall (sd); | |
1122 | } | |
1123 | ||
1124 | ||
1125 | SIM_RC | |
1126 | sim_create_inferior (sd, prog_bfd, argv, env) | |
1127 | SIM_DESC sd; | |
1128 | struct _bfd *prog_bfd; | |
1129 | char **argv; | |
1130 | char **env; | |
1131 | { | |
1132 | memset (&State, 0, sizeof (State)); | |
1133 | if (prog_bfd != NULL) { | |
1134 | PC = bfd_get_start_address (prog_bfd); | |
1135 | } else { | |
1136 | PC = 0; | |
1137 | } | |
1138 | CIA_SET (STATE_CPU (sd, 0), (unsigned64) PC); | |
1139 | ||
1140 | return SIM_RC_OK; | |
1141 | } | |
1142 | ||
1143 | void | |
1144 | sim_do_command (sd, cmd) | |
1145 | SIM_DESC sd; | |
1146 | char *cmd; | |
1147 | { | |
1148 | char *mm_cmd = "memory-map"; | |
1149 | char *int_cmd = "interrupt"; | |
1150 | ||
1151 | if (sim_args_command (sd, cmd) != SIM_RC_OK) | |
1152 | { | |
1153 | if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0)) | |
1154 | sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n"); | |
1155 | else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0) | |
1156 | sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n"); | |
1157 | else | |
1158 | sim_io_eprintf (sd, "Unknown command `%s'\n", cmd); | |
1159 | } | |
1160 | } | |
1161 | #endif /* WITH_COMMON */ | |
1162 | ||
1163 | /* FIXME These would more efficient to use than load_mem/store_mem, | |
1164 | but need to be changed to use the memory map. */ | |
1165 | ||
1166 | uint8 | |
1167 | get_byte (x) | |
1168 | uint8 *x; | |
1169 | { | |
1170 | return *x; | |
1171 | } | |
1172 | ||
1173 | uint16 | |
1174 | get_half (x) | |
1175 | uint8 *x; | |
1176 | { | |
1177 | uint8 *a = x; | |
1178 | return (a[1] << 8) + (a[0]); | |
1179 | } | |
1180 | ||
1181 | uint32 | |
1182 | get_word (x) | |
1183 | uint8 *x; | |
1184 | { | |
1185 | uint8 *a = x; | |
1186 | return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]); | |
1187 | } | |
1188 | ||
1189 | void | |
1190 | put_byte (addr, data) | |
1191 | uint8 *addr; | |
1192 | uint8 data; | |
1193 | { | |
1194 | uint8 *a = addr; | |
1195 | a[0] = data; | |
1196 | } | |
1197 | ||
1198 | void | |
1199 | put_half (addr, data) | |
1200 | uint8 *addr; | |
1201 | uint16 data; | |
1202 | { | |
1203 | uint8 *a = addr; | |
1204 | a[0] = data & 0xff; | |
1205 | a[1] = (data >> 8) & 0xff; | |
1206 | } | |
1207 | ||
1208 | void | |
1209 | put_word (addr, data) | |
1210 | uint8 *addr; | |
1211 | uint32 data; | |
1212 | { | |
1213 | uint8 *a = addr; | |
1214 | a[0] = data & 0xff; | |
1215 | a[1] = (data >> 8) & 0xff; | |
1216 | a[2] = (data >> 16) & 0xff; | |
1217 | a[3] = (data >> 24) & 0xff; | |
1218 | } | |
1219 | ||
1220 | int | |
1221 | sim_fetch_register (sd, rn, memory, length) | |
1222 | SIM_DESC sd; | |
1223 | int rn; | |
1224 | unsigned char *memory; | |
1225 | int length; | |
1226 | { | |
1227 | put_word (memory, State.regs[rn]); | |
1228 | return -1; | |
1229 | } | |
1230 | ||
1231 | int | |
1232 | sim_store_register (sd, rn, memory, length) | |
1233 | SIM_DESC sd; | |
1234 | int rn; | |
1235 | unsigned char *memory; | |
1236 | int length; | |
1237 | { | |
1238 | State.regs[rn] = get_word (memory); | |
1239 | return -1; | |
1240 | } |