[deliverable/binutils-gdb.git] / sim / mn10300 / mn10300_sim.h

#include <stdio.h>
#include <ctype.h>
#include "ansidecl.h"
#include "gdb/callback.h"
#include "opcode/mn10300.h"
#include <limits.h>
#include "gdb/remote-sim.h"
#include "bfd.h"
#include "sim-fpu.h"

extern host_callback *mn10300_callback;
extern SIM_DESC simulator;

#define DEBUG_TRACE		0x00000001
#define DEBUG_VALUES		0x00000002

extern int mn10300_debug;

typedef unsigned8 uint8;
typedef signed8 int8;
typedef unsigned16 uint16;
typedef signed16 int16;
typedef unsigned32 uint32;
typedef signed32 int32;

typedef struct
{
  uint32 low, high;
} dword;
typedef uint32 reg_t;

struct simops 
{
  long opcode;
  long mask;
  void (*func)();
  int length;
  int format;
  int numops;
  int operands[16];
};

/* The current state of the processor; registers, memory, etc.  */

struct _state
{
  reg_t regs[32];		/* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
				   lir, lar, mdrq, plus some room for processor
				   specific regs.  */
  union
  {
    reg_t fs[32]; /* FS0-31 */
    dword fd[16]; /* FD0,2,...,30 */
  } fpregs;
  uint8 *mem;			/* main memory */
  int exception;
  int exited;

  /* All internal state modified by signal_exception() that may need to be
     rolled back for passing moment-of-exception image back to gdb. */
  reg_t exc_trigger_regs[32];
  reg_t exc_suspend_regs[32];
  int exc_suspended;

#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
};

extern struct _state State;
extern uint32 OP[4];
extern struct simops Simops[];

#define PC	(State.regs[REG_PC])
#define SP	(State.regs[REG_SP])

#define PSW (State.regs[11])
#define PSW_Z 0x1
#define PSW_N 0x2
#define PSW_C 0x4
#define PSW_V 0x8
#define PSW_IE LSBIT (11)
#define PSW_LM LSMASK (10, 8)

#define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
#define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)

#define REG_D0 0
#define REG_A0 4
#define REG_SP 8
#define REG_PC 9
#define REG_MDR 10
#define REG_PSW 11
#define REG_LIR 12
#define REG_LAR 13
#define REG_MDRQ 14
#define REG_E0 15
#define REG_SSP 23
#define REG_MSP 24
#define REG_USP 25
#define REG_MCRH 26
#define REG_MCRL 27
#define REG_MCVF 28

#define REG_FPCR 29

#define FPCR (State.regs[REG_FPCR])

#define FCC_MASK LSMASK (21, 18)
#define RM_MASK  LSMASK (17, 16) /* Must always be zero.  */
#define EC_MASK  LSMASK (14, 10)
#define EE_MASK  LSMASK ( 9,  5)
#define EF_MASK  LSMASK ( 4,  0)
#define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)

#define FCC_L LSBIT (21)
#define FCC_G LSBIT (20)
#define FCC_E LSBIT (19)
#define FCC_U LSBIT (18)

#define EC_V LSBIT (14)
#define EC_Z LSBIT (13)
#define EC_O LSBIT (12)
#define EC_U LSBIT (11)
#define EC_I LSBIT (10)

#define EE_V LSBIT (9)
#define EE_Z LSBIT (8)
#define EE_O LSBIT (7)
#define EE_U LSBIT (6)
#define EE_I LSBIT (5)

#define EF_V LSBIT (4)
#define EF_Z LSBIT (3)
#define EF_O LSBIT (2)
#define EF_U LSBIT (1)
#define EF_I LSBIT (0)

#define PSW_FE LSBIT(20)
#define FPU_DISABLED !(PSW & PSW_FE)

#define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
#define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
#define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]

#define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
#define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
#define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
#define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))

#ifdef _WIN32
#define SIGTRAP 5
#define SIGQUIT 3
#endif

#define FETCH32(a,b,c,d) \
 ((a)+((b)<<8)+((c)<<16)+((d)<<24))

#define FETCH24(a,b,c) \
 ((a)+((b)<<8)+((c)<<16))

#define FETCH16(a,b) ((a)+((b)<<8))

#define load_byte(ADDR) \
sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))

#define load_half(ADDR) \
sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))

#define load_word(ADDR) \
sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))

#define load_dword(ADDR) \
u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
				   PC, read_map, (ADDR)))

static INLINE dword
u642dw (unsigned64 dw)
{
  dword r;

  r.low = (unsigned32)dw;
  r.high = (unsigned32)(dw >> 32);
  return r;
}

#define store_byte(ADDR, DATA) \
sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
			    PC, write_map, (ADDR), (DATA))


#define store_half(ADDR, DATA) \
sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
			    PC, write_map, (ADDR), (DATA))


#define store_word(ADDR, DATA) \
sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
			    PC, write_map, (ADDR), (DATA))
#define store_dword(ADDR, DATA) \
sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
			    PC, write_map, (ADDR), dw2u64 (DATA))

static INLINE unsigned64
dw2u64 (dword data)
{
  return data.low | (((unsigned64)data.high) << 32);
}

/* Function declarations.  */

uint32 get_word (uint8 *);
uint16 get_half (uint8 *);
uint8 get_byte (uint8 *);
void put_word (uint8 *, uint32);
void put_half (uint8 *, uint16);
void put_byte (uint8 *, uint8);

extern uint8 *map (SIM_ADDR addr);

INLINE_SIM_MAIN (void) genericAdd (unsigned32 source, unsigned32 destReg);
INLINE_SIM_MAIN (void) genericSub (unsigned32 source, unsigned32 destReg);
INLINE_SIM_MAIN (void) genericCmp (unsigned32 leftOpnd, unsigned32 rightOpnd);
INLINE_SIM_MAIN (void) genericOr (unsigned32 source, unsigned32 destReg);
INLINE_SIM_MAIN (void) genericXor (unsigned32 source, unsigned32 destReg);
INLINE_SIM_MAIN (void) genericBtst (unsigned32 leftOpnd, unsigned32 rightOpnd);
INLINE_SIM_MAIN (int) syscall_read_mem (host_callback *cb,
					struct cb_syscall *sc,
					unsigned long taddr,
					char *buf,
					int bytes);
INLINE_SIM_MAIN (int) syscall_write_mem (host_callback *cb,
					 struct cb_syscall *sc,
					 unsigned long taddr,
					 const char *buf,
					 int bytes); 
INLINE_SIM_MAIN (void) do_syscall (void);
void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);

void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);

void fpu_disabled_exception     (SIM_DESC, sim_cpu *, address_word);
void fpu_unimp_exception        (SIM_DESC, sim_cpu *, address_word);
void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word);

extern const struct fp_prec_t
{
  void (* reg2val) (const void *, sim_fpu *);
  int (*  round)   (sim_fpu *);
  void (* val2reg) (const sim_fpu *, void *);
} fp_single_prec, fp_double_prec;

#define FP_SINGLE (&fp_single_prec)
#define FP_DOUBLE (&fp_double_prec)

void fpu_rsqrt  (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
void fpu_sqrt   (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
void fpu_cmp    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *);
void fpu_add    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
void fpu_sub    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
void fpu_mul    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
void fpu_div    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
void fpu_fmadd  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
void fpu_fmsub  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
Commit	Line	Data
c906108c SS	1	#include <stdio.h>
	2	#include <ctype.h>
	3	#include "ansidecl.h"
3c25f8c7	4	#include "gdb/callback.h"
c906108c SS	5	#include "opcode/mn10300.h"
c906108c SS	6	#include <limits.h>
3c25f8c7	7	#include "gdb/remote-sim.h"
c906108c	8	#include "bfd.h"
c76b4bab	9	#include "sim-fpu.h"
c906108c	10
c906108c SS	11	extern host_callback *mn10300_callback;
	12	extern SIM_DESC simulator;
	13
	14	#define DEBUG_TRACE 0x00000001
	15	#define DEBUG_VALUES 0x00000002
	16
	17	extern int mn10300_debug;
	18
b0e4c8a5 MF	19	typedef unsigned8 uint8;
	20	typedef signed8 int8;
	21	typedef unsigned16 uint16;
	22	typedef signed16 int16;
	23	typedef unsigned32 uint32;
	24	typedef signed32 int32;
c906108c	25
c76b4bab AO	26	typedef struct
	27	{
	28	uint32 low, high;
	29	} dword;
c906108c SS	30	typedef uint32 reg_t;
	31
	32	struct simops
	33	{
	34	long opcode;
	35	long mask;
	36	void (*func)();
	37	int length;
	38	int format;
	39	int numops;
	40	int operands[16];
	41	};
	42
	43	/* The current state of the processor; registers, memory, etc. */
	44
	45	struct _state
	46	{
	47	reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
	48	lir, lar, mdrq, plus some room for processor
	49	specific regs. */
c76b4bab AO	50	union
	51	{
	52	reg_t fs[32]; /* FS0-31 */
	53	dword fd[16]; /* FD0,2,...,30 */
	54	} fpregs;
c906108c SS	55	uint8 mem; / main memory */
	56	int exception;
	57	int exited;
	58
	59	/* All internal state modified by signal_exception() that may need to be
	60	rolled back for passing moment-of-exception image back to gdb. */
	61	reg_t exc_trigger_regs[32];
	62	reg_t exc_suspend_regs[32];
	63	int exc_suspended;
	64
	65	#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
	66	#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
	67	#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
	68	};
	69
	70	extern struct _state State;
	71	extern uint32 OP[4];
	72	extern struct simops Simops[];
	73
	74	#define PC (State.regs[REG_PC])
	75	#define SP (State.regs[REG_SP])
	76
	77	#define PSW (State.regs[11])
	78	#define PSW_Z 0x1
	79	#define PSW_N 0x2
	80	#define PSW_C 0x4
	81	#define PSW_V 0x8
	82	#define PSW_IE LSBIT (11)
	83	#define PSW_LM LSMASK (10, 8)
	84
	85	#define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
	86	#define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
	87
	88	#define REG_D0 0
	89	#define REG_A0 4
	90	#define REG_SP 8
	91	#define REG_PC 9
	92	#define REG_MDR 10
	93	#define REG_PSW 11
	94	#define REG_LIR 12
	95	#define REG_LAR 13
	96	#define REG_MDRQ 14
c2d11a7d JM	97	#define REG_E0 15
	98	#define REG_SSP 23
	99	#define REG_MSP 24
	100	#define REG_USP 25
	101	#define REG_MCRH 26
	102	#define REG_MCRL 27
	103	#define REG_MCVF 28
c906108c	104
c76b4bab AO	105	#define REG_FPCR 29
	106
	107	#define FPCR (State.regs[REG_FPCR])
	108
	109	#define FCC_MASK LSMASK (21, 18)
	110	#define RM_MASK LSMASK (17, 16) /* Must always be zero. */
	111	#define EC_MASK LSMASK (14, 10)
	112	#define EE_MASK LSMASK ( 9, 5)
	113	#define EF_MASK LSMASK ( 4, 0)
	114	#define FPCR_MASK (FCC_MASK \| EC_MASK \| EE_MASK \| EF_MASK)
	115
	116	#define FCC_L LSBIT (21)
	117	#define FCC_G LSBIT (20)
	118	#define FCC_E LSBIT (19)
	119	#define FCC_U LSBIT (18)
	120
	121	#define EC_V LSBIT (14)
	122	#define EC_Z LSBIT (13)
	123	#define EC_O LSBIT (12)
	124	#define EC_U LSBIT (11)
	125	#define EC_I LSBIT (10)
	126
	127	#define EE_V LSBIT (9)
	128	#define EE_Z LSBIT (8)
	129	#define EE_O LSBIT (7)
	130	#define EE_U LSBIT (6)
	131	#define EE_I LSBIT (5)
	132
	133	#define EF_V LSBIT (4)
	134	#define EF_Z LSBIT (3)
	135	#define EF_O LSBIT (2)
	136	#define EF_U LSBIT (1)
	137	#define EF_I LSBIT (0)
	138
	139	#define PSW_FE LSBIT(20)
	140	#define FPU_DISABLED !(PSW & PSW_FE)
	141
	142	#define XS2FS(X,S) State.fpregs.fs[((X<<4)\|(S))]
	143	#define AS2FS(A,S) State.fpregs.fs[((A<<2)\|(S))]
	144	#define Xf2FD(X,f) State.fpregs.fd[((X<<3)\|(f))]
	145
	146	#define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
	147	#define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
	148	#define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
	149	#define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
	150
c906108c SS	151	#ifdef _WIN32
	152	#define SIGTRAP 5
	153	#define SIGQUIT 3
	154	#endif
	155
c906108c SS	156	#define FETCH32(a,b,c,d) \
	157	((a)+((b)<<8)+((c)<<16)+((d)<<24))
	158
	159	#define FETCH24(a,b,c) \
	160	((a)+((b)<<8)+((c)<<16))
	161
	162	#define FETCH16(a,b) ((a)+((b)<<8))
	163
	164	#define load_byte(ADDR) \
	165	sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
	166
	167	#define load_half(ADDR) \
	168	sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
	169
	170	#define load_word(ADDR) \
	171	sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
	172
c76b4bab AO	173	#define load_dword(ADDR) \
	174	u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
	175	PC, read_map, (ADDR)))
	176
	177	static INLINE dword
	178	u642dw (unsigned64 dw)
	179	{
	180	dword r;
	181
	182	r.low = (unsigned32)dw;
	183	r.high = (unsigned32)(dw >> 32);
	184	return r;
	185	}
	186
c906108c SS	187	#define store_byte(ADDR, DATA) \
	188	sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
	189	PC, write_map, (ADDR), (DATA))
	190
	191
	192	#define store_half(ADDR, DATA) \
	193	sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
	194	PC, write_map, (ADDR), (DATA))
	195
	196
	197	#define store_word(ADDR, DATA) \
	198	sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
	199	PC, write_map, (ADDR), (DATA))
c76b4bab AO	200	#define store_dword(ADDR, DATA) \
	201	sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
	202	PC, write_map, (ADDR), dw2u64 (DATA))
	203
	204	static INLINE unsigned64
	205	dw2u64 (dword data)
	206	{
	207	return data.low \| (((unsigned64)data.high) << 32);
	208	}
c906108c SS	209
	210	/* Function declarations. */
	211
489503ee AO	212	uint32 get_word (uint8 *);
	213	uint16 get_half (uint8 *);
	214	uint8 get_byte (uint8 *);
	215	void put_word (uint8 *, uint32);
	216	void put_half (uint8 *, uint16);
	217	void put_byte (uint8 *, uint8);
	218
	219	extern uint8 *map (SIM_ADDR addr);
	220
	221	INLINE_SIM_MAIN (void) genericAdd (unsigned32 source, unsigned32 destReg);
	222	INLINE_SIM_MAIN (void) genericSub (unsigned32 source, unsigned32 destReg);
	223	INLINE_SIM_MAIN (void) genericCmp (unsigned32 leftOpnd, unsigned32 rightOpnd);
	224	INLINE_SIM_MAIN (void) genericOr (unsigned32 source, unsigned32 destReg);
	225	INLINE_SIM_MAIN (void) genericXor (unsigned32 source, unsigned32 destReg);
	226	INLINE_SIM_MAIN (void) genericBtst (unsigned32 leftOpnd, unsigned32 rightOpnd);
	227	INLINE_SIM_MAIN (int) syscall_read_mem (host_callback *cb,
	228	struct cb_syscall *sc,
	229	unsigned long taddr,
	230	char *buf,
	231	int bytes);
	232	INLINE_SIM_MAIN (int) syscall_write_mem (host_callback *cb,
	233	struct cb_syscall *sc,
	234	unsigned long taddr,
	235	const char *buf,
	236	int bytes);
	237	INLINE_SIM_MAIN (void) do_syscall (void);
c906108c SS	238	void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);
	239
	240	void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
	241	void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
	242	void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
c76b4bab AO	243
	244	void fpu_disabled_exception (SIM_DESC, sim_cpu *, address_word);
	245	void fpu_unimp_exception (SIM_DESC, sim_cpu *, address_word);
	246	void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word);
	247
	248	extern const struct fp_prec_t
	249	{
	250	void (* reg2val) (const void , sim_fpu );
	251	int (* round) (sim_fpu *);
	252	void (* val2reg) (const sim_fpu , void );
	253	} fp_single_prec, fp_double_prec;
	254
	255	#define FP_SINGLE (&fp_single_prec)
	256	#define FP_DOUBLE (&fp_double_prec)
	257
	258	void fpu_rsqrt (SIM_DESC, sim_cpu , address_word, const void , void , const struct fp_prec_t );
	259	void fpu_sqrt (SIM_DESC, sim_cpu , address_word, const void , void , const struct fp_prec_t );
	260	void fpu_cmp (SIM_DESC, sim_cpu , address_word, const void , const void , const struct fp_prec_t );
	261	void fpu_add (SIM_DESC, sim_cpu , address_word, const void , const void , void , const struct fp_prec_t *);
	262	void fpu_sub (SIM_DESC, sim_cpu , address_word, const void , const void , void , const struct fp_prec_t *);
	263	void fpu_mul (SIM_DESC, sim_cpu , address_word, const void , const void , void , const struct fp_prec_t *);
	264	void fpu_div (SIM_DESC, sim_cpu , address_word, const void , const void , void , const struct fp_prec_t *);
	265	void fpu_fmadd (SIM_DESC, sim_cpu , address_word, const void , const void , const void , void , const struct fp_prec_t );
	266	void fpu_fmsub (SIM_DESC, sim_cpu , address_word, const void , const void , const void , void , const struct fp_prec_t );
	267	void fpu_fnmadd (SIM_DESC, sim_cpu , address_word, const void , const void , const void , void , const struct fp_prec_t );
	268	void fpu_fnmsub (SIM_DESC, sim_cpu , address_word, const void , const void , const void , void , const struct fp_prec_t );