Commit | Line | Data |
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05ccbdfd JL |
1 | #include "config.h" |
2 | ||
3 | #include <signal.h> | |
4 | #ifdef HAVE_UNISTD_H | |
5 | #include <unistd.h> | |
6 | #endif | |
7 | #include "mn10300_sim.h" | |
8 | #include "simops.h" | |
9 | #include "sys/syscall.h" | |
10 | #include "bfd.h" | |
11 | #include <errno.h> | |
12 | #include <sys/stat.h> | |
13 | #include <sys/times.h> | |
14 | #include <sys/time.h> | |
15 | ||
9f4a551e JL |
16 | #define REG0(X) ((X) & 0x3) |
17 | #define REG1(X) (((X) & 0xc) >> 2) | |
95d18eb7 | 18 | #define REG0_4(X) (((X) & 0x30) >> 4) |
9f4a551e JL |
19 | #define REG0_8(X) (((X) & 0x300) >> 8) |
20 | #define REG1_8(X) (((X) & 0xc00) >> 10) | |
2e8f4133 | 21 | #define REG0_16(X) (((X) & 0x30000) >> 16) |
9f4a551e | 22 | #define REG1_16(X) (((X) & 0xc0000) >> 18) |
05ccbdfd | 23 | \f |
707641f6 | 24 | /* mov imm8, dn */ |
d2523010 JL |
25 | void OP_8000 (insn, extension) |
26 | unsigned long insn, extension; | |
05ccbdfd | 27 | { |
9f4a551e | 28 | State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff); |
05ccbdfd JL |
29 | } |
30 | ||
707641f6 | 31 | /* mov dm, dn */ |
d2523010 JL |
32 | void OP_80 (insn, extension) |
33 | unsigned long insn, extension; | |
05ccbdfd | 34 | { |
9f4a551e | 35 | State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)]; |
05ccbdfd JL |
36 | } |
37 | ||
707641f6 | 38 | /* mov dm, an */ |
d2523010 JL |
39 | void OP_F1E0 (insn, extension) |
40 | unsigned long insn, extension; | |
05ccbdfd | 41 | { |
9f4a551e | 42 | State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)]; |
05ccbdfd JL |
43 | } |
44 | ||
707641f6 | 45 | /* mov am, dn */ |
d2523010 JL |
46 | void OP_F1D0 (insn, extension) |
47 | unsigned long insn, extension; | |
05ccbdfd | 48 | { |
9f4a551e | 49 | State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)]; |
05ccbdfd JL |
50 | } |
51 | ||
707641f6 | 52 | /* mov imm8, an */ |
d2523010 JL |
53 | void OP_9000 (insn, extension) |
54 | unsigned long insn, extension; | |
05ccbdfd | 55 | { |
9f4a551e | 56 | State.regs[REG_A0 + REG0_8 (insn)] = insn & 0xff; |
05ccbdfd JL |
57 | } |
58 | ||
707641f6 | 59 | /* mov am, an */ |
d2523010 JL |
60 | void OP_90 (insn, extension) |
61 | unsigned long insn, extension; | |
05ccbdfd | 62 | { |
9f4a551e | 63 | State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)]; |
05ccbdfd JL |
64 | } |
65 | ||
1f3bea21 | 66 | /* mov sp, an */ |
d2523010 JL |
67 | void OP_3C (insn, extension) |
68 | unsigned long insn, extension; | |
05ccbdfd | 69 | { |
9f4a551e | 70 | State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_SP]; |
05ccbdfd JL |
71 | } |
72 | ||
1f3bea21 | 73 | /* mov am, sp */ |
d2523010 JL |
74 | void OP_F2F0 (insn, extension) |
75 | unsigned long insn, extension; | |
05ccbdfd | 76 | { |
9f4a551e | 77 | State.regs[REG_SP] = State.regs[REG_A0 + REG1 (insn)]; |
05ccbdfd JL |
78 | } |
79 | ||
707641f6 | 80 | /* mov psw, dn */ |
d2523010 JL |
81 | void OP_F2E4 (insn, extension) |
82 | unsigned long insn, extension; | |
05ccbdfd | 83 | { |
9f4a551e | 84 | State.regs[REG_D0 + REG0 (insn)] = PSW; |
05ccbdfd JL |
85 | } |
86 | ||
707641f6 | 87 | /* mov dm, psw */ |
d2523010 JL |
88 | void OP_F2F3 (insn, extension) |
89 | unsigned long insn, extension; | |
05ccbdfd | 90 | { |
9f4a551e | 91 | PSW = State.regs[REG_D0 + REG1 (insn)]; |
05ccbdfd JL |
92 | } |
93 | ||
707641f6 | 94 | /* mov mdr, dn */ |
d2523010 JL |
95 | void OP_F2E0 (insn, extension) |
96 | unsigned long insn, extension; | |
05ccbdfd | 97 | { |
9f4a551e | 98 | State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDR]; |
05ccbdfd JL |
99 | } |
100 | ||
707641f6 | 101 | /* mov dm, mdr */ |
d2523010 JL |
102 | void OP_F2F2 (insn, extension) |
103 | unsigned long insn, extension; | |
05ccbdfd | 104 | { |
9f4a551e | 105 | State.regs[REG_MDR] = State.regs[REG_D0 + REG1 (insn)]; |
05ccbdfd JL |
106 | } |
107 | ||
2e35551c | 108 | /* mov (am), dn */ |
d2523010 JL |
109 | void OP_70 (insn, extension) |
110 | unsigned long insn, extension; | |
05ccbdfd | 111 | { |
9f4a551e JL |
112 | State.regs[REG_D0 + REG1 (insn)] |
113 | = load_mem (State.regs[REG_A0 + REG0 (insn)], 4); | |
05ccbdfd JL |
114 | } |
115 | ||
2e35551c | 116 | /* mov (d8,am), dn */ |
d2523010 JL |
117 | void OP_F80000 (insn, extension) |
118 | unsigned long insn, extension; | |
05ccbdfd | 119 | { |
9f4a551e JL |
120 | State.regs[REG_D0 + REG1_8 (insn)] |
121 | = load_mem ((State.regs[REG_A0 + REG0_8 (insn)] | |
2e35551c | 122 | + SEXT8 (insn & 0xff)), 4); |
05ccbdfd JL |
123 | } |
124 | ||
ecb4b5a3 | 125 | /* mov (d16,am), dn */ |
d2523010 JL |
126 | void OP_FA000000 (insn, extension) |
127 | unsigned long insn, extension; | |
05ccbdfd | 128 | { |
9f4a551e JL |
129 | State.regs[REG_D0 + REG1_16 (insn)] |
130 | = load_mem ((State.regs[REG_A0 + REG0_16 (insn)] | |
ecb4b5a3 | 131 | + SEXT16 (insn & 0xffff)), 4); |
05ccbdfd JL |
132 | } |
133 | ||
de0dce7c | 134 | /* mov (d32,am), dn */ |
d2523010 JL |
135 | void OP_FC000000 (insn, extension) |
136 | unsigned long insn, extension; | |
05ccbdfd | 137 | { |
9f4a551e JL |
138 | State.regs[REG_D0 + REG1_16 (insn)] |
139 | = load_mem ((State.regs[REG_A0 + REG0_16 (insn)] | |
7c52bf32 | 140 | + ((insn & 0xffff) << 16) + extension), 4); |
05ccbdfd JL |
141 | } |
142 | ||
707641f6 | 143 | /* mov (d8,sp), dn */ |
d2523010 JL |
144 | void OP_5800 (insn, extension) |
145 | unsigned long insn, extension; | |
05ccbdfd | 146 | { |
9f4a551e | 147 | State.regs[REG_D0 + REG0_8 (insn)] |
ecb4b5a3 | 148 | = load_mem (State.regs[REG_SP] + (insn & 0xff), 4); |
05ccbdfd JL |
149 | } |
150 | ||
ecb4b5a3 | 151 | /* mov (d16,sp), dn */ |
d2523010 JL |
152 | void OP_FAB40000 (insn, extension) |
153 | unsigned long insn, extension; | |
05ccbdfd | 154 | { |
9f4a551e | 155 | State.regs[REG_D0 + REG0_16 (insn)] |
ecb4b5a3 | 156 | = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4); |
05ccbdfd JL |
157 | } |
158 | ||
de0dce7c | 159 | /* mov (d32,sp), dn */ |
d2523010 JL |
160 | void OP_FCB40000 (insn, extension) |
161 | unsigned long insn, extension; | |
05ccbdfd | 162 | { |
9f4a551e | 163 | State.regs[REG_D0 + REG0_16 (insn)] |
de0dce7c | 164 | = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4); |
05ccbdfd JL |
165 | } |
166 | ||
f5f13c1d | 167 | /* mov (di,am), dn */ |
d2523010 JL |
168 | void OP_F300 (insn, extension) |
169 | unsigned long insn, extension; | |
05ccbdfd | 170 | { |
95d18eb7 | 171 | State.regs[REG_D0 + REG0_4 (insn)] |
9f4a551e JL |
172 | = load_mem ((State.regs[REG_A0 + REG0 (insn)] |
173 | + State.regs[REG_D0 + REG1 (insn)]), 4); | |
05ccbdfd JL |
174 | } |
175 | ||
707641f6 | 176 | /* mov (abs16), dn */ |
d2523010 JL |
177 | void OP_300000 (insn, extension) |
178 | unsigned long insn, extension; | |
05ccbdfd | 179 | { |
9f4a551e | 180 | State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 4); |
05ccbdfd JL |
181 | } |
182 | ||
de0dce7c | 183 | /* mov (abs32), dn */ |
d2523010 JL |
184 | void OP_FCA40000 (insn, extension) |
185 | unsigned long insn, extension; | |
05ccbdfd | 186 | { |
9f4a551e | 187 | State.regs[REG_D0 + REG0_16 (insn)] |
de0dce7c | 188 | = load_mem ((((insn & 0xffff) << 16) + extension), 4); |
05ccbdfd JL |
189 | } |
190 | ||
707641f6 | 191 | /* mov (am), an */ |
d2523010 JL |
192 | void OP_F000 (insn, extension) |
193 | unsigned long insn, extension; | |
05ccbdfd | 194 | { |
9f4a551e JL |
195 | State.regs[REG_A0 + REG1 (insn)] |
196 | = load_mem (State.regs[REG_A0 + REG0 (insn)], 4); | |
05ccbdfd JL |
197 | } |
198 | ||
2e35551c | 199 | /* mov (d8,am), an */ |
d2523010 JL |
200 | void OP_F82000 (insn, extension) |
201 | unsigned long insn, extension; | |
05ccbdfd | 202 | { |
9f4a551e JL |
203 | State.regs[REG_A0 + REG1_8 (insn)] |
204 | = load_mem ((State.regs[REG_A0 + REG0_8 (insn)] | |
2e35551c | 205 | + SEXT8 (insn & 0xff)), 4); |
05ccbdfd JL |
206 | } |
207 | ||
ecb4b5a3 | 208 | /* mov (d16,am), an */ |
d2523010 JL |
209 | void OP_FA200000 (insn, extension) |
210 | unsigned long insn, extension; | |
05ccbdfd | 211 | { |
9f4a551e JL |
212 | State.regs[REG_A0 + REG1_16 (insn)] |
213 | = load_mem ((State.regs[REG_A0 + REG0_16 (insn)] | |
ecb4b5a3 | 214 | + SEXT16 (insn & 0xffff)), 4); |
05ccbdfd JL |
215 | } |
216 | ||
de0dce7c | 217 | /* mov (d32,am), an */ |
d2523010 JL |
218 | void OP_FC200000 (insn, extension) |
219 | unsigned long insn, extension; | |
05ccbdfd | 220 | { |
9f4a551e JL |
221 | State.regs[REG_A0 + REG1_16 (insn)] |
222 | = load_mem ((State.regs[REG_A0 + REG0_16 (insn)] | |
de0dce7c | 223 | + ((insn & 0xffff) << 16) + extension), 4); |
05ccbdfd JL |
224 | } |
225 | ||
707641f6 | 226 | /* mov (d8,sp), an */ |
d2523010 JL |
227 | void OP_5C00 (insn, extension) |
228 | unsigned long insn, extension; | |
05ccbdfd | 229 | { |
9f4a551e | 230 | State.regs[REG_A0 + REG0_8 (insn)] |
ecb4b5a3 | 231 | = load_mem (State.regs[REG_SP] + (insn & 0xff), 4); |
05ccbdfd JL |
232 | } |
233 | ||
ecb4b5a3 | 234 | /* mov (d16,sp), an */ |
d2523010 JL |
235 | void OP_FAB00000 (insn, extension) |
236 | unsigned long insn, extension; | |
05ccbdfd | 237 | { |
9f4a551e | 238 | State.regs[REG_A0 + REG0_16 (insn)] |
ecb4b5a3 | 239 | = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4); |
05ccbdfd JL |
240 | } |
241 | ||
de0dce7c | 242 | /* mov (d32,sp), an */ |
d2523010 JL |
243 | void OP_FCB00000 (insn, extension) |
244 | unsigned long insn, extension; | |
05ccbdfd | 245 | { |
9f4a551e | 246 | State.regs[REG_A0 + REG0_16 (insn)] |
de0dce7c | 247 | = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4); |
05ccbdfd JL |
248 | } |
249 | ||
de0dce7c | 250 | /* mov (di,am), an */ |
d2523010 JL |
251 | void OP_F380 (insn, extension) |
252 | unsigned long insn, extension; | |
05ccbdfd | 253 | { |
95d18eb7 | 254 | State.regs[REG_A0 + REG0_4 (insn)] |
9f4a551e JL |
255 | = load_mem ((State.regs[REG_A0 + REG0 (insn)] |
256 | + State.regs[REG_D0 + REG1 (insn)]), 4); | |
05ccbdfd JL |
257 | } |
258 | ||
ecb4b5a3 | 259 | /* mov (abs16), an */ |
d2523010 JL |
260 | void OP_FAA00000 (insn, extension) |
261 | unsigned long insn, extension; | |
05ccbdfd | 262 | { |
9f4a551e | 263 | State.regs[REG_A0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 4); |
05ccbdfd JL |
264 | } |
265 | ||
de0dce7c | 266 | /* mov (abs32), an */ |
d2523010 JL |
267 | void OP_FCA00000 (insn, extension) |
268 | unsigned long insn, extension; | |
05ccbdfd | 269 | { |
9f4a551e | 270 | State.regs[REG_A0 + REG0_16 (insn)] |
de0dce7c | 271 | = load_mem ((((insn & 0xffff) << 16) + extension), 4); |
05ccbdfd JL |
272 | } |
273 | ||
2e35551c | 274 | /* mov (d8,am), sp */ |
d2523010 JL |
275 | void OP_F8F000 (insn, extension) |
276 | unsigned long insn, extension; | |
05ccbdfd | 277 | { |
2e35551c | 278 | State.regs[REG_SP] |
9f4a551e | 279 | = load_mem ((State.regs[REG_A0 + REG0_8 (insn)] |
2e35551c | 280 | + SEXT8 (insn & 0xff)), 4); |
05ccbdfd JL |
281 | } |
282 | ||
707641f6 | 283 | /* mov dm, (an) */ |
d2523010 JL |
284 | void OP_60 (insn, extension) |
285 | unsigned long insn, extension; | |
05ccbdfd | 286 | { |
9f4a551e JL |
287 | store_mem (State.regs[REG_A0 + REG0 (insn)], 4, |
288 | State.regs[REG_D0 + REG1 (insn)]); | |
05ccbdfd JL |
289 | } |
290 | ||
2e35551c | 291 | /* mov dm, (d8,an) */ |
d2523010 JL |
292 | void OP_F81000 (insn, extension) |
293 | unsigned long insn, extension; | |
05ccbdfd | 294 | { |
9f4a551e | 295 | store_mem ((State.regs[REG_A0 + REG0_8 (insn)] |
2e35551c | 296 | + SEXT8 (insn & 0xff)), 4, |
9f4a551e | 297 | State.regs[REG_D0 + REG1_8 (insn)]); |
05ccbdfd JL |
298 | } |
299 | ||
ecb4b5a3 | 300 | /* mov dm (d16,an) */ |
d2523010 JL |
301 | void OP_FA100000 (insn, extension) |
302 | unsigned long insn, extension; | |
05ccbdfd | 303 | { |
9f4a551e | 304 | store_mem ((State.regs[REG_A0 + REG0_16 (insn)] |
ecb4b5a3 | 305 | + SEXT16 (insn & 0xffff)), 4, |
9f4a551e | 306 | State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
307 | } |
308 | ||
de0dce7c | 309 | /* mov dm (d32,an) */ |
d2523010 JL |
310 | void OP_FC100000 (insn, extension) |
311 | unsigned long insn, extension; | |
05ccbdfd | 312 | { |
9f4a551e | 313 | store_mem ((State.regs[REG_A0 + REG0_16 (insn)] |
de0dce7c | 314 | + ((insn & 0xffff) << 16) + extension), 4, |
9f4a551e | 315 | State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
316 | } |
317 | ||
707641f6 | 318 | /* mov dm, (d8,sp) */ |
d2523010 JL |
319 | void OP_4200 (insn, extension) |
320 | unsigned long insn, extension; | |
05ccbdfd | 321 | { |
ecb4b5a3 | 322 | store_mem (State.regs[REG_SP] + (insn & 0xff), 4, |
9f4a551e | 323 | State.regs[REG_D0 + REG1_8 (insn)]); |
05ccbdfd JL |
324 | } |
325 | ||
ecb4b5a3 | 326 | /* mov dm, (d16,sp) */ |
d2523010 JL |
327 | void OP_FA910000 (insn, extension) |
328 | unsigned long insn, extension; | |
05ccbdfd | 329 | { |
ecb4b5a3 | 330 | store_mem (State.regs[REG_SP] + (insn & 0xffff), 4, |
9f4a551e | 331 | State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
332 | } |
333 | ||
de0dce7c | 334 | /* mov dm, (d32,sp) */ |
d2523010 JL |
335 | void OP_FC910000 (insn, extension) |
336 | unsigned long insn, extension; | |
05ccbdfd | 337 | { |
de0dce7c | 338 | store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4, |
9f4a551e | 339 | State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
340 | } |
341 | ||
f5f13c1d | 342 | /* mov dm, (di,an) */ |
d2523010 JL |
343 | void OP_F340 (insn, extension) |
344 | unsigned long insn, extension; | |
05ccbdfd | 345 | { |
9f4a551e JL |
346 | store_mem ((State.regs[REG_A0 + REG0 (insn)] |
347 | + State.regs[REG_D0 + REG1 (insn)]), 4, | |
95d18eb7 | 348 | State.regs[REG_D0 + REG0_4 (insn)]); |
05ccbdfd JL |
349 | } |
350 | ||
707641f6 | 351 | /* mov dm, (abs16) */ |
d2523010 JL |
352 | void OP_10000 (insn, extension) |
353 | unsigned long insn, extension; | |
05ccbdfd | 354 | { |
9f4a551e | 355 | store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
356 | } |
357 | ||
de0dce7c | 358 | /* mov dm, (abs32) */ |
d2523010 JL |
359 | void OP_FC810000 (insn, extension) |
360 | unsigned long insn, extension; | |
05ccbdfd | 361 | { |
9f4a551e | 362 | store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
363 | } |
364 | ||
707641f6 | 365 | /* mov am, (an) */ |
d2523010 JL |
366 | void OP_F010 (insn, extension) |
367 | unsigned long insn, extension; | |
05ccbdfd | 368 | { |
9f4a551e JL |
369 | store_mem (State.regs[REG_A0 + REG0 (insn)], 4, |
370 | State.regs[REG_A0 + REG1 (insn)]); | |
05ccbdfd JL |
371 | } |
372 | ||
2e35551c | 373 | /* mov am, (d8,an) */ |
d2523010 JL |
374 | void OP_F83000 (insn, extension) |
375 | unsigned long insn, extension; | |
05ccbdfd | 376 | { |
9f4a551e | 377 | store_mem ((State.regs[REG_A0 + REG0_8 (insn)] |
2e35551c | 378 | + SEXT8 (insn & 0xff)), 4, |
9f4a551e | 379 | State.regs[REG_A0 + REG1_8 (insn)]); |
05ccbdfd JL |
380 | } |
381 | ||
de0dce7c | 382 | /* mov am, (d16,an) */ |
d2523010 JL |
383 | void OP_FA300000 (insn, extension) |
384 | unsigned long insn, extension; | |
05ccbdfd | 385 | { |
9f4a551e | 386 | store_mem ((State.regs[REG_A0 + REG0_16 (insn)] |
ecb4b5a3 | 387 | + SEXT16 (insn & 0xffff)), 4, |
9f4a551e | 388 | State.regs[REG_A0 + REG1_16 (insn)]); |
05ccbdfd JL |
389 | } |
390 | ||
de0dce7c | 391 | /* mov am, (d32,an) */ |
d2523010 JL |
392 | void OP_FC300000 (insn, extension) |
393 | unsigned long insn, extension; | |
05ccbdfd | 394 | { |
9f4a551e | 395 | store_mem ((State.regs[REG_A0 + REG0_16 (insn)] |
de0dce7c | 396 | + ((insn & 0xffff) << 16) + extension), 4, |
9f4a551e | 397 | State.regs[REG_A0 + REG1_16 (insn)]); |
05ccbdfd JL |
398 | } |
399 | ||
707641f6 | 400 | /* mov am, (d8,sp) */ |
d2523010 JL |
401 | void OP_4300 (insn, extension) |
402 | unsigned long insn, extension; | |
05ccbdfd | 403 | { |
ecb4b5a3 | 404 | store_mem (State.regs[REG_SP] + (insn & 0xff), 4, |
9f4a551e | 405 | State.regs[REG_A0 + REG1_8 (insn)]); |
05ccbdfd JL |
406 | } |
407 | ||
ecb4b5a3 | 408 | /* mov am, (d16,sp) */ |
d2523010 JL |
409 | void OP_FA900000 (insn, extension) |
410 | unsigned long insn, extension; | |
05ccbdfd | 411 | { |
ecb4b5a3 | 412 | store_mem (State.regs[REG_SP] + (insn & 0xffff), 4, |
9f4a551e | 413 | State.regs[REG_A0 + REG1_16 (insn)]); |
05ccbdfd JL |
414 | } |
415 | ||
de0dce7c | 416 | /* mov am, (d32,sp) */ |
d2523010 JL |
417 | void OP_FC900000 (insn, extension) |
418 | unsigned long insn, extension; | |
05ccbdfd | 419 | { |
de0dce7c | 420 | store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4, |
9f4a551e | 421 | State.regs[REG_A0 + REG1_16 (insn)]); |
05ccbdfd JL |
422 | } |
423 | ||
f5f13c1d | 424 | /* mov am, (di,an) */ |
d2523010 JL |
425 | void OP_F3C0 (insn, extension) |
426 | unsigned long insn, extension; | |
05ccbdfd | 427 | { |
9f4a551e JL |
428 | store_mem ((State.regs[REG_A0 + REG0 (insn)] |
429 | + State.regs[REG_D0 + REG1 (insn)]), 4, | |
95d18eb7 | 430 | State.regs[REG_A0 + REG0_4 (insn)]); |
05ccbdfd JL |
431 | } |
432 | ||
ecb4b5a3 | 433 | /* mov am, (abs16) */ |
d2523010 JL |
434 | void OP_FA800000 (insn, extension) |
435 | unsigned long insn, extension; | |
05ccbdfd | 436 | { |
9f4a551e | 437 | store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + REG1_16 (insn)]); |
05ccbdfd JL |
438 | } |
439 | ||
de0dce7c | 440 | /* mov am, (abs32) */ |
d2523010 JL |
441 | void OP_FC800000 (insn, extension) |
442 | unsigned long insn, extension; | |
05ccbdfd | 443 | { |
9f4a551e | 444 | store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + REG1_16 (insn)]); |
05ccbdfd JL |
445 | } |
446 | ||
2e35551c | 447 | /* mov sp, (d8,an) */ |
d2523010 JL |
448 | void OP_F8F400 (insn, extension) |
449 | unsigned long insn, extension; | |
05ccbdfd | 450 | { |
9f4a551e | 451 | store_mem (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff), |
2e35551c | 452 | 4, State.regs[REG_SP]); |
05ccbdfd JL |
453 | } |
454 | ||
707641f6 | 455 | /* mov imm16, dn */ |
d2523010 JL |
456 | void OP_2C0000 (insn, extension) |
457 | unsigned long insn, extension; | |
05ccbdfd | 458 | { |
707641f6 JL |
459 | unsigned long value; |
460 | ||
461 | value = SEXT16 (insn & 0xffff); | |
9f4a551e | 462 | State.regs[REG_D0 + REG0_16 (insn)] = value; |
05ccbdfd JL |
463 | } |
464 | ||
de0dce7c | 465 | /* mov imm32,dn */ |
d2523010 JL |
466 | void OP_FCCC0000 (insn, extension) |
467 | unsigned long insn, extension; | |
05ccbdfd | 468 | { |
de0dce7c JL |
469 | unsigned long value; |
470 | ||
7c52bf32 | 471 | value = ((insn & 0xffff) << 16) + extension; |
9f4a551e | 472 | State.regs[REG_D0 + REG0_16 (insn)] = value; |
05ccbdfd JL |
473 | } |
474 | ||
707641f6 | 475 | /* mov imm16, an */ |
d2523010 JL |
476 | void OP_240000 (insn, extension) |
477 | unsigned long insn, extension; | |
05ccbdfd | 478 | { |
707641f6 JL |
479 | unsigned long value; |
480 | ||
481 | value = insn & 0xffff; | |
9f4a551e | 482 | State.regs[REG_A0 + REG0_16 (insn)] = value; |
05ccbdfd JL |
483 | } |
484 | ||
de0dce7c | 485 | /* mov imm32, an */ |
d2523010 JL |
486 | void OP_FCDC0000 (insn, extension) |
487 | unsigned long insn, extension; | |
05ccbdfd | 488 | { |
73e65298 JL |
489 | unsigned long value; |
490 | ||
7c52bf32 | 491 | value = ((insn & 0xffff) << 16) + extension; |
9f4a551e | 492 | State.regs[REG_A0 + REG0_16 (insn)] = value; |
05ccbdfd JL |
493 | } |
494 | ||
707641f6 | 495 | /* movbu (am), dn */ |
d2523010 JL |
496 | void OP_F040 (insn, extension) |
497 | unsigned long insn, extension; | |
05ccbdfd | 498 | { |
9f4a551e JL |
499 | State.regs[REG_D0 + REG1 (insn)] |
500 | = load_mem (State.regs[REG_A0 + REG0 (insn)], 1); | |
05ccbdfd JL |
501 | } |
502 | ||
2e35551c | 503 | /* movbu (d8,am), dn */ |
d2523010 JL |
504 | void OP_F84000 (insn, extension) |
505 | unsigned long insn, extension; | |
05ccbdfd | 506 | { |
9f4a551e JL |
507 | State.regs[REG_D0 + REG1_8 (insn)] |
508 | = load_mem ((State.regs[REG_A0 + REG0_8 (insn)] | |
2e35551c | 509 | + SEXT8 (insn & 0xff)), 1); |
05ccbdfd JL |
510 | } |
511 | ||
ecb4b5a3 | 512 | /* movbu (d16,am), dn */ |
d2523010 JL |
513 | void OP_FA400000 (insn, extension) |
514 | unsigned long insn, extension; | |
05ccbdfd | 515 | { |
9f4a551e JL |
516 | State.regs[REG_D0 + REG1_16 (insn)] |
517 | = load_mem ((State.regs[REG_A0 + REG0_16 (insn)] | |
ecb4b5a3 | 518 | + SEXT16 (insn & 0xffff)), 1); |
05ccbdfd JL |
519 | } |
520 | ||
de0dce7c | 521 | /* movbu (d32,am), dn */ |
d2523010 JL |
522 | void OP_FC400000 (insn, extension) |
523 | unsigned long insn, extension; | |
05ccbdfd | 524 | { |
9f4a551e JL |
525 | State.regs[REG_D0 + REG1_16 (insn)] |
526 | = load_mem ((State.regs[REG_A0 + REG0_16 (insn)] | |
de0dce7c | 527 | + ((insn & 0xffff) << 16) + extension), 1); |
05ccbdfd JL |
528 | } |
529 | ||
2e35551c | 530 | /* movbu (d8,sp), dn */ |
d2523010 JL |
531 | void OP_F8B800 (insn, extension) |
532 | unsigned long insn, extension; | |
05ccbdfd | 533 | { |
9f4a551e | 534 | State.regs[REG_D0 + REG0_8 (insn)] |
ecb4b5a3 | 535 | = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1); |
05ccbdfd JL |
536 | } |
537 | ||
ecb4b5a3 | 538 | /* movbu (d16,sp), dn */ |
d2523010 JL |
539 | void OP_FAB80000 (insn, extension) |
540 | unsigned long insn, extension; | |
05ccbdfd | 541 | { |
9f4a551e | 542 | State.regs[REG_D0 + REG0_16 (insn)] |
ecb4b5a3 | 543 | = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1); |
05ccbdfd JL |
544 | } |
545 | ||
de0dce7c | 546 | /* movbu (d32,sp), dn */ |
d2523010 JL |
547 | void OP_FCB80000 (insn, extension) |
548 | unsigned long insn, extension; | |
05ccbdfd | 549 | { |
9f4a551e | 550 | State.regs[REG_D0 + REG0_16 (insn)] |
de0dce7c | 551 | = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1); |
05ccbdfd JL |
552 | } |
553 | ||
f5f13c1d | 554 | /* movbu (di,am), dn */ |
d2523010 JL |
555 | void OP_F400 (insn, extension) |
556 | unsigned long insn, extension; | |
05ccbdfd | 557 | { |
95d18eb7 | 558 | State.regs[REG_D0 + REG0_4 (insn)] |
9f4a551e JL |
559 | = load_mem ((State.regs[REG_A0 + REG0 (insn)] |
560 | + State.regs[REG_D0 + REG1 (insn)]), 1); | |
05ccbdfd JL |
561 | } |
562 | ||
707641f6 | 563 | /* movbu (abs16), dn */ |
d2523010 JL |
564 | void OP_340000 (insn, extension) |
565 | unsigned long insn, extension; | |
05ccbdfd | 566 | { |
9f4a551e | 567 | State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 1); |
05ccbdfd JL |
568 | } |
569 | ||
de0dce7c | 570 | /* movbu (abs32), dn */ |
d2523010 JL |
571 | void OP_FCA80000 (insn, extension) |
572 | unsigned long insn, extension; | |
05ccbdfd | 573 | { |
9f4a551e | 574 | State.regs[REG_D0 + REG0_16 (insn)] |
de0dce7c | 575 | = load_mem ((((insn & 0xffff) << 16) + extension), 1); |
05ccbdfd JL |
576 | } |
577 | ||
707641f6 | 578 | /* movbu dm, (an) */ |
d2523010 JL |
579 | void OP_F050 (insn, extension) |
580 | unsigned long insn, extension; | |
05ccbdfd | 581 | { |
9f4a551e JL |
582 | store_mem (State.regs[REG_A0 + REG0 (insn)], 1, |
583 | State.regs[REG_D0 + REG1 (insn)]); | |
05ccbdfd JL |
584 | } |
585 | ||
2e35551c | 586 | /* movbu dm, (d8,an) */ |
d2523010 JL |
587 | void OP_F85000 (insn, extension) |
588 | unsigned long insn, extension; | |
05ccbdfd | 589 | { |
9f4a551e | 590 | store_mem ((State.regs[REG_A0 + REG0_8 (insn)] |
2e35551c | 591 | + SEXT8 (insn & 0xff)), 1, |
9f4a551e | 592 | State.regs[REG_D0 + REG1_8 (insn)]); |
05ccbdfd JL |
593 | } |
594 | ||
ecb4b5a3 | 595 | /* movbu dm, (d16,an) */ |
d2523010 JL |
596 | void OP_FA500000 (insn, extension) |
597 | unsigned long insn, extension; | |
05ccbdfd | 598 | { |
9f4a551e | 599 | store_mem ((State.regs[REG_A0 + REG0_16 (insn)] |
de0dce7c | 600 | + SEXT16 (insn & 0xffff)), 1, |
9f4a551e | 601 | State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
602 | } |
603 | ||
de0dce7c | 604 | /* movbu dm, (d32,an) */ |
d2523010 JL |
605 | void OP_FC500000 (insn, extension) |
606 | unsigned long insn, extension; | |
05ccbdfd | 607 | { |
9f4a551e | 608 | store_mem ((State.regs[REG_A0 + REG0_16 (insn)] |
de0dce7c | 609 | + ((insn & 0xffff) << 16) + extension), 1, |
9f4a551e | 610 | State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
611 | } |
612 | ||
2e35551c | 613 | /* movbu dm, (d8,sp) */ |
d2523010 JL |
614 | void OP_F89200 (insn, extension) |
615 | unsigned long insn, extension; | |
05ccbdfd | 616 | { |
ecb4b5a3 | 617 | store_mem (State.regs[REG_SP] + (insn & 0xff), 1, |
9f4a551e | 618 | State.regs[REG_D0 + REG1_8 (insn)]); |
05ccbdfd JL |
619 | } |
620 | ||
ecb4b5a3 | 621 | /* movbu dm, (d16,sp) */ |
d2523010 JL |
622 | void OP_FA920000 (insn, extension) |
623 | unsigned long insn, extension; | |
05ccbdfd | 624 | { |
ecb4b5a3 | 625 | store_mem (State.regs[REG_SP] + (insn & 0xffff), 2, |
65b784d8 | 626 | State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
627 | } |
628 | ||
de0dce7c | 629 | /* movbu dm (d32,sp) */ |
d2523010 JL |
630 | void OP_FC920000 (insn, extension) |
631 | unsigned long insn, extension; | |
05ccbdfd | 632 | { |
de0dce7c | 633 | store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2, |
65b784d8 | 634 | State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
635 | } |
636 | ||
f5f13c1d | 637 | /* movbu dm, (di,an) */ |
d2523010 JL |
638 | void OP_F440 (insn, extension) |
639 | unsigned long insn, extension; | |
05ccbdfd | 640 | { |
9f4a551e JL |
641 | store_mem ((State.regs[REG_A0 + REG0 (insn)] |
642 | + State.regs[REG_D0 + REG1 (insn)]), 1, | |
95d18eb7 | 643 | State.regs[REG_D0 + REG0_4 (insn)]); |
05ccbdfd JL |
644 | } |
645 | ||
707641f6 | 646 | /* movbu dm, (abs16) */ |
d2523010 JL |
647 | void OP_20000 (insn, extension) |
648 | unsigned long insn, extension; | |
05ccbdfd | 649 | { |
9f4a551e | 650 | store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
651 | } |
652 | ||
de0dce7c | 653 | /* movbu dm, (abs32) */ |
d2523010 JL |
654 | void OP_FC820000 (insn, extension) |
655 | unsigned long insn, extension; | |
05ccbdfd | 656 | { |
9f4a551e | 657 | store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
658 | } |
659 | ||
707641f6 | 660 | /* movhu (am), dn */ |
d2523010 JL |
661 | void OP_F060 (insn, extension) |
662 | unsigned long insn, extension; | |
05ccbdfd | 663 | { |
9f4a551e JL |
664 | State.regs[REG_D0 + REG1 (insn)] |
665 | = load_mem (State.regs[REG_A0 + REG0 (insn)], 2); | |
05ccbdfd JL |
666 | } |
667 | ||
2e35551c | 668 | /* movhu (d8,am), dn */ |
d2523010 JL |
669 | void OP_F86000 (insn, extension) |
670 | unsigned long insn, extension; | |
05ccbdfd | 671 | { |
9f4a551e JL |
672 | State.regs[REG_D0 + REG1_8 (insn)] |
673 | = load_mem ((State.regs[REG_A0 + REG0_8 (insn)] | |
2e35551c | 674 | + SEXT8 (insn & 0xff)), 2); |
05ccbdfd JL |
675 | } |
676 | ||
ecb4b5a3 | 677 | /* movhu (d16,am), dn */ |
d2523010 JL |
678 | void OP_FA600000 (insn, extension) |
679 | unsigned long insn, extension; | |
05ccbdfd | 680 | { |
9f4a551e JL |
681 | State.regs[REG_D0 + REG1_16 (insn)] |
682 | = load_mem ((State.regs[REG_A0 + REG0_16 (insn)] | |
ecb4b5a3 | 683 | + SEXT16 (insn & 0xffff)), 2); |
05ccbdfd JL |
684 | } |
685 | ||
de0dce7c | 686 | /* movhu (d32,am), dn */ |
d2523010 JL |
687 | void OP_FC600000 (insn, extension) |
688 | unsigned long insn, extension; | |
05ccbdfd | 689 | { |
9f4a551e JL |
690 | State.regs[REG_D0 + REG1_16 (insn)] |
691 | = load_mem ((State.regs[REG_A0 + REG0_16 (insn)] | |
de0dce7c | 692 | + ((insn & 0xffff) << 16) + extension), 2); |
05ccbdfd JL |
693 | } |
694 | ||
2e35551c | 695 | /* movhu (d8,sp) dn */ |
d2523010 JL |
696 | void OP_F8BC00 (insn, extension) |
697 | unsigned long insn, extension; | |
05ccbdfd | 698 | { |
9f4a551e | 699 | State.regs[REG_D0 + REG0_8 (insn)] |
ecb4b5a3 | 700 | = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2); |
05ccbdfd JL |
701 | } |
702 | ||
ecb4b5a3 | 703 | /* movhu (d16,sp), dn */ |
d2523010 JL |
704 | void OP_FABC0000 (insn, extension) |
705 | unsigned long insn, extension; | |
05ccbdfd | 706 | { |
9f4a551e | 707 | State.regs[REG_D0 + REG0_16 (insn)] |
ecb4b5a3 | 708 | = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2); |
05ccbdfd JL |
709 | } |
710 | ||
de0dce7c | 711 | /* movhu (d32,sp), dn */ |
d2523010 JL |
712 | void OP_FCBC0000 (insn, extension) |
713 | unsigned long insn, extension; | |
05ccbdfd | 714 | { |
9f4a551e | 715 | State.regs[REG_D0 + REG0_16 (insn)] |
de0dce7c | 716 | = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2); |
05ccbdfd JL |
717 | } |
718 | ||
f5f13c1d | 719 | /* movhu (di,am), dn */ |
d2523010 JL |
720 | void OP_F480 (insn, extension) |
721 | unsigned long insn, extension; | |
05ccbdfd | 722 | { |
95d18eb7 | 723 | State.regs[REG_D0 + REG0_4 (insn)] |
9f4a551e JL |
724 | = load_mem ((State.regs[REG_A0 + REG0 (insn)] |
725 | + State.regs[REG_D0 + REG1 (insn)]), 2); | |
05ccbdfd JL |
726 | } |
727 | ||
707641f6 | 728 | /* movhu (abs16), dn */ |
d2523010 JL |
729 | void OP_380000 (insn, extension) |
730 | unsigned long insn, extension; | |
05ccbdfd | 731 | { |
9f4a551e | 732 | State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 2); |
05ccbdfd JL |
733 | } |
734 | ||
de0dce7c | 735 | /* movhu (abs32), dn */ |
d2523010 JL |
736 | void OP_FCAC0000 (insn, extension) |
737 | unsigned long insn, extension; | |
05ccbdfd | 738 | { |
9f4a551e | 739 | State.regs[REG_D0 + REG0_16 (insn)] |
de0dce7c | 740 | = load_mem ((((insn & 0xffff) << 16) + extension), 2); |
05ccbdfd JL |
741 | } |
742 | ||
707641f6 | 743 | /* movhu dm, (an) */ |
d2523010 JL |
744 | void OP_F070 (insn, extension) |
745 | unsigned long insn, extension; | |
05ccbdfd | 746 | { |
9f4a551e JL |
747 | store_mem (State.regs[REG_A0 + REG0 (insn)], 2, |
748 | State.regs[REG_D0 + REG1 (insn)]); | |
05ccbdfd JL |
749 | } |
750 | ||
2e35551c | 751 | /* movhu dm, (d8,an) */ |
d2523010 JL |
752 | void OP_F87000 (insn, extension) |
753 | unsigned long insn, extension; | |
05ccbdfd | 754 | { |
9f4a551e | 755 | store_mem ((State.regs[REG_A0 + REG0_8 (insn)] |
2e35551c | 756 | + SEXT8 (insn & 0xff)), 2, |
9f4a551e | 757 | State.regs[REG_D0 + REG1_8 (insn)]); |
05ccbdfd JL |
758 | } |
759 | ||
ecb4b5a3 | 760 | /* movhu dm, (d16,an) */ |
d2523010 JL |
761 | void OP_FA700000 (insn, extension) |
762 | unsigned long insn, extension; | |
05ccbdfd | 763 | { |
9f4a551e | 764 | store_mem ((State.regs[REG_A0 + REG0_16 (insn)] |
ecb4b5a3 | 765 | + SEXT16 (insn & 0xffff)), 2, |
9f4a551e | 766 | State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
767 | } |
768 | ||
de0dce7c | 769 | /* movhu dm, (d32,an) */ |
d2523010 JL |
770 | void OP_FC700000 (insn, extension) |
771 | unsigned long insn, extension; | |
05ccbdfd | 772 | { |
9f4a551e | 773 | store_mem ((State.regs[REG_A0 + REG0_16 (insn)] |
de0dce7c | 774 | + ((insn & 0xffff) << 16) + extension), 2, |
9f4a551e | 775 | State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
776 | } |
777 | ||
2e35551c | 778 | /* movhu dm,(d8,sp) */ |
d2523010 JL |
779 | void OP_F89300 (insn, extension) |
780 | unsigned long insn, extension; | |
05ccbdfd | 781 | { |
ecb4b5a3 | 782 | store_mem (State.regs[REG_SP] + (insn & 0xff), 2, |
9f4a551e | 783 | State.regs[REG_D0 + REG1_8 (insn)]); |
05ccbdfd JL |
784 | } |
785 | ||
ecb4b5a3 | 786 | /* movhu dm,(d16,sp) */ |
d2523010 JL |
787 | void OP_FA930000 (insn, extension) |
788 | unsigned long insn, extension; | |
05ccbdfd | 789 | { |
ecb4b5a3 | 790 | store_mem (State.regs[REG_SP] + (insn & 0xffff), 2, |
9f4a551e | 791 | State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
792 | } |
793 | ||
de0dce7c | 794 | /* movhu dm,(d32,sp) */ |
d2523010 JL |
795 | void OP_FC930000 (insn, extension) |
796 | unsigned long insn, extension; | |
05ccbdfd | 797 | { |
de0dce7c | 798 | store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2, |
9f4a551e | 799 | State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
800 | } |
801 | ||
f5f13c1d | 802 | /* movhu dm, (di,an) */ |
d2523010 JL |
803 | void OP_F4C0 (insn, extension) |
804 | unsigned long insn, extension; | |
05ccbdfd | 805 | { |
9f4a551e JL |
806 | store_mem ((State.regs[REG_A0 + REG0 (insn)] |
807 | + State.regs[REG_D0 + REG1 (insn)]), 2, | |
95d18eb7 | 808 | State.regs[REG_D0 + REG0_4 (insn)]); |
05ccbdfd JL |
809 | } |
810 | ||
707641f6 | 811 | /* movhu dm, (abs16) */ |
d2523010 JL |
812 | void OP_30000 (insn, extension) |
813 | unsigned long insn, extension; | |
05ccbdfd | 814 | { |
9f4a551e | 815 | store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
816 | } |
817 | ||
de0dce7c | 818 | /* movhu dm, (abs32) */ |
d2523010 JL |
819 | void OP_FC830000 (insn, extension) |
820 | unsigned long insn, extension; | |
05ccbdfd | 821 | { |
9f4a551e | 822 | store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
823 | } |
824 | ||
707641f6 | 825 | /* ext dn */ |
d2523010 JL |
826 | void OP_F2D0 (insn, extension) |
827 | unsigned long insn, extension; | |
05ccbdfd | 828 | { |
9f4a551e | 829 | if (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) |
707641f6 JL |
830 | State.regs[REG_MDR] = -1; |
831 | else | |
832 | State.regs[REG_MDR] = 0; | |
05ccbdfd JL |
833 | } |
834 | ||
707641f6 | 835 | /* extb dn */ |
d2523010 JL |
836 | void OP_10 (insn, extension) |
837 | unsigned long insn, extension; | |
05ccbdfd | 838 | { |
9f4a551e | 839 | State.regs[REG_D0 + REG0 (insn)] = SEXT8 (State.regs[REG_D0 + REG0 (insn)]); |
05ccbdfd JL |
840 | } |
841 | ||
707641f6 | 842 | /* extbu dn */ |
d2523010 JL |
843 | void OP_14 (insn, extension) |
844 | unsigned long insn, extension; | |
05ccbdfd | 845 | { |
9f4a551e | 846 | State.regs[REG_D0 + REG0 (insn)] &= 0xff; |
05ccbdfd JL |
847 | } |
848 | ||
707641f6 | 849 | /* exth dn */ |
d2523010 JL |
850 | void OP_18 (insn, extension) |
851 | unsigned long insn, extension; | |
05ccbdfd | 852 | { |
9f4a551e JL |
853 | State.regs[REG_D0 + REG0 (insn)] |
854 | = SEXT16 (State.regs[REG_D0 + REG0 (insn)]); | |
05ccbdfd JL |
855 | } |
856 | ||
707641f6 | 857 | /* exthu dn */ |
d2523010 JL |
858 | void OP_1C (insn, extension) |
859 | unsigned long insn, extension; | |
05ccbdfd | 860 | { |
9f4a551e | 861 | State.regs[REG_D0 + REG0 (insn)] &= 0xffff; |
05ccbdfd JL |
862 | } |
863 | ||
1f3bea21 | 864 | /* movm (sp), reg_list */ |
d2523010 JL |
865 | void OP_CE00 (insn, extension) |
866 | unsigned long insn, extension; | |
05ccbdfd | 867 | { |
1f3bea21 JL |
868 | unsigned long sp = State.regs[REG_SP]; |
869 | unsigned long mask; | |
870 | ||
871 | mask = insn & 0xff; | |
872 | ||
873 | if (mask & 0x8) | |
874 | { | |
875 | sp += 4; | |
876 | State.regs[REG_LAR] = load_mem (sp, 4); | |
877 | sp += 4; | |
878 | State.regs[REG_LIR] = load_mem (sp, 4); | |
879 | sp += 4; | |
880 | State.regs[REG_MDR] = load_mem (sp, 4); | |
881 | sp += 4; | |
882 | State.regs[REG_A0 + 1] = load_mem (sp, 4); | |
883 | sp += 4; | |
884 | State.regs[REG_A0] = load_mem (sp, 4); | |
885 | sp += 4; | |
886 | State.regs[REG_D0 + 1] = load_mem (sp, 4); | |
887 | sp += 4; | |
888 | State.regs[REG_D0] = load_mem (sp, 4); | |
889 | sp += 4; | |
890 | } | |
891 | ||
892 | if (mask & 0x10) | |
893 | { | |
894 | State.regs[REG_A0 + 3] = load_mem (sp, 4); | |
895 | sp += 4; | |
896 | } | |
897 | ||
898 | if (mask & 0x20) | |
899 | { | |
900 | State.regs[REG_A0 + 2] = load_mem (sp, 4); | |
901 | sp += 4; | |
902 | } | |
903 | ||
904 | if (mask & 0x40) | |
905 | { | |
906 | State.regs[REG_D0 + 3] = load_mem (sp, 4); | |
907 | sp += 4; | |
908 | } | |
909 | ||
910 | if (mask & 0x80) | |
911 | { | |
912 | State.regs[REG_D0 + 2] = load_mem (sp, 4); | |
913 | sp += 4; | |
914 | } | |
915 | ||
916 | /* And make sure to update the stack pointer. */ | |
917 | State.regs[REG_SP] = sp; | |
918 | } | |
919 | ||
920 | /* movm reg_list, (sp) */ | |
d2523010 JL |
921 | void OP_CF00 (insn, extension) |
922 | unsigned long insn, extension; | |
05ccbdfd | 923 | { |
1f3bea21 JL |
924 | unsigned long sp = State.regs[REG_SP]; |
925 | unsigned long mask; | |
926 | ||
927 | mask = insn & 0xff; | |
928 | ||
929 | if (mask & 0x80) | |
930 | { | |
931 | sp -= 4; | |
6e7a01c1 | 932 | store_mem (sp, 4, State.regs[REG_D0 + 2]); |
1f3bea21 JL |
933 | } |
934 | ||
935 | if (mask & 0x40) | |
936 | { | |
937 | sp -= 4; | |
6e7a01c1 | 938 | store_mem (sp, 4, State.regs[REG_D0 + 3]); |
1f3bea21 JL |
939 | } |
940 | ||
941 | if (mask & 0x20) | |
942 | { | |
943 | sp -= 4; | |
6e7a01c1 | 944 | store_mem (sp, 4, State.regs[REG_A0 + 2]); |
1f3bea21 JL |
945 | } |
946 | ||
947 | if (mask & 0x10) | |
948 | { | |
949 | sp -= 4; | |
6e7a01c1 | 950 | store_mem (sp, 4, State.regs[REG_A0 + 3]); |
1f3bea21 JL |
951 | } |
952 | ||
953 | if (mask & 0x8) | |
954 | { | |
955 | sp -= 4; | |
6e7a01c1 | 956 | store_mem (sp, 4, State.regs[REG_D0]); |
1f3bea21 | 957 | sp -= 4; |
6e7a01c1 | 958 | store_mem (sp, 4, State.regs[REG_D0 + 1]); |
1f3bea21 | 959 | sp -= 4; |
6e7a01c1 | 960 | store_mem (sp, 4, State.regs[REG_A0]); |
1f3bea21 | 961 | sp -= 4; |
6e7a01c1 | 962 | store_mem (sp, 4, State.regs[REG_A0 + 1]); |
1f3bea21 | 963 | sp -= 4; |
6e7a01c1 | 964 | store_mem (sp, 4, State.regs[REG_MDR]); |
1f3bea21 | 965 | sp -= 4; |
6e7a01c1 | 966 | store_mem (sp, 4, State.regs[REG_LIR]); |
1f3bea21 | 967 | sp -= 4; |
6e7a01c1 | 968 | store_mem (sp, 4, State.regs[REG_LAR]); |
1f3bea21 JL |
969 | sp -= 4; |
970 | } | |
971 | ||
972 | /* And make sure to update the stack pointer. */ | |
973 | State.regs[REG_SP] = sp; | |
05ccbdfd JL |
974 | } |
975 | ||
73e65298 | 976 | /* clr dn */ |
d2523010 JL |
977 | void OP_0 (insn, extension) |
978 | unsigned long insn, extension; | |
05ccbdfd | 979 | { |
9f4a551e | 980 | State.regs[REG_D0 + REG1 (insn)] = 0; |
73e65298 JL |
981 | |
982 | PSW |= PSW_Z; | |
983 | PSW &= ~(PSW_V | PSW_C | PSW_N); | |
05ccbdfd JL |
984 | } |
985 | ||
de0dce7c | 986 | /* add dm,dn */ |
d2523010 JL |
987 | void OP_E0 (insn, extension) |
988 | unsigned long insn, extension; | |
05ccbdfd | 989 | { |
73e65298 JL |
990 | int z, c, n, v; |
991 | unsigned long reg1, reg2, value; | |
992 | ||
9f4a551e JL |
993 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
994 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
73e65298 | 995 | value = reg1 + reg2; |
9f4a551e | 996 | State.regs[REG_D0 + REG0 (insn)] = value; |
73e65298 JL |
997 | |
998 | z = (value == 0); | |
999 | n = (value & 0x80000000); | |
0ade484f | 1000 | c = (value < reg1) || (value < reg2); |
d657034d | 1001 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) |
b7b89deb | 1002 | && (reg2 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1003 | |
1004 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1005 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1006 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1007 | } |
1008 | ||
73e65298 | 1009 | /* add dm, an */ |
d2523010 JL |
1010 | void OP_F160 (insn, extension) |
1011 | unsigned long insn, extension; | |
05ccbdfd | 1012 | { |
73e65298 JL |
1013 | int z, c, n, v; |
1014 | unsigned long reg1, reg2, value; | |
1015 | ||
9f4a551e JL |
1016 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1017 | reg2 = State.regs[REG_A0 + REG0 (insn)]; | |
73e65298 | 1018 | value = reg1 + reg2; |
9f4a551e | 1019 | State.regs[REG_A0 + REG0 (insn)] = value; |
73e65298 JL |
1020 | |
1021 | z = (value == 0); | |
1022 | n = (value & 0x80000000); | |
0ade484f | 1023 | c = (value < reg1) || (value < reg2); |
d657034d | 1024 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) |
b7b89deb | 1025 | && (reg2 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1026 | |
1027 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1028 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1029 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1030 | } |
1031 | ||
de0dce7c | 1032 | /* add am, dn */ |
d2523010 JL |
1033 | void OP_F150 (insn, extension) |
1034 | unsigned long insn, extension; | |
05ccbdfd | 1035 | { |
73e65298 JL |
1036 | int z, c, n, v; |
1037 | unsigned long reg1, reg2, value; | |
1038 | ||
9f4a551e JL |
1039 | reg1 = State.regs[REG_A0 + REG1 (insn)]; |
1040 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
73e65298 | 1041 | value = reg1 + reg2; |
9f4a551e | 1042 | State.regs[REG_D0 + REG0 (insn)] = value; |
73e65298 JL |
1043 | |
1044 | z = (value == 0); | |
1045 | n = (value & 0x80000000); | |
0ade484f | 1046 | c = (value < reg1) || (value < reg2); |
d657034d | 1047 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) |
b7b89deb | 1048 | && (reg2 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1049 | |
1050 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1051 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1052 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1053 | } |
1054 | ||
73e65298 | 1055 | /* add am,an */ |
d2523010 JL |
1056 | void OP_F170 (insn, extension) |
1057 | unsigned long insn, extension; | |
05ccbdfd | 1058 | { |
73e65298 JL |
1059 | int z, c, n, v; |
1060 | unsigned long reg1, reg2, value; | |
1061 | ||
9f4a551e JL |
1062 | reg1 = State.regs[REG_A0 + REG1 (insn)]; |
1063 | reg2 = State.regs[REG_A0 + REG0 (insn)]; | |
73e65298 | 1064 | value = reg1 + reg2; |
9f4a551e | 1065 | State.regs[REG_A0 + REG0 (insn)] = value; |
73e65298 JL |
1066 | |
1067 | z = (value == 0); | |
1068 | n = (value & 0x80000000); | |
0ade484f | 1069 | c = (value < reg1) || (value < reg2); |
d657034d | 1070 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) |
b7b89deb | 1071 | && (reg2 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1072 | |
1073 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1074 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1075 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1076 | } |
1077 | ||
73e65298 | 1078 | /* add imm8, dn */ |
d2523010 JL |
1079 | void OP_2800 (insn, extension) |
1080 | unsigned long insn, extension; | |
05ccbdfd | 1081 | { |
73e65298 JL |
1082 | int z, c, n, v; |
1083 | unsigned long reg1, imm, value; | |
1084 | ||
9f4a551e | 1085 | reg1 = State.regs[REG_D0 + REG0_8 (insn)]; |
73e65298 JL |
1086 | imm = SEXT8 (insn & 0xff); |
1087 | value = reg1 + imm; | |
9f4a551e | 1088 | State.regs[REG_D0 + REG0_8 (insn)] = value; |
73e65298 JL |
1089 | |
1090 | z = (value == 0); | |
1091 | n = (value & 0x80000000); | |
0ade484f | 1092 | c = (value < reg1) || (value < imm); |
d657034d | 1093 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
b7b89deb | 1094 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1095 | |
1096 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1097 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1098 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1099 | } |
1100 | ||
73e65298 | 1101 | /* add imm16, dn */ |
d2523010 JL |
1102 | void OP_FAC00000 (insn, extension) |
1103 | unsigned long insn, extension; | |
05ccbdfd | 1104 | { |
73e65298 JL |
1105 | int z, c, n, v; |
1106 | unsigned long reg1, imm, value; | |
1107 | ||
9f4a551e | 1108 | reg1 = State.regs[REG_D0 + REG0_16 (insn)]; |
73e65298 JL |
1109 | imm = SEXT16 (insn & 0xffff); |
1110 | value = reg1 + imm; | |
9f4a551e | 1111 | State.regs[REG_D0 + REG0_16 (insn)] = value; |
73e65298 JL |
1112 | |
1113 | z = (value == 0); | |
1114 | n = (value & 0x80000000); | |
0ade484f | 1115 | c = (value < reg1) || (value < imm); |
d657034d | 1116 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
b7b89deb | 1117 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1118 | |
1119 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1120 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1121 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1122 | } |
1123 | ||
73e65298 | 1124 | /* add imm32,dn */ |
d2523010 JL |
1125 | void OP_FCC00000 (insn, extension) |
1126 | unsigned long insn, extension; | |
05ccbdfd | 1127 | { |
73e65298 JL |
1128 | int z, c, n, v; |
1129 | unsigned long reg1, imm, value; | |
1130 | ||
9f4a551e | 1131 | reg1 = State.regs[REG_D0 + REG0_16 (insn)]; |
7c52bf32 | 1132 | imm = ((insn & 0xffff) << 16) + extension; |
73e65298 | 1133 | value = reg1 + imm; |
9f4a551e | 1134 | State.regs[REG_D0 + REG0_16 (insn)] = value; |
73e65298 JL |
1135 | |
1136 | z = (value == 0); | |
1137 | n = (value & 0x80000000); | |
0ade484f | 1138 | c = (value < reg1) || (value < imm); |
d657034d | 1139 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
b7b89deb | 1140 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1141 | |
1142 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1143 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1144 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1145 | } |
1146 | ||
73e65298 | 1147 | /* add imm8, an */ |
d2523010 JL |
1148 | void OP_2000 (insn, extension) |
1149 | unsigned long insn, extension; | |
05ccbdfd | 1150 | { |
73e65298 JL |
1151 | int z, c, n, v; |
1152 | unsigned long reg1, imm, value; | |
1153 | ||
9f4a551e | 1154 | reg1 = State.regs[REG_A0 + REG0_8 (insn)]; |
6e7a01c1 | 1155 | imm = SEXT8 (insn & 0xff); |
73e65298 | 1156 | value = reg1 + imm; |
9f4a551e | 1157 | State.regs[REG_A0 + REG0_8 (insn)] = value; |
73e65298 JL |
1158 | |
1159 | z = (value == 0); | |
1160 | n = (value & 0x80000000); | |
0ade484f | 1161 | c = (value < reg1) || (value < imm); |
d657034d | 1162 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
b7b89deb | 1163 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1164 | |
1165 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1166 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1167 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1168 | } |
1169 | ||
73e65298 | 1170 | /* add imm16, an */ |
d2523010 JL |
1171 | void OP_FAD00000 (insn, extension) |
1172 | unsigned long insn, extension; | |
05ccbdfd | 1173 | { |
73e65298 JL |
1174 | int z, c, n, v; |
1175 | unsigned long reg1, imm, value; | |
1176 | ||
9f4a551e | 1177 | reg1 = State.regs[REG_A0 + REG0_16 (insn)]; |
6e7a01c1 | 1178 | imm = SEXT16 (insn & 0xffff); |
73e65298 | 1179 | value = reg1 + imm; |
9f4a551e | 1180 | State.regs[REG_A0 + REG0_16 (insn)] = value; |
73e65298 JL |
1181 | |
1182 | z = (value == 0); | |
1183 | n = (value & 0x80000000); | |
0ade484f | 1184 | c = (value < reg1) || (value < imm); |
d657034d | 1185 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
b7b89deb | 1186 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1187 | |
1188 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1189 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1190 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1191 | } |
1192 | ||
73e65298 | 1193 | /* add imm32, an */ |
d2523010 JL |
1194 | void OP_FCD00000 (insn, extension) |
1195 | unsigned long insn, extension; | |
05ccbdfd | 1196 | { |
73e65298 JL |
1197 | int z, c, n, v; |
1198 | unsigned long reg1, imm, value; | |
1199 | ||
9f4a551e | 1200 | reg1 = State.regs[REG_A0 + REG0_16 (insn)]; |
7c52bf32 | 1201 | imm = ((insn & 0xffff) << 16) + extension; |
73e65298 | 1202 | value = reg1 + imm; |
9f4a551e | 1203 | State.regs[REG_A0 + REG0_16 (insn)] = value; |
73e65298 JL |
1204 | |
1205 | z = (value == 0); | |
1206 | n = (value & 0x80000000); | |
0ade484f | 1207 | c = (value < reg1) || (value < imm); |
d657034d | 1208 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
b7b89deb | 1209 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1210 | |
1211 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1212 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1213 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1214 | } |
1215 | ||
de0dce7c | 1216 | /* add imm8, sp */ |
d2523010 JL |
1217 | void OP_F8FE00 (insn, extension) |
1218 | unsigned long insn, extension; | |
05ccbdfd | 1219 | { |
73e65298 JL |
1220 | unsigned long reg1, imm, value; |
1221 | ||
1222 | reg1 = State.regs[REG_SP]; | |
1223 | imm = SEXT8 (insn & 0xff); | |
1224 | value = reg1 + imm; | |
1225 | State.regs[REG_SP] = value; | |
05ccbdfd JL |
1226 | } |
1227 | ||
73e65298 | 1228 | /* add imm16,sp */ |
d2523010 JL |
1229 | void OP_FAFE0000 (insn, extension) |
1230 | unsigned long insn, extension; | |
05ccbdfd | 1231 | { |
73e65298 JL |
1232 | unsigned long reg1, imm, value; |
1233 | ||
1234 | reg1 = State.regs[REG_SP]; | |
1235 | imm = SEXT16 (insn & 0xffff); | |
1236 | value = reg1 + imm; | |
1237 | State.regs[REG_SP] = value; | |
05ccbdfd JL |
1238 | } |
1239 | ||
de0dce7c | 1240 | /* add imm32, sp */ |
d2523010 JL |
1241 | void OP_FCFE0000 (insn, extension) |
1242 | unsigned long insn, extension; | |
05ccbdfd | 1243 | { |
73e65298 JL |
1244 | unsigned long reg1, imm, value; |
1245 | ||
1246 | reg1 = State.regs[REG_SP]; | |
7c52bf32 | 1247 | imm = ((insn & 0xffff) << 16) + extension; |
73e65298 JL |
1248 | value = reg1 + imm; |
1249 | State.regs[REG_SP] = value; | |
05ccbdfd JL |
1250 | } |
1251 | ||
de0dce7c | 1252 | /* addc dm,dn */ |
d2523010 JL |
1253 | void OP_F140 (insn, extension) |
1254 | unsigned long insn, extension; | |
05ccbdfd | 1255 | { |
73e65298 JL |
1256 | int z, c, n, v; |
1257 | unsigned long reg1, reg2, value; | |
1258 | ||
9f4a551e JL |
1259 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1260 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
73e65298 | 1261 | value = reg1 + reg2 + ((PSW & PSW_C) != 0); |
9f4a551e | 1262 | State.regs[REG_D0 + REG0 (insn)] = value; |
73e65298 JL |
1263 | |
1264 | z = (value == 0); | |
1265 | n = (value & 0x80000000); | |
0ade484f | 1266 | c = (value < reg1) || (value < reg2); |
d657034d | 1267 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) |
b7b89deb | 1268 | && (reg2 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1269 | |
1270 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1271 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1272 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1273 | } |
1274 | ||
707641f6 | 1275 | /* sub dm, dn */ |
d2523010 JL |
1276 | void OP_F100 (insn, extension) |
1277 | unsigned long insn, extension; | |
05ccbdfd | 1278 | { |
707641f6 JL |
1279 | int z, c, n, v; |
1280 | unsigned long reg1, reg2, value; | |
1281 | ||
9f4a551e JL |
1282 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1283 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
707641f6 | 1284 | value = reg2 - reg1; |
65b784d8 | 1285 | State.regs[REG_D0 + REG0 (insn)] = value; |
707641f6 JL |
1286 | |
1287 | z = (value == 0); | |
1288 | n = (value & 0x80000000); | |
216e6557 | 1289 | c = (reg1 > reg2); |
b7b89deb JL |
1290 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1291 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1292 | |
1293 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1294 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1295 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1296 | } |
1297 | ||
707641f6 | 1298 | /* sub dm, an */ |
d2523010 JL |
1299 | void OP_F120 (insn, extension) |
1300 | unsigned long insn, extension; | |
05ccbdfd | 1301 | { |
707641f6 JL |
1302 | int z, c, n, v; |
1303 | unsigned long reg1, reg2, value; | |
1304 | ||
9f4a551e JL |
1305 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1306 | reg2 = State.regs[REG_A0 + REG0 (insn)]; | |
707641f6 | 1307 | value = reg2 - reg1; |
65b784d8 | 1308 | State.regs[REG_A0 + REG0 (insn)] = value; |
707641f6 JL |
1309 | |
1310 | z = (value == 0); | |
1311 | n = (value & 0x80000000); | |
216e6557 | 1312 | c = (reg1 > reg2); |
b7b89deb JL |
1313 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1314 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1315 | |
1316 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1317 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1318 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1319 | } |
1320 | ||
707641f6 | 1321 | /* sub am, dn */ |
d2523010 JL |
1322 | void OP_F110 (insn, extension) |
1323 | unsigned long insn, extension; | |
05ccbdfd | 1324 | { |
707641f6 JL |
1325 | int z, c, n, v; |
1326 | unsigned long reg1, reg2, value; | |
1327 | ||
9f4a551e JL |
1328 | reg1 = State.regs[REG_A0 + REG1 (insn)]; |
1329 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
707641f6 | 1330 | value = reg2 - reg1; |
65b784d8 | 1331 | State.regs[REG_D0 + REG0 (insn)] = value; |
707641f6 JL |
1332 | |
1333 | z = (value == 0); | |
1334 | n = (value & 0x80000000); | |
216e6557 | 1335 | c = (reg1 > reg2); |
b7b89deb JL |
1336 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1337 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1338 | |
1339 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1340 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1341 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1342 | } |
1343 | ||
707641f6 | 1344 | /* sub am, an */ |
d2523010 JL |
1345 | void OP_F130 (insn, extension) |
1346 | unsigned long insn, extension; | |
05ccbdfd | 1347 | { |
707641f6 JL |
1348 | int z, c, n, v; |
1349 | unsigned long reg1, reg2, value; | |
1350 | ||
9f4a551e JL |
1351 | reg1 = State.regs[REG_A0 + REG1 (insn)]; |
1352 | reg2 = State.regs[REG_A0 + REG0 (insn)]; | |
707641f6 | 1353 | value = reg2 - reg1; |
65b784d8 | 1354 | State.regs[REG_A0 + REG0 (insn)] = value; |
707641f6 JL |
1355 | |
1356 | z = (value == 0); | |
1357 | n = (value & 0x80000000); | |
216e6557 | 1358 | c = (reg1 > reg2); |
b7b89deb JL |
1359 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1360 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1361 | |
1362 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1363 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1364 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1365 | } |
1366 | ||
de0dce7c | 1367 | /* sub imm32, dn */ |
d2523010 JL |
1368 | void OP_FCC40000 (insn, extension) |
1369 | unsigned long insn, extension; | |
05ccbdfd | 1370 | { |
707641f6 JL |
1371 | int z, c, n, v; |
1372 | unsigned long reg1, imm, value; | |
1373 | ||
9f4a551e | 1374 | reg1 = State.regs[REG_D0 + REG0_16 (insn)]; |
7c52bf32 | 1375 | imm = ((insn & 0xffff) << 16) + extension; |
707641f6 | 1376 | value = reg1 - imm; |
65b784d8 | 1377 | State.regs[REG_D0 + REG0_16 (insn)] = value; |
707641f6 JL |
1378 | |
1379 | z = (value == 0); | |
1380 | n = (value & 0x80000000); | |
1381 | c = (reg1 < imm); | |
b7b89deb JL |
1382 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1383 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1384 | |
1385 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1386 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1387 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1388 | } |
1389 | ||
de0dce7c | 1390 | /* sub imm32, an */ |
d2523010 JL |
1391 | void OP_FCD40000 (insn, extension) |
1392 | unsigned long insn, extension; | |
05ccbdfd | 1393 | { |
707641f6 JL |
1394 | int z, c, n, v; |
1395 | unsigned long reg1, imm, value; | |
1396 | ||
9f4a551e | 1397 | reg1 = State.regs[REG_A0 + REG0_16 (insn)]; |
7c52bf32 | 1398 | imm = ((insn & 0xffff) << 16) + extension; |
707641f6 | 1399 | value = reg1 - imm; |
65b784d8 | 1400 | State.regs[REG_A0 + REG0_16 (insn)] = value; |
707641f6 JL |
1401 | |
1402 | z = (value == 0); | |
1403 | n = (value & 0x80000000); | |
1404 | c = (reg1 < imm); | |
b7b89deb JL |
1405 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1406 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1407 | |
1408 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1409 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1410 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1411 | } |
1412 | ||
de0dce7c | 1413 | /* subc dm, dn */ |
d2523010 JL |
1414 | void OP_F180 (insn, extension) |
1415 | unsigned long insn, extension; | |
05ccbdfd | 1416 | { |
707641f6 JL |
1417 | int z, c, n, v; |
1418 | unsigned long reg1, reg2, value; | |
1419 | ||
9f4a551e JL |
1420 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1421 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
707641f6 | 1422 | value = reg2 - reg1 - ((PSW & PSW_C) != 0); |
65b784d8 | 1423 | State.regs[REG_D0 + REG0 (insn)] = value; |
707641f6 JL |
1424 | |
1425 | z = (value == 0); | |
1426 | n = (value & 0x80000000); | |
216e6557 | 1427 | c = (reg1 > reg2); |
b7b89deb JL |
1428 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1429 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1430 | |
1431 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1432 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1433 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1434 | } |
1435 | ||
de0dce7c | 1436 | /* mul dm, dn */ |
d2523010 JL |
1437 | void OP_F240 (insn, extension) |
1438 | unsigned long insn, extension; | |
05ccbdfd | 1439 | { |
707641f6 JL |
1440 | unsigned long long temp; |
1441 | int n, z; | |
1442 | ||
65b784d8 JL |
1443 | temp = ((signed long)State.regs[REG_D0 + REG0 (insn)] |
1444 | * (signed long)State.regs[REG_D0 + REG1 (insn)]); | |
9f4a551e | 1445 | State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; |
65b784d8 | 1446 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;; |
9f4a551e JL |
1447 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); |
1448 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1449 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1450 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1451 | } |
1452 | ||
de0dce7c | 1453 | /* mulu dm, dn */ |
d2523010 JL |
1454 | void OP_F250 (insn, extension) |
1455 | unsigned long insn, extension; | |
05ccbdfd | 1456 | { |
707641f6 JL |
1457 | unsigned long long temp; |
1458 | int n, z; | |
1459 | ||
9f4a551e JL |
1460 | temp = (State.regs[REG_D0 + REG0 (insn)] |
1461 | * State.regs[REG_D0 + REG1 (insn)]); | |
1462 | State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; | |
65b784d8 | 1463 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; |
9f4a551e JL |
1464 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); |
1465 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1466 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1467 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1468 | } |
1469 | ||
de0dce7c | 1470 | /* div dm, dn */ |
d2523010 JL |
1471 | void OP_F260 (insn, extension) |
1472 | unsigned long insn, extension; | |
05ccbdfd | 1473 | { |
707641f6 JL |
1474 | long long temp; |
1475 | int n, z; | |
1476 | ||
1477 | temp = State.regs[REG_MDR]; | |
1478 | temp <<= 32; | |
9f4a551e JL |
1479 | temp |= State.regs[REG_D0 + REG0 (insn)]; |
1480 | State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + REG1 (insn)]; | |
1481 | temp /= (long)State.regs[REG_D0 + REG1 (insn)]; | |
1482 | State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; | |
9f4a551e JL |
1483 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); |
1484 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1485 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1486 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1487 | } |
1488 | ||
de0dce7c | 1489 | /* divu dm, dn */ |
d2523010 JL |
1490 | void OP_F270 (insn, extension) |
1491 | unsigned long insn, extension; | |
05ccbdfd | 1492 | { |
707641f6 JL |
1493 | unsigned long long temp; |
1494 | int n, z; | |
1495 | ||
1496 | temp = State.regs[REG_MDR]; | |
1497 | temp <<= 32; | |
9f4a551e JL |
1498 | temp |= State.regs[REG_D0 + REG0 (insn)]; |
1499 | State.regs[REG_MDR] = temp % State.regs[REG_D0 + REG1 (insn)]; | |
1500 | temp /= State.regs[REG_D0 + REG1 (insn)]; | |
1501 | State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; | |
9f4a551e JL |
1502 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); |
1503 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1504 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1505 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1506 | } |
1507 | ||
73e65298 | 1508 | /* inc dn */ |
d2523010 JL |
1509 | void OP_40 (insn, extension) |
1510 | unsigned long insn, extension; | |
05ccbdfd | 1511 | { |
61ecca95 | 1512 | int z,n,c,v; |
4d8ced6c | 1513 | unsigned int value, imm, reg1; |
61ecca95 | 1514 | |
9f4a551e | 1515 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
4d8ced6c JL |
1516 | imm = 1; |
1517 | value = reg1 + imm; | |
9f4a551e | 1518 | State.regs[REG_D0 + REG1 (insn)] = value; |
61ecca95 JL |
1519 | |
1520 | z = (value == 0); | |
1521 | n = (value & 0x80000000); | |
4d8ced6c | 1522 | c = (reg1 < imm); |
d657034d | 1523 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
4d8ced6c | 1524 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
61ecca95 JL |
1525 | |
1526 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1527 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1528 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1529 | } |
1530 | ||
73e65298 | 1531 | /* inc an */ |
d2523010 JL |
1532 | void OP_41 (insn, extension) |
1533 | unsigned long insn, extension; | |
05ccbdfd | 1534 | { |
9f4a551e | 1535 | State.regs[REG_A0 + REG1 (insn)] += 1; |
05ccbdfd JL |
1536 | } |
1537 | ||
92284aaa | 1538 | /* inc4 an */ |
d2523010 JL |
1539 | void OP_50 (insn, extension) |
1540 | unsigned long insn, extension; | |
05ccbdfd | 1541 | { |
9f4a551e | 1542 | State.regs[REG_A0 + REG0 (insn)] += 4; |
05ccbdfd JL |
1543 | } |
1544 | ||
92284aaa | 1545 | /* cmp imm8, dn */ |
d2523010 JL |
1546 | void OP_A000 (insn, extension) |
1547 | unsigned long insn, extension; | |
05ccbdfd | 1548 | { |
92284aaa JL |
1549 | int z, c, n, v; |
1550 | unsigned long reg1, imm, value; | |
1551 | ||
9f4a551e | 1552 | reg1 = State.regs[REG_D0 + REG0_8 (insn)]; |
92284aaa JL |
1553 | imm = SEXT8 (insn & 0xff); |
1554 | value = reg1 - imm; | |
1555 | ||
1556 | z = (value == 0); | |
1557 | n = (value & 0x80000000); | |
1558 | c = (reg1 < imm); | |
b7b89deb JL |
1559 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1560 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1561 | |
1562 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1563 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1564 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1565 | } |
1566 | ||
92284aaa | 1567 | /* cmp dm, dn */ |
d2523010 JL |
1568 | void OP_A0 (insn, extension) |
1569 | unsigned long insn, extension; | |
05ccbdfd | 1570 | { |
92284aaa JL |
1571 | int z, c, n, v; |
1572 | unsigned long reg1, reg2, value; | |
1573 | ||
9f4a551e JL |
1574 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1575 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
707641f6 | 1576 | value = reg2 - reg1; |
92284aaa JL |
1577 | |
1578 | z = (value == 0); | |
1579 | n = (value & 0x80000000); | |
216e6557 | 1580 | c = (reg1 > reg2); |
b7b89deb JL |
1581 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1582 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1583 | |
1584 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1585 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1586 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1587 | } |
1588 | ||
92284aaa | 1589 | /* cmp dm, an */ |
d2523010 JL |
1590 | void OP_F1A0 (insn, extension) |
1591 | unsigned long insn, extension; | |
05ccbdfd | 1592 | { |
92284aaa JL |
1593 | int z, c, n, v; |
1594 | unsigned long reg1, reg2, value; | |
1595 | ||
9f4a551e JL |
1596 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1597 | reg2 = State.regs[REG_A0 + REG0 (insn)]; | |
707641f6 | 1598 | value = reg2 - reg1; |
92284aaa JL |
1599 | |
1600 | z = (value == 0); | |
1601 | n = (value & 0x80000000); | |
216e6557 | 1602 | c = (reg1 > reg2); |
b7b89deb JL |
1603 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1604 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1605 | |
1606 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1607 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1608 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1609 | } |
1610 | ||
92284aaa | 1611 | /* cmp am, dn */ |
d2523010 JL |
1612 | void OP_F190 (insn, extension) |
1613 | unsigned long insn, extension; | |
05ccbdfd | 1614 | { |
92284aaa JL |
1615 | int z, c, n, v; |
1616 | unsigned long reg1, reg2, value; | |
1617 | ||
9f4a551e JL |
1618 | reg1 = State.regs[REG_A0 + REG1 (insn)]; |
1619 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
707641f6 | 1620 | value = reg2 - reg1; |
92284aaa JL |
1621 | |
1622 | z = (value == 0); | |
1623 | n = (value & 0x80000000); | |
216e6557 | 1624 | c = (reg1 > reg2); |
b7b89deb JL |
1625 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1626 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1627 | |
1628 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1629 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1630 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1631 | } |
1632 | ||
92284aaa | 1633 | /* cmp imm8, an */ |
d2523010 JL |
1634 | void OP_B000 (insn, extension) |
1635 | unsigned long insn, extension; | |
05ccbdfd | 1636 | { |
92284aaa JL |
1637 | int z, c, n, v; |
1638 | unsigned long reg1, imm, value; | |
1639 | ||
9f4a551e | 1640 | reg1 = State.regs[REG_A0 + REG0_8 (insn)]; |
92284aaa JL |
1641 | imm = insn & 0xff; |
1642 | value = reg1 - imm; | |
1643 | ||
1644 | z = (value == 0); | |
1645 | n = (value & 0x80000000); | |
1646 | c = (reg1 < imm); | |
b7b89deb JL |
1647 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1648 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1649 | |
1650 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1651 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1652 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1653 | } |
1654 | ||
707641f6 | 1655 | /* cmp am, an */ |
d2523010 JL |
1656 | void OP_B0 (insn, extension) |
1657 | unsigned long insn, extension; | |
05ccbdfd | 1658 | { |
73e65298 JL |
1659 | int z, c, n, v; |
1660 | unsigned long reg1, reg2, value; | |
1661 | ||
9f4a551e JL |
1662 | reg1 = State.regs[REG_A0 + REG1 (insn)]; |
1663 | reg2 = State.regs[REG_A0 + REG0 (insn)]; | |
707641f6 | 1664 | value = reg2 - reg1; |
73e65298 JL |
1665 | |
1666 | z = (value == 0); | |
1667 | n = (value & 0x80000000); | |
216e6557 | 1668 | c = (reg1 > reg2); |
b7b89deb JL |
1669 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1670 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
73e65298 JL |
1671 | |
1672 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1673 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1674 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1675 | } |
1676 | ||
707641f6 | 1677 | /* cmp imm16, dn */ |
d2523010 JL |
1678 | void OP_FAC80000 (insn, extension) |
1679 | unsigned long insn, extension; | |
05ccbdfd | 1680 | { |
92284aaa JL |
1681 | int z, c, n, v; |
1682 | unsigned long reg1, imm, value; | |
1683 | ||
9f4a551e | 1684 | reg1 = State.regs[REG_D0 + REG0_16 (insn)]; |
92284aaa JL |
1685 | imm = SEXT16 (insn & 0xffff); |
1686 | value = reg1 - imm; | |
1687 | ||
1688 | z = (value == 0); | |
1689 | n = (value & 0x80000000); | |
1690 | c = (reg1 < imm); | |
b7b89deb JL |
1691 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1692 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1693 | |
1694 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1695 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1696 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1697 | } |
1698 | ||
707641f6 | 1699 | /* cmp imm32, dn */ |
d2523010 JL |
1700 | void OP_FCC80000 (insn, extension) |
1701 | unsigned long insn, extension; | |
05ccbdfd | 1702 | { |
92284aaa JL |
1703 | int z, c, n, v; |
1704 | unsigned long reg1, imm, value; | |
1705 | ||
9f4a551e | 1706 | reg1 = State.regs[REG_D0 + REG0_16 (insn)]; |
7c52bf32 | 1707 | imm = ((insn & 0xffff) << 16) + extension; |
92284aaa JL |
1708 | value = reg1 - imm; |
1709 | ||
1710 | z = (value == 0); | |
1711 | n = (value & 0x80000000); | |
1712 | c = (reg1 < imm); | |
b7b89deb JL |
1713 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1714 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1715 | |
1716 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1717 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1718 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1719 | } |
1720 | ||
707641f6 | 1721 | /* cmp imm16, an */ |
d2523010 JL |
1722 | void OP_FAD80000 (insn, extension) |
1723 | unsigned long insn, extension; | |
05ccbdfd | 1724 | { |
92284aaa JL |
1725 | int z, c, n, v; |
1726 | unsigned long reg1, imm, value; | |
1727 | ||
9f4a551e | 1728 | reg1 = State.regs[REG_A0 + REG0_16 (insn)]; |
92284aaa JL |
1729 | imm = insn & 0xffff; |
1730 | value = reg1 - imm; | |
1731 | ||
1732 | z = (value == 0); | |
1733 | n = (value & 0x80000000); | |
1734 | c = (reg1 < imm); | |
b7b89deb JL |
1735 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1736 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1737 | |
1738 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1739 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1740 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1741 | } |
1742 | ||
707641f6 | 1743 | /* cmp imm32, an */ |
d2523010 JL |
1744 | void OP_FCD80000 (insn, extension) |
1745 | unsigned long insn, extension; | |
05ccbdfd | 1746 | { |
92284aaa JL |
1747 | int z, c, n, v; |
1748 | unsigned long reg1, imm, value; | |
1749 | ||
9f4a551e | 1750 | reg1 = State.regs[REG_A0 + REG0_16 (insn)]; |
7c52bf32 | 1751 | imm = ((insn & 0xffff) << 16) + extension; |
92284aaa JL |
1752 | value = reg1 - imm; |
1753 | ||
1754 | z = (value == 0); | |
1755 | n = (value & 0x80000000); | |
1756 | c = (reg1 < imm); | |
b7b89deb JL |
1757 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1758 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1759 | |
1760 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1761 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1762 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1763 | } |
1764 | ||
707641f6 | 1765 | /* and dm, dn */ |
d2523010 JL |
1766 | void OP_F200 (insn, extension) |
1767 | unsigned long insn, extension; | |
05ccbdfd | 1768 | { |
707641f6 JL |
1769 | int n, z; |
1770 | ||
9f4a551e JL |
1771 | State.regs[REG_D0 + REG0 (insn)] &= State.regs[REG_D0 + REG1 (insn)]; |
1772 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
1773 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1774 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1775 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1776 | } |
1777 | ||
2e35551c | 1778 | /* and imm8, dn */ |
d2523010 JL |
1779 | void OP_F8E000 (insn, extension) |
1780 | unsigned long insn, extension; | |
05ccbdfd | 1781 | { |
2e35551c JL |
1782 | int n, z; |
1783 | ||
9f4a551e JL |
1784 | State.regs[REG_D0 + REG0_8 (insn)] &= (insn & 0xff); |
1785 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); | |
1786 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
2e35551c JL |
1787 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1788 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1789 | } |
1790 | ||
ecb4b5a3 | 1791 | /* and imm16, dn */ |
d2523010 JL |
1792 | void OP_FAE00000 (insn, extension) |
1793 | unsigned long insn, extension; | |
05ccbdfd | 1794 | { |
ecb4b5a3 JL |
1795 | int n, z; |
1796 | ||
9f4a551e JL |
1797 | State.regs[REG_D0 + REG0_16 (insn)] &= (insn & 0xffff); |
1798 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
1799 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
ecb4b5a3 JL |
1800 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1801 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1802 | } |
1803 | ||
de0dce7c | 1804 | /* and imm32, dn */ |
d2523010 JL |
1805 | void OP_FCE00000 (insn, extension) |
1806 | unsigned long insn, extension; | |
05ccbdfd | 1807 | { |
de0dce7c JL |
1808 | int n, z; |
1809 | ||
9f4a551e | 1810 | State.regs[REG_D0 + REG0_16 (insn)] |
7c52bf32 | 1811 | &= ((insn & 0xffff) << 16) + extension; |
9f4a551e JL |
1812 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); |
1813 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
de0dce7c JL |
1814 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1815 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1816 | } |
1817 | ||
ecb4b5a3 | 1818 | /* and imm16, psw */ |
d2523010 JL |
1819 | void OP_FAFC0000 (insn, extension) |
1820 | unsigned long insn, extension; | |
05ccbdfd | 1821 | { |
ecb4b5a3 | 1822 | PSW &= (insn & 0xffff); |
05ccbdfd JL |
1823 | } |
1824 | ||
707641f6 | 1825 | /* or dm, dn*/ |
d2523010 JL |
1826 | void OP_F210 (insn, extension) |
1827 | unsigned long insn, extension; | |
05ccbdfd | 1828 | { |
707641f6 JL |
1829 | int n, z; |
1830 | ||
9f4a551e JL |
1831 | State.regs[REG_D0 + REG0 (insn)] |= State.regs[REG_D0 + REG1 (insn)]; |
1832 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
1833 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1834 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1835 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1836 | } |
1837 | ||
2e35551c | 1838 | /* or imm8, dn */ |
d2523010 JL |
1839 | void OP_F8E400 (insn, extension) |
1840 | unsigned long insn, extension; | |
05ccbdfd | 1841 | { |
2e35551c JL |
1842 | int n, z; |
1843 | ||
9f4a551e JL |
1844 | State.regs[REG_D0 + REG0_8 (insn)] |= insn & 0xff; |
1845 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); | |
1846 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
2e35551c JL |
1847 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1848 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1849 | } |
1850 | ||
ecb4b5a3 | 1851 | /* or imm16, dn*/ |
d2523010 JL |
1852 | void OP_FAE40000 (insn, extension) |
1853 | unsigned long insn, extension; | |
05ccbdfd | 1854 | { |
ecb4b5a3 JL |
1855 | int n, z; |
1856 | ||
9f4a551e JL |
1857 | State.regs[REG_D0 + REG0_16 (insn)] |= insn & 0xffff; |
1858 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
1859 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
ecb4b5a3 JL |
1860 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1861 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1862 | } |
1863 | ||
de0dce7c | 1864 | /* or imm32, dn */ |
d2523010 JL |
1865 | void OP_FCE40000 (insn, extension) |
1866 | unsigned long insn, extension; | |
05ccbdfd | 1867 | { |
de0dce7c JL |
1868 | int n, z; |
1869 | ||
9f4a551e | 1870 | State.regs[REG_D0 + REG0_16 (insn)] |
7c52bf32 | 1871 | |= ((insn & 0xffff) << 16) + extension; |
9f4a551e JL |
1872 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); |
1873 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
de0dce7c JL |
1874 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1875 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1876 | } |
1877 | ||
ecb4b5a3 | 1878 | /* or imm16,psw */ |
d2523010 JL |
1879 | void OP_FAFD0000 (insn, extension) |
1880 | unsigned long insn, extension; | |
05ccbdfd | 1881 | { |
ecb4b5a3 | 1882 | PSW |= (insn & 0xffff); |
05ccbdfd JL |
1883 | } |
1884 | ||
65b784d8 | 1885 | /* xor dm, dn */ |
d2523010 JL |
1886 | void OP_F220 (insn, extension) |
1887 | unsigned long insn, extension; | |
05ccbdfd | 1888 | { |
707641f6 JL |
1889 | int n, z; |
1890 | ||
9f4a551e JL |
1891 | State.regs[REG_D0 + REG0 (insn)] ^= State.regs[REG_D0 + REG1 (insn)]; |
1892 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
1893 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1894 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1895 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1896 | } |
1897 | ||
ecb4b5a3 | 1898 | /* xor imm16, dn */ |
d2523010 JL |
1899 | void OP_FAE80000 (insn, extension) |
1900 | unsigned long insn, extension; | |
05ccbdfd | 1901 | { |
ecb4b5a3 JL |
1902 | int n, z; |
1903 | ||
9f4a551e JL |
1904 | State.regs[REG_D0 + REG0_16 (insn)] ^= insn & 0xffff; |
1905 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
1906 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
ecb4b5a3 JL |
1907 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1908 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1909 | } |
1910 | ||
de0dce7c | 1911 | /* xor imm32, dn */ |
d2523010 JL |
1912 | void OP_FCE80000 (insn, extension) |
1913 | unsigned long insn, extension; | |
05ccbdfd | 1914 | { |
de0dce7c JL |
1915 | int n, z; |
1916 | ||
9f4a551e | 1917 | State.regs[REG_D0 + REG0_16 (insn)] |
7c52bf32 | 1918 | ^= ((insn & 0xffff) << 16) + extension; |
9f4a551e JL |
1919 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); |
1920 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
de0dce7c JL |
1921 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1922 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1923 | } |
1924 | ||
de0dce7c | 1925 | /* not dn */ |
d2523010 JL |
1926 | void OP_F230 (insn, extension) |
1927 | unsigned long insn, extension; | |
05ccbdfd | 1928 | { |
707641f6 JL |
1929 | int n, z; |
1930 | ||
9f4a551e JL |
1931 | State.regs[REG_D0 + REG0 (insn)] = ~State.regs[REG_D0 + REG0 (insn)]; |
1932 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
1933 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1934 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1935 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1936 | } |
1937 | ||
2e35551c | 1938 | /* btst imm8, dn */ |
d2523010 JL |
1939 | void OP_F8EC00 (insn, extension) |
1940 | unsigned long insn, extension; | |
05ccbdfd | 1941 | { |
2e35551c JL |
1942 | unsigned long temp; |
1943 | int z, n; | |
1944 | ||
9f4a551e | 1945 | temp = State.regs[REG_D0 + REG0_8 (insn)]; |
2e35551c JL |
1946 | temp &= (insn & 0xff); |
1947 | n = (temp & 0x80000000) != 0; | |
1948 | z = (temp == 0); | |
1949 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1950 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
05ccbdfd JL |
1951 | } |
1952 | ||
ecb4b5a3 | 1953 | /* btst imm16, dn */ |
d2523010 JL |
1954 | void OP_FAEC0000 (insn, extension) |
1955 | unsigned long insn, extension; | |
05ccbdfd | 1956 | { |
ecb4b5a3 JL |
1957 | unsigned long temp; |
1958 | int z, n; | |
1959 | ||
9f4a551e | 1960 | temp = State.regs[REG_D0 + REG0_16 (insn)]; |
ecb4b5a3 JL |
1961 | temp &= (insn & 0xffff); |
1962 | n = (temp & 0x80000000) != 0; | |
1963 | z = (temp == 0); | |
1964 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1965 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
05ccbdfd JL |
1966 | } |
1967 | ||
de0dce7c | 1968 | /* btst imm32, dn */ |
d2523010 JL |
1969 | void OP_FCEC0000 (insn, extension) |
1970 | unsigned long insn, extension; | |
05ccbdfd | 1971 | { |
de0dce7c JL |
1972 | unsigned long temp; |
1973 | int z, n; | |
1974 | ||
9f4a551e | 1975 | temp = State.regs[REG_D0 + REG0_16 (insn)]; |
7c52bf32 | 1976 | temp &= ((insn & 0xffff) << 16) + extension; |
de0dce7c JL |
1977 | n = (temp & 0x80000000) != 0; |
1978 | z = (temp == 0); | |
1979 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1980 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
05ccbdfd JL |
1981 | } |
1982 | ||
de0dce7c | 1983 | /* btst imm8,(abs32) */ |
d2523010 JL |
1984 | void OP_FE020000 (insn, extension) |
1985 | unsigned long insn, extension; | |
05ccbdfd | 1986 | { |
de0dce7c JL |
1987 | unsigned long temp; |
1988 | int n, z; | |
1989 | ||
1990 | temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1); | |
1991 | temp &= (extension & 0xff); | |
1992 | n = (temp & 0x80000000) != 0; | |
1993 | z = (temp == 0); | |
1994 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1995 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
05ccbdfd JL |
1996 | } |
1997 | ||
ecb4b5a3 | 1998 | /* btst imm8,(d8,an) */ |
d2523010 JL |
1999 | void OP_FAF80000 (insn, extension) |
2000 | unsigned long insn, extension; | |
05ccbdfd | 2001 | { |
ecb4b5a3 JL |
2002 | unsigned long temp; |
2003 | int n, z; | |
2004 | ||
9f4a551e | 2005 | temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)] |
ecb4b5a3 JL |
2006 | + SEXT8 ((insn & 0xff00) >> 8)), 1); |
2007 | temp &= (insn & 0xff); | |
2008 | n = (temp & 0x80000000) != 0; | |
2009 | z = (temp == 0); | |
2010 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2011 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
05ccbdfd JL |
2012 | } |
2013 | ||
707641f6 | 2014 | /* bset dm, (an) */ |
d2523010 JL |
2015 | void OP_F080 (insn, extension) |
2016 | unsigned long insn, extension; | |
05ccbdfd | 2017 | { |
707641f6 JL |
2018 | unsigned long temp; |
2019 | int z; | |
2020 | ||
2da0bc1b | 2021 | temp = load_mem (State.regs[REG_A0 + REG0 (insn)], 1); |
9f4a551e JL |
2022 | z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0; |
2023 | temp |= State.regs[REG_D0 + REG1 (insn)]; | |
2da0bc1b | 2024 | store_mem (State.regs[REG_A0 + REG0 (insn)], 1, temp); |
707641f6 JL |
2025 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2026 | PSW |= (z ? PSW_Z : 0); | |
05ccbdfd JL |
2027 | } |
2028 | ||
de0dce7c | 2029 | /* bset imm8, (abs32) */ |
d2523010 JL |
2030 | void OP_FE000000 (insn, extension) |
2031 | unsigned long insn, extension; | |
05ccbdfd | 2032 | { |
de0dce7c JL |
2033 | unsigned long temp; |
2034 | int z; | |
2035 | ||
2036 | temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1); | |
2037 | z = (temp & (extension & 0xff)) == 0; | |
2038 | temp |= (extension & 0xff); | |
2039 | store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp); | |
2040 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2041 | PSW |= (z ? PSW_Z : 0); | |
05ccbdfd JL |
2042 | } |
2043 | ||
ecb4b5a3 | 2044 | /* bset imm8,(d8,an) */ |
d2523010 JL |
2045 | void OP_FAF00000 (insn, extension) |
2046 | unsigned long insn, extension; | |
05ccbdfd | 2047 | { |
ecb4b5a3 JL |
2048 | unsigned long temp; |
2049 | int z; | |
2050 | ||
9f4a551e | 2051 | temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)] |
ecb4b5a3 JL |
2052 | + SEXT8 ((insn & 0xff00) >> 8)), 1); |
2053 | z = (temp & (insn & 0xff)) == 0; | |
2054 | temp |= (insn & 0xff); | |
09eef8af JL |
2055 | store_mem ((State.regs[REG_A0 + REG0_16 (insn)] |
2056 | + SEXT8 ((insn & 0xff00) >> 8)), 1, temp); | |
ecb4b5a3 JL |
2057 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2058 | PSW |= (z ? PSW_Z : 0); | |
05ccbdfd JL |
2059 | } |
2060 | ||
707641f6 | 2061 | /* bclr dm, (an) */ |
d2523010 JL |
2062 | void OP_F090 (insn, extension) |
2063 | unsigned long insn, extension; | |
05ccbdfd | 2064 | { |
707641f6 JL |
2065 | unsigned long temp; |
2066 | int z; | |
2067 | ||
2da0bc1b | 2068 | temp = load_mem (State.regs[REG_A0 + REG0 (insn)], 1); |
9f4a551e | 2069 | z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0; |
09eef8af | 2070 | temp = temp & ~State.regs[REG_D0 + REG1 (insn)]; |
2da0bc1b | 2071 | store_mem (State.regs[REG_A0 + REG0 (insn)], 1, temp); |
707641f6 JL |
2072 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2073 | PSW |= (z ? PSW_Z : 0); | |
05ccbdfd JL |
2074 | } |
2075 | ||
de0dce7c | 2076 | /* bclr imm8, (abs32) */ |
d2523010 JL |
2077 | void OP_FE010000 (insn, extension) |
2078 | unsigned long insn, extension; | |
05ccbdfd | 2079 | { |
de0dce7c JL |
2080 | unsigned long temp; |
2081 | int z; | |
2082 | ||
2083 | temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1); | |
2084 | z = (temp & (extension & 0xff)) == 0; | |
09eef8af | 2085 | temp = temp & ~(extension & 0xff); |
de0dce7c JL |
2086 | store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp); |
2087 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2088 | PSW |= (z ? PSW_Z : 0); | |
05ccbdfd JL |
2089 | } |
2090 | ||
ecb4b5a3 | 2091 | /* bclr imm8,(d8,an) */ |
d2523010 JL |
2092 | void OP_FAF40000 (insn, extension) |
2093 | unsigned long insn, extension; | |
05ccbdfd | 2094 | { |
ecb4b5a3 JL |
2095 | unsigned long temp; |
2096 | int z; | |
2097 | ||
9f4a551e | 2098 | temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)] |
ecb4b5a3 JL |
2099 | + SEXT8 ((insn & 0xff00) >> 8)), 1); |
2100 | z = (temp & (insn & 0xff)) == 0; | |
09eef8af JL |
2101 | temp = temp & ~(insn & 0xff); |
2102 | store_mem ((State.regs[REG_A0 + REG0_16 (insn)] | |
2103 | + SEXT8 ((insn & 0xff00) >> 8)), 1, temp); | |
ecb4b5a3 JL |
2104 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2105 | PSW |= (z ? PSW_Z : 0); | |
05ccbdfd JL |
2106 | } |
2107 | ||
2e35551c | 2108 | /* asr dm, dn */ |
d2523010 JL |
2109 | void OP_F2B0 (insn, extension) |
2110 | unsigned long insn, extension; | |
05ccbdfd | 2111 | { |
707641f6 JL |
2112 | long temp; |
2113 | int z, n, c; | |
2114 | ||
9f4a551e | 2115 | temp = State.regs[REG_D0 + REG0 (insn)]; |
707641f6 | 2116 | c = temp & 1; |
9f4a551e JL |
2117 | temp >>= State.regs[REG_D0 + REG1 (insn)]; |
2118 | State.regs[REG_D0 + REG0 (insn)] = temp; | |
2119 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
2120 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
2121 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
2122 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
05ccbdfd JL |
2123 | } |
2124 | ||
2e35551c | 2125 | /* asr imm8, dn */ |
d2523010 JL |
2126 | void OP_F8C800 (insn, extension) |
2127 | unsigned long insn, extension; | |
05ccbdfd | 2128 | { |
2e35551c JL |
2129 | long temp; |
2130 | int z, n, c; | |
2131 | ||
9f4a551e | 2132 | temp = State.regs[REG_D0 + REG0_8 (insn)]; |
2e35551c JL |
2133 | c = temp & 1; |
2134 | temp >>= (insn & 0xff); | |
9f4a551e JL |
2135 | State.regs[REG_D0 + REG0_8 (insn)] = temp; |
2136 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); | |
2137 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
2e35551c JL |
2138 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
2139 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
05ccbdfd JL |
2140 | } |
2141 | ||
2e35551c | 2142 | /* lsr dm, dn */ |
d2523010 JL |
2143 | void OP_F2A0 (insn, extension) |
2144 | unsigned long insn, extension; | |
05ccbdfd | 2145 | { |
707641f6 JL |
2146 | int z, n, c; |
2147 | ||
9f4a551e JL |
2148 | c = State.regs[REG_D0 + REG0 (insn)] & 1; |
2149 | State.regs[REG_D0 + REG0 (insn)] | |
2150 | >>= State.regs[REG_D0 + REG1 (insn)]; | |
2151 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
2152 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
2153 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
2154 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
05ccbdfd JL |
2155 | } |
2156 | ||
43eb4bed | 2157 | /* lsr imm8, dn */ |
d2523010 JL |
2158 | void OP_F8C400 (insn, extension) |
2159 | unsigned long insn, extension; | |
05ccbdfd | 2160 | { |
2e35551c JL |
2161 | int z, n, c; |
2162 | ||
9f4a551e JL |
2163 | c = State.regs[REG_D0 + REG0_8 (insn)] & 1; |
2164 | State.regs[REG_D0 + REG0_8 (insn)] >>= (insn & 0xff); | |
43eb4bed JL |
2165 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); |
2166 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
2e35551c JL |
2167 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
2168 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
05ccbdfd JL |
2169 | } |
2170 | ||
2e35551c | 2171 | /* asl dm, dn */ |
d2523010 JL |
2172 | void OP_F290 (insn, extension) |
2173 | unsigned long insn, extension; | |
05ccbdfd | 2174 | { |
707641f6 JL |
2175 | int n, z; |
2176 | ||
9f4a551e JL |
2177 | State.regs[REG_D0 + REG0 (insn)] |
2178 | <<= State.regs[REG_D0 + REG1 (insn)]; | |
2179 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
2180 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
2181 | PSW &= ~(PSW_Z | PSW_N); |
2182 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
2183 | } |
2184 | ||
2e35551c | 2185 | /* asl imm8, dn */ |
d2523010 JL |
2186 | void OP_F8C000 (insn, extension) |
2187 | unsigned long insn, extension; | |
05ccbdfd | 2188 | { |
2e35551c JL |
2189 | int n, z; |
2190 | ||
9f4a551e JL |
2191 | State.regs[REG_D0 + REG0_8 (insn)] <<= (insn & 0xff); |
2192 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); | |
2193 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
2e35551c JL |
2194 | PSW &= ~(PSW_Z | PSW_N); |
2195 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
2196 | } |
2197 | ||
707641f6 | 2198 | /* asl2 dn */ |
d2523010 JL |
2199 | void OP_54 (insn, extension) |
2200 | unsigned long insn, extension; | |
05ccbdfd | 2201 | { |
707641f6 JL |
2202 | int n, z; |
2203 | ||
9f4a551e JL |
2204 | State.regs[REG_D0 + REG0 (insn)] <<= 2; |
2205 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
2206 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
2207 | PSW &= ~(PSW_Z | PSW_N); |
2208 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
2209 | } |
2210 | ||
707641f6 | 2211 | /* ror dn */ |
d2523010 JL |
2212 | void OP_F284 (insn, extension) |
2213 | unsigned long insn, extension; | |
05ccbdfd | 2214 | { |
707641f6 JL |
2215 | unsigned long value; |
2216 | int c,n,z; | |
2217 | ||
9f4a551e | 2218 | value = State.regs[REG_D0 + REG0 (insn)]; |
7c52bf32 | 2219 | c = (value & 0x1); |
707641f6 JL |
2220 | |
2221 | value >>= 1; | |
f95251f0 | 2222 | value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0; |
9f4a551e | 2223 | State.regs[REG_D0 + REG0 (insn)] = value; |
707641f6 | 2224 | z = (value == 0); |
b7b89deb | 2225 | n = (value & 0x80000000) != 0; |
707641f6 JL |
2226 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2227 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
05ccbdfd JL |
2228 | } |
2229 | ||
707641f6 | 2230 | /* rol dn */ |
d2523010 JL |
2231 | void OP_F280 (insn, extension) |
2232 | unsigned long insn, extension; | |
05ccbdfd | 2233 | { |
707641f6 JL |
2234 | unsigned long value; |
2235 | int c,n,z; | |
2236 | ||
9f4a551e | 2237 | value = State.regs[REG_D0 + REG0 (insn)]; |
7c52bf32 | 2238 | c = (value & 0x80000000) ? 1 : 0; |
707641f6 JL |
2239 | |
2240 | value <<= 1; | |
f95251f0 | 2241 | value |= ((PSW & PSW_C) != 0); |
9f4a551e | 2242 | State.regs[REG_D0 + REG0 (insn)] = value; |
707641f6 | 2243 | z = (value == 0); |
b7b89deb | 2244 | n = (value & 0x80000000) != 0; |
707641f6 JL |
2245 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2246 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
05ccbdfd JL |
2247 | } |
2248 | ||
f5f13c1d | 2249 | /* beq label:8 */ |
d2523010 JL |
2250 | void OP_C800 (insn, extension) |
2251 | unsigned long insn, extension; | |
05ccbdfd | 2252 | { |
73e65298 JL |
2253 | /* The dispatching code will add 2 after we return, so |
2254 | we subtract two here to make things right. */ | |
2255 | if (PSW & PSW_Z) | |
b774c0e4 | 2256 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2257 | } |
2258 | ||
f5f13c1d | 2259 | /* bne label:8 */ |
d2523010 JL |
2260 | void OP_C900 (insn, extension) |
2261 | unsigned long insn, extension; | |
05ccbdfd | 2262 | { |
73e65298 JL |
2263 | /* The dispatching code will add 2 after we return, so |
2264 | we subtract two here to make things right. */ | |
2265 | if (!(PSW & PSW_Z)) | |
b774c0e4 | 2266 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2267 | } |
2268 | ||
f5f13c1d | 2269 | /* bgt label:8 */ |
d2523010 JL |
2270 | void OP_C100 (insn, extension) |
2271 | unsigned long insn, extension; | |
05ccbdfd | 2272 | { |
f5f13c1d JL |
2273 | /* The dispatching code will add 2 after we return, so |
2274 | we subtract two here to make things right. */ | |
2275 | if (!((PSW & PSW_Z) | |
7c52bf32 | 2276 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))) |
b774c0e4 | 2277 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2278 | } |
2279 | ||
f5f13c1d | 2280 | /* bge label:8 */ |
d2523010 JL |
2281 | void OP_C200 (insn, extension) |
2282 | unsigned long insn, extension; | |
05ccbdfd | 2283 | { |
f5f13c1d JL |
2284 | /* The dispatching code will add 2 after we return, so |
2285 | we subtract two here to make things right. */ | |
7c52bf32 | 2286 | if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) |
b774c0e4 | 2287 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2288 | } |
2289 | ||
f5f13c1d | 2290 | /* ble label:8 */ |
d2523010 JL |
2291 | void OP_C300 (insn, extension) |
2292 | unsigned long insn, extension; | |
05ccbdfd | 2293 | { |
f5f13c1d JL |
2294 | /* The dispatching code will add 2 after we return, so |
2295 | we subtract two here to make things right. */ | |
2296 | if ((PSW & PSW_Z) | |
7c52bf32 | 2297 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) |
b774c0e4 | 2298 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2299 | } |
2300 | ||
f5f13c1d | 2301 | /* blt label:8 */ |
d2523010 JL |
2302 | void OP_C000 (insn, extension) |
2303 | unsigned long insn, extension; | |
05ccbdfd | 2304 | { |
f5f13c1d JL |
2305 | /* The dispatching code will add 2 after we return, so |
2306 | we subtract two here to make things right. */ | |
7c52bf32 | 2307 | if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)) |
b774c0e4 | 2308 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2309 | } |
2310 | ||
f5f13c1d | 2311 | /* bhi label:8 */ |
d2523010 JL |
2312 | void OP_C500 (insn, extension) |
2313 | unsigned long insn, extension; | |
05ccbdfd | 2314 | { |
f5f13c1d JL |
2315 | /* The dispatching code will add 2 after we return, so |
2316 | we subtract two here to make things right. */ | |
2317 | if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)) | |
b774c0e4 | 2318 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2319 | } |
2320 | ||
f5f13c1d | 2321 | /* bcc label:8 */ |
d2523010 JL |
2322 | void OP_C600 (insn, extension) |
2323 | unsigned long insn, extension; | |
05ccbdfd | 2324 | { |
f5f13c1d JL |
2325 | /* The dispatching code will add 2 after we return, so |
2326 | we subtract two here to make things right. */ | |
2327 | if (!(PSW & PSW_C)) | |
b774c0e4 | 2328 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2329 | } |
2330 | ||
f5f13c1d | 2331 | /* bls label:8 */ |
d2523010 JL |
2332 | void OP_C700 (insn, extension) |
2333 | unsigned long insn, extension; | |
05ccbdfd | 2334 | { |
f5f13c1d JL |
2335 | /* The dispatching code will add 2 after we return, so |
2336 | we subtract two here to make things right. */ | |
2337 | if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0) | |
b774c0e4 | 2338 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2339 | } |
2340 | ||
f5f13c1d | 2341 | /* bcs label:8 */ |
d2523010 JL |
2342 | void OP_C400 (insn, extension) |
2343 | unsigned long insn, extension; | |
05ccbdfd | 2344 | { |
f5f13c1d JL |
2345 | /* The dispatching code will add 2 after we return, so |
2346 | we subtract two here to make things right. */ | |
2347 | if (PSW & PSW_C) | |
b774c0e4 | 2348 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2349 | } |
2350 | ||
f5f13c1d | 2351 | /* bvc label:8 */ |
d2523010 JL |
2352 | void OP_F8E800 (insn, extension) |
2353 | unsigned long insn, extension; | |
05ccbdfd | 2354 | { |
f5f13c1d JL |
2355 | /* The dispatching code will add 3 after we return, so |
2356 | we subtract two here to make things right. */ | |
2357 | if (!(PSW & PSW_V)) | |
b774c0e4 | 2358 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3; |
05ccbdfd JL |
2359 | } |
2360 | ||
f5f13c1d | 2361 | /* bvs label:8 */ |
d2523010 JL |
2362 | void OP_F8E900 (insn, extension) |
2363 | unsigned long insn, extension; | |
05ccbdfd | 2364 | { |
f5f13c1d JL |
2365 | /* The dispatching code will add 3 after we return, so |
2366 | we subtract two here to make things right. */ | |
2367 | if (PSW & PSW_V) | |
b774c0e4 | 2368 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3; |
05ccbdfd JL |
2369 | } |
2370 | ||
f5f13c1d | 2371 | /* bnc label:8 */ |
d2523010 JL |
2372 | void OP_F8EA00 (insn, extension) |
2373 | unsigned long insn, extension; | |
05ccbdfd | 2374 | { |
f5f13c1d JL |
2375 | /* The dispatching code will add 3 after we return, so |
2376 | we subtract two here to make things right. */ | |
2377 | if (!(PSW & PSW_N)) | |
b774c0e4 | 2378 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3; |
05ccbdfd JL |
2379 | } |
2380 | ||
f5f13c1d | 2381 | /* bns label:8 */ |
d2523010 JL |
2382 | void OP_F8EB00 (insn, extension) |
2383 | unsigned long insn, extension; | |
05ccbdfd | 2384 | { |
f5f13c1d JL |
2385 | /* The dispatching code will add 3 after we return, so |
2386 | we subtract two here to make things right. */ | |
2387 | if (PSW & PSW_N) | |
b774c0e4 | 2388 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3; |
05ccbdfd JL |
2389 | } |
2390 | ||
f5f13c1d | 2391 | /* bra label:8 */ |
d2523010 JL |
2392 | void OP_CA00 (insn, extension) |
2393 | unsigned long insn, extension; | |
05ccbdfd | 2394 | { |
f5f13c1d JL |
2395 | /* The dispatching code will add 2 after we return, so |
2396 | we subtract two here to make things right. */ | |
b774c0e4 | 2397 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2398 | } |
2399 | ||
2400 | /* leq */ | |
d2523010 JL |
2401 | void OP_D8 (insn, extension) |
2402 | unsigned long insn, extension; | |
05ccbdfd | 2403 | { |
65b784d8 JL |
2404 | /* The dispatching code will add 1 after we return, so |
2405 | we subtract one here to make things right. */ | |
2406 | if (PSW & PSW_Z) | |
2407 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2408 | } |
2409 | ||
2410 | /* lne */ | |
d2523010 JL |
2411 | void OP_D9 (insn, extension) |
2412 | unsigned long insn, extension; | |
05ccbdfd | 2413 | { |
65b784d8 JL |
2414 | /* The dispatching code will add 1 after we return, so |
2415 | we subtract one here to make things right. */ | |
2416 | if (!(PSW & PSW_Z)) | |
2417 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2418 | } |
2419 | ||
2420 | /* lgt */ | |
d2523010 JL |
2421 | void OP_D1 (insn, extension) |
2422 | unsigned long insn, extension; | |
05ccbdfd | 2423 | { |
65b784d8 JL |
2424 | /* The dispatching code will add 1 after we return, so |
2425 | we subtract one here to make things right. */ | |
2426 | if (!((PSW & PSW_Z) | |
2427 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))) | |
2428 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2429 | } |
2430 | ||
2431 | /* lge */ | |
d2523010 JL |
2432 | void OP_D2 (insn, extension) |
2433 | unsigned long insn, extension; | |
05ccbdfd | 2434 | { |
65b784d8 JL |
2435 | /* The dispatching code will add 1 after we return, so |
2436 | we subtract one here to make things right. */ | |
2437 | if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) | |
2438 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2439 | } |
2440 | ||
2441 | /* lle */ | |
d2523010 JL |
2442 | void OP_D3 (insn, extension) |
2443 | unsigned long insn, extension; | |
05ccbdfd | 2444 | { |
65b784d8 JL |
2445 | /* The dispatching code will add 1 after we return, so |
2446 | we subtract one here to make things right. */ | |
2447 | if ((PSW & PSW_Z) | |
2448 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) | |
2449 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2450 | } |
2451 | ||
2452 | /* llt */ | |
d2523010 JL |
2453 | void OP_D0 (insn, extension) |
2454 | unsigned long insn, extension; | |
05ccbdfd | 2455 | { |
65b784d8 JL |
2456 | /* The dispatching code will add 1 after we return, so |
2457 | we subtract one here to make things right. */ | |
2458 | if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)) | |
2459 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2460 | } |
2461 | ||
2462 | /* lhi */ | |
d2523010 JL |
2463 | void OP_D5 (insn, extension) |
2464 | unsigned long insn, extension; | |
05ccbdfd | 2465 | { |
65b784d8 JL |
2466 | /* The dispatching code will add 1 after we return, so |
2467 | we subtract one here to make things right. */ | |
2468 | if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)) | |
2469 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2470 | } |
2471 | ||
2472 | /* lcc */ | |
d2523010 JL |
2473 | void OP_D6 (insn, extension) |
2474 | unsigned long insn, extension; | |
05ccbdfd | 2475 | { |
65b784d8 JL |
2476 | /* The dispatching code will add 1 after we return, so |
2477 | we subtract one here to make things right. */ | |
2478 | if (!(PSW & PSW_C)) | |
2479 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2480 | } |
2481 | ||
2482 | /* lls */ | |
d2523010 JL |
2483 | void OP_D7 (insn, extension) |
2484 | unsigned long insn, extension; | |
05ccbdfd | 2485 | { |
65b784d8 JL |
2486 | /* The dispatching code will add 1 after we return, so |
2487 | we subtract one here to make things right. */ | |
2488 | if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0) | |
2489 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2490 | } |
2491 | ||
2492 | /* lcs */ | |
d2523010 JL |
2493 | void OP_D4 (insn, extension) |
2494 | unsigned long insn, extension; | |
05ccbdfd | 2495 | { |
65b784d8 JL |
2496 | /* The dispatching code will add 1 after we return, so |
2497 | we subtract one here to make things right. */ | |
2498 | if (PSW & PSW_C) | |
2499 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2500 | } |
2501 | ||
2502 | /* lra */ | |
d2523010 JL |
2503 | void OP_DA (insn, extension) |
2504 | unsigned long insn, extension; | |
05ccbdfd | 2505 | { |
65b784d8 | 2506 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; |
05ccbdfd JL |
2507 | } |
2508 | ||
2509 | /* setlb */ | |
d2523010 JL |
2510 | void OP_DB (insn, extension) |
2511 | unsigned long insn, extension; | |
05ccbdfd | 2512 | { |
65b784d8 JL |
2513 | State.regs[REG_LIR] = load_mem_big (State.regs[REG_PC] + 1, 4); |
2514 | State.regs[REG_LAR] = State.regs[REG_PC] + 5; | |
05ccbdfd JL |
2515 | } |
2516 | ||
707641f6 | 2517 | /* jmp (an) */ |
d2523010 JL |
2518 | void OP_F0F4 (insn, extension) |
2519 | unsigned long insn, extension; | |
05ccbdfd | 2520 | { |
b774c0e4 | 2521 | State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2; |
05ccbdfd JL |
2522 | } |
2523 | ||
707641f6 | 2524 | /* jmp label:16 */ |
d2523010 JL |
2525 | void OP_CC0000 (insn, extension) |
2526 | unsigned long insn, extension; | |
05ccbdfd | 2527 | { |
b774c0e4 | 2528 | State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 3; |
05ccbdfd JL |
2529 | } |
2530 | ||
707641f6 | 2531 | /* jmp label:32 */ |
d2523010 JL |
2532 | void OP_DC000000 (insn, extension) |
2533 | unsigned long insn, extension; | |
05ccbdfd | 2534 | { |
b774c0e4 | 2535 | State.regs[REG_PC] += (((insn & 0xffffff) << 8) + extension) - 5; |
05ccbdfd JL |
2536 | } |
2537 | ||
707641f6 | 2538 | /* call label:16,reg_list,imm8 */ |
d2523010 JL |
2539 | void OP_CD000000 (insn, extension) |
2540 | unsigned long insn, extension; | |
05ccbdfd | 2541 | { |
707641f6 JL |
2542 | unsigned int next_pc, sp, adjust; |
2543 | unsigned long mask; | |
2544 | ||
2545 | sp = State.regs[REG_SP]; | |
b774c0e4 | 2546 | next_pc = State.regs[REG_PC] + 2; |
707641f6 | 2547 | State.mem[sp] = next_pc & 0xff; |
3bb3fe44 JL |
2548 | State.mem[sp+1] = (next_pc & 0xff00) >> 8; |
2549 | State.mem[sp+2] = (next_pc & 0xff0000) >> 16; | |
2550 | State.mem[sp+3] = (next_pc & 0xff000000) >> 24; | |
707641f6 JL |
2551 | |
2552 | mask = insn & 0xff; | |
2553 | ||
2554 | adjust = 0; | |
2555 | if (mask & 0x80) | |
2556 | { | |
2557 | adjust -= 4; | |
2558 | State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4); | |
2559 | } | |
2560 | ||
2561 | if (mask & 0x40) | |
2562 | { | |
2563 | adjust -= 4; | |
2564 | State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4); | |
2565 | } | |
2566 | ||
2567 | if (mask & 0x20) | |
2568 | { | |
2569 | adjust -= 4; | |
2570 | State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4); | |
2571 | } | |
2572 | ||
2573 | if (mask & 0x10) | |
2574 | { | |
2575 | adjust -= 4; | |
2576 | State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4); | |
2577 | } | |
2578 | ||
2579 | if (mask & 0x8) | |
2580 | { | |
2581 | adjust -= 4; | |
2582 | State.regs[REG_D0] = load_mem (sp + adjust, 4); | |
2583 | adjust -= 4; | |
2584 | State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4); | |
2585 | adjust -= 4; | |
2586 | State.regs[REG_A0] = load_mem (sp + adjust, 4); | |
2587 | adjust -= 4; | |
2588 | State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4); | |
2589 | adjust -= 4; | |
2590 | State.regs[REG_MDR] = load_mem (sp + adjust, 4); | |
2591 | adjust -= 4; | |
2592 | State.regs[REG_LIR] = load_mem (sp + adjust, 4); | |
2593 | adjust -= 4; | |
2594 | State.regs[REG_LAR] = load_mem (sp + adjust, 4); | |
2595 | adjust -= 4; | |
2596 | } | |
2597 | ||
2598 | /* And make sure to update the stack pointer. */ | |
2599 | State.regs[REG_SP] -= extension; | |
2600 | State.regs[REG_MDR] = next_pc; | |
b774c0e4 | 2601 | State.regs[REG_PC] += SEXT16 ((insn & 0xffff00) >> 8) - 5; |
05ccbdfd JL |
2602 | } |
2603 | ||
707641f6 | 2604 | /* call label:32,reg_list,imm8*/ |
d2523010 JL |
2605 | void OP_DD000000 (insn, extension) |
2606 | unsigned long insn, extension; | |
05ccbdfd | 2607 | { |
707641f6 JL |
2608 | unsigned int next_pc, sp, adjust; |
2609 | unsigned long mask; | |
2610 | ||
2611 | sp = State.regs[REG_SP]; | |
b774c0e4 | 2612 | next_pc = State.regs[REG_PC] + 2; |
707641f6 | 2613 | State.mem[sp] = next_pc & 0xff; |
3bb3fe44 JL |
2614 | State.mem[sp+1] = (next_pc & 0xff00) >> 8; |
2615 | State.mem[sp+2] = (next_pc & 0xff0000) >> 16; | |
2616 | State.mem[sp+3] = (next_pc & 0xff000000) >> 24; | |
707641f6 JL |
2617 | |
2618 | mask = (extension & 0xff00) >> 8; | |
2619 | ||
2620 | adjust = 0; | |
2621 | if (mask & 0x80) | |
2622 | { | |
2623 | adjust -= 4; | |
2624 | State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4); | |
2625 | } | |
2626 | ||
2627 | if (mask & 0x40) | |
2628 | { | |
2629 | adjust -= 4; | |
2630 | State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4); | |
2631 | } | |
2632 | ||
2633 | if (mask & 0x20) | |
2634 | { | |
2635 | adjust -= 4; | |
2636 | State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4); | |
2637 | } | |
2638 | ||
2639 | if (mask & 0x10) | |
2640 | { | |
2641 | adjust -= 4; | |
2642 | State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4); | |
2643 | } | |
2644 | ||
2645 | if (mask & 0x8) | |
2646 | { | |
2647 | adjust -= 4; | |
2648 | State.regs[REG_D0] = load_mem (sp + adjust, 4); | |
2649 | adjust -= 4; | |
2650 | State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4); | |
2651 | adjust -= 4; | |
2652 | State.regs[REG_A0] = load_mem (sp + adjust, 4); | |
2653 | adjust -= 4; | |
2654 | State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4); | |
2655 | adjust -= 4; | |
2656 | State.regs[REG_MDR] = load_mem (sp + adjust, 4); | |
2657 | adjust -= 4; | |
2658 | State.regs[REG_LIR] = load_mem (sp + adjust, 4); | |
2659 | adjust -= 4; | |
2660 | State.regs[REG_LAR] = load_mem (sp + adjust, 4); | |
2661 | adjust -= 4; | |
2662 | } | |
2663 | ||
2664 | /* And make sure to update the stack pointer. */ | |
2665 | State.regs[REG_SP] -= (extension & 0xff); | |
2666 | State.regs[REG_MDR] = next_pc; | |
b774c0e4 | 2667 | State.regs[REG_PC] += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7; |
05ccbdfd JL |
2668 | } |
2669 | ||
707641f6 | 2670 | /* calls (an) */ |
d2523010 JL |
2671 | void OP_F0F0 (insn, extension) |
2672 | unsigned long insn, extension; | |
05ccbdfd | 2673 | { |
92284aaa JL |
2674 | unsigned int next_pc, sp; |
2675 | ||
2676 | sp = State.regs[REG_SP]; | |
b774c0e4 | 2677 | next_pc = State.regs[REG_PC] + 2; |
92284aaa | 2678 | State.mem[sp] = next_pc & 0xff; |
3bb3fe44 JL |
2679 | State.mem[sp+1] = (next_pc & 0xff00) >> 8; |
2680 | State.mem[sp+2] = (next_pc & 0xff0000) >> 16; | |
2681 | State.mem[sp+3] = (next_pc & 0xff000000) >> 24; | |
92284aaa | 2682 | State.regs[REG_MDR] = next_pc; |
b774c0e4 | 2683 | State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2; |
05ccbdfd JL |
2684 | } |
2685 | ||
707641f6 | 2686 | /* calls label:16 */ |
d2523010 JL |
2687 | void OP_FAFF0000 (insn, extension) |
2688 | unsigned long insn, extension; | |
05ccbdfd | 2689 | { |
92284aaa JL |
2690 | unsigned int next_pc, sp; |
2691 | ||
2692 | sp = State.regs[REG_SP]; | |
b774c0e4 | 2693 | next_pc = State.regs[REG_PC] + 4; |
92284aaa | 2694 | State.mem[sp] = next_pc & 0xff; |
3bb3fe44 JL |
2695 | State.mem[sp+1] = (next_pc & 0xff00) >> 8; |
2696 | State.mem[sp+2] = (next_pc & 0xff0000) >> 16; | |
2697 | State.mem[sp+3] = (next_pc & 0xff000000) >> 24; | |
92284aaa | 2698 | State.regs[REG_MDR] = next_pc; |
b774c0e4 | 2699 | State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 4; |
05ccbdfd JL |
2700 | } |
2701 | ||
707641f6 | 2702 | /* calls label:32 */ |
d2523010 JL |
2703 | void OP_FCFF0000 (insn, extension) |
2704 | unsigned long insn, extension; | |
05ccbdfd | 2705 | { |
92284aaa JL |
2706 | unsigned int next_pc, sp; |
2707 | ||
2708 | sp = State.regs[REG_SP]; | |
b774c0e4 | 2709 | next_pc = State.regs[REG_PC] + 6; |
92284aaa | 2710 | State.mem[sp] = next_pc & 0xff; |
3bb3fe44 JL |
2711 | State.mem[sp+1] = (next_pc & 0xff00) >> 8; |
2712 | State.mem[sp+2] = (next_pc & 0xff0000) >> 16; | |
2713 | State.mem[sp+3] = (next_pc & 0xff000000) >> 24; | |
92284aaa | 2714 | State.regs[REG_MDR] = next_pc; |
b774c0e4 | 2715 | State.regs[REG_PC] += (((insn & 0xffff) << 16) + extension) - 6; |
05ccbdfd JL |
2716 | } |
2717 | ||
de0dce7c | 2718 | /* ret reg_list, imm8 */ |
d2523010 JL |
2719 | void OP_DF0000 (insn, extension) |
2720 | unsigned long insn, extension; | |
05ccbdfd | 2721 | { |
707641f6 JL |
2722 | unsigned int sp; |
2723 | unsigned long mask; | |
2724 | ||
2725 | State.regs[REG_SP] += insn & 0xff; | |
707641f6 JL |
2726 | sp = State.regs[REG_SP]; |
2727 | ||
2728 | mask = (insn & 0xff00) >> 8; | |
2729 | ||
2730 | if (mask & 0x8) | |
2731 | { | |
2732 | sp += 4; | |
2733 | State.regs[REG_LAR] = load_mem (sp, 4); | |
2734 | sp += 4; | |
2735 | State.regs[REG_LIR] = load_mem (sp, 4); | |
2736 | sp += 4; | |
2737 | State.regs[REG_MDR] = load_mem (sp, 4); | |
2738 | sp += 4; | |
2739 | State.regs[REG_A0 + 1] = load_mem (sp, 4); | |
2740 | sp += 4; | |
2741 | State.regs[REG_A0] = load_mem (sp, 4); | |
2742 | sp += 4; | |
2743 | State.regs[REG_D0 + 1] = load_mem (sp, 4); | |
2744 | sp += 4; | |
2745 | State.regs[REG_D0] = load_mem (sp, 4); | |
2746 | sp += 4; | |
2747 | } | |
2748 | ||
2749 | if (mask & 0x10) | |
2750 | { | |
2751 | State.regs[REG_A0 + 3] = load_mem (sp, 4); | |
2752 | sp += 4; | |
2753 | } | |
2754 | ||
2755 | if (mask & 0x20) | |
2756 | { | |
2757 | State.regs[REG_A0 + 2] = load_mem (sp, 4); | |
2758 | sp += 4; | |
2759 | } | |
2760 | ||
2761 | if (mask & 0x40) | |
2762 | { | |
2763 | State.regs[REG_D0 + 3] = load_mem (sp, 4); | |
2764 | sp += 4; | |
2765 | } | |
2766 | ||
2767 | if (mask & 0x80) | |
2768 | { | |
2769 | State.regs[REG_D0 + 2] = load_mem (sp, 4); | |
2770 | sp += 4; | |
2771 | } | |
16d2e2b6 JL |
2772 | |
2773 | /* And make sure to update the stack pointer. */ | |
2774 | State.regs[REG_SP] = sp; | |
2775 | ||
2776 | /* Restore the PC value. */ | |
b774c0e4 | 2777 | State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8) |
16d2e2b6 | 2778 | | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24)); |
b774c0e4 | 2779 | State.regs[REG_PC] -= 3; |
05ccbdfd JL |
2780 | } |
2781 | ||
707641f6 | 2782 | /* retf reg_list,imm8 */ |
d2523010 JL |
2783 | void OP_DE0000 (insn, extension) |
2784 | unsigned long insn, extension; | |
05ccbdfd | 2785 | { |
707641f6 JL |
2786 | unsigned int sp; |
2787 | unsigned long mask; | |
2788 | ||
7c52bf32 JL |
2789 | sp = State.regs[REG_SP] + (insn & 0xff); |
2790 | State.regs[REG_SP] = sp; | |
b774c0e4 | 2791 | State.regs[REG_PC] = State.regs[REG_MDR] - 3; |
707641f6 JL |
2792 | |
2793 | sp = State.regs[REG_SP]; | |
2794 | ||
2795 | mask = (insn & 0xff00) >> 8; | |
2796 | ||
2797 | if (mask & 0x8) | |
2798 | { | |
2799 | sp += 4; | |
2800 | State.regs[REG_LAR] = load_mem (sp, 4); | |
2801 | sp += 4; | |
2802 | State.regs[REG_LIR] = load_mem (sp, 4); | |
2803 | sp += 4; | |
2804 | State.regs[REG_MDR] = load_mem (sp, 4); | |
2805 | sp += 4; | |
2806 | State.regs[REG_A0 + 1] = load_mem (sp, 4); | |
2807 | sp += 4; | |
2808 | State.regs[REG_A0] = load_mem (sp, 4); | |
2809 | sp += 4; | |
2810 | State.regs[REG_D0 + 1] = load_mem (sp, 4); | |
2811 | sp += 4; | |
2812 | State.regs[REG_D0] = load_mem (sp, 4); | |
2813 | sp += 4; | |
2814 | } | |
2815 | ||
2816 | if (mask & 0x10) | |
2817 | { | |
2818 | State.regs[REG_A0 + 3] = load_mem (sp, 4); | |
2819 | sp += 4; | |
2820 | } | |
2821 | ||
2822 | if (mask & 0x20) | |
2823 | { | |
2824 | State.regs[REG_A0 + 2] = load_mem (sp, 4); | |
2825 | sp += 4; | |
2826 | } | |
2827 | ||
2828 | if (mask & 0x40) | |
2829 | { | |
2830 | State.regs[REG_D0 + 3] = load_mem (sp, 4); | |
2831 | sp += 4; | |
2832 | } | |
2833 | ||
2834 | if (mask & 0x80) | |
2835 | { | |
2836 | State.regs[REG_D0 + 2] = load_mem (sp, 4); | |
2837 | sp += 4; | |
2838 | } | |
16d2e2b6 JL |
2839 | |
2840 | /* And make sure to update the stack pointer. */ | |
2841 | State.regs[REG_SP] = sp; | |
05ccbdfd JL |
2842 | } |
2843 | ||
2844 | /* rets */ | |
d2523010 JL |
2845 | void OP_F0FC (insn, extension) |
2846 | unsigned long insn, extension; | |
05ccbdfd | 2847 | { |
92284aaa JL |
2848 | unsigned int sp; |
2849 | ||
2850 | sp = State.regs[REG_SP]; | |
b774c0e4 | 2851 | State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8) |
92284aaa | 2852 | | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24)); |
b774c0e4 | 2853 | State.regs[REG_PC] -= 2; |
05ccbdfd JL |
2854 | } |
2855 | ||
2856 | /* rti */ | |
d2523010 JL |
2857 | void OP_F0FD (insn, extension) |
2858 | unsigned long insn, extension; | |
05ccbdfd | 2859 | { |
65b784d8 JL |
2860 | unsigned int sp, next_pc; |
2861 | ||
2862 | PSW = State.mem[sp] | (State.mem[sp + 1] << 8); | |
2863 | State.regs[REG_PC] = (State.mem[sp+4] | (State.mem[sp+5] << 8) | |
2864 | | (State.mem[sp+6] << 16) | (State.mem[sp+7] << 24)); | |
2865 | State.regs[REG_SP] += 8; | |
05ccbdfd JL |
2866 | } |
2867 | ||
2868 | /* trap */ | |
d2523010 JL |
2869 | void OP_F0FE (insn, extension) |
2870 | unsigned long insn, extension; | |
0915c843 | 2871 | { |
65b784d8 JL |
2872 | unsigned int sp, next_pc; |
2873 | ||
2874 | sp = State.regs[REG_SP]; | |
2875 | next_pc = State.regs[REG_PC] + 2; | |
2876 | State.mem[sp] = next_pc & 0xff; | |
2877 | State.mem[sp+1] = (next_pc & 0xff00) >> 8; | |
2878 | State.mem[sp+2] = (next_pc & 0xff0000) >> 16; | |
2879 | State.mem[sp+3] = (next_pc & 0xff000000) >> 24; | |
2880 | State.regs[REG_PC] = 0x40000010 - 2; | |
0915c843 JL |
2881 | } |
2882 | ||
2883 | /* syscall */ | |
65b784d8 | 2884 | void OP_F020 (insn, extension) |
0915c843 | 2885 | unsigned long insn, extension; |
05ccbdfd | 2886 | { |
3bb3fe44 JL |
2887 | /* We use this for simulated system calls; we may need to change |
2888 | it to a reserved instruction if we conflict with uses at | |
2889 | Matsushita. */ | |
2890 | int save_errno = errno; | |
2891 | errno = 0; | |
2892 | ||
2893 | /* Registers passed to trap 0 */ | |
2894 | ||
2895 | /* Function number. */ | |
81f13ed1 | 2896 | #define FUNC (State.regs[0]) |
3bb3fe44 JL |
2897 | |
2898 | /* Parameters. */ | |
81f13ed1 | 2899 | #define PARM1 (State.regs[1]) |
3bb3fe44 JL |
2900 | #define PARM2 (load_mem (State.regs[REG_SP] + 12, 4)) |
2901 | #define PARM3 (load_mem (State.regs[REG_SP] + 16, 4)) | |
2902 | ||
2903 | /* Registers set by trap 0 */ | |
2904 | ||
2905 | #define RETVAL State.regs[0] /* return value */ | |
2906 | #define RETERR State.regs[1] /* return error code */ | |
2907 | ||
2908 | /* Turn a pointer in a register into a pointer into real memory. */ | |
2909 | ||
2910 | #define MEMPTR(x) (State.mem + x) | |
2911 | ||
2912 | switch (FUNC) | |
2913 | { | |
2914 | #if !defined(__GO32__) && !defined(_WIN32) | |
2915 | case SYS_fork: | |
2916 | RETVAL = fork (); | |
2917 | break; | |
2918 | case SYS_execve: | |
2919 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), | |
2920 | (char **)MEMPTR (PARM3)); | |
2921 | break; | |
87e43259 | 2922 | #ifdef SYS_execv |
3bb3fe44 JL |
2923 | case SYS_execv: |
2924 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL); | |
2925 | break; | |
87e43259 | 2926 | #endif |
3bb3fe44 JL |
2927 | #endif |
2928 | ||
2929 | case SYS_read: | |
2930 | RETVAL = mn10300_callback->read (mn10300_callback, PARM1, | |
2931 | MEMPTR (PARM2), PARM3); | |
2932 | break; | |
2933 | case SYS_write: | |
2934 | if (PARM1 == 1) | |
2935 | RETVAL = (int)mn10300_callback->write_stdout (mn10300_callback, | |
2936 | MEMPTR (PARM2), PARM3); | |
2937 | else | |
2938 | RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1, | |
2939 | MEMPTR (PARM2), PARM3); | |
2940 | break; | |
2941 | case SYS_lseek: | |
2942 | RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3); | |
2943 | break; | |
2944 | case SYS_close: | |
2945 | RETVAL = mn10300_callback->close (mn10300_callback, PARM1); | |
2946 | break; | |
2947 | case SYS_open: | |
2948 | RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2); | |
2949 | break; | |
2950 | case SYS_exit: | |
2951 | /* EXIT - caller can look in PARM1 to work out the | |
2952 | reason */ | |
2953 | if (PARM1 == 0xdead || PARM1 == 0x1) | |
2954 | State.exception = SIGABRT; | |
2955 | else | |
2956 | State.exception = SIGQUIT; | |
2957 | break; | |
2958 | ||
2959 | case SYS_stat: /* added at hmsi */ | |
2960 | /* stat system call */ | |
2961 | { | |
2962 | struct stat host_stat; | |
2963 | reg_t buf; | |
2964 | ||
2965 | RETVAL = stat (MEMPTR (PARM1), &host_stat); | |
2966 | ||
2967 | buf = PARM2; | |
2968 | ||
2969 | /* Just wild-assed guesses. */ | |
2970 | store_mem (buf, 2, host_stat.st_dev); | |
2971 | store_mem (buf + 2, 2, host_stat.st_ino); | |
2972 | store_mem (buf + 4, 4, host_stat.st_mode); | |
2973 | store_mem (buf + 8, 2, host_stat.st_nlink); | |
2974 | store_mem (buf + 10, 2, host_stat.st_uid); | |
2975 | store_mem (buf + 12, 2, host_stat.st_gid); | |
2976 | store_mem (buf + 14, 2, host_stat.st_rdev); | |
2977 | store_mem (buf + 16, 4, host_stat.st_size); | |
2978 | store_mem (buf + 20, 4, host_stat.st_atime); | |
2979 | store_mem (buf + 28, 4, host_stat.st_mtime); | |
2980 | store_mem (buf + 36, 4, host_stat.st_ctime); | |
2981 | } | |
2982 | break; | |
2983 | ||
2984 | case SYS_chown: | |
2985 | RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3); | |
2986 | break; | |
2987 | case SYS_chmod: | |
2988 | RETVAL = chmod (MEMPTR (PARM1), PARM2); | |
2989 | break; | |
87e43259 | 2990 | #ifdef SYS_time |
3bb3fe44 | 2991 | case SYS_time: |
87e43259 | 2992 | RETVAL = time ((void*) MEMPTR (PARM1)); |
3bb3fe44 | 2993 | break; |
87e43259 AC |
2994 | #endif |
2995 | #ifdef SYS_times | |
3bb3fe44 JL |
2996 | case SYS_times: |
2997 | { | |
2998 | struct tms tms; | |
2999 | RETVAL = times (&tms); | |
3000 | store_mem (PARM1, 4, tms.tms_utime); | |
3001 | store_mem (PARM1 + 4, 4, tms.tms_stime); | |
3002 | store_mem (PARM1 + 8, 4, tms.tms_cutime); | |
3003 | store_mem (PARM1 + 12, 4, tms.tms_cstime); | |
3004 | break; | |
3005 | } | |
87e43259 | 3006 | #endif |
3bb3fe44 JL |
3007 | case SYS_gettimeofday: |
3008 | { | |
3009 | struct timeval t; | |
3010 | struct timezone tz; | |
3011 | RETVAL = gettimeofday (&t, &tz); | |
3012 | store_mem (PARM1, 4, t.tv_sec); | |
3013 | store_mem (PARM1 + 4, 4, t.tv_usec); | |
3014 | store_mem (PARM2, 4, tz.tz_minuteswest); | |
3015 | store_mem (PARM2 + 4, 4, tz.tz_dsttime); | |
3016 | break; | |
3017 | } | |
87e43259 | 3018 | #ifdef SYS_utime |
3bb3fe44 JL |
3019 | case SYS_utime: |
3020 | /* Cast the second argument to void *, to avoid type mismatch | |
3021 | if a prototype is present. */ | |
3022 | RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)); | |
3023 | break; | |
87e43259 | 3024 | #endif |
3bb3fe44 JL |
3025 | default: |
3026 | abort (); | |
3027 | } | |
3028 | RETERR = errno; | |
3029 | errno = save_errno; | |
05ccbdfd JL |
3030 | } |
3031 | ||
3032 | /* rtm */ | |
d2523010 JL |
3033 | void OP_F0FF (insn, extension) |
3034 | unsigned long insn, extension; | |
05ccbdfd | 3035 | { |
f5f13c1d | 3036 | abort (); |
05ccbdfd JL |
3037 | } |
3038 | ||
3039 | /* nop */ | |
d2523010 JL |
3040 | void OP_CB (insn, extension) |
3041 | unsigned long insn, extension; | |
05ccbdfd JL |
3042 | { |
3043 | } | |
3044 | ||
26e9f63c | 3045 | /* putx dm,dm */ |
d2523010 JL |
3046 | void OP_F500 (insn, extension) |
3047 | unsigned long insn, extension; | |
05ccbdfd | 3048 | { |
26e9f63c | 3049 | State.regs[REG_MDRQ] = State.regs[REG_D0 + REG0 (insn)]; |
05ccbdfd JL |
3050 | } |
3051 | ||
26e9f63c | 3052 | /* getx dm,dm */ |
d2523010 JL |
3053 | void OP_F6F0 (insn, extension) |
3054 | unsigned long insn, extension; | |
05ccbdfd | 3055 | { |
26e9f63c JL |
3056 | int z, n; |
3057 | z = (State.regs[REG_MDRQ] == 0); | |
3058 | n = ((State.regs[REG_MDRQ] & 0x80000000) != 0); | |
3059 | State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDRQ]; | |
3060 | ||
3061 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3062 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
05ccbdfd JL |
3063 | } |
3064 | ||
26e9f63c | 3065 | /* mulq dm,dn */ |
d2523010 JL |
3066 | void OP_F600 (insn, extension) |
3067 | unsigned long insn, extension; | |
05ccbdfd | 3068 | { |
26e9f63c JL |
3069 | unsigned long long temp; |
3070 | int n, z; | |
3071 | ||
3072 | temp = ((signed long)State.regs[REG_D0 + REG0 (insn)] | |
3073 | * (signed long)State.regs[REG_D0 + REG1 (insn)]); | |
3074 | State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; | |
3075 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3076 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
3077 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
3078 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3079 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3080 | } |
3081 | ||
26e9f63c | 3082 | /* mulq imm8,dn */ |
d2523010 JL |
3083 | void OP_F90000 (insn, extension) |
3084 | unsigned long insn, extension; | |
05ccbdfd | 3085 | { |
26e9f63c JL |
3086 | unsigned long long temp; |
3087 | int n, z; | |
3088 | ||
3089 | temp = ((signed long)State.regs[REG_D0 + REG0_8 (insn)] | |
3090 | * (signed long)SEXT8 (insn & 0xff)); | |
3091 | State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff; | |
3092 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3093 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); | |
3094 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
3095 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3096 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3097 | } |
3098 | ||
26e9f63c | 3099 | /* mulq imm16,dn */ |
d2523010 JL |
3100 | void OP_FB000000 (insn, extension) |
3101 | unsigned long insn, extension; | |
05ccbdfd | 3102 | { |
26e9f63c JL |
3103 | unsigned long long temp; |
3104 | int n, z; | |
3105 | ||
3106 | temp = ((signed long)State.regs[REG_D0 + REG0_16 (insn)] | |
3107 | * (signed long)SEXT16 (insn & 0xffff)); | |
3108 | State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; | |
3109 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3110 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
3111 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
3112 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3113 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3114 | } |
3115 | ||
26e9f63c | 3116 | /* mulq imm32,dn */ |
d2523010 JL |
3117 | void OP_FD000000 (insn, extension) |
3118 | unsigned long insn, extension; | |
05ccbdfd | 3119 | { |
26e9f63c JL |
3120 | unsigned long long temp; |
3121 | int n, z; | |
3122 | ||
3123 | temp = ((signed long)State.regs[REG_D0 + REG0_16 (insn)] | |
3124 | * (signed long)(((insn & 0xffff) << 16) + extension)); | |
3125 | State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; | |
3126 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3127 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
3128 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
3129 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3130 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3131 | } |
3132 | ||
26e9f63c | 3133 | /* mulqu dm,dn */ |
d2523010 JL |
3134 | void OP_F610 (insn, extension) |
3135 | unsigned long insn, extension; | |
05ccbdfd | 3136 | { |
26e9f63c JL |
3137 | unsigned long long temp; |
3138 | int n, z; | |
3139 | ||
3140 | temp = (State.regs[REG_D0 + REG0 (insn)] * State.regs[REG_D0 + REG1 (insn)]); | |
3141 | State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; | |
3142 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3143 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
3144 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
3145 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3146 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3147 | } |
3148 | ||
26e9f63c | 3149 | /* mulqu imm8,dn */ |
d2523010 JL |
3150 | void OP_F91400 (insn, extension) |
3151 | unsigned long insn, extension; | |
05ccbdfd | 3152 | { |
26e9f63c JL |
3153 | unsigned long long temp; |
3154 | int n, z; | |
3155 | ||
3156 | temp = (State.regs[REG_D0 + REG0_8 (insn)] * SEXT8 (insn & 0xff)); | |
3157 | State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff; | |
3158 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3159 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); | |
3160 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
3161 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3162 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3163 | } |
3164 | ||
26e9f63c | 3165 | /* mulqu imm16,dn */ |
d2523010 JL |
3166 | void OP_FB140000 (insn, extension) |
3167 | unsigned long insn, extension; | |
05ccbdfd | 3168 | { |
26e9f63c JL |
3169 | unsigned long long temp; |
3170 | int n, z; | |
3171 | ||
3172 | temp = (State.regs[REG_D0 + REG0_16 (insn)] * SEXT16 (insn & 0xffff)); | |
3173 | State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; | |
3174 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3175 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
3176 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
3177 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3178 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3179 | } |
3180 | ||
26e9f63c | 3181 | /* mulqu imm32,dn */ |
d2523010 JL |
3182 | void OP_FD140000 (insn, extension) |
3183 | unsigned long insn, extension; | |
05ccbdfd | 3184 | { |
26e9f63c JL |
3185 | unsigned long long temp; |
3186 | int n, z; | |
3187 | ||
3188 | temp = (State.regs[REG_D0 + REG0_16 (insn)] | |
3189 | * (((insn & 0xffff) << 16) + extension)); | |
3190 | State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; | |
3191 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3192 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
3193 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
3194 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3195 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3196 | } |
3197 | ||
26e9f63c | 3198 | /* sat16 dm,dn */ |
d2523010 JL |
3199 | void OP_F640 (insn, extension) |
3200 | unsigned long insn, extension; | |
05ccbdfd | 3201 | { |
26e9f63c JL |
3202 | int temp; |
3203 | ||
3204 | temp = State.regs[REG_D0 + REG1 (insn)]; | |
3205 | temp = (temp > 0x7fff ? 0x7fff : temp); | |
3206 | temp = (temp < -0x8000 ? -0x8000 : temp); | |
3207 | State.regs[REG_D0 + REG0 (insn)] = temp; | |
05ccbdfd JL |
3208 | } |
3209 | ||
26e9f63c | 3210 | /* sat24 dm,dn */ |
d2523010 JL |
3211 | void OP_F650 (insn, extension) |
3212 | unsigned long insn, extension; | |
05ccbdfd | 3213 | { |
26e9f63c JL |
3214 | int temp; |
3215 | ||
3216 | temp = State.regs[REG_D0 + REG1 (insn)]; | |
3217 | temp = (temp > 0x7fffff ? 0x7fffff : temp); | |
3218 | temp = (temp < -0x800000 ? -0x800000 : temp); | |
3219 | State.regs[REG_D0 + REG0 (insn)] = temp; | |
05ccbdfd JL |
3220 | } |
3221 | ||
26e9f63c | 3222 | /* bsch dm,dn */ |
d2523010 JL |
3223 | void OP_F670 (insn, extension) |
3224 | unsigned long insn, extension; | |
05ccbdfd | 3225 | { |
26e9f63c JL |
3226 | int temp, c; |
3227 | ||
3228 | temp = State.regs[REG_D0 + REG1 (insn)]; | |
3229 | temp <<= (State.regs[REG_D0 + REG0 (insn)] & 0x1f); | |
3230 | c = (temp != 0 ? 1 : 0); | |
3231 | PSW &= ~(PSW_C); | |
3232 | PSW |= (c ? PSW_C : 0); | |
05ccbdfd | 3233 | } |
093e9a32 JL |
3234 | |
3235 | /* breakpoint */ | |
3236 | void | |
3237 | OP_FF (insn, extension) | |
3238 | unsigned long insn, extension; | |
3239 | { | |
3240 | State.exception = SIGTRAP; | |
3241 | PC -= 1; | |
3242 | } | |
3243 |