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1 | # Altivec instruction set, for PSIM, the PowerPC simulator. |
2 | ||
3 | # Copyright 2003 Free Software Foundation, Inc. | |
4 | ||
5 | # Contributed by Red Hat Inc; developed under contract from Motorola. | |
6 | # Written by matthew green <mrg@redhat.com>. | |
7 | ||
8 | # This file is part of GDB. | |
9 | ||
10 | # This program is free software; you can redistribute it and/or modify | |
11 | # it under the terms of the GNU General Public License as published by | |
12 | # the Free Software Foundation; either version 2 of the License, or | |
13 | # (at your option) any later version. | |
14 | ||
15 | # This program is distributed in the hope that it will be useful, | |
16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | # GNU General Public License for more details. | |
19 | ||
20 | # You should have received a copy of the GNU General Public License | |
21 | # along with this program; if not, write to the Free Software | |
22 | # Foundation, Inc., 59 Temple Place - Suite 330, | |
23 | # Boston, MA 02111-1307, USA. */ | |
24 | ||
25 | ||
26 | # | |
27 | # Motorola AltiVec instructions. | |
28 | # | |
29 | ||
30 | :cache:av:::VS:VS: | |
31 | :cache:av::vreg *:vS:VS:(cpu_registers(processor)->altivec.vr + VS) | |
32 | :cache:av::unsigned32:VS_BITMASK:VS:(1 << VS) | |
33 | :cache:av:::VA:VA: | |
34 | :cache:av::vreg *:vA:VA:(cpu_registers(processor)->altivec.vr + VA) | |
35 | :cache:av::unsigned32:VA_BITMASK:VA:(1 << VA) | |
36 | :cache:av:::VB:VB: | |
37 | :cache:av::vreg *:vB:VB:(cpu_registers(processor)->altivec.vr + VB) | |
38 | :cache:av::unsigned32:VB_BITMASK:VB:(1 << VB) | |
39 | :cache:av:::VC:VC: | |
40 | :cache:av::vreg *:vC:VC:(cpu_registers(processor)->altivec.vr + VC) | |
41 | :cache:av::unsigned32:VC_BITMASK:VC:(1 << VC) | |
42 | ||
43 | # Flags for model.h | |
44 | ::model-macro::: | |
45 | #define PPC_INSN_INT_VR(OUT_MASK, IN_MASK, OUT_VMASK, IN_VMASK) \ | |
46 | do { \ | |
47 | if (CURRENT_MODEL_ISSUE > 0) \ | |
48 | ppc_insn_int_vr(MY_INDEX, cpu_model(processor), OUT_MASK, IN_MASK, OUT_VMASK, IN_VMASK); \ | |
49 | } while (0) | |
50 | ||
51 | #define PPC_INSN_VR(OUT_VMASK, IN_VMASK) \ | |
52 | do { \ | |
53 | if (CURRENT_MODEL_ISSUE > 0) \ | |
54 | ppc_insn_vr(MY_INDEX, cpu_model(processor), OUT_VMASK, IN_VMASK); \ | |
55 | } while (0) | |
56 | ||
57 | #define PPC_INSN_VR_CR(OUT_VMASK, IN_VMASK, CR_MASK) \ | |
58 | do { \ | |
59 | if (CURRENT_MODEL_ISSUE > 0) \ | |
60 | ppc_insn_vr_cr(MY_INDEX, cpu_model(processor), OUT_VMASK, IN_VMASK, CR_MASK); \ | |
61 | } while (0) | |
62 | ||
63 | #define PPC_INSN_VR_VSCR(OUT_VMASK, IN_VMASK) \ | |
64 | do { \ | |
65 | if (CURRENT_MODEL_ISSUE > 0) \ | |
66 | ppc_insn_vr_vscr(MY_INDEX, cpu_model(processor), OUT_VMASK, IN_VMASK); \ | |
67 | } while (0) | |
68 | ||
69 | #define PPC_INSN_FROM_VSCR(VR_MASK) \ | |
70 | do { \ | |
71 | if (CURRENT_MODEL_ISSUE > 0) \ | |
72 | ppc_insn_from_vscr(MY_INDEX, cpu_model(processor), VR_MASK); \ | |
73 | } while (0) | |
74 | ||
75 | #define PPC_INSN_TO_VSCR(VR_MASK) \ | |
76 | do { \ | |
77 | if (CURRENT_MODEL_ISSUE > 0) \ | |
78 | ppc_insn_to_vscr(MY_INDEX, cpu_model(processor), VR_MASK); \ | |
79 | } while (0) | |
80 | ||
81 | # Trace waiting for AltiVec registers to become available | |
82 | void::model-static::model_trace_altivec_busy_p:model_data *model_ptr, unsigned32 vr_busy | |
83 | int i; | |
84 | if (vr_busy) { | |
85 | vr_busy &= model_ptr->vr_busy; | |
86 | for(i = 0; i < 32; i++) { | |
87 | if (((1 << i) & vr_busy) != 0) { | |
88 | TRACE(trace_model, ("Waiting for register v%d.\n", i)); | |
89 | } | |
90 | } | |
91 | } | |
92 | if (model_ptr->vscr_busy) | |
93 | TRACE(trace_model, ("Waiting for VSCR\n")); | |
94 | ||
95 | # Trace making AltiVec registers busy | |
96 | void::model-static::model_trace_altivec_make_busy:model_data *model_ptr, unsigned32 vr_mask, unsigned32 cr_mask | |
97 | int i; | |
98 | if (vr_mask) { | |
99 | for(i = 0; i < 32; i++) { | |
100 | if (((1 << i) & vr_mask) != 0) { | |
101 | TRACE(trace_model, ("Register v%d is now busy.\n", i)); | |
102 | } | |
103 | } | |
104 | } | |
105 | if (cr_mask) { | |
106 | for(i = 0; i < 8; i++) { | |
107 | if (((1 << i) & cr_mask) != 0) { | |
108 | TRACE(trace_model, ("Register cr%d is now busy.\n", i)); | |
109 | } | |
110 | } | |
111 | } | |
112 | ||
113 | # Schedule an AltiVec instruction that takes integer input registers and produces output registers | |
114 | void::model-function::ppc_insn_int_vr:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask, const unsigned32 out_vmask, const unsigned32 in_vmask | |
115 | const unsigned32 int_mask = out_mask | in_mask; | |
116 | const unsigned32 vr_mask = out_vmask | in_vmask; | |
117 | model_busy *busy_ptr; | |
118 | ||
119 | if ((model_ptr->int_busy & int_mask) != 0 || (model_ptr->vr_busy & vr_mask)) { | |
120 | model_new_cycle(model_ptr); /* don't count first dependency as a stall */ | |
121 | ||
122 | while ((model_ptr->int_busy & int_mask) != 0 || (model_ptr->vr_busy & vr_mask)) { | |
123 | if (WITH_TRACE && ppc_trace[trace_model]) { | |
124 | model_trace_busy_p(model_ptr, int_mask, 0, 0, PPC_NO_SPR); | |
125 | model_trace_altivec_busy_p(model_ptr, vr_mask); | |
126 | } | |
127 | ||
128 | model_ptr->nr_stalls_data++; | |
129 | model_new_cycle(model_ptr); | |
130 | } | |
131 | } | |
132 | ||
133 | busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); | |
134 | model_ptr->int_busy |= out_mask; | |
135 | busy_ptr->int_busy |= out_mask; | |
136 | model_ptr->vr_busy |= out_vmask; | |
137 | busy_ptr->vr_busy |= out_vmask; | |
138 | ||
139 | if (out_mask) | |
140 | busy_ptr->nr_writebacks = (PPC_ONE_BIT_SET_P(out_vmask)) ? 1 : 2; | |
141 | ||
142 | if (out_vmask) | |
143 | busy_ptr->nr_writebacks += (PPC_ONE_BIT_SET_P(out_vmask)) ? 1 : 2; | |
144 | ||
145 | if (WITH_TRACE && ppc_trace[trace_model]) { | |
146 | model_trace_make_busy(model_ptr, out_mask, 0, 0); | |
147 | model_trace_altivec_make_busy(model_ptr, vr_mask, 0); | |
148 | } | |
149 | ||
150 | # Schedule an AltiVec instruction that takes vector input registers and produces vector output registers | |
151 | void::model-function::ppc_insn_vr:itable_index index, model_data *model_ptr, const unsigned32 out_vmask, const unsigned32 in_vmask | |
152 | const unsigned32 vr_mask = out_vmask | in_vmask; | |
153 | model_busy *busy_ptr; | |
154 | ||
155 | if (model_ptr->vr_busy & vr_mask) { | |
156 | model_new_cycle(model_ptr); /* don't count first dependency as a stall */ | |
157 | ||
158 | while (model_ptr->vr_busy & vr_mask) { | |
159 | if (WITH_TRACE && ppc_trace[trace_model]) { | |
160 | model_trace_altivec_busy_p(model_ptr, vr_mask); | |
161 | } | |
162 | ||
163 | model_ptr->nr_stalls_data++; | |
164 | model_new_cycle(model_ptr); | |
165 | } | |
166 | } | |
167 | ||
168 | busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); | |
169 | model_ptr->vr_busy |= out_vmask; | |
170 | busy_ptr->vr_busy |= out_vmask; | |
171 | if (out_vmask) | |
172 | busy_ptr->nr_writebacks = (PPC_ONE_BIT_SET_P(out_vmask)) ? 1 : 2; | |
173 | ||
174 | if (WITH_TRACE && ppc_trace[trace_model]) { | |
175 | model_trace_altivec_make_busy(model_ptr, vr_mask, 0); | |
176 | } | |
177 | ||
178 | # Schedule an AltiVec instruction that takes vector input registers and produces vector output registers, touches CR | |
179 | void::model-function::ppc_insn_vr_cr:itable_index index, model_data *model_ptr, const unsigned32 out_vmask, const unsigned32 in_vmask, const unsigned32 cr_mask | |
180 | const unsigned32 vr_mask = out_vmask | in_vmask; | |
181 | model_busy *busy_ptr; | |
182 | ||
183 | if ((model_ptr->vr_busy & vr_mask) || (model_ptr->cr_fpscr_busy & cr_mask)) { | |
184 | model_new_cycle(model_ptr); /* don't count first dependency as a stall */ | |
185 | ||
186 | while ((model_ptr->vr_busy & vr_mask) || (model_ptr->cr_fpscr_busy & cr_mask)) { | |
187 | if (WITH_TRACE && ppc_trace[trace_model]) { | |
188 | model_trace_busy_p(model_ptr, 0, 0, cr_mask, PPC_NO_SPR); | |
189 | model_trace_altivec_busy_p(model_ptr, vr_mask); | |
190 | } | |
191 | ||
192 | model_ptr->nr_stalls_data++; | |
193 | model_new_cycle(model_ptr); | |
194 | } | |
195 | } | |
196 | ||
197 | busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); | |
198 | model_ptr->cr_fpscr_busy |= cr_mask; | |
199 | busy_ptr->cr_fpscr_busy |= cr_mask; | |
200 | model_ptr->vr_busy |= out_vmask; | |
201 | busy_ptr->vr_busy |= out_vmask; | |
202 | ||
203 | if (out_vmask) | |
204 | busy_ptr->nr_writebacks = (PPC_ONE_BIT_SET_P(out_vmask)) ? 1 : 2; | |
205 | ||
206 | if (cr_mask) | |
207 | busy_ptr->nr_writebacks++; | |
208 | ||
209 | if (WITH_TRACE && ppc_trace[trace_model]) | |
210 | model_trace_altivec_make_busy(model_ptr, vr_mask, cr_mask); | |
211 | ||
212 | # Schedule an AltiVec instruction that takes vector input registers and produces vector output registers, touches VSCR | |
213 | void::model-function::ppc_insn_vr_vscr:itable_index index, model_data *model_ptr, const unsigned32 out_vmask, const unsigned32 in_vmask | |
214 | const unsigned32 vr_mask = out_vmask | in_vmask; | |
215 | model_busy *busy_ptr; | |
216 | ||
217 | if ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) { | |
218 | model_new_cycle(model_ptr); /* don't count first dependency as a stall */ | |
219 | ||
220 | while ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) { | |
221 | if (WITH_TRACE && ppc_trace[trace_model]) | |
222 | model_trace_altivec_busy_p(model_ptr, vr_mask); | |
223 | ||
224 | model_ptr->nr_stalls_data++; | |
225 | model_new_cycle(model_ptr); | |
226 | } | |
227 | } | |
228 | ||
229 | busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); | |
230 | model_ptr->vr_busy |= out_vmask; | |
231 | busy_ptr->vr_busy |= out_vmask; | |
232 | model_ptr->vscr_busy = 1; | |
233 | busy_ptr->vscr_busy = 1; | |
234 | ||
235 | if (out_vmask) | |
236 | busy_ptr->nr_writebacks = 1 + (PPC_ONE_BIT_SET_P(out_vmask)) ? 1 : 2; | |
237 | ||
238 | if (WITH_TRACE && ppc_trace[trace_model]) | |
239 | model_trace_altivec_make_busy(model_ptr, vr_mask, 0); | |
240 | ||
241 | # Schedule an MFVSCR instruction that VSCR input register and produces an AltiVec output register | |
242 | void::model-function::ppc_insn_from_vscr:itable_index index, model_data *model_ptr, const unsigned32 vr_mask | |
243 | model_busy *busy_ptr; | |
244 | ||
245 | while ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) { | |
246 | if (WITH_TRACE && ppc_trace[trace_model]) | |
247 | model_trace_altivec_busy_p(model_ptr, vr_mask); | |
248 | ||
249 | model_ptr->nr_stalls_data++; | |
250 | model_new_cycle(model_ptr); | |
251 | } | |
252 | busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); | |
253 | model_ptr->cr_fpscr_busy |= vr_mask; | |
254 | busy_ptr->cr_fpscr_busy |= vr_mask; | |
255 | ||
256 | if (vr_mask) | |
257 | busy_ptr->nr_writebacks = 1; | |
258 | ||
259 | model_ptr->vr_busy |= vr_mask; | |
260 | if (WITH_TRACE && ppc_trace[trace_model]) | |
261 | model_trace_altivec_make_busy(model_ptr, vr_mask, 0); | |
262 | ||
263 | # Schedule an MTVSCR instruction that one AltiVec input register and produces a vscr output register | |
264 | void::model-function::ppc_insn_to_vscr:itable_index index, model_data *model_ptr, const unsigned32 vr_mask | |
265 | model_busy *busy_ptr; | |
266 | ||
267 | while ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) { | |
268 | if (WITH_TRACE && ppc_trace[trace_model]) | |
269 | model_trace_altivec_busy_p(model_ptr, vr_mask); | |
270 | ||
271 | model_ptr->nr_stalls_data++; | |
272 | model_new_cycle(model_ptr); | |
273 | } | |
274 | busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); | |
275 | busy_ptr ->vscr_busy = 1; | |
276 | model_ptr->vscr_busy = 1; | |
277 | busy_ptr->nr_writebacks = 1; | |
278 | ||
279 | TRACE(trace_model,("Making VSCR busy.\n")); | |
280 | ||
281 | # The follow are AltiVec saturate operations | |
282 | ||
283 | signed8::model-function::altivec_signed_saturate_8:signed16 val, int *sat | |
284 | signed8 rv; | |
285 | if (val > 127) { | |
286 | rv = 127; | |
287 | *sat = 1; | |
288 | } else if (val < -128) { | |
289 | rv = -128; | |
290 | *sat = 1; | |
291 | } else { | |
292 | rv = val; | |
293 | *sat = 0; | |
294 | } | |
295 | return rv; | |
296 | ||
297 | signed16::model-function::altivec_signed_saturate_16:signed32 val, int *sat | |
298 | signed16 rv; | |
299 | if (val > 32767) { | |
300 | rv = 32767; | |
301 | *sat = 1; | |
302 | } else if (val < -32768) { | |
303 | rv = -32768; | |
304 | *sat = 1; | |
305 | } else { | |
306 | rv = val; | |
307 | *sat = 0; | |
308 | } | |
309 | return rv; | |
310 | ||
311 | signed32::model-function::altivec_signed_saturate_32:signed64 val, int *sat | |
312 | signed32 rv; | |
313 | if (val > 2147483647) { | |
314 | rv = 2147483647; | |
315 | *sat = 1; | |
316 | } else if (val < -2147483648LL) { | |
317 | rv = -2147483648LL; | |
318 | *sat = 1; | |
319 | } else { | |
320 | rv = val; | |
321 | *sat = 0; | |
322 | } | |
323 | return rv; | |
324 | ||
325 | unsigned8::model-function::altivec_unsigned_saturate_8:signed16 val, int *sat | |
326 | unsigned8 rv; | |
327 | if (val > 255) { | |
328 | rv = 255; | |
329 | *sat = 1; | |
330 | } else if (val < 0) { | |
331 | rv = 0; | |
332 | *sat = 1; | |
333 | } else { | |
334 | rv = val; | |
335 | *sat = 0; | |
336 | } | |
337 | return rv; | |
338 | ||
339 | unsigned16::model-function::altivec_unsigned_saturate_16:signed32 val, int *sat | |
340 | unsigned16 rv; | |
341 | if (val > 65535) { | |
342 | rv = 65535; | |
343 | *sat = 1; | |
344 | } else if (val < 0) { | |
345 | rv = 0; | |
346 | *sat = 1; | |
347 | } else { | |
348 | rv = val; | |
349 | *sat = 0; | |
350 | } | |
351 | return rv; | |
352 | ||
353 | unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat | |
354 | unsigned32 rv; | |
355 | if (val > 4294967295LL) { | |
356 | rv = 4294967295LL; | |
357 | *sat = 1; | |
358 | } else if (val < 0) { | |
359 | rv = 0; | |
360 | *sat = 1; | |
361 | } else { | |
362 | rv = val; | |
363 | *sat = 0; | |
364 | } | |
365 | return rv; | |
366 | ||
367 | # | |
368 | # Load instructions, 6-14 ... 6-22. | |
369 | # | |
370 | ||
371 | 0.31,6.VS,11.RA,16.RB,21.7,31.0:X:av:lvebx %VD, %RA, %RB:Load Vector Element Byte Indexed | |
372 | unsigned_word b; | |
373 | unsigned_word EA; | |
374 | unsigned_word eb; | |
375 | if (RA_is_0) b = 0; | |
376 | else b = *rA; | |
377 | EA = b + *rB; | |
378 | eb = EA & 0xf; | |
379 | (*vS).b[AV_BINDEX(eb)] = MEM(unsigned, EA, 1); | |
380 | PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); | |
381 | ||
382 | 0.31,6.VS,11.RA,16.RB,21.39,31.0:X:av:lvehx %VD, %RA, %RB:Load Vector Element Half Word Indexed | |
383 | unsigned_word b; | |
384 | unsigned_word EA; | |
385 | unsigned_word eb; | |
386 | if (RA_is_0) b = 0; | |
387 | else b = *rA; | |
388 | EA = (b + *rB) & ~1; | |
389 | eb = EA & 0xf; | |
390 | (*vS).h[AV_HINDEX(eb/2)] = MEM(unsigned, EA, 2); | |
391 | PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); | |
392 | ||
393 | 0.31,6.VS,11.RA,16.RB,21.71,31.0:X:av:lvewx %VD, %RA, %RB:Load Vector Element Word Indexed | |
394 | unsigned_word b; | |
395 | unsigned_word EA; | |
396 | unsigned_word eb; | |
397 | if (RA_is_0) b = 0; | |
398 | else b = *rA; | |
399 | EA = (b + *rB) & ~3; | |
400 | eb = EA & 0xf; | |
401 | (*vS).w[eb/4] = MEM(unsigned, EA, 4); | |
402 | PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); | |
403 | ||
404 | ||
405 | 0.31,6.VS,11.RA,16.RB,21.6,31.0:X:av:lvsl %VD, %RA, %RB:Load Vector for Shift Left | |
406 | unsigned_word b; | |
407 | unsigned_word addr; | |
408 | int i, j; | |
409 | if (RA_is_0) b = 0; | |
410 | else b = *rA; | |
411 | addr = b + *rB; | |
412 | j = addr & 0xf; | |
413 | for (i = 0; i < 16; i++) | |
414 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) | |
415 | (*vS).b[AV_BINDEX(i)] = j++; | |
416 | else | |
417 | (*vS).b[AV_BINDEX(15 - i)] = j++; | |
418 | PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); | |
419 | ||
420 | 0.31,6.VS,11.RA,16.RB,21.38,31.0:X:av:lvsr %VD, %RA, %RB:Load Vector for Shift Right | |
421 | unsigned_word b; | |
422 | unsigned_word addr; | |
423 | int i, j; | |
424 | if (RA_is_0) b = 0; | |
425 | else b = *rA; | |
426 | addr = b + *rB; | |
427 | j = 0x10 - (addr & 0xf); | |
428 | for (i = 0; i < 16; i++) | |
429 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) | |
430 | (*vS).b[AV_BINDEX(i)] = j++; | |
431 | else | |
432 | (*vS).b[AV_BINDEX(15 - i)] = j++; | |
433 | PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); | |
434 | ||
435 | ||
436 | 0.31,6.VS,11.RA,16.RB,21.103,31.0:X:av:lvx %VD, %RA, %RB:Load Vector Indexed | |
437 | unsigned_word b; | |
438 | unsigned_word EA; | |
439 | if (RA_is_0) b = 0; | |
440 | else b = *rA; | |
441 | EA = (b + *rB) & ~0xf; | |
442 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) { | |
443 | (*vS).w[0] = MEM(unsigned, EA + 0, 4); | |
444 | (*vS).w[1] = MEM(unsigned, EA + 4, 4); | |
445 | (*vS).w[2] = MEM(unsigned, EA + 8, 4); | |
446 | (*vS).w[3] = MEM(unsigned, EA + 12, 4); | |
447 | } else { | |
448 | (*vS).w[0] = MEM(unsigned, EA + 12, 4); | |
449 | (*vS).w[1] = MEM(unsigned, EA + 8, 4); | |
450 | (*vS).w[2] = MEM(unsigned, EA + 4, 4); | |
451 | (*vS).w[3] = MEM(unsigned, EA + 0, 4); | |
452 | } | |
453 | PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); | |
454 | ||
455 | 0.31,6.VS,11.RA,16.RB,21.359,31.0:X:av:lvxl %VD, %RA, %RB:Load Vector Indexed LRU | |
456 | unsigned_word b; | |
457 | unsigned_word EA; | |
458 | if (RA_is_0) b = 0; | |
459 | else b = *rA; | |
460 | EA = (b + *rB) & ~0xf; | |
461 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) { | |
462 | (*vS).w[0] = MEM(unsigned, EA + 0, 4); | |
463 | (*vS).w[1] = MEM(unsigned, EA + 4, 4); | |
464 | (*vS).w[2] = MEM(unsigned, EA + 8, 4); | |
465 | (*vS).w[3] = MEM(unsigned, EA + 12, 4); | |
466 | } else { | |
467 | (*vS).w[0] = MEM(unsigned, EA + 12, 4); | |
468 | (*vS).w[1] = MEM(unsigned, EA + 8, 4); | |
469 | (*vS).w[2] = MEM(unsigned, EA + 4, 4); | |
470 | (*vS).w[3] = MEM(unsigned, EA + 0, 4); | |
471 | } | |
472 | PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); | |
473 | ||
474 | # | |
475 | # Move to/from VSCR instructions, 6-23 & 6-24. | |
476 | # | |
477 | ||
478 | 0.4,6.VS,11.0,16.0,21.1540:VX:av:mfvscr %VS:Move from Vector Status and Control Register | |
479 | (*vS).w[0] = 0; | |
480 | (*vS).w[1] = 0; | |
481 | (*vS).w[2] = 0; | |
482 | (*vS).w[3] = VSCR; | |
483 | PPC_INSN_FROM_VSCR(VS_BITMASK); | |
484 | ||
485 | 0.4,6.0,11.0,16.VB,21.1604:VX:av:mtvscr %VB:Move to Vector Status and Control Register | |
486 | VSCR = (*vB).w[3]; | |
487 | PPC_INSN_TO_VSCR(VB_BITMASK); | |
488 | ||
489 | # | |
490 | # Store instructions, 6-25 ... 6-29. | |
491 | # | |
492 | ||
493 | 0.31,6.VS,11.RA,16.RB,21.135,31.0:X:av:stvebx %VD, %RA, %RB:Store Vector Element Byte Indexed | |
494 | unsigned_word b; | |
495 | unsigned_word EA; | |
496 | unsigned_word eb; | |
497 | if (RA_is_0) b = 0; | |
498 | else b = *rA; | |
499 | EA = b + *rB; | |
500 | eb = EA & 0xf; | |
501 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) | |
502 | STORE(EA, 1, (*vS).b[eb]); | |
503 | else | |
504 | STORE(EA, 1, (*vS).b[15-eb]); | |
505 | PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); | |
506 | ||
507 | 0.31,6.VS,11.RA,16.RB,21.167,31.0:X:av:stvehx %VD, %RA, %RB:Store Vector Element Half Word Indexed | |
508 | unsigned_word b; | |
509 | unsigned_word EA; | |
510 | unsigned_word eb; | |
511 | if (RA_is_0) b = 0; | |
512 | else b = *rA; | |
513 | EA = (b + *rB) & ~1; | |
514 | eb = EA & 0xf; | |
515 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) | |
516 | STORE(EA, 2, (*vS).h[eb/2]); | |
517 | else | |
518 | STORE(EA, 2, (*vS).h[7-eb]); | |
519 | PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); | |
520 | ||
521 | 0.31,6.VS,11.RA,16.RB,21.199,31.0:X:av:stvewx %VD, %RA, %RB:Store Vector Element Word Indexed | |
522 | unsigned_word b; | |
523 | unsigned_word EA; | |
524 | unsigned_word eb; | |
525 | if (RA_is_0) b = 0; | |
526 | else b = *rA; | |
527 | EA = (b + *rB) & ~3; | |
528 | eb = EA & 0xf; | |
529 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) | |
530 | STORE(EA, 4, (*vS).w[eb/4]); | |
531 | else | |
532 | STORE(EA, 4, (*vS).w[3-(eb/4)]); | |
533 | PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); | |
534 | ||
535 | 0.31,6.VS,11.RA,16.RB,21.231,31.0:X:av:stvx %VD, %RA, %RB:Store Vector Indexed | |
536 | unsigned_word b; | |
537 | unsigned_word EA; | |
538 | if (RA_is_0) b = 0; | |
539 | else b = *rA; | |
540 | EA = (b + *rB) & ~0xf; | |
541 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) { | |
542 | STORE(EA + 0, 4, (*vS).w[0]); | |
543 | STORE(EA + 4, 4, (*vS).w[1]); | |
544 | STORE(EA + 8, 4, (*vS).w[2]); | |
545 | STORE(EA + 12, 4, (*vS).w[3]); | |
546 | } else { | |
547 | STORE(EA + 12, 4, (*vS).w[0]); | |
548 | STORE(EA + 8, 4, (*vS).w[1]); | |
549 | STORE(EA + 4, 4, (*vS).w[2]); | |
550 | STORE(EA + 0, 4, (*vS).w[3]); | |
551 | } | |
552 | PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); | |
553 | ||
554 | 0.31,6.VS,11.RA,16.RB,21.487,31.0:X:av:stvxl %VD, %RA, %RB:Store Vector Indexed LRU | |
555 | unsigned_word b; | |
556 | unsigned_word EA; | |
557 | if (RA_is_0) b = 0; | |
558 | else b = *rA; | |
559 | EA = (b + *rB) & ~0xf; | |
560 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) { | |
561 | STORE(EA + 0, 4, (*vS).w[0]); | |
562 | STORE(EA + 4, 4, (*vS).w[1]); | |
563 | STORE(EA + 8, 4, (*vS).w[2]); | |
564 | STORE(EA + 12, 4, (*vS).w[3]); | |
565 | } else { | |
566 | STORE(EA + 12, 4, (*vS).w[0]); | |
567 | STORE(EA + 8, 4, (*vS).w[1]); | |
568 | STORE(EA + 4, 4, (*vS).w[2]); | |
569 | STORE(EA + 0, 4, (*vS).w[3]); | |
570 | } | |
571 | PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); | |
572 | ||
573 | # | |
574 | # Vector Add instructions, 6-30 ... 6-40. | |
575 | # | |
576 | ||
577 | 0.4,6.VS,11.VA,16.VB,21.384:VX:av:vaddcuw %VD, %VA, %VB:Vector Add Carryout Unsigned Word | |
578 | unsigned64 temp; | |
579 | int i; | |
580 | for (i = 0; i < 4; i++) { | |
581 | temp = (unsigned64)(*vA).w[i] + (unsigned64)(*vB).w[i]; | |
582 | (*vS).w[i] = temp >> 32; | |
583 | } | |
584 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
585 | ||
586 | 0.4,6.VS,11.VA,16.VB,21.10:VX:av:vaddfp %VD, %VA, %VB:Vector Add Floating Point | |
587 | int i; | |
588 | unsigned32 f; | |
589 | sim_fpu a, b, d; | |
590 | for (i = 0; i < 4; i++) { | |
591 | sim_fpu_32to (&a, (*vA).w[i]); | |
592 | sim_fpu_32to (&b, (*vB).w[i]); | |
593 | sim_fpu_add (&d, &a, &b); | |
594 | sim_fpu_to32 (&f, &d); | |
595 | (*vS).w[i] = f; | |
596 | } | |
597 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
598 | ||
599 | 0.4,6.VS,11.VA,16.VB,21.768:VX:av:vaddsbs %VD, %VA, %VB:Vector Add Signed Byte Saturate | |
600 | int i, sat, tempsat; | |
601 | signed16 temp; | |
602 | for (i = 0; i < 16; i++) { | |
603 | temp = (signed16)(signed8)(*vA).b[i] + (signed16)(signed8)(*vB).b[i]; | |
604 | (*vS).b[i] = altivec_signed_saturate_8(temp, &tempsat); | |
605 | sat |= tempsat; | |
606 | } | |
607 | ALTIVEC_SET_SAT(sat); | |
608 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
609 | ||
610 | 0.4,6.VS,11.VA,16.VB,21.832:VX:av:vaddshs %VD, %VA, %VB:Vector Add Signed Half Word Saturate | |
611 | int i, sat, tempsat; | |
612 | signed32 temp, a, b; | |
613 | for (i = 0; i < 8; i++) { | |
614 | a = (signed32)(signed16)(*vA).h[i]; | |
615 | b = (signed32)(signed16)(*vB).h[i]; | |
616 | temp = a + b; | |
617 | (*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat); | |
618 | sat |= tempsat; | |
619 | } | |
620 | ALTIVEC_SET_SAT(sat); | |
621 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
622 | ||
623 | 0.4,6.VS,11.VA,16.VB,21.896:VX:av:vaddsws %VD, %VA, %VB:Vector Add Signed Word Saturate | |
624 | int i, sat, tempsat; | |
625 | signed64 temp; | |
626 | for (i = 0; i < 4; i++) { | |
627 | temp = (signed64)(signed32)(*vA).w[i] + (signed64)(signed32)(*vB).w[i]; | |
628 | (*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat); | |
629 | sat |= tempsat; | |
630 | } | |
631 | ALTIVEC_SET_SAT(sat); | |
632 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
633 | ||
634 | 0.4,6.VS,11.VA,16.VB,21.0:VX:av:vaddubm %VD, %VA, %VB:Vector Add Unsigned Byte Modulo | |
635 | int i; | |
636 | for (i = 0; i < 16; i++) | |
637 | (*vS).b[i] = ((*vA).b[i] + (*vB).b[i]) & 0xff; | |
638 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
639 | ||
640 | 0.4,6.VS,11.VA,16.VB,21.512:VX:av:vaddubs %VD, %VA, %VB:Vector Add Unsigned Byte Saturate | |
641 | int i, sat, tempsat; | |
642 | signed16 temp; | |
643 | sat = 0; | |
644 | for (i = 0; i < 16; i++) { | |
645 | temp = (signed16)(unsigned8)(*vA).b[i] + (signed16)(unsigned8)(*vB).b[i]; | |
646 | (*vS).b[i] = altivec_unsigned_saturate_8(temp, &tempsat); | |
647 | sat |= tempsat; | |
648 | } | |
649 | ALTIVEC_SET_SAT(sat); | |
650 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
651 | ||
652 | 0.4,6.VS,11.VA,16.VB,21.64:VX:av:vadduhm %VD, %VA, %VB:Vector Add Unsigned Half Word Modulo | |
653 | int i; | |
654 | for (i = 0; i < 8; i++) | |
655 | (*vS).h[i] = ((*vA).h[i] + (*vB).h[i]) & 0xffff; | |
656 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
657 | ||
658 | 0.4,6.VS,11.VA,16.VB,21.576:VX:av:vadduhs %VD, %VA, %VB:Vector Add Unsigned Half Word Saturate | |
659 | int i, sat, tempsat; | |
660 | signed32 temp; | |
661 | for (i = 0; i < 8; i++) { | |
662 | temp = (signed32)(unsigned16)(*vA).h[i] + (signed32)(unsigned16)(*vB).h[i]; | |
663 | (*vS).h[i] = altivec_unsigned_saturate_16(temp, &tempsat); | |
664 | sat |= tempsat; | |
665 | } | |
666 | ALTIVEC_SET_SAT(sat); | |
667 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
668 | ||
669 | 0.4,6.VS,11.VA,16.VB,21.128:VX:av:vadduwm %VD, %VA, %VB:Vector Add Unsigned Word Modulo | |
670 | int i; | |
671 | for (i = 0; i < 4; i++) | |
672 | (*vS).w[i] = (*vA).w[i] + (*vB).w[i]; | |
673 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
674 | ||
675 | 0.4,6.VS,11.VA,16.VB,21.640:VX:av:vadduws %VD, %VA, %VB:Vector Add Unsigned Word Saturate | |
676 | int i, sat, tempsat; | |
677 | signed64 temp; | |
678 | for (i = 0; i < 4; i++) { | |
679 | temp = (signed64)(unsigned32)(*vA).w[i] + (signed64)(unsigned32)(*vB).w[i]; | |
680 | (*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat); | |
681 | sat |= tempsat; | |
682 | } | |
683 | ALTIVEC_SET_SAT(sat); | |
684 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
685 | ||
686 | # | |
687 | # Vector AND instructions, 6-41, 6-42 | |
688 | # | |
689 | ||
690 | 0.4,6.VS,11.VA,16.VB,21.1028:VX:av:vand %VD, %VA, %VB:Vector Logical AND | |
691 | int i; | |
692 | for (i = 0; i < 4; i++) | |
693 | (*vS).w[i] = (*vA).w[i] & (*vB).w[i]; | |
694 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
695 | ||
696 | 0.4,6.VS,11.VA,16.VB,21.1092:VX:av:vandc %VD, %VA, %VB:Vector Logical AND with Compliment | |
697 | int i; | |
698 | for (i = 0; i < 4; i++) | |
699 | (*vS).w[i] = (*vA).w[i] & ~((*vB).w[i]); | |
700 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
701 | ||
702 | ||
703 | # | |
704 | # Vector Average instructions, 6-43, 6-48 | |
705 | # | |
706 | ||
707 | 0.4,6.VS,11.VA,16.VB,21.1282:VX:av:vavgsb %VD, %VA, %VB:Vector Average Signed Byte | |
708 | int i; | |
709 | signed16 temp, a, b; | |
710 | for (i = 0; i < 16; i++) { | |
711 | a = (signed16)(signed8)(*vA).b[i]; | |
712 | b = (signed16)(signed8)(*vB).b[i]; | |
713 | temp = a + b + 1; | |
714 | (*vS).b[i] = (temp >> 1) & 0xff; | |
715 | } | |
716 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
717 | ||
718 | 0.4,6.VS,11.VA,16.VB,21.1346:VX:av:vavgsh %VD, %VA, %VB:Vector Average Signed Half Word | |
719 | int i; | |
720 | signed32 temp, a, b; | |
721 | for (i = 0; i < 8; i++) { | |
722 | a = (signed32)(signed16)(*vA).h[i]; | |
723 | b = (signed32)(signed16)(*vB).h[i]; | |
724 | temp = a + b + 1; | |
725 | (*vS).h[i] = (temp >> 1) & 0xffff; | |
726 | } | |
727 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
728 | ||
729 | 0.4,6.VS,11.VA,16.VB,21.1410:VX:av:vavgsw %VD, %VA, %VB:Vector Average Signed Word | |
730 | int i; | |
731 | signed64 temp, a, b; | |
732 | for (i = 0; i < 4; i++) { | |
733 | a = (signed64)(signed32)(*vA).w[i]; | |
734 | b = (signed64)(signed32)(*vB).w[i]; | |
735 | temp = a + b + 1; | |
736 | (*vS).w[i] = (temp >> 1) & 0xffffffff; | |
737 | } | |
738 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
739 | ||
740 | 0.4,6.VS,11.VA,16.VB,21.1026:VX:av:vavgub %VD, %VA, %VB:Vector Average Unsigned Byte | |
741 | int i; | |
742 | unsigned16 temp, a, b; | |
743 | for (i = 0; i < 16; i++) { | |
744 | a = (*vA).b[i]; | |
745 | b = (*vB).b[i]; | |
746 | temp = a + b + 1; | |
747 | (*vS).b[i] = (temp >> 1) & 0xff; | |
748 | } | |
749 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
750 | ||
751 | 0.4,6.VS,11.VA,16.VB,21.1090:VX:av:vavguh %VD, %VA, %VB:Vector Average Unsigned Half Word | |
752 | int i; | |
753 | unsigned32 temp, a, b; | |
754 | for (i = 0; i < 8; i++) { | |
755 | a = (*vA).h[i]; | |
756 | b = (*vB).h[i]; | |
757 | temp = a + b + 1; | |
758 | (*vS).h[i] = (temp >> 1) & 0xffff; | |
759 | } | |
760 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
761 | ||
762 | 0.4,6.VS,11.VA,16.VB,21.1154:VX:av:vavguw %VD, %VA, %VB:Vector Average Unsigned Word | |
763 | int i; | |
764 | unsigned64 temp, a, b; | |
765 | for (i = 0; i < 4; i++) { | |
766 | a = (*vA).w[i]; | |
767 | b = (*vB).w[i]; | |
768 | temp = a + b + 1; | |
769 | (*vS).w[i] = (temp >> 1) & 0xffffffff; | |
770 | } | |
771 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
772 | ||
773 | # | |
774 | # Vector Fixed Point Convert instructions, 6-49, 6-50 | |
775 | # | |
776 | ||
777 | 0.4,6.VS,11.UIMM,16.VB,21.842:VX:av:vcfsx %VD, %VB, %UIMM:Vector Convert From Signed Fixed-Point Word | |
778 | int i; | |
779 | unsigned32 f; | |
780 | sim_fpu b, div, d; | |
781 | for (i = 0; i < 4; i++) { | |
782 | sim_fpu_32to (&b, (*vB).w[i]); | |
783 | sim_fpu_u32to (&div, 2 << UIMM, sim_fpu_round_default); | |
784 | sim_fpu_div (&d, &b, &div); | |
785 | sim_fpu_to32 (&f, &d); | |
786 | (*vS).w[i] = f; | |
787 | } | |
788 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
789 | ||
790 | 0.4,6.VS,11.UIMM,16.VB,21.778:VX:av:vcfux %VD, %VA, %UIMM:Vector Convert From Unsigned Fixed-Point Word | |
791 | int i; | |
792 | unsigned32 f; | |
793 | sim_fpu b, d, div; | |
794 | for (i = 0; i < 4; i++) { | |
795 | sim_fpu_32to (&b, (*vB).w[i]); | |
796 | sim_fpu_u32to (&div, 2 << UIMM, sim_fpu_round_default); | |
797 | sim_fpu_div (&d, &b, &div); | |
798 | sim_fpu_to32u (&f, &d, sim_fpu_round_default); | |
799 | (*vS).w[i] = f; | |
800 | } | |
801 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
802 | ||
803 | # | |
804 | # Vector Compare instructions, 6-51 ... 6-64 | |
805 | # | |
806 | ||
807 | 0.4,6.VS,11.VA,16.VB,21.RC,22.966:VXR:av:vcmpbpfpx %VD, %VA, %VB:Vector Compare Bounds Floating Point | |
808 | int i, le, ge; | |
809 | sim_fpu a, b, d; | |
810 | for (i = 0; i < 4; i++) { | |
811 | sim_fpu_32to (&a, (*vA).w[i]); | |
812 | sim_fpu_32to (&b, (*vB).w[i]); | |
813 | le = sim_fpu_is_le(&a, &b); | |
814 | ge = sim_fpu_is_ge(&a, &b); | |
815 | (*vS).w[i] = (le ? 0 : 1 << 31) | (ge ? 0 : 1 << 30); | |
816 | } | |
817 | if (RC) | |
818 | ALTIVEC_SET_CR6(vS, 0); | |
819 | PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); | |
820 | ||
821 | 0.4,6.VS,11.VA,16.VB,21.RC,22.198:VXR:av:vcmpeqfpx %VD, %VA, %VB:Vector Compare Equal-to-Floating Point | |
822 | int i; | |
823 | sim_fpu a, b; | |
824 | for (i = 0; i < 4; i++) { | |
825 | sim_fpu_32to (&a, (*vA).w[i]); | |
826 | sim_fpu_32to (&b, (*vB).w[i]); | |
827 | if (sim_fpu_is_eq(&a, &b)) | |
828 | (*vS).w[i] = 0xffffffff; | |
829 | else | |
830 | (*vS).w[i] = 0; | |
831 | } | |
832 | if (RC) | |
833 | ALTIVEC_SET_CR6(vS, 1); | |
834 | PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); | |
835 | ||
836 | 0.4,6.VS,11.VA,16.VB,21.RC,22.6:VXR:av:vcmpequbx %VD, %VA, %VB:Vector Compare Equal-to Unsigned Byte | |
837 | int i; | |
838 | for (i = 0; i < 16; i++) | |
839 | if ((*vA).b[i] == (*vB).b[i]) | |
840 | (*vS).b[i] = 0xff; | |
841 | else | |
842 | (*vS).b[i] = 0; | |
843 | if (RC) | |
844 | ALTIVEC_SET_CR6(vS, 1); | |
845 | PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); | |
846 | ||
847 | 0.4,6.VS,11.VA,16.VB,21.RC,22.70:VXR:av:vcmpequhx %VD, %VA, %VB:Vector Compare Equal-to Unsigned Half Word | |
848 | int i; | |
849 | for (i = 0; i < 8; i++) | |
850 | if ((*vA).h[i] == (*vB).h[i]) | |
851 | (*vS).h[i] = 0xffff; | |
852 | else | |
853 | (*vS).h[i] = 0; | |
854 | if (RC) | |
855 | ALTIVEC_SET_CR6(vS, 1); | |
856 | PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); | |
857 | ||
858 | 0.4,6.VS,11.VA,16.VB,21.RC,22.134:VXR:av:vcmpequwx %VD, %VA, %VB:Vector Compare Equal-to Unsigned Word | |
859 | int i; | |
860 | for (i = 0; i < 4; i++) | |
861 | if ((*vA).w[i] == (*vB).w[i]) | |
862 | (*vS).w[i] = 0xffffffff; | |
863 | else | |
864 | (*vS).w[i] = 0; | |
865 | if (RC) | |
866 | ALTIVEC_SET_CR6(vS, 1); | |
867 | PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); | |
868 | ||
869 | 0.4,6.VS,11.VA,16.VB,21.RC,22.454:VXR:av:vcmpgefpx %VD, %VA, %VB:Vector Compare Greater-Than-or-Equal-to Floating Point | |
870 | int i; | |
871 | sim_fpu a, b; | |
872 | for (i = 0; i < 4; i++) { | |
873 | sim_fpu_32to (&a, (*vA).w[i]); | |
874 | sim_fpu_32to (&b, (*vB).w[i]); | |
875 | if (sim_fpu_is_ge(&a, &b)) | |
876 | (*vS).w[i] = 0xffffffff; | |
877 | else | |
878 | (*vS).w[i] = 0; | |
879 | } | |
880 | if (RC) | |
881 | ALTIVEC_SET_CR6(vS, 1); | |
882 | PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); | |
883 | ||
884 | 0.4,6.VS,11.VA,16.VB,21.RC,22.710:VXR:av:vcmpgtfpx %VD, %VA, %VB:Vector Compare Greater-Than Floating Point | |
885 | int i; | |
886 | sim_fpu a, b; | |
887 | for (i = 0; i < 4; i++) { | |
888 | sim_fpu_32to (&a, (*vA).w[i]); | |
889 | sim_fpu_32to (&b, (*vB).w[i]); | |
890 | if (sim_fpu_is_gt(&a, &b)) | |
891 | (*vS).w[i] = 0xffffffff; | |
892 | else | |
893 | (*vS).w[i] = 0; | |
894 | } | |
895 | if (RC) | |
896 | ALTIVEC_SET_CR6(vS, 1); | |
897 | PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); | |
898 | ||
899 | 0.4,6.VS,11.VA,16.VB,21.RC,22.774:VXR:av:vcmpgtsbx %VD, %VA, %VB:Vector Compare Greater-Than Signed Byte | |
900 | int i; | |
901 | signed8 a, b; | |
902 | for (i = 0; i < 16; i++) { | |
903 | a = (*vA).b[i]; | |
904 | b = (*vB).b[i]; | |
905 | if (a > b) | |
906 | (*vS).b[i] = 0xff; | |
907 | else | |
908 | (*vS).b[i] = 0; | |
909 | } | |
910 | if (RC) | |
911 | ALTIVEC_SET_CR6(vS, 1); | |
912 | PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); | |
913 | ||
914 | 0.4,6.VS,11.VA,16.VB,21.RC,22.838:VXR:av:vcmpgtshx %VD, %VA, %VB:Vector Compare Greater-Than Signed Half Word | |
915 | int i; | |
916 | signed16 a, b; | |
917 | for (i = 0; i < 8; i++) { | |
918 | a = (*vA).h[i]; | |
919 | b = (*vB).h[i]; | |
920 | if (a > b) | |
921 | (*vS).h[i] = 0xffff; | |
922 | else | |
923 | (*vS).h[i] = 0; | |
924 | } | |
925 | if (RC) | |
926 | ALTIVEC_SET_CR6(vS, 1); | |
927 | PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); | |
928 | ||
929 | 0.4,6.VS,11.VA,16.VB,21.RC,22.902:VXR:av:vcmpgtswx %VD, %VA, %VB:Vector Compare Greater-Than Signed Word | |
930 | int i; | |
931 | signed32 a, b; | |
932 | for (i = 0; i < 4; i++) { | |
933 | a = (*vA).w[i]; | |
934 | b = (*vB).w[i]; | |
935 | if (a > b) | |
936 | (*vS).w[i] = 0xffffffff; | |
937 | else | |
938 | (*vS).w[i] = 0; | |
939 | } | |
940 | if (RC) | |
941 | ALTIVEC_SET_CR6(vS, 1); | |
942 | PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); | |
943 | ||
944 | 0.4,6.VS,11.VA,16.VB,21.RC,22.518:VXR:av:vcmpgtubx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Byte | |
945 | int i; | |
946 | unsigned8 a, b; | |
947 | for (i = 0; i < 16; i++) { | |
948 | a = (*vA).b[i]; | |
949 | b = (*vB).b[i]; | |
950 | if (a > b) | |
951 | (*vS).b[i] = 0xff; | |
952 | else | |
953 | (*vS).b[i] = 0; | |
954 | } | |
955 | if (RC) | |
956 | ALTIVEC_SET_CR6(vS, 1); | |
957 | PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); | |
958 | ||
959 | 0.4,6.VS,11.VA,16.VB,21.RC,22.582:VXR:av:vcmpgtuhx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Half Word | |
960 | int i; | |
961 | unsigned16 a, b; | |
962 | for (i = 0; i < 8; i++) { | |
963 | a = (*vA).h[i]; | |
964 | b = (*vB).h[i]; | |
965 | if (a > b) | |
966 | (*vS).h[i] = 0xffff; | |
967 | else | |
968 | (*vS).h[i] = 0; | |
969 | } | |
970 | if (RC) | |
971 | ALTIVEC_SET_CR6(vS, 1); | |
972 | PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); | |
973 | ||
974 | 0.4,6.VS,11.VA,16.VB,21.RC,22.646:VXR:av:vcmpgtuwx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Word | |
975 | int i; | |
976 | unsigned32 a, b; | |
977 | for (i = 0; i < 4; i++) { | |
978 | a = (*vA).w[i]; | |
979 | b = (*vB).w[i]; | |
980 | if (a > b) | |
981 | (*vS).w[i] = 0xffffffff; | |
982 | else | |
983 | (*vS).w[i] = 0; | |
984 | } | |
985 | if (RC) | |
986 | ALTIVEC_SET_CR6(vS, 1); | |
987 | PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); | |
988 | ||
989 | # | |
990 | # Vector Convert instructions, 6-65, 6-66. | |
991 | # | |
992 | ||
993 | 0.4,6.VS,11.UIMM,16.VB,21.970:VX:av:vctsxs %VD, %VB, %UIMM:Vector Convert to Signed Fixed-Point Word Saturate | |
994 | int i, sat, tempsat; | |
995 | signed64 temp; | |
996 | sim_fpu a, b, m; | |
997 | sat = 0; | |
998 | for (i = 0; i < 4; i++) { | |
999 | sim_fpu_32to (&b, (*vB).w[i]); | |
1000 | sim_fpu_u32to (&m, 2 << UIMM, sim_fpu_round_default); | |
1001 | sim_fpu_mul (&a, &b, &m); | |
1002 | sim_fpu_to64i (&temp, &a, sim_fpu_round_default); | |
1003 | (*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat); | |
1004 | sat |= tempsat; | |
1005 | } | |
1006 | ALTIVEC_SET_SAT(sat); | |
1007 | PPC_INSN_VR_VSCR(VS_BITMASK, VB_BITMASK); | |
1008 | ||
1009 | 0.4,6.VS,11.UIMM,16.VB,21.906:VX:av:vctuxs %VD, %VB, %UIMM:Vector Convert to Unsigned Fixed-Point Word Saturate | |
1010 | int i, sat, tempsat; | |
1011 | signed64 temp; | |
1012 | sim_fpu a, b, m; | |
1013 | sat = 0; | |
1014 | for (i = 0; i < 4; i++) { | |
1015 | sim_fpu_32to (&b, (*vB).w[i]); | |
1016 | sim_fpu_u32to (&m, 2 << UIMM, sim_fpu_round_default); | |
1017 | sim_fpu_mul (&a, &b, &m); | |
1018 | sim_fpu_to64u (&temp, &a, sim_fpu_round_default); | |
1019 | (*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat); | |
1020 | sat |= tempsat; | |
1021 | } | |
1022 | ALTIVEC_SET_SAT(sat); | |
1023 | PPC_INSN_VR_VSCR(VS_BITMASK, VB_BITMASK); | |
1024 | ||
1025 | # | |
1026 | # Vector Estimate instructions, 6-67 ... 6-70. | |
1027 | # | |
1028 | ||
1029 | 0.4,6.VS,11.0,16.VB,21.394:VX:av:vexptefp %VD, %VB:Vector 2 Raised to the Exponent Estimate Floating Point | |
1030 | int i; | |
1031 | unsigned32 f; | |
1032 | signed32 bi; | |
1033 | sim_fpu b, d; | |
1034 | for (i = 0; i < 4; i++) { | |
1035 | /*HACK!*/ | |
1036 | sim_fpu_32to (&b, (*vB).w[i]); | |
1037 | sim_fpu_to32i (&bi, &b, sim_fpu_round_default); | |
1038 | bi = 2 ^ bi; | |
1039 | sim_fpu_32to (&d, bi); | |
1040 | sim_fpu_to32 (&f, &d); | |
1041 | (*vS).w[i] = f; | |
1042 | } | |
1043 | PPC_INSN_VR_VSCR(VS_BITMASK, VB_BITMASK); | |
1044 | ||
1045 | 0.4,6.VS,11.0,16.VB,21.458:VX:av:vlogefp %VD, %VB:Vector Log2 Estimate Floating Point | |
1046 | int i; | |
1047 | unsigned32 c, u, f; | |
1048 | sim_fpu b, cfpu, d; | |
1049 | for (i = 0; i < 4; i++) { | |
1050 | /*HACK!*/ | |
1051 | sim_fpu_32to (&b, (*vB).w[i]); | |
1052 | sim_fpu_to32u (&u, &b, sim_fpu_round_default); | |
1053 | for (c = 0; (u /= 2) > 1; c++) | |
1054 | ; | |
1055 | sim_fpu_32to (&cfpu, c); | |
1056 | sim_fpu_add (&d, &b, &cfpu); | |
1057 | sim_fpu_to32 (&f, &d); | |
1058 | (*vS).w[i] = f; | |
1059 | } | |
1060 | PPC_INSN_VR_VSCR(VS_BITMASK, VB_BITMASK); | |
1061 | ||
1062 | # | |
1063 | # Vector Multiply Add instruction, 6-71 | |
1064 | # | |
1065 | ||
1066 | 0.4,6.VS,11.VA,16.VB,21.VC,26.46:VAX:av:vmaddfp %VD, %VA, %VB, %VC:Vector Multiply Add Floating Point | |
1067 | int i; | |
1068 | unsigned32 f; | |
1069 | sim_fpu a, b, c, d, e; | |
1070 | for (i = 0; i < 4; i++) { | |
1071 | sim_fpu_32to (&a, (*vA).w[i]); | |
1072 | sim_fpu_32to (&b, (*vB).w[i]); | |
1073 | sim_fpu_32to (&c, (*vC).w[i]); | |
1074 | sim_fpu_mul (&e, &a, &c); | |
1075 | sim_fpu_add (&d, &e, &b); | |
1076 | sim_fpu_to32 (&f, &d); | |
1077 | (*vS).w[i] = f; | |
1078 | } | |
1079 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); | |
1080 | ||
1081 | ||
1082 | # | |
1083 | # Vector Maximum instructions, 6-72 ... 6-78. | |
1084 | # | |
1085 | ||
1086 | 0.4,6.VS,11.VA,16.VB,21.1034:VX:av:vmaxfp %VD, %VA, %VB:Vector Maximum Floating Point | |
1087 | int i; | |
1088 | unsigned32 f; | |
1089 | sim_fpu a, b, d; | |
1090 | for (i = 0; i < 4; i++) { | |
1091 | sim_fpu_32to (&a, (*vA).w[i]); | |
1092 | sim_fpu_32to (&b, (*vB).w[i]); | |
1093 | sim_fpu_max (&d, &a, &b); | |
1094 | sim_fpu_to32 (&f, &d); | |
1095 | (*vS).w[i] = f; | |
1096 | } | |
1097 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1098 | ||
1099 | 0.4,6.VS,11.VA,16.VB,21.258:VX:av:vmaxsb %VD, %VA, %VB:Vector Maximum Signed Byte | |
1100 | int i; | |
1101 | signed8 a, b; | |
1102 | for (i = 0; i < 16; i++) { | |
1103 | a = (*vA).b[i]; | |
1104 | b = (*vB).b[i]; | |
1105 | if (a > b) | |
1106 | (*vS).b[i] = a; | |
1107 | else | |
1108 | (*vS).b[i] = b; | |
1109 | } | |
1110 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1111 | ||
1112 | 0.4,6.VS,11.VA,16.VB,21.322:VX:av:vmaxsh %VD, %VA, %VB:Vector Maximum Signed Half Word | |
1113 | int i; | |
1114 | signed16 a, b; | |
1115 | for (i = 0; i < 8; i++) { | |
1116 | a = (*vA).h[i]; | |
1117 | b = (*vB).h[i]; | |
1118 | if (a > b) | |
1119 | (*vS).h[i] = a; | |
1120 | else | |
1121 | (*vS).h[i] = b; | |
1122 | } | |
1123 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1124 | ||
1125 | 0.4,6.VS,11.VA,16.VB,21.386:VX:av:vmaxsw %VD, %VA, %VB:Vector Maximum Signed Word | |
1126 | int i; | |
1127 | signed32 a, b; | |
1128 | for (i = 0; i < 4; i++) { | |
1129 | a = (*vA).w[i]; | |
1130 | b = (*vB).w[i]; | |
1131 | if (a > b) | |
1132 | (*vS).w[i] = a; | |
1133 | else | |
1134 | (*vS).w[i] = b; | |
1135 | } | |
1136 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1137 | ||
1138 | 0.4,6.VS,11.VA,16.VB,21.2:VX:av:vmaxub %VD, %VA, %VB:Vector Maximum Unsigned Byte | |
1139 | int i; | |
1140 | unsigned8 a, b; | |
1141 | for (i = 0; i < 16; i++) { | |
1142 | a = (*vA).b[i]; | |
1143 | b = (*vB).b[i]; | |
1144 | if (a > b) | |
1145 | (*vS).b[i] = a; | |
1146 | else | |
1147 | (*vS).b[i] = b; | |
1148 | }; | |
1149 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1150 | ||
1151 | 0.4,6.VS,11.VA,16.VB,21.66:VX:av:vmaxus %VD, %VA, %VB:Vector Maximum Unsigned Half Word | |
1152 | int i; | |
1153 | unsigned16 a, b; | |
1154 | for (i = 0; i < 8; i++) { | |
1155 | a = (*vA).h[i]; | |
1156 | b = (*vB).h[i]; | |
1157 | if (a > b) | |
1158 | (*vS).h[i] = a; | |
1159 | else | |
1160 | (*vS).h[i] = b; | |
1161 | } | |
1162 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1163 | ||
1164 | 0.4,6.VS,11.VA,16.VB,21.130:VX:av:vmaxuw %VD, %VA, %VB:Vector Maximum Unsigned Word | |
1165 | int i; | |
1166 | unsigned32 a, b; | |
1167 | for (i = 0; i < 4; i++) { | |
1168 | a = (*vA).w[i]; | |
1169 | b = (*vB).w[i]; | |
1170 | if (a > b) | |
1171 | (*vS).w[i] = a; | |
1172 | else | |
1173 | (*vS).w[i] = b; | |
1174 | } | |
1175 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1176 | ||
1177 | ||
1178 | # | |
1179 | # Vector Multiple High instructions, 6-79, 6-80. | |
1180 | # | |
1181 | ||
1182 | 0.4,6.VS,11.VA,16.VB,21.VC,26.32:VAX:av:vmhaddshs %VD, %VA, %VB, %VC:Vector Multiple High and Add Signed Half Word Saturate | |
1183 | int i, sat, tempsat; | |
1184 | signed16 a, b; | |
1185 | signed32 prod, temp, c; | |
1186 | for (i = 0; i < 8; i++) { | |
1187 | a = (*vA).h[i]; | |
1188 | b = (*vB).h[i]; | |
1189 | c = (signed32)(signed16)(*vC).h[i]; | |
1190 | prod = (signed32)a * (signed32)b; | |
1191 | temp = (prod >> 15) + c; | |
1192 | (*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat); | |
1193 | sat |= tempsat; | |
1194 | } | |
1195 | ALTIVEC_SET_SAT(sat); | |
1196 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); | |
1197 | ||
1198 | 0.4,6.VS,11.VA,16.VB,21.VC,26.33:VAX:av:vmhraddshs %VD, %VA, %VB, %VC:Vector Multiple High Round and Add Signed Half Word Saturate | |
1199 | int i, sat, tempsat; | |
1200 | signed16 a, b; | |
1201 | signed32 prod, temp, c; | |
1202 | for (i = 0; i < 8; i++) { | |
1203 | a = (*vA).h[i]; | |
1204 | b = (*vB).h[i]; | |
1205 | c = (signed32)(signed16)(*vC).h[i]; | |
1206 | prod = (signed32)a * (signed32)b; | |
1207 | prod += 0x4000; | |
1208 | temp = (prod >> 15) + c; | |
1209 | (*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat); | |
1210 | sat |= tempsat; | |
1211 | } | |
1212 | ALTIVEC_SET_SAT(sat); | |
1213 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); | |
1214 | ||
1215 | ||
1216 | # | |
1217 | # Vector Minimum instructions, 6-81 ... 6-87 | |
1218 | # | |
1219 | ||
1220 | 0.4,6.VS,11.VA,16.VB,21.1098:VX:av:vminfp %VD, %VA, %VB:Vector Minimum Floating Point | |
1221 | int i; | |
1222 | unsigned32 f; | |
1223 | sim_fpu a, b, d; | |
1224 | for (i = 0; i < 4; i++) { | |
1225 | sim_fpu_32to (&a, (*vA).w[i]); | |
1226 | sim_fpu_32to (&b, (*vB).w[i]); | |
1227 | sim_fpu_min (&d, &a, &b); | |
1228 | sim_fpu_to32 (&f, &d); | |
1229 | (*vS).w[i] = f; | |
1230 | } | |
1231 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1232 | ||
1233 | 0.4,6.VS,11.VA,16.VB,21.770:VX:av:vminsb %VD, %VA, %VB:Vector Minimum Signed Byte | |
1234 | int i; | |
1235 | signed8 a, b; | |
1236 | for (i = 0; i < 16; i++) { | |
1237 | a = (*vA).b[i]; | |
1238 | b = (*vB).b[i]; | |
1239 | if (a < b) | |
1240 | (*vS).b[i] = a; | |
1241 | else | |
1242 | (*vS).b[i] = b; | |
1243 | } | |
1244 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1245 | ||
1246 | 0.4,6.VS,11.VA,16.VB,21.834:VX:av:vminsh %VD, %VA, %VB:Vector Minimum Signed Half Word | |
1247 | int i; | |
1248 | signed16 a, b; | |
1249 | for (i = 0; i < 8; i++) { | |
1250 | a = (*vA).h[i]; | |
1251 | b = (*vB).h[i]; | |
1252 | if (a < b) | |
1253 | (*vS).h[i] = a; | |
1254 | else | |
1255 | (*vS).h[i] = b; | |
1256 | } | |
1257 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1258 | ||
1259 | 0.4,6.VS,11.VA,16.VB,21.898:VX:av:vminsw %VD, %VA, %VB:Vector Minimum Signed Word | |
1260 | int i; | |
1261 | signed32 a, b; | |
1262 | for (i = 0; i < 4; i++) { | |
1263 | a = (*vA).w[i]; | |
1264 | b = (*vB).w[i]; | |
1265 | if (a < b) | |
1266 | (*vS).w[i] = a; | |
1267 | else | |
1268 | (*vS).w[i] = b; | |
1269 | } | |
1270 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1271 | ||
1272 | 0.4,6.VS,11.VA,16.VB,21.514:VX:av:vminub %VD, %VA, %VB:Vector Minimum Unsigned Byte | |
1273 | int i; | |
1274 | unsigned8 a, b; | |
1275 | for (i = 0; i < 16; i++) { | |
1276 | a = (*vA).b[i]; | |
1277 | b = (*vB).b[i]; | |
1278 | if (a < b) | |
1279 | (*vS).b[i] = a; | |
1280 | else | |
1281 | (*vS).b[i] = b; | |
1282 | }; | |
1283 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1284 | ||
1285 | 0.4,6.VS,11.VA,16.VB,21.578:VX:av:vminuh %VD, %VA, %VB:Vector Minimum Unsigned Half Word | |
1286 | int i; | |
1287 | unsigned16 a, b; | |
1288 | for (i = 0; i < 8; i++) { | |
1289 | a = (*vA).h[i]; | |
1290 | b = (*vB).h[i]; | |
1291 | if (a < b) | |
1292 | (*vS).h[i] = a; | |
1293 | else | |
1294 | (*vS).h[i] = b; | |
1295 | } | |
1296 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1297 | ||
1298 | 0.4,6.VS,11.VA,16.VB,21.642:VX:av:vminuw %VD, %VA, %VB:Vector Minimum Unsigned Word | |
1299 | int i; | |
1300 | unsigned32 a, b; | |
1301 | for (i = 0; i < 4; i++) { | |
1302 | a = (*vA).w[i]; | |
1303 | b = (*vB).w[i]; | |
1304 | if (a < b) | |
1305 | (*vS).w[i] = a; | |
1306 | else | |
1307 | (*vS).w[i] = b; | |
1308 | } | |
1309 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1310 | ||
1311 | ||
1312 | # | |
1313 | # Vector Multiply Low instruction, 6-88 | |
1314 | # | |
1315 | ||
1316 | 0.4,6.VS,11.VA,16.VB,21.VC,26.34:VAX:av:vmladduhm %VD, %VA, %VB, %VC:Vector Multiply Low and Add Unsigned Half Word Modulo | |
1317 | int i; | |
1318 | unsigned16 a, b, c; | |
1319 | unsigned32 prod; | |
1320 | for (i = 0; i < 8; i++) { | |
1321 | a = (*vA).h[i]; | |
1322 | b = (*vB).h[i]; | |
1323 | c = (*vC).h[i]; | |
1324 | prod = (unsigned32)a * (unsigned32)b; | |
1325 | (*vS).h[i] = (prod + c) & 0xffff; | |
1326 | } | |
1327 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); | |
1328 | ||
1329 | ||
1330 | # | |
1331 | # Vector Merge instructions, 6-89 ... 6-94 | |
1332 | # | |
1333 | ||
1334 | 0.4,6.VS,11.VA,16.VB,21.12:VX:av:vmrghb %VD, %VA, %VB:Vector Merge High Byte | |
1335 | int i; | |
1336 | for (i = 0; i < 16; i += 2) { | |
1337 | (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(i/2)]; | |
1338 | (*vS).b[AV_BINDEX(i+1)] = (*vB).b[AV_BINDEX(i/2)]; | |
1339 | } | |
1340 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1341 | ||
1342 | 0.4,6.VS,11.VA,16.VB,21.76:VX:av:vmrghh %VD, %VA, %VB:Vector Merge High Half Word | |
1343 | int i; | |
1344 | for (i = 0; i < 8; i += 2) { | |
1345 | (*vS).h[AV_HINDEX(i)] = (*vA).h[AV_HINDEX(i/2)]; | |
1346 | (*vS).h[AV_HINDEX(i+1)] = (*vB).h[AV_HINDEX(i/2)]; | |
1347 | } | |
1348 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1349 | ||
1350 | 0.4,6.VS,11.VA,16.VB,21.140:VX:av:vmrghw %VD, %VA, %VB:Vector Merge High Word | |
1351 | int i; | |
1352 | for (i = 0; i < 4; i += 2) { | |
1353 | (*vS).w[i] = (*vA).w[i/2]; | |
1354 | (*vS).w[i+1] = (*vB).w[i/2]; | |
1355 | } | |
1356 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1357 | ||
1358 | 0.4,6.VS,11.VA,16.VB,21.268:VX:av:vmrglb %VD, %VA, %VB:Vector Merge Low Byte | |
1359 | int i; | |
1360 | for (i = 0; i < 16; i += 2) { | |
1361 | (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX((i/2) + 8)]; | |
1362 | (*vS).b[AV_BINDEX(i+1)] = (*vB).b[AV_BINDEX((i/2) + 8)]; | |
1363 | } | |
1364 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1365 | ||
1366 | 0.4,6.VS,11.VA,16.VB,21.332:VX:av:vmrglh %VD, %VA, %VB:Vector Merge Low Half Word | |
1367 | int i; | |
1368 | for (i = 0; i < 8; i += 2) { | |
1369 | (*vS).h[AV_HINDEX(i)] = (*vA).h[AV_HINDEX((i/2) + 4)]; | |
1370 | (*vS).h[AV_HINDEX(i+1)] = (*vB).h[AV_HINDEX((i/2) + 4)]; | |
1371 | } | |
1372 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1373 | ||
1374 | 0.4,6.VS,11.VA,16.VB,21.396:VX:av:vmrglw %VD, %VA, %VB:Vector Merge Low Word | |
1375 | int i; | |
1376 | for (i = 0; i < 4; i += 2) { | |
1377 | (*vS).w[i] = (*vA).w[(i/2) + 2]; | |
1378 | (*vS).w[i+1] = (*vB).w[(i/2) + 2]; | |
1379 | } | |
1380 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1381 | ||
1382 | ||
1383 | # | |
1384 | # Vector Multiply Sum instructions, 6-95 ... 6-100 | |
1385 | # | |
1386 | ||
1387 | 0.4,6.VS,11.VA,16.VB,21.VC,26.37:VAX:av:vmsummbm %VD, %VA, %VB, %VC:Vector Multiply Sum Mixed-Sign Byte Modulo | |
1388 | int i, j; | |
1389 | signed32 temp; | |
1390 | signed16 prod, a; | |
1391 | unsigned16 b; | |
1392 | for (i = 0; i < 4; i++) { | |
1393 | temp = (*vC).w[i]; | |
1394 | for (j = 0; j < 4; j++) { | |
1395 | a = (signed16)(signed8)(*vA).b[i*4+j]; | |
1396 | b = (*vB).b[i*4+j]; | |
1397 | prod = a * b; | |
1398 | temp += (signed32)prod; | |
1399 | } | |
1400 | (*vS).w[i] = temp; | |
1401 | } | |
1402 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); | |
1403 | ||
1404 | 0.4,6.VS,11.VA,16.VB,21.VC,26.40:VAX:av:vmsumshm %VD, %VA, %VB, %VC:Vector Multiply Sum Signed Half Word Modulo | |
1405 | int i, j; | |
1406 | signed32 temp, prod, a, b; | |
1407 | for (i = 0; i < 4; i++) { | |
1408 | temp = (*vC).w[i]; | |
1409 | for (j = 0; j < 2; j++) { | |
1410 | a = (signed32)(signed16)(*vA).h[i*2+j]; | |
1411 | b = (signed32)(signed16)(*vB).h[i*2+j]; | |
1412 | prod = a * b; | |
1413 | temp += prod; | |
1414 | } | |
1415 | (*vS).w[i] = temp; | |
1416 | } | |
1417 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); | |
1418 | ||
1419 | 0.4,6.VS,11.VA,16.VB,21.VC,26.41:VAX:av:vmsumshs %VD, %VA, %VB, %VC:Vector Multiply Sum Signed Half Word Saturate | |
1420 | int i, j, sat, tempsat; | |
1421 | signed64 temp; | |
1422 | signed32 prod, a, b; | |
1423 | sat = 0; | |
1424 | for (i = 0; i < 4; i++) { | |
1425 | temp = (signed64)(signed32)(*vC).w[i]; | |
1426 | for (j = 0; j < 2; j++) { | |
1427 | a = (signed32)(signed16)(*vA).h[i*2+j]; | |
1428 | b = (signed32)(signed16)(*vB).h[i*2+j]; | |
1429 | prod = a * b; | |
1430 | temp += (signed64)prod; | |
1431 | } | |
1432 | (*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat); | |
1433 | sat |= tempsat; | |
1434 | } | |
1435 | ALTIVEC_SET_SAT(sat); | |
1436 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); | |
1437 | ||
1438 | 0.4,6.VS,11.VA,16.VB,21.VC,26.36:VAX:av:vmsumubm %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Byte Modulo | |
1439 | int i, j; | |
1440 | unsigned32 temp; | |
1441 | unsigned16 prod, a, b; | |
1442 | for (i = 0; i < 4; i++) { | |
1443 | temp = (*vC).w[i]; | |
1444 | for (j = 0; j < 4; j++) { | |
1445 | a = (*vA).b[i*4+j]; | |
1446 | b = (*vB).b[i*4+j]; | |
1447 | prod = a * b; | |
1448 | temp += prod; | |
1449 | } | |
1450 | (*vS).w[i] = temp; | |
1451 | } | |
1452 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); | |
1453 | ||
1454 | 0.4,6.VS,11.VA,16.VB,21.VC,26.38:VAX:av:vmsumuhm %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Half Word Modulo | |
1455 | int i, j; | |
1456 | unsigned32 temp, prod, a, b; | |
1457 | for (i = 0; i < 4; i++) { | |
1458 | temp = (*vC).w[i]; | |
1459 | for (j = 0; j < 2; j++) { | |
1460 | a = (*vA).h[i*2+j]; | |
1461 | b = (*vB).h[i*2+j]; | |
1462 | prod = a * b; | |
1463 | temp += prod; | |
1464 | } | |
1465 | (*vS).w[i] = temp; | |
1466 | } | |
1467 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); | |
1468 | ||
1469 | 0.4,6.VS,11.VA,16.VB,21.VC,26.39:VAX:av:vmsumuhs %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Half Word Saturate | |
1470 | int i, j, sat, tempsat; | |
1471 | unsigned32 temp, prod, a, b; | |
1472 | sat = 0; | |
1473 | for (i = 0; i < 4; i++) { | |
1474 | temp = (*vC).w[i]; | |
1475 | for (j = 0; j < 2; j++) { | |
1476 | a = (*vA).h[i*2+j]; | |
1477 | b = (*vB).h[i*2+j]; | |
1478 | prod = a * b; | |
1479 | temp += prod; | |
1480 | } | |
1481 | (*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat); | |
1482 | sat |= tempsat; | |
1483 | } | |
1484 | ALTIVEC_SET_SAT(sat); | |
1485 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); | |
1486 | ||
1487 | ||
1488 | # | |
1489 | # Vector Multiply Even/Odd instructions, 6-101 ... 6-108 | |
1490 | # | |
1491 | ||
1492 | 0.4,6.VS,11.VA,16.VB,21.776:VX:av:vmulesb %VD, %VA, %VB:Vector Multiply Even Signed Byte | |
1493 | int i; | |
1494 | signed8 a, b; | |
1495 | signed16 prod; | |
1496 | for (i = 0; i < 8; i++) { | |
1497 | a = (*vA).b[AV_BINDEX(i*2)]; | |
1498 | b = (*vB).b[AV_BINDEX(i*2)]; | |
1499 | prod = a * b; | |
1500 | (*vS).h[AV_HINDEX(i)] = prod; | |
1501 | } | |
1502 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1503 | ||
1504 | 0.4,6.VS,11.VA,16.VB,21.840:VX:av:vmulesh %VD, %VA, %VB:Vector Multiply Even Signed Half Word | |
1505 | int i; | |
1506 | signed16 a, b; | |
1507 | signed32 prod; | |
1508 | for (i = 0; i < 4; i++) { | |
1509 | a = (*vA).h[AV_HINDEX(i*2)]; | |
1510 | b = (*vB).h[AV_HINDEX(i*2)]; | |
1511 | prod = a * b; | |
1512 | (*vS).w[i] = prod; | |
1513 | } | |
1514 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1515 | ||
1516 | 0.4,6.VS,11.VA,16.VB,21.520:VX:av:vmuleub %VD, %VA, %VB:Vector Multiply Even Unsigned Byte | |
1517 | int i; | |
1518 | unsigned8 a, b; | |
1519 | unsigned16 prod; | |
1520 | for (i = 0; i < 8; i++) { | |
1521 | a = (*vA).b[AV_BINDEX(i*2)]; | |
1522 | b = (*vB).b[AV_BINDEX(i*2)]; | |
1523 | prod = a * b; | |
1524 | (*vS).h[AV_HINDEX(i)] = prod; | |
1525 | } | |
1526 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1527 | ||
1528 | 0.4,6.VS,11.VA,16.VB,21.584:VX:av:vmuleuh %VD, %VA, %VB:Vector Multiply Even Unsigned Half Word | |
1529 | int i; | |
1530 | unsigned16 a, b; | |
1531 | unsigned32 prod; | |
1532 | for (i = 0; i < 4; i++) { | |
1533 | a = (*vA).h[AV_HINDEX(i*2)]; | |
1534 | b = (*vB).h[AV_HINDEX(i*2)]; | |
1535 | prod = a * b; | |
1536 | (*vS).w[i] = prod; | |
1537 | } | |
1538 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1539 | ||
1540 | 0.4,6.VS,11.VA,16.VB,21.264:VX:av:vmulosb %VD, %VA, %VB:Vector Multiply Odd Signed Byte | |
1541 | int i; | |
1542 | signed8 a, b; | |
1543 | signed16 prod; | |
1544 | for (i = 0; i < 8; i++) { | |
1545 | a = (*vA).b[AV_BINDEX((i*2)+1)]; | |
1546 | b = (*vB).b[AV_BINDEX((i*2)+1)]; | |
1547 | prod = a * b; | |
1548 | (*vS).h[AV_HINDEX(i)] = prod; | |
1549 | } | |
1550 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1551 | ||
1552 | 0.4,6.VS,11.VA,16.VB,21.328:VX:av:vmulosh %VD, %VA, %VB:Vector Multiply Odd Signed Half Word | |
1553 | int i; | |
1554 | signed16 a, b; | |
1555 | signed32 prod; | |
1556 | for (i = 0; i < 4; i++) { | |
1557 | a = (*vA).h[AV_HINDEX((i*2)+1)]; | |
1558 | b = (*vB).h[AV_HINDEX((i*2)+1)]; | |
1559 | prod = a * b; | |
1560 | (*vS).w[i] = prod; | |
1561 | } | |
1562 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1563 | ||
1564 | 0.4,6.VS,11.VA,16.VB,21.8:VX:av:vmuloub %VD, %VA, %VB:Vector Multiply Odd Unsigned Byte | |
1565 | int i; | |
1566 | unsigned8 a, b; | |
1567 | unsigned16 prod; | |
1568 | for (i = 0; i < 8; i++) { | |
1569 | a = (*vA).b[AV_BINDEX((i*2)+1)]; | |
1570 | b = (*vB).b[AV_BINDEX((i*2)+1)]; | |
1571 | prod = a * b; | |
1572 | (*vS).h[AV_HINDEX(i)] = prod; | |
1573 | } | |
1574 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1575 | ||
1576 | 0.4,6.VS,11.VA,16.VB,21.72:VX:av:vmulouh %VD, %VA, %VB:Vector Multiply Odd Unsigned Half Word | |
1577 | int i; | |
1578 | unsigned16 a, b; | |
1579 | unsigned32 prod; | |
1580 | for (i = 0; i < 4; i++) { | |
1581 | a = (*vA).h[AV_HINDEX((i*2)+1)]; | |
1582 | b = (*vB).h[AV_HINDEX((i*2)+1)]; | |
1583 | prod = a * b; | |
1584 | (*vS).w[i] = prod; | |
1585 | } | |
1586 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1587 | ||
1588 | ||
1589 | # | |
1590 | # Vector Negative Multiply-Subtract instruction, 6-109 | |
1591 | # | |
1592 | ||
1593 | 0.4,6.VS,11.VA,16.VB,21.VC,26.47:VX:av:vnmsubfp %VD, %VA, %VB, %VC:Vector Negative Multiply-Subtract Floating Point | |
1594 | int i; | |
1595 | unsigned32 f; | |
1596 | sim_fpu a, b, c, d, i1, i2; | |
1597 | for (i = 0; i < 4; i++) { | |
1598 | sim_fpu_32to (&a, (*vA).w[i]); | |
1599 | sim_fpu_32to (&b, (*vB).w[i]); | |
1600 | sim_fpu_32to (&c, (*vC).w[i]); | |
1601 | sim_fpu_mul (&i1, &a, &c); | |
1602 | sim_fpu_sub (&i2, &i1, &b); | |
1603 | sim_fpu_neg (&d, &i2); | |
1604 | sim_fpu_to32 (&f, &d); | |
1605 | (*vS).w[i] = f; | |
1606 | } | |
1607 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); | |
1608 | ||
1609 | ||
1610 | # | |
1611 | # Vector Logical OR instructions, 6-110, 6-111, 6-177 | |
1612 | # | |
1613 | ||
1614 | 0.4,6.VS,11.VA,16.VB,21.1284:VX:av:vnor %VD, %VA, %VB:Vector Logical NOR | |
1615 | int i; | |
1616 | for (i = 0; i < 4; i++) | |
1617 | (*vS).w[i] = ~((*vA).w[i] | (*vB).w[i]); | |
1618 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1619 | ||
1620 | 0.4,6.VS,11.VA,16.VB,21.1156:VX:av:vor %VD, %VA, %VB:Vector Logical OR | |
1621 | int i; | |
1622 | for (i = 0; i < 4; i++) | |
1623 | (*vS).w[i] = (*vA).w[i] | (*vB).w[i]; | |
1624 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1625 | ||
1626 | 0.4,6.VS,11.VA,16.VB,21.1220:VX:av:vxor %VD, %VA, %VB:Vector Logical XOR | |
1627 | int i; | |
1628 | for (i = 0; i < 4; i++) | |
1629 | (*vS).w[i] = (*vA).w[i] ^ (*vB).w[i]; | |
1630 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1631 | ||
1632 | ||
1633 | # | |
1634 | # Vector Permute instruction, 6-112 | |
1635 | # | |
1636 | ||
1637 | 0.4,6.VS,11.VA,16.VB,21.VC,26.43:VX:av:vperm %VD, %VA, %VB, %VC:Vector Permute | |
1638 | int i, who; | |
1639 | for (i = 0; i < 16; i++) { | |
1640 | who = (*vC).b[AV_BINDEX(i)] & 0x1f; | |
1641 | if (who & 0x10) | |
1642 | (*vS).b[AV_BINDEX(i)] = (*vB).b[AV_BINDEX(who & 0xf)]; | |
1643 | else | |
1644 | (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(who & 0xf)]; | |
1645 | } | |
1646 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); | |
1647 | ||
1648 | ||
1649 | # | |
1650 | # Vector Pack instructions, 6-113 ... 6-121 | |
1651 | # | |
1652 | ||
1653 | 0.4,6.VS,11.VA,16.VB,21.782:VX:av:vpkpx %VD, %VA, %VB:Vector Pack Pixel32 | |
1654 | int i; | |
1655 | for (i = 0; i < 4; i++) { | |
1656 | (*vS).h[AV_HINDEX(i+4)] = ((((*vB).w[i]) >> 9) & 0xfc00) | |
1657 | | ((((*vB).w[i]) >> 6) & 0x03e0) | |
1658 | | ((((*vB).w[i]) >> 3) & 0x001f); | |
1659 | (*vS).h[AV_HINDEX(i)] = ((((*vA).w[i]) >> 9) & 0xfc00) | |
1660 | | ((((*vA).w[i]) >> 6) & 0x03e0) | |
1661 | | ((((*vA).w[i]) >> 3) & 0x001f); | |
1662 | } | |
1663 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1664 | ||
1665 | 0.4,6.VS,11.VA,16.VB,21.398:VX:av:vpkshss %VD, %VA, %VB:Vector Pack Signed Half Word Signed Saturate | |
1666 | int i, sat, tempsat; | |
1667 | signed16 temp; | |
1668 | sat = 0; | |
1669 | for (i = 0; i < 16; i++) { | |
1670 | if (i < 8) | |
1671 | temp = (*vA).h[AV_HINDEX(i)]; | |
1672 | else | |
1673 | temp = (*vB).h[AV_HINDEX(i-8)]; | |
1674 | (*vS).b[AV_BINDEX(i)] = altivec_signed_saturate_8(temp, &tempsat); | |
1675 | sat |= tempsat; | |
1676 | } | |
1677 | ALTIVEC_SET_SAT(sat); | |
1678 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1679 | ||
1680 | 0.4,6.VS,11.VA,16.VB,21.270:VX:av:vpkshus %VD, %VA, %VB:Vector Pack Signed Half Word Unsigned Saturate | |
1681 | int i, sat, tempsat; | |
1682 | signed16 temp; | |
1683 | sat = 0; | |
1684 | for (i = 0; i < 16; i++) { | |
1685 | if (i < 8) | |
1686 | temp = (*vA).h[AV_HINDEX(i)]; | |
1687 | else | |
1688 | temp = (*vB).h[AV_HINDEX(i-8)]; | |
1689 | (*vS).b[AV_BINDEX(i)] = altivec_unsigned_saturate_8(temp, &tempsat); | |
1690 | sat |= tempsat; | |
1691 | } | |
1692 | ALTIVEC_SET_SAT(sat); | |
1693 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1694 | ||
1695 | 0.4,6.VS,11.VA,16.VB,21.462:VX:av:vpkswss %VD, %VA, %VB:Vector Pack Signed Word Signed Saturate | |
1696 | int i, sat, tempsat; | |
1697 | signed32 temp; | |
1698 | sat = 0; | |
1699 | for (i = 0; i < 8; i++) { | |
1700 | if (i < 4) | |
1701 | temp = (*vA).w[i]; | |
1702 | else | |
1703 | temp = (*vB).w[i-4]; | |
1704 | (*vS).h[AV_HINDEX(i)] = altivec_signed_saturate_16(temp, &tempsat); | |
1705 | sat |= tempsat; | |
1706 | } | |
1707 | ALTIVEC_SET_SAT(sat); | |
1708 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1709 | ||
1710 | 0.4,6.VS,11.VA,16.VB,21.334:VX:av:vpkswus %VD, %VA, %VB:Vector Pack Signed Word Unsigned Saturate | |
1711 | int i, sat, tempsat; | |
1712 | signed32 temp; | |
1713 | sat = 0; | |
1714 | for (i = 0; i < 8; i++) { | |
1715 | if (i < 4) | |
1716 | temp = (*vA).w[i]; | |
1717 | else | |
1718 | temp = (*vB).w[i-4]; | |
1719 | (*vS).h[AV_HINDEX(i)] = altivec_unsigned_saturate_16(temp, &tempsat); | |
1720 | sat |= tempsat; | |
1721 | } | |
1722 | ALTIVEC_SET_SAT(sat); | |
1723 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1724 | ||
1725 | 0.4,6.VS,11.VA,16.VB,21.14:VX:av:vpkuhum %VD, %VA, %VB:Vector Pack Unsigned Half Word Unsigned Modulo | |
1726 | int i; | |
1727 | for (i = 0; i < 16; i++) | |
1728 | if (i < 8) | |
1729 | (*vS).b[AV_BINDEX(i)] = (*vA).h[AV_HINDEX(i)]; | |
1730 | else | |
1731 | (*vS).b[AV_BINDEX(i)] = (*vB).h[AV_HINDEX(i-8)]; | |
1732 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1733 | ||
1734 | 0.4,6.VS,11.VA,16.VB,21.142:VX:av:vpkuhus %VD, %VA, %VB:Vector Pack Unsigned Half Word Unsigned Saturate | |
1735 | int i, sat, tempsat; | |
1736 | signed16 temp; | |
1737 | sat = 0; | |
1738 | for (i = 0; i < 16; i++) { | |
1739 | if (i < 8) | |
1740 | temp = (*vA).h[AV_HINDEX(i)]; | |
1741 | else | |
1742 | temp = (*vB).h[AV_HINDEX(i-8)]; | |
1743 | /* force positive in signed16, ok as we'll toss the bit away anyway */ | |
1744 | temp &= ~0x8000; | |
1745 | (*vS).b[AV_BINDEX(i)] = altivec_unsigned_saturate_8(temp, &tempsat); | |
1746 | sat |= tempsat; | |
1747 | } | |
1748 | ALTIVEC_SET_SAT(sat); | |
1749 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1750 | ||
1751 | 0.4,6.VS,11.VA,16.VB,21.78:VX:av:vpkuwum %VD, %VA, %VB:Vector Pack Unsigned Word Unsigned Modulo | |
1752 | int i; | |
1753 | for (i = 0; i < 8; i++) | |
1754 | if (i < 8) | |
1755 | (*vS).h[AV_HINDEX(i)] = (*vA).w[i]; | |
1756 | else | |
1757 | (*vS).h[AV_HINDEX(i)] = (*vB).w[i-8]; | |
1758 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1759 | ||
1760 | 0.4,6.VS,11.VA,16.VB,21.206:VX:av:vpkuwus %VD, %VA, %VB:Vector Pack Unsigned Word Unsigned Saturate | |
1761 | int i, sat, tempsat; | |
1762 | signed32 temp; | |
1763 | sat = 0; | |
1764 | for (i = 0; i < 8; i++) { | |
1765 | if (i < 4) | |
1766 | temp = (*vA).w[i]; | |
1767 | else | |
1768 | temp = (*vB).w[i-4]; | |
1769 | /* force positive in signed32, ok as we'll toss the bit away anyway */ | |
1770 | temp &= ~0x80000000; | |
1771 | (*vS).h[AV_HINDEX(i)] = altivec_unsigned_saturate_16(temp, &tempsat); | |
1772 | sat |= tempsat; | |
1773 | } | |
1774 | ALTIVEC_SET_SAT(sat); | |
1775 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1776 | ||
1777 | ||
1778 | # | |
1779 | # Vector Reciprocal instructions, 6-122, 6-123, 6-131 | |
1780 | # | |
1781 | ||
1782 | 0.4,6.VS,11.0,16.VB,21.266:VX:av:vrefp %VD, %VB:Vector Reciprocal Estimate Floating Point | |
1783 | int i; | |
1784 | unsigned32 f; | |
1785 | sim_fpu op, d; | |
1786 | for (i = 0; i < 4; i++) { | |
1787 | sim_fpu_32to (&op, (*vB).w[i]); | |
1788 | sim_fpu_div (&d, &sim_fpu_one, &op); | |
1789 | sim_fpu_to32 (&f, &d); | |
1790 | (*vS).w[i] = f; | |
1791 | } | |
1792 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
1793 | ||
1794 | 0.4,6.VS,11.0,16.VB,21.330:VX:av:vrsqrtefp %VD, %VB:Vector Reciprocal Square Root Estimate Floating Point | |
1795 | int i; | |
1796 | unsigned32 f; | |
1797 | sim_fpu op, i1, one, d; | |
1798 | for (i = 0; i < 4; i++) { | |
1799 | sim_fpu_32to (&op, (*vB).w[i]); | |
1800 | sim_fpu_sqrt (&i1, &op); | |
1801 | sim_fpu_div (&d, &sim_fpu_one, &i1); | |
1802 | sim_fpu_to32 (&f, &d); | |
1803 | (*vS).w[i] = f; | |
1804 | } | |
1805 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
1806 | ||
1807 | ||
1808 | # | |
1809 | # Vector Round instructions, 6-124 ... 6-127 | |
1810 | # | |
1811 | ||
1812 | 0.4,6.VS,11.0,16.VB,21.714:VX:av:vrfim %VD, %VB:Vector Round to Floating-Point Integer towards Minus Infinity | |
1813 | int i; | |
1814 | unsigned32 f; | |
1815 | sim_fpu op; | |
1816 | for (i = 0; i < 4; i++) { | |
1817 | sim_fpu_32to (&op, (*vB).w[i]); | |
1818 | sim_fpu_round_32(&op, sim_fpu_round_down, sim_fpu_denorm_default); | |
1819 | sim_fpu_to32 (&f, &op); | |
1820 | (*vS).w[i] = f; | |
1821 | } | |
1822 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
1823 | ||
1824 | 0.4,6.VS,11.0,16.VB,21.522:VX:av:vrfin %VD, %VB:Vector Round to Floating-Point Integer Nearest | |
1825 | int i; | |
1826 | unsigned32 f; | |
1827 | sim_fpu op; | |
1828 | for (i = 0; i < 4; i++) { | |
1829 | sim_fpu_32to (&op, (*vB).w[i]); | |
1830 | sim_fpu_round_32(&op, sim_fpu_round_near, sim_fpu_denorm_default); | |
1831 | sim_fpu_to32 (&f, &op); | |
1832 | (*vS).w[i] = f; | |
1833 | } | |
1834 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
1835 | ||
1836 | 0.4,6.VS,11.0,16.VB,21.650:VX:av:vrfip %VD, %VB:Vector Round to Floating-Point Integer towards Plus Infinity | |
1837 | int i; | |
1838 | unsigned32 f; | |
1839 | sim_fpu op; | |
1840 | for (i = 0; i < 4; i++) { | |
1841 | sim_fpu_32to (&op, (*vB).w[i]); | |
1842 | sim_fpu_round_32(&op, sim_fpu_round_up, sim_fpu_denorm_default); | |
1843 | sim_fpu_to32 (&f, &op); | |
1844 | (*vS).w[i] = f; | |
1845 | } | |
1846 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
1847 | ||
1848 | 0.4,6.VS,11.0,16.VB,21.586:VX:av:vrfiz %VD, %VB:Vector Round to Floating-Point Integer towards Zero | |
1849 | int i; | |
1850 | unsigned32 f; | |
1851 | sim_fpu op; | |
1852 | for (i = 0; i < 4; i++) { | |
1853 | sim_fpu_32to (&op, (*vB).w[i]); | |
1854 | sim_fpu_round_32(&op, sim_fpu_round_zero, sim_fpu_denorm_default); | |
1855 | sim_fpu_to32 (&f, &op); | |
1856 | (*vS).w[i] = f; | |
1857 | } | |
1858 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
1859 | ||
1860 | ||
1861 | # | |
1862 | # Vector Rotate Left instructions, 6-128 ... 6-130 | |
1863 | # | |
1864 | ||
1865 | 0.4,6.VS,11.VA,16.VB,21.4:VX:av:vrlb %VD, %VA, %VB:Vector Rotate Left Integer Byte | |
1866 | int i; | |
1867 | unsigned16 temp; | |
1868 | for (i = 0; i < 16; i++) { | |
1869 | temp = (unsigned16)(*vA).b[i] << (((*vB).b[i]) & 7); | |
1870 | (*vS).b[i] = (temp & 0xff) | ((temp >> 8) & 0xff); | |
1871 | } | |
1872 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1873 | ||
1874 | 0.4,6.VS,11.VA,16.VB,21.68:VX:av:vrlh %VD, %VA, %VB:Vector Rotate Left Integer Half Word | |
1875 | int i; | |
1876 | unsigned32 temp; | |
1877 | for (i = 0; i < 8; i++) { | |
1878 | temp = (unsigned32)(*vA).h[i] << (((*vB).h[i]) & 0xf); | |
1879 | (*vS).h[i] = (temp & 0xffff) | ((temp >> 16) & 0xffff); | |
1880 | } | |
1881 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1882 | ||
1883 | 0.4,6.VS,11.VA,16.VB,21.132:VX:av:vrlw %VD, %VA, %VB:Vector Rotate Left Integer Word | |
1884 | int i; | |
1885 | unsigned64 temp; | |
1886 | for (i = 0; i < 4; i++) { | |
1887 | temp = (unsigned64)(*vA).w[i] << (((*vB).w[i]) & 0x1f); | |
1888 | (*vS).w[i] = (temp & 0xffffffff) | ((temp >> 32) & 0xffffffff); | |
1889 | } | |
1890 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1891 | ||
1892 | ||
1893 | # | |
1894 | # Vector Conditional Select instruction, 6-133 | |
1895 | # | |
1896 | ||
1897 | 0.4,6.VS,11.VA,16.VB,21.VC,26.42:VAX:av:vsel %VD, %VA, %VB, %VC:Vector Conditional Select | |
1898 | int i; | |
1899 | unsigned32 c; | |
1900 | for (i = 0; i < 4; i++) { | |
1901 | c = (*vC).w[i]; | |
1902 | (*vS).w[i] = ((*vB).w[i] & c) | ((*vA).w[i] & ~c); | |
1903 | } | |
1904 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); | |
1905 | ||
1906 | # | |
1907 | # Vector Shift Left instructions, 6-134 ... 6-139 | |
1908 | # | |
1909 | ||
1910 | 0.4,6.VS,11.VA,16.VB,21.452:VX:av:vsl %VD, %VA, %VB:Vector Shift Left | |
1911 | int sh, i, j, carry, new_carry; | |
1912 | sh = (*vB).b[0] & 7; /* don't bother checking everything */ | |
1913 | carry = 0; | |
1914 | for (j = 3; j >= 0; j--) { | |
1915 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1916 | i = j; | |
1917 | else | |
1918 | i = (j + 2) % 4; | |
1919 | new_carry = (*vA).w[i] >> (32 - sh); | |
1920 | (*vS).w[i] = ((*vA).w[i] << sh) | carry; | |
1921 | carry = new_carry; | |
1922 | } | |
1923 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1924 | ||
1925 | 0.4,6.VS,11.VA,16.VB,21.260:VX:av:vslb %VD, %VA, %VB:Vector Shift Left Integer Byte | |
1926 | int i, sh; | |
1927 | for (i = 0; i < 16; i++) { | |
1928 | sh = ((*vB).b[i]) & 7; | |
1929 | (*vS).b[i] = (*vA).b[i] << sh; | |
1930 | } | |
1931 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1932 | ||
1933 | 0.4,6.VS,11.VA,16.VB,21.0,22.SH,26.44:VX:av:vsldol %VD, %VA, %VB:Vector Shift Left Double by Octet Immediate | |
1934 | int i, j; | |
1935 | for (j = 0, i = SH; i < 16; i++) | |
1936 | (*vS).b[j++] = (*vA).b[i]; | |
1937 | for (i = 0; i < SH; i++) | |
1938 | (*vS).b[j++] = (*vB).b[i]; | |
1939 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1940 | ||
1941 | 0.4,6.VS,11.VA,16.VB,21.324:VX:av:vslh %VD, %VA, %VB:Vector Shift Left Half Word | |
1942 | int i, sh; | |
1943 | for (i = 0; i < 8; i++) { | |
1944 | sh = ((*vB).h[i]) & 0xf; | |
1945 | (*vS).h[i] = (*vA).h[i] << sh; | |
1946 | } | |
1947 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1948 | ||
1949 | 0.4,6.VS,11.VA,16.VB,21.1036:VX:av:vslo %VD, %VA, %VB:Vector Shift Left by Octet | |
1950 | int i, sh; | |
1951 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1952 | sh = ((*vB).b[AV_BINDEX(15)] >> 3) & 0xf; | |
1953 | else | |
1954 | sh = ((*vB).b[AV_BINDEX(0)] >> 3) & 0xf; | |
1955 | for (i = 0; i < 16; i++) { | |
1956 | if (15 - i > sh) | |
1957 | (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(i + sh)]; | |
1958 | else | |
1959 | (*vS).b[AV_BINDEX(i)] = 0; | |
1960 | } | |
1961 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1962 | ||
1963 | 0.4,6.VS,11.VA,16.VB,21.388:VX:av:vslw %VD, %VA, %VB:Vector Shift Left Integer Word | |
1964 | int i, sh; | |
1965 | for (i = 0; i < 4; i++) { | |
1966 | sh = ((*vB).w[i]) & 0x1f; | |
1967 | (*vS).w[i] = (*vA).w[i] << sh; | |
1968 | } | |
1969 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
1970 | ||
1971 | ||
1972 | # | |
1973 | # Vector Splat instructions, 6-140 ... 6-145 | |
1974 | # | |
1975 | ||
1976 | 0.4,6.VS,11.UIMM,16.VB,21.524:VX:av:vspltb %VD, %VB, %UIMM:Vector Splat Byte | |
1977 | int i; | |
1978 | unsigned8 b; | |
1979 | b = (*vB).b[AV_BINDEX(UIMM & 0xf)]; | |
1980 | for (i = 0; i < 16; i++) | |
1981 | (*vS).b[i] = b; | |
1982 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
1983 | ||
1984 | 0.4,6.VS,11.UIMM,16.VB,21.588:VX:av:vsplth %VD, %VB, %UIMM:Vector Splat Half Word | |
1985 | int i; | |
1986 | unsigned16 h; | |
1987 | h = (*vB).h[AV_HINDEX(UIMM & 0x7)]; | |
1988 | for (i = 0; i < 8; i++) | |
1989 | (*vS).h[i] = h; | |
1990 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
1991 | ||
1992 | 0.4,6.VS,11.SIMM,16.0,21.780:VX:av:vspltisb %VD, %SIMM:Vector Splat Immediate Signed Byte | |
1993 | int i; | |
1994 | signed8 b = SIMM; | |
1995 | /* manual 5-bit signed extension */ | |
1996 | if (b & 0x10) | |
1997 | b -= 0x20; | |
1998 | for (i = 0; i < 16; i++) | |
1999 | (*vS).b[i] = b; | |
2000 | PPC_INSN_VR(VS_BITMASK, 0); | |
2001 | ||
2002 | 0.4,6.VS,11.SIMM,16.0,21.844:VX:av:vspltish %VD, %SIMM:Vector Splat Immediate Signed Half Word | |
2003 | int i; | |
2004 | signed16 h = SIMM; | |
2005 | /* manual 5-bit signed extension */ | |
2006 | if (h & 0x10) | |
2007 | h -= 0x20; | |
2008 | for (i = 0; i < 8; i++) | |
2009 | (*vS).h[i] = h; | |
2010 | PPC_INSN_VR(VS_BITMASK, 0); | |
2011 | ||
2012 | 0.4,6.VS,11.SIMM,16.0,21.908:VX:av:vspltisw %VD, %SIMM:Vector Splat Immediate Signed Word | |
2013 | int i; | |
2014 | signed32 w = SIMM; | |
2015 | /* manual 5-bit signed extension */ | |
2016 | if (w & 0x10) | |
2017 | w -= 0x20; | |
2018 | for (i = 0; i < 4; i++) | |
2019 | (*vS).w[i] = w; | |
2020 | PPC_INSN_VR(VS_BITMASK, 0); | |
2021 | ||
2022 | 0.4,6.VS,11.UIMM,16.VB,21.652:VX:av:vspltw %VD, %VB, %UIMM:Vector Splat Word | |
2023 | int i; | |
2024 | unsigned32 w; | |
2025 | w = (*vB).w[UIMM & 0x3]; | |
2026 | for (i = 0; i < 4; i++) | |
2027 | (*vS).w[i] = w; | |
2028 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
2029 | ||
2030 | ||
2031 | # | |
2032 | # Vector Shift Right instructions, 6-146 ... 6-154 | |
2033 | # | |
2034 | ||
2035 | 0.4,6.VS,11.VA,16.VB,21.708:VX:av:vsr %VD, %VA, %VB:Vector Shift Right | |
2036 | int sh, i, j, carry, new_carry; | |
2037 | sh = (*vB).b[0] & 7; /* don't bother checking everything */ | |
2038 | carry = 0; | |
2039 | for (j = 0; j < 4; j++) { | |
2040 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) | |
2041 | i = j; | |
2042 | else | |
2043 | i = (j + 2) % 4; | |
2044 | new_carry = (*vA).w[i] << (32 - sh); | |
2045 | (*vS).w[i] = ((*vA).w[i] >> sh) | carry; | |
2046 | carry = new_carry; | |
2047 | } | |
2048 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2049 | ||
2050 | 0.4,6.VS,11.VA,16.VB,21.772:VX:av:vsrab %VD, %VA, %VB:Vector Shift Right Algebraic Byte | |
2051 | int i, sh; | |
2052 | signed16 a; | |
2053 | for (i = 0; i < 16; i++) { | |
2054 | sh = ((*vB).b[i]) & 7; | |
2055 | a = (signed16)(signed8)(*vA).b[i]; | |
2056 | (*vS).b[i] = (a >> sh) & 0xff; | |
2057 | } | |
2058 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2059 | ||
2060 | 0.4,6.VS,11.VA,16.VB,21.836:VX:av:vsrah %VD, %VA, %VB:Vector Shift Right Algebraic Half Word | |
2061 | int i, sh; | |
2062 | signed32 a; | |
2063 | for (i = 0; i < 8; i++) { | |
2064 | sh = ((*vB).h[i]) & 0xf; | |
2065 | a = (signed32)(signed16)(*vA).h[i]; | |
2066 | (*vS).h[i] = (a >> sh) & 0xffff; | |
2067 | } | |
2068 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2069 | ||
2070 | 0.4,6.VS,11.VA,16.VB,21.900:VX:av:vsraw %VD, %VA, %VB:Vector Shift Right Algebraic Word | |
2071 | int i, sh; | |
2072 | signed64 a; | |
2073 | for (i = 0; i < 4; i++) { | |
2074 | sh = ((*vB).w[i]) & 0xf; | |
2075 | a = (signed64)(signed32)(*vA).w[i]; | |
2076 | (*vS).w[i] = (a >> sh) & 0xffffffff; | |
2077 | } | |
2078 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2079 | ||
2080 | 0.4,6.VS,11.VA,16.VB,21.516:VX:av:vsrb %VD, %VA, %VB:Vector Shift Right Byte | |
2081 | int i, sh; | |
2082 | for (i = 0; i < 16; i++) { | |
2083 | sh = ((*vB).b[i]) & 7; | |
2084 | (*vS).b[i] = (*vA).b[i] >> sh; | |
2085 | } | |
2086 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2087 | ||
2088 | 0.4,6.VS,11.VA,16.VB,21.580:VX:av:vsrh %VD, %VA, %VB:Vector Shift Right Half Word | |
2089 | int i, sh; | |
2090 | for (i = 0; i < 8; i++) { | |
2091 | sh = ((*vB).h[i]) & 0xf; | |
2092 | (*vS).h[i] = (*vA).h[i] >> sh; | |
2093 | } | |
2094 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2095 | ||
2096 | 0.4,6.VS,11.VA,16.VB,21.1100:VX:av:vsro %VD, %VA, %VB:Vector Shift Right Octet | |
2097 | int i, sh; | |
2098 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) | |
2099 | sh = ((*vB).b[AV_BINDEX(15)] >> 3) & 0xf; | |
2100 | else | |
2101 | sh = ((*vB).b[AV_BINDEX(0)] >> 3) & 0xf; | |
2102 | for (i = 0; i < 16; i++) { | |
2103 | if (i < sh) | |
2104 | (*vS).b[AV_BINDEX(i)] = 0; | |
2105 | else | |
2106 | (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(i - sh)]; | |
2107 | } | |
2108 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2109 | ||
2110 | 0.4,6.VS,11.VA,16.VB,21.644:VX:av:vsrw %VD, %VA, %VB:Vector Shift Right Word | |
2111 | int i, sh; | |
2112 | for (i = 0; i < 4; i++) { | |
2113 | sh = ((*vB).w[i]) & 0x1f; | |
2114 | (*vS).w[i] = (*vA).w[i] >> sh; | |
2115 | } | |
2116 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2117 | ||
2118 | ||
2119 | # | |
2120 | # Vector Subtract instructions, 6-155 ... 6-165 | |
2121 | # | |
2122 | ||
2123 | 0.4,6.VS,11.VA,16.VB,21.1408:VX:av:vsubcuw %VD, %VA, %VB:Vector Subtract Carryout Unsigned Word | |
2124 | int i; | |
2125 | signed64 temp, a, b; | |
2126 | for (i = 0; i < 4; i++) { | |
2127 | a = (signed64)(unsigned32)(*vA).w[i]; | |
2128 | b = (signed64)(unsigned32)(*vB).w[i]; | |
2129 | temp = a - b; | |
2130 | (*vS).w[i] = ~(temp >> 32) & 1; | |
2131 | } | |
2132 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2133 | ||
2134 | 0.4,6.VS,11.VA,16.VB,21.74:VX:av:vsubfp %VD, %VA, %VB:Vector Subtract Floating Point | |
2135 | int i; | |
2136 | unsigned32 f; | |
2137 | sim_fpu a, b, d; | |
2138 | for (i = 0; i < 4; i++) { | |
2139 | sim_fpu_32to (&a, (*vA).w[i]); | |
2140 | sim_fpu_32to (&b, (*vB).w[i]); | |
2141 | sim_fpu_sub (&d, &a, &b); | |
2142 | sim_fpu_to32 (&f, &d); | |
2143 | (*vS).w[i] = f; | |
2144 | } | |
2145 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2146 | ||
2147 | 0.4,6.VS,11.VA,16.VB,21.1792:VX:av:vsubsbs %VD, %VA, %VB:Vector Subtract Signed Byte Saturate | |
2148 | int i, sat, tempsat; | |
2149 | signed16 temp; | |
2150 | sat = 0; | |
2151 | for (i = 0; i < 16; i++) { | |
2152 | temp = (signed16)(signed8)(*vA).b[i] - (signed16)(signed8)(*vB).b[i]; | |
2153 | (*vS).b[i] = altivec_signed_saturate_8(temp, &tempsat); | |
2154 | sat |= tempsat; | |
2155 | } | |
2156 | ALTIVEC_SET_SAT(sat); | |
2157 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2158 | ||
2159 | 0.4,6.VS,11.VA,16.VB,21.1856:VX:av:vsubshs %VD, %VA, %VB:Vector Subtract Signed Half Word Saturate | |
2160 | int i, sat, tempsat; | |
2161 | signed32 temp; | |
2162 | sat = 0; | |
2163 | for (i = 0; i < 8; i++) { | |
2164 | temp = (signed32)(signed16)(*vA).h[i] - (signed32)(signed16)(*vB).h[i]; | |
2165 | (*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat); | |
2166 | sat |= tempsat; | |
2167 | } | |
2168 | ALTIVEC_SET_SAT(sat); | |
2169 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2170 | ||
2171 | 0.4,6.VS,11.VA,16.VB,21.1920:VX:av:vsubsws %VD, %VA, %VB:Vector Subtract Signed Word Saturate | |
2172 | int i, sat, tempsat; | |
2173 | signed64 temp; | |
2174 | sat = 0; | |
2175 | for (i = 0; i < 4; i++) { | |
2176 | temp = (signed64)(signed32)(*vA).w[i] - (signed64)(signed32)(*vB).w[i]; | |
2177 | (*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat); | |
2178 | sat |= tempsat; | |
2179 | } | |
2180 | ALTIVEC_SET_SAT(sat); | |
2181 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2182 | ||
2183 | 0.4,6.VS,11.VA,16.VB,21.1024:VX:av:vsububm %VD, %VA, %VB:Vector Subtract Unsigned Byte Modulo | |
2184 | int i; | |
2185 | for (i = 0; i < 16; i++) | |
2186 | (*vS).b[i] = (*vA).b[i] - (*vB).b[i]; | |
2187 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2188 | ||
2189 | 0.4,6.VS,11.VA,16.VB,21.1536:VX:av:vsububs %VD, %VA, %VB:Vector Subtract Unsigned Byte Saturate | |
2190 | int i, sat, tempsat; | |
2191 | signed16 temp; | |
2192 | sat = 0; | |
2193 | for (i = 0; i < 16; i++) { | |
2194 | temp = (signed16)(unsigned8)(*vA).b[i] - (signed16)(unsigned8)(*vB).b[i]; | |
2195 | (*vS).b[i] = altivec_unsigned_saturate_8(temp, &tempsat); | |
2196 | sat |= tempsat; | |
2197 | } | |
2198 | ALTIVEC_SET_SAT(sat); | |
2199 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2200 | ||
2201 | 0.4,6.VS,11.VA,16.VB,21.1088:VX:av:vsubuhm %VD, %VA, %VB:Vector Subtract Unsigned Half Word Modulo | |
2202 | int i; | |
2203 | for (i = 0; i < 8; i++) | |
2204 | (*vS).h[i] = ((*vA).h[i] - (*vB).h[i]) & 0xffff; | |
2205 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2206 | ||
2207 | 0.4,6.VS,11.VA,16.VB,21.1600:VX:av:vsubuhs %VD, %VA, %VB:Vector Subtract Unsigned Half Word Saturate | |
2208 | int i, sat, tempsat; | |
2209 | signed32 temp; | |
2210 | for (i = 0; i < 8; i++) { | |
2211 | temp = (signed32)(unsigned16)(*vA).h[i] - (signed32)(unsigned16)(*vB).h[i]; | |
2212 | (*vS).h[i] = altivec_unsigned_saturate_16(temp, &tempsat); | |
2213 | sat |= tempsat; | |
2214 | } | |
2215 | ALTIVEC_SET_SAT(sat); | |
2216 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2217 | ||
2218 | 0.4,6.VS,11.VA,16.VB,21.1152:VX:av:vsubuwm %VD, %VA, %VB:Vector Subtract Unsigned Word Modulo | |
2219 | int i; | |
2220 | for (i = 0; i < 4; i++) | |
2221 | (*vS).w[i] = (*vA).w[i] - (*vB).w[i]; | |
2222 | PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2223 | ||
2224 | 0.4,6.VS,11.VA,16.VB,21.1664:VX:av:vsubuws %VD, %VA, %VB:Vector Subtract Unsigned Word Saturate | |
2225 | int i, sat, tempsat; | |
2226 | signed64 temp; | |
2227 | for (i = 0; i < 4; i++) { | |
2228 | temp = (signed64)(unsigned32)(*vA).w[i] - (signed64)(unsigned32)(*vB).w[i]; | |
2229 | (*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat); | |
2230 | sat |= tempsat; | |
2231 | } | |
2232 | ALTIVEC_SET_SAT(sat); | |
2233 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2234 | ||
2235 | ||
2236 | # | |
2237 | # Vector Sum instructions, 6-166 ... 6-170 | |
2238 | # | |
2239 | ||
2240 | 0.4,6.VS,11.VA,16.VB,21.1928:VX:av:vsumsws %VD, %VA, %VB:Vector Sum Across Signed Word Saturate | |
2241 | int i, sat; | |
2242 | signed64 temp; | |
2243 | temp = (signed64)(signed32)(*vB).w[3]; | |
2244 | for (i = 0; i < 4; i++) | |
2245 | temp += (signed64)(signed32)(*vA).w[i]; | |
2246 | (*vS).w[3] = altivec_signed_saturate_32(temp, &sat); | |
2247 | (*vS).w[0] = (*vS).w[1] = (*vS).w[2] = 0; | |
2248 | ALTIVEC_SET_SAT(sat); | |
2249 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2250 | ||
2251 | 0.4,6.VS,11.VA,16.VB,21.1672:VX:av:vsum2sws %VD, %VA, %VB:Vector Sum Across Partial (1/2) Signed Word Saturate | |
2252 | int i, j, sat, tempsat; | |
2253 | signed64 temp; | |
2254 | for (j = 0; j < 4; j += 2) { | |
2255 | temp = (signed64)(signed32)(*vB).w[j+1]; | |
2256 | temp += (signed64)(signed32)(*vA).w[j] + (signed64)(signed32)(*vA).w[j+1]; | |
2257 | (*vS).w[j+1] = altivec_signed_saturate_32(temp, &tempsat); | |
2258 | sat |= tempsat; | |
2259 | } | |
2260 | (*vS).w[0] = (*vS).w[2] = 0; | |
2261 | ALTIVEC_SET_SAT(sat); | |
2262 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2263 | ||
2264 | 0.4,6.VS,11.VA,16.VB,21.1800:VX:av:vsum4sbs %VD, %VA, %VB:Vector Sum Across Partial (1/4) Signed Byte Saturate | |
2265 | int i, j, sat, tempsat; | |
2266 | signed64 temp; | |
2267 | for (j = 0; j < 4; j++) { | |
2268 | temp = (signed64)(signed32)(*vB).w[j]; | |
2269 | for (i = 0; i < 4; i++) | |
2270 | temp += (signed64)(signed8)(*vA).b[i+(j*4)]; | |
2271 | (*vS).w[j] = altivec_signed_saturate_32(temp, &tempsat); | |
2272 | sat |= tempsat; | |
2273 | } | |
2274 | ALTIVEC_SET_SAT(sat); | |
2275 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2276 | ||
2277 | 0.4,6.VS,11.VA,16.VB,21.1608:VX:av:vsum4shs %VD, %VA, %VB:Vector Sum Across Partial (1/4) Signed Half Word Saturate | |
2278 | int i, j, sat, tempsat; | |
2279 | signed64 temp; | |
2280 | for (j = 0; j < 4; j++) { | |
2281 | temp = (signed64)(signed32)(*vB).w[j]; | |
2282 | for (i = 0; i < 2; i++) | |
2283 | temp += (signed64)(signed16)(*vA).h[i+(j*2)]; | |
2284 | (*vS).w[j] = altivec_signed_saturate_32(temp, &tempsat); | |
2285 | sat |= tempsat; | |
2286 | } | |
2287 | ALTIVEC_SET_SAT(sat); | |
2288 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2289 | ||
2290 | 0.4,6.VS,11.VA,16.VB,21.1544:VX:av:vsum4ubs %VD, %VA, %VB:Vector Sum Across Partial (1/4) Unsigned Byte Saturate | |
2291 | int i, j, sat, tempsat; | |
2292 | signed64 utemp; | |
2293 | signed64 temp; | |
2294 | for (j = 0; j < 4; j++) { | |
2295 | utemp = (signed64)(unsigned32)(*vB).w[j]; | |
2296 | for (i = 0; i < 4; i++) | |
2297 | utemp += (signed64)(unsigned16)(*vA).b[i+(j*4)]; | |
2298 | temp = utemp; | |
2299 | (*vS).w[j] = altivec_unsigned_saturate_32(temp, &tempsat); | |
2300 | sat |= tempsat; | |
2301 | } | |
2302 | ALTIVEC_SET_SAT(sat); | |
2303 | PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); | |
2304 | ||
2305 | ||
2306 | # | |
2307 | # Vector Unpack instructions, 6-171 ... 6-176 | |
2308 | # | |
2309 | ||
2310 | 0.4,6.VS,11.0,16.VB,21.846:VX:av:vupkhpx %VD, %VB:Vector Unpack High Pixel16 | |
2311 | int i; | |
2312 | unsigned16 h; | |
2313 | for (i = 0; i < 4; i++) { | |
2314 | h = (*vB).h[AV_HINDEX(i)]; | |
2315 | (*vS).w[i] = ((h & 0x8000) ? 0xff000000 : 0) | |
2316 | | ((h & 0x7c00) << 6) | |
2317 | | ((h & 0x03e0) << 3) | |
2318 | | ((h & 0x001f)); | |
2319 | } | |
2320 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
2321 | ||
2322 | 0.4,6.VS,11.0,16.VB,21.526:VX:av:vupkhsb %VD, %VB:Vector Unpack High Signed Byte | |
2323 | int i; | |
2324 | for (i = 0; i < 8; i++) | |
2325 | (*vS).h[AV_HINDEX(i)] = (signed16)(signed8)(*vB).b[AV_BINDEX(i)]; | |
2326 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
2327 | ||
2328 | 0.4,6.VS,11.0,16.VB,21.590:VX:av:vupkhsh %VD, %VB:Vector Unpack High Signed Half Word | |
2329 | int i; | |
2330 | for (i = 0; i < 4; i++) | |
2331 | (*vS).w[i] = (signed32)(signed16)(*vB).h[AV_HINDEX(i)]; | |
2332 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
2333 | ||
2334 | 0.4,6.VS,11.0,16.VB,21.974:VX:av:vupklpx %VD, %VB:Vector Unpack Low Pixel16 | |
2335 | int i; | |
2336 | unsigned16 h; | |
2337 | for (i = 0; i < 4; i++) { | |
2338 | h = (*vB).h[AV_HINDEX(i + 4)]; | |
2339 | (*vS).w[i] = ((h & 0x8000) ? 0xff000000 : 0) | |
2340 | | ((h & 0x7c00) << 6) | |
2341 | | ((h & 0x03e0) << 3) | |
2342 | | ((h & 0x001f)); | |
2343 | } | |
2344 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
2345 | ||
2346 | 0.4,6.VS,11.0,16.VB,21.654:VX:av:vupklsb %VD, %VB:Vector Unpack Low Signed Byte | |
2347 | int i; | |
2348 | for (i = 0; i < 8; i++) | |
2349 | (*vS).h[AV_HINDEX(i)] = (signed16)(signed8)(*vB).b[AV_BINDEX(i + 8)]; | |
2350 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); | |
2351 | ||
2352 | 0.4,6.VS,11.0,16.VB,21.718:VX:av:vupklsh %VD, %VB:Vector Unpack Low Signed Half Word | |
2353 | int i; | |
2354 | for (i = 0; i < 4; i++) | |
2355 | (*vS).w[i] = (signed32)(signed16)(*vB).h[AV_HINDEX(i + 4)]; | |
2356 | PPC_INSN_VR(VS_BITMASK, VB_BITMASK); |