[deliverable/binutils-gdb.git] / sim / ppc / corefile.h

/*  This file is part of the program psim.

    Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 
    */


#ifndef _CORE_H_
#define _CORE_H_

/* basic types */

typedef struct _core core;
typedef struct _core_map core_map;

/* constructor */

core INLINE_CORE *core_create
(void);

device INLINE_CORE *core_device_create
(core *);


/* the core has three sub mappings that the more efficient
   read/write fixed quantity functions use */

core_map INLINE_CORE *core_readable
(core *memory);

core_map INLINE_CORE *core_writeable
(core *memory);

core_map INLINE_CORE *core_executable
(core *memory);


/* operators to add/remove a mapping in the core

   callback-memory:

   All access are passed onto the specified devices callback routines
   after being `translated'.  DEFAULT indicates that the specified
   memory should be called if all other mappings fail.
   
   For callback-memory, the device must be specified.

   raw-memory:

   While RAM could be implemented using the callback interface
   core instead treats it as the common case including the code
   directly in the read/write operators.

   For raw-memory, the device is ignored and the core alloc's a
   block to act as the memory.

   default-memory:

   Should, for the core, there be no defined mapping for a given
   address then the default map (if present) is called.

   For default-memory, the device must be specified. */

void INLINE_CORE core_attach
(core *map,
 attach_type attach,
 int address_space,
 access_type access,
 unsigned_word addr,
 unsigned nr_bytes, /* host limited */
 device *device); /*callback/default*/

void INLINE_CORE core_detach
(core *map,
 attach_type attach,
 int address_space,
 unsigned_word addr,
 unsigned nr_bytes, /* host limited */
 access_type access,
 device *device); /*callback/default*/


/* Variable sized read/write:

   Transfer (zero) a variable size block of data between the host and
   target (possibly byte swapping it).  Should any problems occure,
   the number of bytes actually transfered is returned. */

unsigned INLINE_CORE core_map_read_buffer
(core_map *map,
 void *buffer,
 unsigned_word addr,
 unsigned nr_bytes);

unsigned INLINE_CORE core_map_write_buffer
(core_map *map,
 const void *buffer,
 unsigned_word addr,
 unsigned nr_bytes);


/* Fixed sized read/write:

   Transfer a fixed amout of memory between the host and target.  The
   memory always being translated and the operation always aborting
   should a problem occure */

#define DECLARE_CORE_WRITE_N(N) \
void INLINE_CORE core_map_write_##N \
(core_map *map, \
 unsigned_word addr, \
 unsigned_##N val, \
 cpu *processor, \
 unsigned_word cia);

DECLARE_CORE_WRITE_N(1)
DECLARE_CORE_WRITE_N(2)
DECLARE_CORE_WRITE_N(4)
DECLARE_CORE_WRITE_N(8)
DECLARE_CORE_WRITE_N(word)

#define DECLARE_CORE_READ_N(N) \
unsigned_##N INLINE_CORE core_map_read_##N \
(core_map *map, \
 unsigned_word addr, \
 cpu *processor, \
 unsigned_word cia);

DECLARE_CORE_READ_N(1)
DECLARE_CORE_READ_N(2)
DECLARE_CORE_READ_N(4)
DECLARE_CORE_READ_N(8)
DECLARE_CORE_READ_N(word)

#endif
Commit	Line	Data
93fac324 MM	1	/* This file is part of the program psim.
	2
	3	Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
	4
	5	This program is free software; you can redistribute it and/or modify
	6	it under the terms of the GNU General Public License as published by
	7	the Free Software Foundation; either version 2 of the License, or
	8	(at your option) any later version.
	9
	10	This program is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	GNU General Public License for more details.
	14
	15	You should have received a copy of the GNU General Public License
	16	along with this program; if not, write to the Free Software
	17	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	18
	19	*/
	20
	21
	22	#ifndef _CORE_H_
	23	#define _CORE_H_
	24
	25	/* basic types */
	26
	27	typedef struct _core core;
	28	typedef struct _core_map core_map;
	29
	30	/* constructor */
	31
	32	core INLINE_CORE *core_create
	33	(void);
	34
	35	device INLINE_CORE *core_device_create
	36	(core *);
	37
	38
	39
	40	/* the core has three sub mappings that the more efficient
	41	read/write fixed quantity functions use */
	42
	43	core_map INLINE_CORE *core_readable
	44	(core *memory);
	45
	46	core_map INLINE_CORE *core_writeable
	47	(core *memory);
	48
	49	core_map INLINE_CORE *core_executable
	50	(core *memory);
	51
	52
	53
	54	/* operators to add/remove a mapping in the core
	55
	56	callback-memory:
	57
	58	All access are passed onto the specified devices callback routines
	59	after being `translated'. DEFAULT indicates that the specified
	60	memory should be called if all other mappings fail.
	61
	62	For callback-memory, the device must be specified.
	63
	64	raw-memory:
65
66	While RAM could be implemented using the callback interface
67	core instead treats it as the common case including the code
68	directly in the read/write operators.
69
70	For raw-memory, the device is ignored and the core alloc's a
71	block to act as the memory.
72
73	default-memory:
74
75	Should, for the core, there be no defined mapping for a given
76	address then the default map (if present) is called.
77
78	For default-memory, the device must be specified. */
79
80	void INLINE_CORE core_attach
81	(core *map,
82	attach_type attach,
83	int address_space,
84	access_type access,
85	unsigned_word addr,
86	unsigned nr_bytes, /* host limited */
87	device device); /callback/default*/
88
89	void INLINE_CORE core_detach
90	(core *map,
91	attach_type attach,
92	int address_space,
93	unsigned_word addr,
94	unsigned nr_bytes, /* host limited */
95	access_type access,
96	device device); /callback/default*/
97
98
99	/* Variable sized read/write:
100
101	Transfer (zero) a variable size block of data between the host and
102	target (possibly byte swapping it). Should any problems occure,
103	the number of bytes actually transfered is returned. */
104
105	unsigned INLINE_CORE core_map_read_buffer
106	(core_map *map,
107	void *buffer,
108	unsigned_word addr,
109	unsigned nr_bytes);
110
111	unsigned INLINE_CORE core_map_write_buffer
112	(core_map *map,
113	const void *buffer,
114	unsigned_word addr,
115	unsigned nr_bytes);
116
117
118	/* Fixed sized read/write:
119
120	Transfer a fixed amout of memory between the host and target. The
121	memory always being translated and the operation always aborting
122	should a problem occure */
123
124	#define DECLARE_CORE_WRITE_N(N) \
125	void INLINE_CORE core_map_write_##N \
126	(core_map *map, \
127	unsigned_word addr, \
128	unsigned_##N val, \
129	cpu *processor, \
130	unsigned_word cia);
131
132	DECLARE_CORE_WRITE_N(1)
133	DECLARE_CORE_WRITE_N(2)
134	DECLARE_CORE_WRITE_N(4)
135	DECLARE_CORE_WRITE_N(8)
136	DECLARE_CORE_WRITE_N(word)
137
138	#define DECLARE_CORE_READ_N(N) \
139	unsigned_##N INLINE_CORE core_map_read_##N \
140	(core_map *map, \
141	unsigned_word addr, \
142	cpu *processor, \
143	unsigned_word cia);
144
145	DECLARE_CORE_READ_N(1)
146	DECLARE_CORE_READ_N(2)
147	DECLARE_CORE_READ_N(4)
148	DECLARE_CORE_READ_N(8)
149	DECLARE_CORE_READ_N(word)
150
151	#endif