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8e20a3ac MM |
1 | /* This file is part of the program psim. |
2 | ||
3 | Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | ||
19 | */ | |
20 | ||
21 | ||
22 | #ifndef _CONFIG_H_ | |
23 | #define _CONFIG_H_ | |
24 | ||
25 | ||
26 | /* endianness of the host/target: | |
27 | ||
28 | If the build process is aware (at compile time) of the endianness | |
29 | of the host/target it is able to eliminate slower generic endian | |
30 | handling code. | |
31 | ||
5b4d72dd | 32 | Possible values are 0 (unknown), LITTLE_ENDIAN, BIG_ENDIAN */ |
8e20a3ac | 33 | |
5b4d72dd | 34 | #ifndef WITH_HOST_BYTE_ORDER |
8e20a3ac | 35 | #define WITH_HOST_BYTE_ORDER 0 /*unknown*/ |
5b4d72dd MM |
36 | #endif |
37 | ||
38 | #ifndef WITH_TARGET_BYTE_ORDER | |
8e20a3ac | 39 | #define WITH_TARGET_BYTE_ORDER 0 /*unknown*/ |
5b4d72dd | 40 | #endif |
8e20a3ac MM |
41 | |
42 | extern int current_host_byte_order; | |
8e20a3ac MM |
43 | #define CURRENT_HOST_BYTE_ORDER (WITH_HOST_BYTE_ORDER \ |
44 | ? WITH_HOST_BYTE_ORDER \ | |
45 | : current_host_byte_order) | |
5b4d72dd | 46 | extern int current_target_byte_order; |
8e20a3ac MM |
47 | #define CURRENT_TARGET_BYTE_ORDER (WITH_TARGET_BYTE_ORDER \ |
48 | ? WITH_TARGET_BYTE_ORDER \ | |
49 | : current_target_byte_order) | |
50 | ||
51 | ||
acb06d30 MM |
52 | /* PowerPC XOR endian. |
53 | ||
54 | In addition to the above, the simulator can support the PowerPC's | |
55 | horrible XOR endian mode. This feature makes it possible to | |
56 | control the endian mode of a processor using the MSR. */ | |
57 | ||
58 | #ifndef WITH_XOR_ENDIAN | |
59 | #define WITH_XOR_ENDIAN 8 | |
60 | #endif | |
61 | ||
62 | ||
5b4d72dd MM |
63 | /* Intel host BSWAP support: |
64 | ||
65 | Whether to use bswap on the 486 and pentiums rather than the 386 | |
66 | sequence that uses xchgb/rorl/xchgb */ | |
67 | #ifndef WITH_BSWAP | |
68 | #define WITH_BSWAP 0 | |
69 | #endif | |
70 | ||
71 | ||
8e20a3ac MM |
72 | /* SMP support: |
73 | ||
74 | Sets a limit on the number of processors that can be simulated. If | |
75 | WITH_SMP is set to zero (0), the simulator is restricted to | |
76 | suporting only on processor (and as a consequence leaves the SMP | |
5b4d72dd MM |
77 | code out of the build process). |
78 | ||
79 | The actual number of processors is taken from the device | |
80 | /options/smp@<nr-cpu> */ | |
8e20a3ac MM |
81 | |
82 | #ifndef WITH_SMP | |
acb06d30 | 83 | #define WITH_SMP 5 |
5b4d72dd MM |
84 | #endif |
85 | #if WITH_SMP | |
86 | #define MAX_NR_PROCESSORS WITH_SMP | |
87 | #else | |
88 | #define MAX_NR_PROCESSORS 1 | |
8e20a3ac MM |
89 | #endif |
90 | ||
91 | ||
92 | /* Word size of host/target: | |
93 | ||
94 | Set these according to your host and target requirements. At this | |
95 | point in time, I've only compiled (not run) for a 64bit and never | |
96 | built for a 64bit host. This will always remain a compile time | |
97 | option */ | |
98 | ||
99 | #ifndef WITH_TARGET_WORD_BITSIZE | |
100 | #define WITH_TARGET_WORD_BITSIZE 32 /* compiled only */ | |
101 | #endif | |
5b4d72dd | 102 | |
8e20a3ac MM |
103 | #ifndef WITH_HOST_WORD_BITSIZE |
104 | #define WITH_HOST_WORD_BITSIZE 32 /* 64bit ready? */ | |
105 | #endif | |
106 | ||
107 | ||
108 | /* Program environment: | |
109 | ||
a983c8f0 MM |
110 | Three environments are available - UEA (user), VEA (virtual) and |
111 | OEA (perating). The former two are environment that users would | |
112 | expect to see (VEA includes things like coherency and the time | |
113 | base) while OEA is what an operating system expects to see. By | |
8e20a3ac MM |
114 | setting these to specific values, the build process is able to |
115 | eliminate non relevent environment code | |
116 | ||
117 | CURRENT_ENVIRONMENT specifies which of vea or oea is required for | |
118 | the current runtime. */ | |
119 | ||
a983c8f0 MM |
120 | #define USER_ENVIRONMENT 1 |
121 | #define VIRTUAL_ENVIRONMENT 2 | |
122 | #define OPERATING_ENVIRONMENT 3 | |
8e20a3ac | 123 | |
5b4d72dd MM |
124 | #ifndef WITH_ENVIRONMENT |
125 | #define WITH_ENVIRONMENT 0 | |
126 | #endif | |
127 | ||
8e20a3ac MM |
128 | extern int current_environment; |
129 | #define CURRENT_ENVIRONMENT (WITH_ENVIRONMENT \ | |
130 | ? WITH_ENVIRONMENT \ | |
131 | : current_environment) | |
132 | ||
133 | ||
134 | /* Optional VEA/OEA code: | |
135 | ||
136 | The below, required for the OEA model may also be included in the | |
137 | VEA model however, as far as I can tell only make things | |
138 | slower... */ | |
139 | ||
140 | ||
141 | /* Events. Devices modeling real H/W need to be able to efficiently | |
142 | schedule things to do at known times in the future. The event | |
143 | queue implements this. Unfortunatly this adds the need to check | |
144 | for any events once each full instruction cycle. */ | |
145 | ||
a983c8f0 | 146 | #define WITH_EVENTS (WITH_ENVIRONMENT != USER_ENVIRONMENT) |
8e20a3ac MM |
147 | |
148 | ||
149 | /* Time base: | |
150 | ||
151 | The PowerPC architecture includes the addition of both a time base | |
152 | register and a decrement timer. Like events adds to the overhead | |
153 | of of some instruction cycles. */ | |
154 | ||
155 | #ifndef WITH_TIME_BASE | |
a983c8f0 | 156 | #define WITH_TIME_BASE (WITH_ENVIRONMENT != USER_ENVIRONMENT) |
8e20a3ac MM |
157 | #endif |
158 | ||
159 | ||
160 | /* Callback/Default Memory. | |
161 | ||
162 | Core includes a builtin memory type (raw_memory) that is | |
163 | implemented using an array. raw_memory does not require any | |
164 | additional functions etc. | |
165 | ||
166 | Callback memory is where the core calls a core device for the data | |
167 | it requires. | |
168 | ||
169 | Default memory is an extenstion of this where for addresses that do | |
170 | not map into either a callback or core memory range a default map | |
171 | can be used. | |
172 | ||
173 | The OEA model uses callback memory for devices and default memory | |
174 | for buses. | |
175 | ||
176 | The VEA model uses callback memory to capture `page faults'. | |
177 | ||
178 | While it may be possible to eliminate callback/default memory (and | |
179 | hence also eliminate an additional test per memory fetch) it | |
180 | probably is not worth the effort. | |
181 | ||
182 | BTW, while raw_memory could have been implemented as a callback, | |
183 | profiling has shown that there is a biger win (at least for the | |
184 | x86) in eliminating a function call for the most common | |
185 | (raw_memory) case. */ | |
186 | ||
187 | #define WITH_CALLBACK_MEMORY 1 | |
188 | ||
189 | ||
190 | /* Alignment: | |
191 | ||
192 | The PowerPC may or may not handle miss aligned transfers. An | |
193 | implementation normally handles miss aligned transfers in big | |
194 | endian mode but generates an exception in little endian mode. | |
195 | ||
196 | This model. Instead allows both little and big endian modes to | |
197 | either take exceptions or handle miss aligned transfers. | |
198 | ||
199 | If 0 is specified then for big-endian mode miss alligned accesses | |
200 | are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the | |
201 | processor will fault on them (STRICT_ALIGNMENT). */ | |
202 | ||
203 | #define NONSTRICT_ALIGNMENT 1 | |
204 | #define STRICT_ALIGNMENT 2 | |
205 | ||
206 | #ifndef WITH_ALIGNMENT | |
207 | #define WITH_ALIGNMENT 0 | |
208 | #endif | |
5b4d72dd | 209 | |
8e20a3ac MM |
210 | extern int current_alignment; |
211 | #define CURRENT_ALIGNMENT (WITH_ALIGNMENT \ | |
212 | ? WITH_ALIGNMENT \ | |
213 | : current_alignment) | |
214 | ||
215 | ||
216 | /* Floating point suport: | |
217 | ||
218 | Still under development. */ | |
219 | ||
220 | #define SOFT_FLOATING_POINT 1 | |
221 | #define HARD_FLOATING_POINT 2 | |
222 | ||
223 | #ifndef WITH_FLOATING_POINT | |
224 | #define WITH_FLOATING_POINT HARD_FLOATING_POINT | |
225 | #endif | |
226 | extern int current_floating_point; | |
227 | #define CURRENT_FLOATING_POINT (WITH_FLOATING_POINT \ | |
228 | ? WITH_FLOATING_POINT \ | |
229 | : current_floating_point) | |
230 | ||
231 | ||
232 | /* Debugging: | |
233 | ||
234 | Control the inclusion of debugging code. */ | |
235 | ||
236 | /* Include the tracing code. Disabling this eliminates all tracing | |
237 | code */ | |
238 | ||
239 | #ifndef WITH_TRACE | |
240 | #define WITH_TRACE 1 | |
241 | #endif | |
242 | ||
243 | /* include code that checks assertions scattered through out the | |
244 | program */ | |
245 | ||
246 | #ifndef WITH_ASSERT | |
247 | #define WITH_ASSERT 1 | |
248 | #endif | |
249 | ||
28816f45 MM |
250 | /* Whether to check instructions for reserved bits being set */ |
251 | ||
252 | #ifndef WITH_RESERVED_BITS | |
253 | #define WITH_RESERVED_BITS 1 | |
254 | #endif | |
255 | ||
5b4d72dd | 256 | /* include monitoring code */ |
8e20a3ac | 257 | |
5b4d72dd MM |
258 | #define MONITOR_INSTRUCTION_ISSUE 1 |
259 | #define MONITOR_LOAD_STORE_UNIT 2 | |
260 | #ifndef WITH_MON | |
261 | #define WITH_MON (MONITOR_LOAD_STORE_UNIT \ | |
262 | | MONITOR_INSTRUCTION_ISSUE) | |
8e20a3ac MM |
263 | #endif |
264 | ||
28816f45 MM |
265 | /* Current CPU model (models are in the generated models.h include file) */ |
266 | #ifndef WITH_MODEL | |
267 | #define WITH_MODEL 0 | |
268 | #endif | |
269 | ||
270 | #define CURRENT_MODEL (WITH_MODEL \ | |
271 | ? WITH_MODEL \ | |
272 | : current_model) | |
273 | ||
274 | #ifndef WITH_DEFAULT_MODEL | |
275 | #define WITH_DEFAULT_MODEL DEFAULT_MODEL | |
276 | #endif | |
277 | ||
290ad14a MM |
278 | #define MODEL_ISSUE_IGNORE (-1) |
279 | #define MODEL_ISSUE_PROCESS 1 | |
280 | ||
70fc4ad3 | 281 | #ifndef WITH_MODEL_ISSUE |
290ad14a | 282 | #define WITH_MODEL_ISSUE 0 |
70fc4ad3 MM |
283 | #endif |
284 | ||
290ad14a MM |
285 | extern int current_model_issue; |
286 | #define CURRENT_MODEL_ISSUE (WITH_MODEL_ISSUE \ | |
287 | ? WITH_MODEL_ISSUE \ | |
288 | : current_model_issue) | |
289 | ||
8e20a3ac MM |
290 | /* INLINE CODE SELECTION: |
291 | ||
292 | GCC -O3 attempts to inline any function or procedure in scope. The | |
293 | options below facilitate fine grained control over what is and what | |
294 | isn't made inline. For instance it can control things down to a | |
295 | specific modules static routines. This control is implemented in | |
296 | two parts. Doing this allows the compiler to both eliminate the | |
297 | overhead of function calls and (as a consequence) also eliminate | |
298 | further dead code. | |
299 | ||
300 | Experementing with CISC (x86) I've found that I can achieve an | |
301 | order of magintude speed improvement (x3-x5). In the case of RISC | |
302 | (sparc) while the performance gain isn't as great it is still | |
303 | significant. | |
304 | ||
305 | Part One - Static functions: It is possible to control how static | |
306 | functions within each module are to be compiled. On a per module | |
307 | or global basis, it is possible to specify that a modules static | |
308 | functions should be compiled inline. This is controled by the the | |
309 | macro's STATIC_INLINE and INLINE_STATIC_<module>. | |
310 | ||
311 | Part Two - External functions: Again it is possible to allow the | |
312 | inlining of calls to external functions. This is far more | |
313 | complicated and much heaver on the compiler. In this case, it is | |
314 | controled by the <module>_INLINE macro's. Where each can have a | |
315 | value: | |
316 | ||
5b4d72dd | 317 | 0 Make a normal external call to functions in the module. |
8e20a3ac | 318 | |
5b4d72dd MM |
319 | 1 Include the module but to not inline functions within it. |
320 | This allows functions within the module to inline functions | |
321 | from other modules that have been included. | |
8e20a3ac | 322 | |
5b4d72dd MM |
323 | 2 Both include the module and inline functions contained within |
324 | it. | |
8e20a3ac MM |
325 | |
326 | Finally, this is not for the faint harted. I've seen GCC get up to | |
327 | 200mb trying to compile what this can create */ | |
328 | ||
329 | /* Your compilers inline reserved word */ | |
330 | ||
331 | #ifndef INLINE | |
acb06d30 MM |
332 | #if defined(__GNUC__) && defined(__OPTIMIZE__) && \ |
333 | (DEFAULT_INLINE || SIM_ENDIAN_INLINE || BITS_INLINE || CPU_INLINE || VM_INLINE || CORE_INLINE \ | |
334 | || EVENTS_INLINE || MON_INLINE || INTERRUPTS_INLINE || REGISTERS_INLINE || DEVICE_TREE_INLINE \ | |
70fc4ad3 | 335 | || DEVICES_INLINE || SPREG_INLINE || SEMANTICS_INLINE || IDECODE_INLINE || MODEL_INLINE) |
8e20a3ac MM |
336 | #define INLINE __inline__ |
337 | #else | |
338 | #define INLINE /*inline*/ | |
339 | #endif | |
340 | #endif | |
341 | ||
342 | /* Default prefix for static functions */ | |
343 | ||
344 | #ifndef STATIC_INLINE | |
345 | #define STATIC_INLINE static INLINE | |
346 | #endif | |
347 | ||
5b4d72dd | 348 | /* Default macro to simplify control several of key the inlines */ |
8e20a3ac MM |
349 | |
350 | #ifndef DEFAULT_INLINE | |
351 | #define DEFAULT_INLINE 0 | |
352 | #endif | |
353 | ||
5b4d72dd | 354 | /* Code that converts between hosts and target byte order. Used on |
73c4941b | 355 | every memory access (instruction and data). (See sim-endian.h for |
5b4d72dd | 356 | additional byte swapping configuration information) */ |
8e20a3ac | 357 | |
73c4941b MM |
358 | #ifndef SIM_ENDIAN_INLINE |
359 | #define SIM_ENDIAN_INLINE DEFAULT_INLINE | |
360 | #endif | |
361 | ||
362 | /* Low level bit manipulation routines used to work around a compiler | |
363 | bug in 2.6.3. */ | |
364 | ||
365 | #ifndef BITS_INLINE | |
366 | #define BITS_INLINE DEFAULT_INLINE | |
8e20a3ac MM |
367 | #endif |
368 | ||
5b4d72dd MM |
369 | /* Code that gives access to various CPU internals such as registers. |
370 | Used every time an instruction is executed */ | |
8e20a3ac | 371 | |
5b4d72dd MM |
372 | #ifndef CPU_INLINE |
373 | #define CPU_INLINE DEFAULT_INLINE | |
8e20a3ac MM |
374 | #endif |
375 | ||
5b4d72dd MM |
376 | /* Code that translates between an effective and real address. Used |
377 | by every load or store. */ | |
8e20a3ac MM |
378 | |
379 | #ifndef VM_INLINE | |
380 | #define VM_INLINE DEFAULT_INLINE | |
381 | #endif | |
382 | ||
5b4d72dd MM |
383 | /* Code that loads/stores data to/from the memory data structure. |
384 | Used by every load or store */ | |
8e20a3ac | 385 | |
5b4d72dd MM |
386 | #ifndef CORE_INLINE |
387 | #define CORE_INLINE DEFAULT_INLINE | |
8e20a3ac MM |
388 | #endif |
389 | ||
5b4d72dd MM |
390 | /* Code to check for and process any events scheduled in the future. |
391 | Called once per instruction cycle */ | |
8e20a3ac MM |
392 | |
393 | #ifndef EVENTS_INLINE | |
394 | #define EVENTS_INLINE DEFAULT_INLINE | |
395 | #endif | |
396 | ||
5b4d72dd MM |
397 | /* Code monotoring the processors performance. It counts events on |
398 | every instruction cycle */ | |
8e20a3ac | 399 | |
5b4d72dd MM |
400 | #ifndef MON_INLINE |
401 | #define MON_INLINE DEFAULT_INLINE | |
8e20a3ac MM |
402 | #endif |
403 | ||
5b4d72dd | 404 | /* Code called on the rare occasions that an interrupt occures. */ |
8e20a3ac MM |
405 | |
406 | #ifndef INTERRUPTS_INLINE | |
5b4d72dd MM |
407 | #define INTERRUPTS_INLINE 0 |
408 | #endif | |
409 | ||
410 | /* Code called on the rare occasion that either gdb or the device tree | |
411 | need to manipulate a register within a processor */ | |
412 | ||
413 | #ifndef REGISTERS_INLINE | |
414 | #define REGISTERS_INLINE 0 | |
8e20a3ac MM |
415 | #endif |
416 | ||
5b4d72dd MM |
417 | /* Code called on the rare occasion that a processor is manipulating |
418 | real hardware instead of RAM. | |
419 | ||
420 | Also, most of the functions in devices.c are always called through | |
421 | a jump table. | |
8e20a3ac MM |
422 | |
423 | There seems to be some problem with making either device_tree or | |
5b4d72dd MM |
424 | devices inline. It reports the message: device_tree_find_node() |
425 | not a leaf */ | |
8e20a3ac MM |
426 | |
427 | #ifndef DEVICE_TREE_INLINE | |
a983c8f0 | 428 | #define DEVICE_TREE_INLINE 0 |
8e20a3ac MM |
429 | #endif |
430 | ||
431 | #ifndef DEVICES_INLINE | |
432 | #define DEVICES_INLINE 0 | |
433 | #endif | |
434 | ||
5b4d72dd MM |
435 | /* Code called whenever information on a Special Purpose Register is |
436 | required. Called by the mflr/mtlr pseudo instructions */ | |
8e20a3ac MM |
437 | |
438 | #ifndef SPREG_INLINE | |
439 | #define SPREG_INLINE DEFAULT_INLINE | |
440 | #endif | |
441 | ||
442 | /* Functions modeling the semantics of each instruction. Two cases to | |
443 | consider, firstly of idecode is implemented with a switch then this | |
444 | allows the idecode function to inline each semantic function | |
445 | (avoiding a call). The second case is when idecode is using a | |
446 | table, even then while the semantic functions can't be inlined, | |
447 | setting it to one still enables each semantic function to inline | |
448 | anything they call (if that code is marked for being inlined). | |
449 | ||
450 | WARNING: you need lots (like 200mb of swap) of swap. Setting this | |
451 | to 1 is useful when using a table as it enables the sematic code to | |
452 | inline all of their called functions */ | |
453 | ||
454 | #ifndef SEMANTICS_INLINE | |
5b4d72dd | 455 | #define SEMANTICS_INLINE (DEFAULT_INLINE ? 1 : 0) |
8e20a3ac MM |
456 | #endif |
457 | ||
5b4d72dd MM |
458 | /* Code to decode an instruction. Normally called on every instruction |
459 | cycle */ | |
8e20a3ac MM |
460 | |
461 | #ifndef IDECODE_INLINE | |
462 | #define IDECODE_INLINE DEFAULT_INLINE | |
463 | #endif | |
464 | ||
70fc4ad3 MM |
465 | /* Model specific code used in simulating functional units. Note, it actaully |
466 | pays NOT to inline the PowerPC model functions (at least on the x86). This | |
467 | is because if it is inlined, each PowerPC instruction gets a separate copy | |
468 | of the code, which is not friendly to the cache. */ | |
28816f45 MM |
469 | |
470 | #ifndef MODEL_INLINE | |
70fc4ad3 | 471 | #define MODEL_INLINE (DEFAULT_INLINE ? 1 : 0) |
73c4941b MM |
472 | #endif |
473 | ||
acb06d30 MM |
474 | /* Code to print out what options we were compiled with. Because this |
475 | is called at process startup, it doesn't have to be inlined, but | |
476 | if it isn't brought in and the model routines are inline, the model | |
477 | routines will be pulled in twice. */ | |
478 | ||
479 | #ifndef OPTIONS_INLINE | |
480 | #define OPTIONS_INLINE (DEFAULT_INLINE ? 1 : 0) | |
481 | #endif | |
482 | ||
8e20a3ac | 483 | #endif /* _CONFIG_H */ |