sim: Add PRU simulator port
[deliverable/binutils-gdb.git] / sim / pru / pru.h
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1/* Copyright 2016-2019 Free Software Foundation, Inc.
2 Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
3
4 This file is part of the PRU simulator.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, see <http://www.gnu.org/licenses/>. */
18
19#ifndef PRU_H
20#define PRU_H
21
22#include "config.h"
23#include "opcode/pru.h"
24
25/* Needed for handling the dual PRU address space. */
26#define IMEM_ADDR_MASK ((1u << 23) - 1)
27
28#define IMEM_ADDR_DEFAULT 0x20000000
29
30/* Define memory sizes to allocate for simulated target. Sizes are
31 artificially large to accommodate execution of compiler test suite.
32 Please synchronize with the linker script for prusim target. */
33#define DMEM_DEFAULT_SIZE (64 * 1024 * 1024)
34
35/* 16-bit word addressable space. */
36#define IMEM_DEFAULT_SIZE (64 * 4 * 1024)
37
38/* For AM335x SoCs. */
39#define XFRID_SCRATCH_BANK_0 10
40#define XFRID_SCRATCH_BANK_1 11
41#define XFRID_SCRATCH_BANK_2 12
42#define XFRID_SCRATCH_BANK_PEER 14
43#define XFRID_MAX 255
44
45#define CPU (cpu->pru_cpu)
46
47#define PC (CPU.pc)
48#define PC_byteaddr ((PC << 2) | PC_ADDR_SPACE_MARKER)
49
50/* Various opcode fields. */
51#define RS1 extract_regval (CPU.regs[GET_INSN_FIELD (RS1, inst)], \
52 GET_INSN_FIELD (RS1SEL, inst))
53#define RS2 extract_regval (CPU.regs[GET_INSN_FIELD (RS2, inst)], \
54 GET_INSN_FIELD (RS2SEL, inst))
55
56#define RS2_w0 extract_regval (CPU.regs[GET_INSN_FIELD (RS2, inst)], \
57 RSEL_15_0)
58
59#define XBBO_BASEREG (CPU.regs[GET_INSN_FIELD (RS1, inst)])
60
61#define RDSEL GET_INSN_FIELD (RDSEL, inst)
62#define RD_WIDTH regsel_width (RDSEL)
63#define RD_REGN GET_INSN_FIELD (RD, inst)
64#define IO GET_INSN_FIELD (IO, inst)
65#define IMM8 GET_INSN_FIELD (IMM8, inst)
66#define IMM16 GET_INSN_FIELD (IMM16, inst)
67#define WAKEONSTATUS GET_INSN_FIELD (WAKEONSTATUS, inst)
68#define CB GET_INSN_FIELD (CB, inst)
69#define RDB GET_INSN_FIELD (RDB, inst)
70#define XFR_WBA GET_INSN_FIELD (XFR_WBA, inst)
71#define LOOP_JMPOFFS GET_INSN_FIELD (LOOP_JMPOFFS, inst)
72#define BROFF ((uint32_t) GET_BROFF_SIGNED (inst))
73
74#define _BURSTLEN_CALCULATE(BITFIELD) \
75 ((BITFIELD) >= LSSBBO_BYTECOUNT_R0_BITS7_0 ? \
76 (CPU.regs[0] >> ((BITFIELD) - LSSBBO_BYTECOUNT_R0_BITS7_0) * 8) & 0xff \
77 : (BITFIELD) + 1)
78
79#define BURSTLEN _BURSTLEN_CALCULATE (GET_BURSTLEN (inst))
80#define XFR_LENGTH _BURSTLEN_CALCULATE (GET_INSN_FIELD (XFR_LENGTH, inst))
81
82#define DO_XIN(wba,regn,rdb,l) \
83 pru_sim_xin (sd, cpu, (wba), (regn), (rdb), (l))
84#define DO_XOUT(wba,regn,rdb,l) \
85 pru_sim_xout (sd, cpu, (wba), (regn), (rdb), (l))
86#define DO_XCHG(wba,regn,rdb,l) \
87 pru_sim_xchg (sd, cpu, (wba), (regn), (rdb), (l))
88
89#define RAISE_SIGILL(sd) sim_engine_halt ((sd), NULL, NULL, PC_byteaddr, \
90 sim_stopped, SIM_SIGILL)
91#define RAISE_SIGINT(sd) sim_engine_halt ((sd), NULL, NULL, PC_byteaddr, \
92 sim_stopped, SIM_SIGINT)
93
94#define MAC_R25_MAC_MODE_MASK (1u << 0)
95#define MAC_R25_ACC_CARRY_MASK (1u << 1)
96
97#define CARRY CPU.carry
98#define CTABLE CPU.ctable
99
100#define PC_ADDR_SPACE_MARKER CPU.pc_addr_space_marker
101
102#define LOOPTOP CPU.loop.looptop
103#define LOOPEND CPU.loop.loopend
104#define LOOP_IN_PROGRESS CPU.loop.loop_in_progress
105#define LOOPCNT CPU.loop.loop_counter
106
107/* 32 GP registers plus PC. */
108#define NUM_REGS 33
109
110#endif /* PRU_H */
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