[deliverable/binutils-gdb.git] / sim / sh64 / cpu.h

/* CPU family header for sh64.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.

This file is part of the GNU Simulators.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/

#ifndef CPU_SH64_H
#define CPU_SH64_H

/* Maximum number of instructions that are fetched at a time.
   This is for LIW type instructions sets (e.g. m32r).  */
#define MAX_LIW_INSNS 1

/* Maximum number of instructions that can be executed in parallel.  */
#define MAX_PARALLEL_INSNS 1

/* CPU state information.  */
typedef struct {
  /* Hardware elements.  */
  struct {
  /* Program counter */
  UDI h_pc;
#define GET_H_PC() CPU (h_pc)
#define SET_H_PC(x) \
do { \
{\
CPU (h_ism) = ANDDI ((x), 1);\
CPU (h_pc) = ANDDI ((x), INVDI (1));\
}\
;} while (0)
  /* General purpose integer registers */
  DI h_gr[64];
#define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index])))
#define SET_H_GR(index, x) \
do { \
if ((((index)) != (63))) {\
CPU (h_gr[(index)]) = (x);\
} else {\
((void) 0); /*nop*/\
}\
;} while (0)
  /* Control registers */
  DI h_cr[64];
#define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index])))
#define SET_H_CR(index, x) \
do { \
if ((((index)) == (0))) {\
CPU (h_sr) = (x);\
} else {\
CPU (h_cr[(index)]) = (x);\
}\
;} while (0)
  /* Status register */
  SI h_sr;
#define GET_H_SR() CPU (h_sr)
#define SET_H_SR(x) (CPU (h_sr) = (x))
  /* Floating point status and control register */
  SI h_fpscr;
#define GET_H_FPSCR() CPU (h_fpscr)
#define SET_H_FPSCR(x) (CPU (h_fpscr) = (x))
  /* Single precision floating point registers */
  SF h_fr[64];
#define GET_H_FR(a1) CPU (h_fr)[a1]
#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
  /* Single precision floating point register pairs */
  DF h_fp[32];
#define GET_H_FP(a1) CPU (h_fp)[a1]
#define SET_H_FP(a1, x) (CPU (h_fp)[a1] = (x))
  /* Branch target registers */
  DI h_tr[8];
#define GET_H_TR(a1) CPU (h_tr)[a1]
#define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x))
  /* Current instruction set mode */
  BI h_ism;
#define GET_H_ISM() CPU (h_ism)
#define SET_H_ISM(x) \
do { \
cgen_rtx_error (current_cpu, "cannot set ism directly");\
;} while (0)
  } hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
} SH64_CPU_DATA;

/* Virtual regs.  */

#define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff))
#define SET_H_GRC(index, x) \
do { \
CPU (h_gr[(index)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_sr), 14), 1)
#define SET_H_FRBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (14))))), SLLSI ((x), 14));\
;} while (0)
#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_sr), 13), 1)
#define SET_H_SZBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (13))))), SLLSI ((x), 13));\
;} while (0)
#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_sr), 12), 1)
#define SET_H_PRBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (12))))), SLLSI ((x), 12));\
;} while (0)
#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1)
#define SET_H_SBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\
;} while (0)
#define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1)
#define SET_H_MBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\
;} while (0)
#define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1)
#define SET_H_QBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\
;} while (0)
#define GET_H_FV(index) CPU (h_fr[MULQI (ANDQI (index, 15), 4)])
#define SET_H_FV(index, x) \
do { \
CPU (h_fr[MULQI (ANDQI ((index), 15), 4)]) = (x);\
;} while (0)
#define GET_H_FMTX(index) CPU (h_fr[MULQI (ANDQI (index, 3), 16)])
#define SET_H_FMTX(index, x) \
do { \
CPU (h_fr[MULQI (ANDQI ((index), 3), 16)]) = (x);\
;} while (0)
#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))])))))
#define SET_H_DR(index, x) \
do { \
{\
CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\
CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\
}\
;} while (0)
#define GET_H_ENDIAN() sh64_endian (current_cpu)
#define SET_H_ENDIAN(x) \
do { \
cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\
;} while (0)
#define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
#define SET_H_FRC(index, x) \
do { \
CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
;} while (0)
#define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index)))
#define SET_H_DRC(index, x) \
do { \
SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\
;} while (0)
#define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))])
#define SET_H_XF(index, x) \
do { \
CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\
;} while (0)
#define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index)))
#define SET_H_XD(index, x) \
do { \
SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\
;} while (0)
#define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
#define SET_H_FVC(index, x) \
do { \
CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
;} while (0)
#define GET_H_FPCCR() ORSI (ORSI (ORSI (CPU (h_fpscr), SLLSI (GET_H_PRBIT (), 19)), SLLSI (GET_H_SZBIT (), 20)), SLLSI (GET_H_FRBIT (), 21))
#define SET_H_FPCCR(x) \
do { \
{\
CPU (h_fpscr) = (x);\
SET_H_PRBIT (ANDSI (SRLSI ((x), 19), 1));\
SET_H_SZBIT (ANDSI (SRLSI ((x), 20), 1));\
SET_H_FRBIT (ANDSI (SRLSI ((x), 21), 1));\
}\
;} while (0)
#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1)
#define SET_H_GBR(x) \
do { \
CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1)
#define SET_H_PR(x) \
do { \
CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)
#define SET_H_MACL(x) \
do { \
CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\
;} while (0)
#define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)
#define SET_H_MACH(x) \
do { \
CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\
;} while (0)
#define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1)
#define SET_H_TBIT(x) \
do { \
CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\
;} while (0)

/* Cover fns for register access.  */
UDI sh64_h_pc_get (SIM_CPU *);
void sh64_h_pc_set (SIM_CPU *, UDI);
DI sh64_h_gr_get (SIM_CPU *, UINT);
void sh64_h_gr_set (SIM_CPU *, UINT, DI);
SI sh64_h_grc_get (SIM_CPU *, UINT);
void sh64_h_grc_set (SIM_CPU *, UINT, SI);
DI sh64_h_cr_get (SIM_CPU *, UINT);
void sh64_h_cr_set (SIM_CPU *, UINT, DI);
SI sh64_h_sr_get (SIM_CPU *);
void sh64_h_sr_set (SIM_CPU *, SI);
SI sh64_h_fpscr_get (SIM_CPU *);
void sh64_h_fpscr_set (SIM_CPU *, SI);
BI sh64_h_frbit_get (SIM_CPU *);
void sh64_h_frbit_set (SIM_CPU *, BI);
BI sh64_h_szbit_get (SIM_CPU *);
void sh64_h_szbit_set (SIM_CPU *, BI);
BI sh64_h_prbit_get (SIM_CPU *);
void sh64_h_prbit_set (SIM_CPU *, BI);
BI sh64_h_sbit_get (SIM_CPU *);
void sh64_h_sbit_set (SIM_CPU *, BI);
BI sh64_h_mbit_get (SIM_CPU *);
void sh64_h_mbit_set (SIM_CPU *, BI);
BI sh64_h_qbit_get (SIM_CPU *);
void sh64_h_qbit_set (SIM_CPU *, BI);
SF sh64_h_fr_get (SIM_CPU *, UINT);
void sh64_h_fr_set (SIM_CPU *, UINT, SF);
DF sh64_h_fp_get (SIM_CPU *, UINT);
void sh64_h_fp_set (SIM_CPU *, UINT, DF);
SF sh64_h_fv_get (SIM_CPU *, UINT);
void sh64_h_fv_set (SIM_CPU *, UINT, SF);
SF sh64_h_fmtx_get (SIM_CPU *, UINT);
void sh64_h_fmtx_set (SIM_CPU *, UINT, SF);
DF sh64_h_dr_get (SIM_CPU *, UINT);
void sh64_h_dr_set (SIM_CPU *, UINT, DF);
DI sh64_h_tr_get (SIM_CPU *, UINT);
void sh64_h_tr_set (SIM_CPU *, UINT, DI);
BI sh64_h_endian_get (SIM_CPU *);
void sh64_h_endian_set (SIM_CPU *, BI);
BI sh64_h_ism_get (SIM_CPU *);
void sh64_h_ism_set (SIM_CPU *, BI);
SF sh64_h_frc_get (SIM_CPU *, UINT);
void sh64_h_frc_set (SIM_CPU *, UINT, SF);
DF sh64_h_drc_get (SIM_CPU *, UINT);
void sh64_h_drc_set (SIM_CPU *, UINT, DF);
SF sh64_h_xf_get (SIM_CPU *, UINT);
void sh64_h_xf_set (SIM_CPU *, UINT, SF);
DF sh64_h_xd_get (SIM_CPU *, UINT);
void sh64_h_xd_set (SIM_CPU *, UINT, DF);
SF sh64_h_fvc_get (SIM_CPU *, UINT);
void sh64_h_fvc_set (SIM_CPU *, UINT, SF);
SI sh64_h_fpccr_get (SIM_CPU *);
void sh64_h_fpccr_set (SIM_CPU *, SI);
SI sh64_h_gbr_get (SIM_CPU *);
void sh64_h_gbr_set (SIM_CPU *, SI);
SI sh64_h_pr_get (SIM_CPU *);
void sh64_h_pr_set (SIM_CPU *, SI);
SI sh64_h_macl_get (SIM_CPU *);
void sh64_h_macl_set (SIM_CPU *, SI);
SI sh64_h_mach_get (SIM_CPU *);
void sh64_h_mach_set (SIM_CPU *, SI);
BI sh64_h_tbit_get (SIM_CPU *);
void sh64_h_tbit_set (SIM_CPU *, BI);

/* These must be hand-written.  */
extern CPUREG_FETCH_FN sh64_fetch_register;
extern CPUREG_STORE_FN sh64_store_register;

typedef struct {
  int empty;
} MODEL_SH5_DATA;

/* Collection of various things for the trace handler to use.  */

typedef struct trace_record {
  IADDR pc;
  /* FIXME:wip */
} TRACE_RECORD;

#endif /* CPU_SH64_H */
Commit	Line	Data
cbb38b47 BE	1	/* CPU family header for sh64.
	2
	3	THIS FILE IS MACHINE GENERATED WITH CGEN.
	4
	5	Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
	6
	7	This file is part of the GNU Simulators.
	8
	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 2, or (at your option)
	12	any later version.
	13
	14	This program is distributed in the hope that it will be useful,
	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License along
	20	with this program; if not, write to the Free Software Foundation, Inc.,
	21	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	22
	23	*/
	24
	25	#ifndef CPU_SH64_H
	26	#define CPU_SH64_H
	27
	28	/* Maximum number of instructions that are fetched at a time.
	29	This is for LIW type instructions sets (e.g. m32r). */
	30	#define MAX_LIW_INSNS 1
	31
	32	/* Maximum number of instructions that can be executed in parallel. */
	33	#define MAX_PARALLEL_INSNS 1
	34
	35	/* CPU state information. */
	36	typedef struct {
	37	/* Hardware elements. */
	38	struct {
	39	/* Program counter */
	40	UDI h_pc;
	41	#define GET_H_PC() CPU (h_pc)
	42	#define SET_H_PC(x) \
	43	do { \
	44	{\
	45	CPU (h_ism) = ANDDI ((x), 1);\
	46	CPU (h_pc) = ANDDI ((x), INVDI (1));\
	47	}\
	48	;} while (0)
	49	/* General purpose integer registers */
	50	DI h_gr[64];
	51	#define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index])))
	52	#define SET_H_GR(index, x) \
	53	do { \
	54	if ((((index)) != (63))) {\
	55	CPU (h_gr[(index)]) = (x);\
	56	} else {\
	57	((void) 0); /nop/\
	58	}\
	59	;} while (0)
	60	/* Control registers */
	61	DI h_cr[64];
	62	#define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index])))
	63	#define SET_H_CR(index, x) \
	64	do { \
65	if ((((index)) == (0))) {\
66	CPU (h_sr) = (x);\
67	} else {\
68	CPU (h_cr[(index)]) = (x);\
69	}\
70	;} while (0)
71	/* Status register */
72	SI h_sr;
73	#define GET_H_SR() CPU (h_sr)
74	#define SET_H_SR(x) (CPU (h_sr) = (x))
75	/* Floating point status and control register */
76	SI h_fpscr;
77	#define GET_H_FPSCR() CPU (h_fpscr)
78	#define SET_H_FPSCR(x) (CPU (h_fpscr) = (x))
79	/* Single precision floating point registers */
80	SF h_fr[64];
81	#define GET_H_FR(a1) CPU (h_fr)[a1]
82	#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
83	/* Single precision floating point register pairs */
84	DF h_fp[32];
85	#define GET_H_FP(a1) CPU (h_fp)[a1]
86	#define SET_H_FP(a1, x) (CPU (h_fp)[a1] = (x))
87	/* Branch target registers */
88	DI h_tr[8];
89	#define GET_H_TR(a1) CPU (h_tr)[a1]
90	#define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x))
91	/* Current instruction set mode */
92	BI h_ism;
93	#define GET_H_ISM() CPU (h_ism)
94	#define SET_H_ISM(x) \
95	do { \
96	cgen_rtx_error (current_cpu, "cannot set ism directly");\
97	;} while (0)
98	} hardware;
99	#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
100	} SH64_CPU_DATA;
101
102	/* Virtual regs. */
103
104	#define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff))
105	#define SET_H_GRC(index, x) \
106	do { \
107	CPU (h_gr[(index)]) = EXTSIDI ((x));\
108	;} while (0)
109	#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_sr), 14), 1)
110	#define SET_H_FRBIT(x) \
111	do { \
112	CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (14))))), SLLSI ((x), 14));\
113	;} while (0)
114	#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_sr), 13), 1)
115	#define SET_H_SZBIT(x) \
116	do { \
117	CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (13))))), SLLSI ((x), 13));\
118	;} while (0)
119	#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_sr), 12), 1)
120	#define SET_H_PRBIT(x) \
121	do { \
122	CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (12))))), SLLSI ((x), 12));\
123	;} while (0)
124	#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1)
125	#define SET_H_SBIT(x) \
126	do { \
127	CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\
128	;} while (0)
129	#define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1)
130	#define SET_H_MBIT(x) \
131	do { \
132	CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\
133	;} while (0)
134	#define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1)
135	#define SET_H_QBIT(x) \
136	do { \
137	CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\
138	;} while (0)
139	#define GET_H_FV(index) CPU (h_fr[MULQI (ANDQI (index, 15), 4)])
140	#define SET_H_FV(index, x) \
141	do { \
142	CPU (h_fr[MULQI (ANDQI ((index), 15), 4)]) = (x);\
143	;} while (0)
144	#define GET_H_FMTX(index) CPU (h_fr[MULQI (ANDQI (index, 3), 16)])
145	#define SET_H_FMTX(index, x) \
146	do { \
147	CPU (h_fr[MULQI (ANDQI ((index), 3), 16)]) = (x);\
148	;} while (0)
149	#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))])))))
150	#define SET_H_DR(index, x) \
151	do { \
152	{\
153	CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\
154	CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\
155	}\
156	;} while (0)
157	#define GET_H_ENDIAN() sh64_endian (current_cpu)
158	#define SET_H_ENDIAN(x) \
159	do { \
160	cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\
161	;} while (0)
162	#define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
163	#define SET_H_FRC(index, x) \
164	do { \
165	CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
166	;} while (0)
167	#define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index)))
168	#define SET_H_DRC(index, x) \
169	do { \
170	SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\
171	;} while (0)
172	#define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))])
173	#define SET_H_XF(index, x) \
174	do { \
175	CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\
176	;} while (0)
177	#define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index)))
178	#define SET_H_XD(index, x) \
179	do { \
180	SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\
181	;} while (0)
182	#define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
183	#define SET_H_FVC(index, x) \
184	do { \
185	CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
186	;} while (0)
187	#define GET_H_FPCCR() ORSI (ORSI (ORSI (CPU (h_fpscr), SLLSI (GET_H_PRBIT (), 19)), SLLSI (GET_H_SZBIT (), 20)), SLLSI (GET_H_FRBIT (), 21))
188	#define SET_H_FPCCR(x) \
189	do { \
190	{\
191	CPU (h_fpscr) = (x);\
192	SET_H_PRBIT (ANDSI (SRLSI ((x), 19), 1));\
193	SET_H_SZBIT (ANDSI (SRLSI ((x), 20), 1));\
194	SET_H_FRBIT (ANDSI (SRLSI ((x), 21), 1));\
195	}\
196	;} while (0)
197	#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1)
198	#define SET_H_GBR(x) \
199	do { \
200	CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\
201	;} while (0)
202	#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1)
203	#define SET_H_PR(x) \
204	do { \
205	CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\
206	;} while (0)
207	#define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)
208	#define SET_H_MACL(x) \
209	do { \
210	CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\
211	;} while (0)
212	#define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)
213	#define SET_H_MACH(x) \
214	do { \
215	CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\
216	;} while (0)
217	#define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1)
218	#define SET_H_TBIT(x) \
219	do { \
220	CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\
221	;} while (0)
222
223	/* Cover fns for register access. */
224	UDI sh64_h_pc_get (SIM_CPU *);
225	void sh64_h_pc_set (SIM_CPU *, UDI);
226	DI sh64_h_gr_get (SIM_CPU *, UINT);
227	void sh64_h_gr_set (SIM_CPU *, UINT, DI);
228	SI sh64_h_grc_get (SIM_CPU *, UINT);
229	void sh64_h_grc_set (SIM_CPU *, UINT, SI);
230	DI sh64_h_cr_get (SIM_CPU *, UINT);
231	void sh64_h_cr_set (SIM_CPU *, UINT, DI);
232	SI sh64_h_sr_get (SIM_CPU *);
233	void sh64_h_sr_set (SIM_CPU *, SI);
234	SI sh64_h_fpscr_get (SIM_CPU *);
235	void sh64_h_fpscr_set (SIM_CPU *, SI);
236	BI sh64_h_frbit_get (SIM_CPU *);
237	void sh64_h_frbit_set (SIM_CPU *, BI);
238	BI sh64_h_szbit_get (SIM_CPU *);
239	void sh64_h_szbit_set (SIM_CPU *, BI);
240	BI sh64_h_prbit_get (SIM_CPU *);
241	void sh64_h_prbit_set (SIM_CPU *, BI);
242	BI sh64_h_sbit_get (SIM_CPU *);
243	void sh64_h_sbit_set (SIM_CPU *, BI);
244	BI sh64_h_mbit_get (SIM_CPU *);
245	void sh64_h_mbit_set (SIM_CPU *, BI);
246	BI sh64_h_qbit_get (SIM_CPU *);
247	void sh64_h_qbit_set (SIM_CPU *, BI);
248	SF sh64_h_fr_get (SIM_CPU *, UINT);
249	void sh64_h_fr_set (SIM_CPU *, UINT, SF);
250	DF sh64_h_fp_get (SIM_CPU *, UINT);
251	void sh64_h_fp_set (SIM_CPU *, UINT, DF);
252	SF sh64_h_fv_get (SIM_CPU *, UINT);
253	void sh64_h_fv_set (SIM_CPU *, UINT, SF);
254	SF sh64_h_fmtx_get (SIM_CPU *, UINT);
255	void sh64_h_fmtx_set (SIM_CPU *, UINT, SF);
256	DF sh64_h_dr_get (SIM_CPU *, UINT);
257	void sh64_h_dr_set (SIM_CPU *, UINT, DF);
258	DI sh64_h_tr_get (SIM_CPU *, UINT);
259	void sh64_h_tr_set (SIM_CPU *, UINT, DI);
260	BI sh64_h_endian_get (SIM_CPU *);
261	void sh64_h_endian_set (SIM_CPU *, BI);
262	BI sh64_h_ism_get (SIM_CPU *);
263	void sh64_h_ism_set (SIM_CPU *, BI);
264	SF sh64_h_frc_get (SIM_CPU *, UINT);
265	void sh64_h_frc_set (SIM_CPU *, UINT, SF);
266	DF sh64_h_drc_get (SIM_CPU *, UINT);
267	void sh64_h_drc_set (SIM_CPU *, UINT, DF);
268	SF sh64_h_xf_get (SIM_CPU *, UINT);
269	void sh64_h_xf_set (SIM_CPU *, UINT, SF);
270	DF sh64_h_xd_get (SIM_CPU *, UINT);
271	void sh64_h_xd_set (SIM_CPU *, UINT, DF);
272	SF sh64_h_fvc_get (SIM_CPU *, UINT);
273	void sh64_h_fvc_set (SIM_CPU *, UINT, SF);
274	SI sh64_h_fpccr_get (SIM_CPU *);
275	void sh64_h_fpccr_set (SIM_CPU *, SI);
276	SI sh64_h_gbr_get (SIM_CPU *);
277	void sh64_h_gbr_set (SIM_CPU *, SI);
278	SI sh64_h_pr_get (SIM_CPU *);
279	void sh64_h_pr_set (SIM_CPU *, SI);
280	SI sh64_h_macl_get (SIM_CPU *);
281	void sh64_h_macl_set (SIM_CPU *, SI);
282	SI sh64_h_mach_get (SIM_CPU *);
283	void sh64_h_mach_set (SIM_CPU *, SI);
284	BI sh64_h_tbit_get (SIM_CPU *);
285	void sh64_h_tbit_set (SIM_CPU *, BI);
286
287	/* These must be hand-written. */
288	extern CPUREG_FETCH_FN sh64_fetch_register;
289	extern CPUREG_STORE_FN sh64_store_register;
290
291	typedef struct {
292	int empty;
293	} MODEL_SH5_DATA;
294
295	/* Collection of various things for the trace handler to use. */
296
297	typedef struct trace_record {
298	IADDR pc;
299	/* FIXME:wip */
300	} TRACE_RECORD;
301
302	#endif /* CPU_SH64_H */