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* sem-switch.c: Regenerate. Redo computed goto label handling.
[deliverable/binutils-gdb.git] / sim / testsuite / ChangeLog
CommitLineData
dca2d4f4
DE		 1Wed Apr 22 12:26:28 1998 Doug Evans <devans@canuck.cygnus.com>
2
3 * Makefile.in (TARGET_FLAGS_TO_PASS): Delete LIBS, LDFLAGS.
4
aa467704
DE		 5Tue Apr 21 10:49:03 1998 Doug Evans <devans@canuck.cygnus.com>
6
7 * lib/sim-defs.exp (run_sim_test): Don't exit early if one mach fails,
8 try all machs.
9
581fd042
DE		 10 * sim/m32r/addx.cgs: Test (-1)+(-1)+1.
11
aa467704
DE		 12Fri Apr 17 16:00:52 1998 Doug Evans <devans@canuck.cygnus.com>
13
14 * sim/m32r/mv[ft]achi.cgs: Fix expected result
15 (sign extension of top 8 bits).
16start-sanitize-m32rx
17 * sim/m32r/mv[ft]achi-a.cgs: Ditto.
18end-sanitize-m32rx
19
489564e2
DE		 20start-sanitize-m32rx
21Tue Apr 14 14:06:34 1998 Doug Evans <devans@canuck.cygnus.com>
22
23 * sim/m32r/maclh1.cgs: Fix testcase.
24 * sim/m32r/maclh1-2.cgs: New testcase.
25
26Tue Mar 3 19:09:09 1998 Doug Evans <devans@canuck.cygnus.com>
27
28 * sim/m32r/sat.cgs: Change sath to sat.
29
30end-sanitize-m32rx
9495a61e
DE		 31Wed Feb 25 11:01:17 1998 Doug Evans <devans@canuck.cygnus.com>
32
33 * Makefile.in (RUNTEST): Fix path to runtest.
34
559eba20
FCE		 35start-sanitize-sky
36Tue Feb 24 19:47:56 1998 Frank Ch. Eigler <fche@cygnus.com>
37
38 * configure.in (testdir): Added sky subdir for mips64r5900-sky-elf
39 target.
40 * configure: Regenerate.
41end-sanitize-sky
42
f83a90c4
NC		 43Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com>
44
c801e51b 45 * sim/m32r/unlock.cgs: Fixed test.
ab361c35 46 * sim/m32r/mvfc.cgs: Fixed test.
78cbe8f6
NC		 47 * sim/m32r/remu.cgs: Fixed test.
48
caa71f09
NC		 49 * sim/m32r/bnc24.cgs: Test long BNC instruction.
50 * sim/m32r/bnc8.cgs: Test short BNC instruction.
51 * sim/m32r/ld-plus.cgs: Test LD instruction.
52 * sim/m32r/macwhi.cgs: Test MACWHI instruction.
53 * sim/m32r/macwlo.cgs: Test MACWLO instruction.
54 * sim/m32r/mulwhi.cgs: Test MULWHI instruction.
55 * sim/m32r/mulwlo.cgs: Test MULWLO instruction.
56 * sim/m32r/mvfachi.cgs: Test MVFACHI instruction.
57 * sim/m32r/mvfaclo.cgs: Test MVFACLO instruction.
58 * sim/m32r/mvtaclo.cgs: Test MVTACLO instruction.
f83a90c4
NC		 59 * sim/m32r/addv.cgs: Test ADDV instruction.
60 * sim/m32r/addv3.cgs: Test ADDV3 instruction.
61 * sim/m32r/addx.cgs: Test ADDX instruction.
62 * sim/m32r/lock.cgs: Test LOCK instruction.
63 * sim/m32r/neg.cgs: Test NEG instruction.
64 * sim/m32r/not.cgs: Test NOT instruction.
65 * sim/m32r/unlock.cgs: Test UNLOCK instruction.
caa71f09
NC		 66start-sanitize-m32rx
67 * sim/m32r/mvfachi-a.cgs: Test extended MVFACHI instruction.
aa467704 68 * sim/m32r/mvfaclo-a.cgs: Test extended MVFACLO instruction.
caa71f09
NC		 69 * sim/m32r/mvtachi-a.cgs: Test extended MVTACHI instruction.
70 * sim/m32r/mvtaclo-a.cgs: Test extended MVTACLO instruction.
71end-sanitize-m32rx
d03da19e
NC		 72Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
73
e843e28b
NC		 74 * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an
75 address into a general register.
76
c4448eec
NC		 77 * sim/m32r/or3.cgs: Test OR3 instruction.
78 * sim/m32r/rach.cgs: Test RACH instruction.
79 * sim/m32r/rem.cgs: Test REM instruction.
80 * sim/m32r/sub.cgs: Test SUB instruction.
81 * sim/m32r/mv.cgs: Test MV instruction.
82 * sim/m32r/mul.cgs: Test MUL instruction.
67dfe6e8
NC		 83 * sim/m32r/bl24.cgs: Test long BL instruction.
84 * sim/m32r/bl8.cgs: Test short BL instruction.
85 * sim/m32r/blez.cgs: Test BLEZ instruction.
86 * sim/m32r/bltz.cgs: Test BLTZ instruction.
87 * sim/m32r/bne.cgs: Test BNE instruction.
88 * sim/m32r/bnez.cgs: Test BNEZ instruction.
89 * sim/m32r/bra24.cgs: Test long BRA instruction.
90 * sim/m32r/bra8.cgs: Test short BRA instruction.
91 * sim/m32r/jl.cgs: Test JL instruction.
92 * sim/m32r/or.cgs: Test OR instruction.
93 * sim/m32r/jmp.cgs: Test JMP instruction.
dfe9df58
NC		 94 * sim/m32r/and.cgs: Test AND instruction.
95 * sim/m32r/and3.cgs: Test AND3 instruction.
96 * sim/m32r/beq.cgs: Test BEQ instruction.
97 * sim/m32r/beqz.cgs: Test BEQZ instruction.
98 * sim/m32r/bgez.cgs: Test BGEZ instruction.
99 * sim/m32r/bgtz.cgs: Test BGTZ instruction.
100 * sim/m32r/cmp.cgs: Test CMP instruction.
101 * sim/m32r/cmpi.cgs: Test CMPI instruction.
102 * sim/m32r/cmpu.cgs: Test CMPU instruction.
103 * sim/m32r/cmpui.cgs: Test CMPUI instruction.
104 * sim/m32r/div.cgs: Test DIV instruction.
67dfe6e8 105 * sim/m32r/divu.cgs: Test DIVU instruction.
dfe9df58 106 * sim/m32r/cmpeq.cgs: Test CMPEQ instruction.
dfe9df58
NC		 107 * sim/m32r/sll.cgs: Test SLL instruction.
108 * sim/m32r/sll3.cgs: Test SLL3 instruction.
109 * sim/m32r/slli.cgs: Test SLLI instruction.
0a2f6d93
NC		 110 * sim/m32r/sra.cgs: Test SRA instruction.
111 * sim/m32r/sra3.cgs: Test SRA3 instruction.
112 * sim/m32r/srai.cgs: Test SRAI instruction.
113 * sim/m32r/srl.cgs: Test SRL instruction.
114 * sim/m32r/srl3.cgs: Test SRL3 instruction.
115 * sim/m32r/srli.cgs: Test SRLI instruction.
116 * sim/m32r/xor3.cgs: Test XOR3 instruction.
117 * sim/m32r/xor.cgs: Test XOR instruction.
489564e2 118start-sanitize-m32rx
67dfe6e8
NC		 119 * sim/m32r/jnc.cgs: Test JNC instruction.
120 * sim/m32r/jc.cgs: Test JC instruction.
121 * sim/m32r/cmpz.cgs: Test CMPZ instruction.
122 * sim/m32r/bcl24.cgs: Test long version of BCL instruction
123 * sim/m32r/bcl8.cgs: Test short BCL instruction.
124 * sim/m32r/bncl24.cgs: Test long BNCL instruction.
125 * sim/m32r/bncl8.cgs: Test short BNCL instruction.
126 * sim/m32r/divh.cgs: Test DIVH instruction.
c4448eec 127 * sim/m32r/rach-dsi.cgs: Test extended RACH instruction.
489564e2 128end-sanitize-m32rx
ed063d52
DE		 129Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com>
130
fdad7ba5
DE		 131 * config/default.exp: New file.
132 * lib/sim-defs.exp: New file.
133 * sim/m32r/*: m32r dejagnu simulator testsuite.
134
ed063d52
DE		 135 * Makefile.in (build_alias): Define.
136 (arch): Define.
137 (RUNTEST_FOR_TARGET): Delete.
138 (RUNTEST): Fix.
d03da19e 139 (SCHEME,SCHEMEFLAGS,CGENDIR,CGENFLAGS): Define.
ed063d52
DE		 140 (check): Depend on site.exp. Run dejagnu.
141 (site.exp): New target.
142 (cgen): New target.
143 * configure.in: Call AC_CHECK_PROG(SCHEME) if using cgen.
144 (arch): Define from target_cpu.
145 * configure: Regenerate.
146
1a6eb36b
AC		 147Wed Sep 17 10:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
148
149 * common/bits-gen.c (gen_bit): Pass in the full name of the macro.
150 (gen_mask): Ditto.
151
152 * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT.
153 (calc): Add support for 8 bit version of macros.
154 (main): Add tests for 8 bit versions of macros.
155 (check_sext): Check SEXT of zero clears bits.
156
157 * common/bits-gen.c (main): Generate tests for 8 bit versions of
158 macros.
159
a2ab5e65
AC		 160Thu Sep 11 13:04:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
161
162 * common/Make-common.in: New file, provide generic rules for
163 running checks.
164
52352d38
AC		 165Mon Sep 1 16:43:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
166
167 * configure.in (configdirs): Test for the target directory instead
168 of matching on a target.
169
ed063d52 170start-sanitize-r5900
52352d38
AC		 171Tue Jul 15 13:43:20 1997 Andrew Cagney <cagney@sendai.cygnus.com>
172
ed063d52 173 * configure.in (configdirs): Configure mips64vr5900el
52352d38
AC		 174 directory.
175 * configure: Regenerate.
176
ed063d52 177end-sanitize-r5900
GDB Binutils - Deliverables
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