Commit | Line | Data |
---|---|---|
41ab9a4b DE |
1 | Thu May 14 11:48:35 1998 Doug Evans <devans@canuck.cygnus.com> |
2 | ||
3 | * lib/sim-defs.exp (sim_run): Fix handling of output redirection. | |
4 | New arg prog_opts. All callers updated. | |
5 | ||
6 | Fri May 8 18:10:28 1998 Jillian Ye <jillian@cygnus.com> | |
7 | ||
8 | * Makefile.in: Made "check" the target of two | |
9 | dependencies (test1, test2) so that test2 get a chance to | |
10 | run even when test1 failed if "make -k check" is used. | |
11 | ||
801354e7 DE |
12 | Fri May 8 14:41:28 1998 Doug Evans <devans@canuck.cygnus.com> |
13 | ||
14 | * lib/sim-defs.exp (sim_version): Simplify. | |
15 | (sim_run): Implement. | |
16 | (run_sim_test): Use sim_run. | |
17 | (sim_compile): New proc. | |
18 | ||
19 | Mon May 4 17:59:11 1998 Frank Ch. Eigler <fche@cygnus.com> | |
20 | ||
21 | start-sanitize-sky | |
22 | * configure.in (testdir): Don't use old sky test directory. | |
23 | * configure: Regenerated | |
24 | * sky/Makefile.in: swallow stderr on buggy tests | |
25 | end-sanitize-sky | |
26 | * config/default.exp: Added C compiler settings. | |
27 | ||
dca2d4f4 DE |
28 | Wed Apr 22 12:26:28 1998 Doug Evans <devans@canuck.cygnus.com> |
29 | ||
30 | * Makefile.in (TARGET_FLAGS_TO_PASS): Delete LIBS, LDFLAGS. | |
31 | ||
aa467704 DE |
32 | Tue Apr 21 10:49:03 1998 Doug Evans <devans@canuck.cygnus.com> |
33 | ||
34 | * lib/sim-defs.exp (run_sim_test): Don't exit early if one mach fails, | |
35 | try all machs. | |
36 | ||
581fd042 DE |
37 | * sim/m32r/addx.cgs: Test (-1)+(-1)+1. |
38 | ||
aa467704 DE |
39 | Fri Apr 17 16:00:52 1998 Doug Evans <devans@canuck.cygnus.com> |
40 | ||
41 | * sim/m32r/mv[ft]achi.cgs: Fix expected result | |
42 | (sign extension of top 8 bits). | |
43 | start-sanitize-m32rx | |
44 | * sim/m32r/mv[ft]achi-a.cgs: Ditto. | |
45 | end-sanitize-m32rx | |
46 | ||
489564e2 DE |
47 | start-sanitize-m32rx |
48 | Tue Apr 14 14:06:34 1998 Doug Evans <devans@canuck.cygnus.com> | |
49 | ||
50 | * sim/m32r/maclh1.cgs: Fix testcase. | |
51 | * sim/m32r/maclh1-2.cgs: New testcase. | |
52 | ||
53 | Tue Mar 3 19:09:09 1998 Doug Evans <devans@canuck.cygnus.com> | |
54 | ||
55 | * sim/m32r/sat.cgs: Change sath to sat. | |
56 | ||
57 | end-sanitize-m32rx | |
9495a61e DE |
58 | Wed Feb 25 11:01:17 1998 Doug Evans <devans@canuck.cygnus.com> |
59 | ||
60 | * Makefile.in (RUNTEST): Fix path to runtest. | |
61 | ||
559eba20 FCE |
62 | start-sanitize-sky |
63 | Tue Feb 24 19:47:56 1998 Frank Ch. Eigler <fche@cygnus.com> | |
64 | ||
65 | * configure.in (testdir): Added sky subdir for mips64r5900-sky-elf | |
66 | target. | |
67 | * configure: Regenerate. | |
68 | end-sanitize-sky | |
69 | ||
f83a90c4 NC |
70 | Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com> |
71 | ||
c801e51b | 72 | * sim/m32r/unlock.cgs: Fixed test. |
ab361c35 | 73 | * sim/m32r/mvfc.cgs: Fixed test. |
78cbe8f6 NC |
74 | * sim/m32r/remu.cgs: Fixed test. |
75 | ||
caa71f09 NC |
76 | * sim/m32r/bnc24.cgs: Test long BNC instruction. |
77 | * sim/m32r/bnc8.cgs: Test short BNC instruction. | |
78 | * sim/m32r/ld-plus.cgs: Test LD instruction. | |
79 | * sim/m32r/macwhi.cgs: Test MACWHI instruction. | |
80 | * sim/m32r/macwlo.cgs: Test MACWLO instruction. | |
81 | * sim/m32r/mulwhi.cgs: Test MULWHI instruction. | |
82 | * sim/m32r/mulwlo.cgs: Test MULWLO instruction. | |
83 | * sim/m32r/mvfachi.cgs: Test MVFACHI instruction. | |
84 | * sim/m32r/mvfaclo.cgs: Test MVFACLO instruction. | |
85 | * sim/m32r/mvtaclo.cgs: Test MVTACLO instruction. | |
f83a90c4 NC |
86 | * sim/m32r/addv.cgs: Test ADDV instruction. |
87 | * sim/m32r/addv3.cgs: Test ADDV3 instruction. | |
88 | * sim/m32r/addx.cgs: Test ADDX instruction. | |
89 | * sim/m32r/lock.cgs: Test LOCK instruction. | |
90 | * sim/m32r/neg.cgs: Test NEG instruction. | |
91 | * sim/m32r/not.cgs: Test NOT instruction. | |
92 | * sim/m32r/unlock.cgs: Test UNLOCK instruction. | |
caa71f09 NC |
93 | start-sanitize-m32rx |
94 | * sim/m32r/mvfachi-a.cgs: Test extended MVFACHI instruction. | |
aa467704 | 95 | * sim/m32r/mvfaclo-a.cgs: Test extended MVFACLO instruction. |
caa71f09 NC |
96 | * sim/m32r/mvtachi-a.cgs: Test extended MVTACHI instruction. |
97 | * sim/m32r/mvtaclo-a.cgs: Test extended MVTACLO instruction. | |
98 | end-sanitize-m32rx | |
d03da19e NC |
99 | Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com> |
100 | ||
e843e28b NC |
101 | * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an |
102 | address into a general register. | |
103 | ||
c4448eec NC |
104 | * sim/m32r/or3.cgs: Test OR3 instruction. |
105 | * sim/m32r/rach.cgs: Test RACH instruction. | |
106 | * sim/m32r/rem.cgs: Test REM instruction. | |
107 | * sim/m32r/sub.cgs: Test SUB instruction. | |
108 | * sim/m32r/mv.cgs: Test MV instruction. | |
109 | * sim/m32r/mul.cgs: Test MUL instruction. | |
67dfe6e8 NC |
110 | * sim/m32r/bl24.cgs: Test long BL instruction. |
111 | * sim/m32r/bl8.cgs: Test short BL instruction. | |
112 | * sim/m32r/blez.cgs: Test BLEZ instruction. | |
113 | * sim/m32r/bltz.cgs: Test BLTZ instruction. | |
114 | * sim/m32r/bne.cgs: Test BNE instruction. | |
115 | * sim/m32r/bnez.cgs: Test BNEZ instruction. | |
116 | * sim/m32r/bra24.cgs: Test long BRA instruction. | |
117 | * sim/m32r/bra8.cgs: Test short BRA instruction. | |
118 | * sim/m32r/jl.cgs: Test JL instruction. | |
119 | * sim/m32r/or.cgs: Test OR instruction. | |
120 | * sim/m32r/jmp.cgs: Test JMP instruction. | |
dfe9df58 NC |
121 | * sim/m32r/and.cgs: Test AND instruction. |
122 | * sim/m32r/and3.cgs: Test AND3 instruction. | |
123 | * sim/m32r/beq.cgs: Test BEQ instruction. | |
124 | * sim/m32r/beqz.cgs: Test BEQZ instruction. | |
125 | * sim/m32r/bgez.cgs: Test BGEZ instruction. | |
126 | * sim/m32r/bgtz.cgs: Test BGTZ instruction. | |
127 | * sim/m32r/cmp.cgs: Test CMP instruction. | |
128 | * sim/m32r/cmpi.cgs: Test CMPI instruction. | |
129 | * sim/m32r/cmpu.cgs: Test CMPU instruction. | |
130 | * sim/m32r/cmpui.cgs: Test CMPUI instruction. | |
131 | * sim/m32r/div.cgs: Test DIV instruction. | |
67dfe6e8 | 132 | * sim/m32r/divu.cgs: Test DIVU instruction. |
dfe9df58 | 133 | * sim/m32r/cmpeq.cgs: Test CMPEQ instruction. |
dfe9df58 NC |
134 | * sim/m32r/sll.cgs: Test SLL instruction. |
135 | * sim/m32r/sll3.cgs: Test SLL3 instruction. | |
136 | * sim/m32r/slli.cgs: Test SLLI instruction. | |
0a2f6d93 NC |
137 | * sim/m32r/sra.cgs: Test SRA instruction. |
138 | * sim/m32r/sra3.cgs: Test SRA3 instruction. | |
139 | * sim/m32r/srai.cgs: Test SRAI instruction. | |
140 | * sim/m32r/srl.cgs: Test SRL instruction. | |
141 | * sim/m32r/srl3.cgs: Test SRL3 instruction. | |
142 | * sim/m32r/srli.cgs: Test SRLI instruction. | |
143 | * sim/m32r/xor3.cgs: Test XOR3 instruction. | |
144 | * sim/m32r/xor.cgs: Test XOR instruction. | |
489564e2 | 145 | start-sanitize-m32rx |
67dfe6e8 NC |
146 | * sim/m32r/jnc.cgs: Test JNC instruction. |
147 | * sim/m32r/jc.cgs: Test JC instruction. | |
148 | * sim/m32r/cmpz.cgs: Test CMPZ instruction. | |
149 | * sim/m32r/bcl24.cgs: Test long version of BCL instruction | |
150 | * sim/m32r/bcl8.cgs: Test short BCL instruction. | |
151 | * sim/m32r/bncl24.cgs: Test long BNCL instruction. | |
152 | * sim/m32r/bncl8.cgs: Test short BNCL instruction. | |
153 | * sim/m32r/divh.cgs: Test DIVH instruction. | |
c4448eec | 154 | * sim/m32r/rach-dsi.cgs: Test extended RACH instruction. |
489564e2 | 155 | end-sanitize-m32rx |
ed063d52 DE |
156 | Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com> |
157 | ||
fdad7ba5 DE |
158 | * config/default.exp: New file. |
159 | * lib/sim-defs.exp: New file. | |
160 | * sim/m32r/*: m32r dejagnu simulator testsuite. | |
161 | ||
ed063d52 DE |
162 | * Makefile.in (build_alias): Define. |
163 | (arch): Define. | |
164 | (RUNTEST_FOR_TARGET): Delete. | |
165 | (RUNTEST): Fix. | |
d03da19e | 166 | (SCHEME,SCHEMEFLAGS,CGENDIR,CGENFLAGS): Define. |
ed063d52 DE |
167 | (check): Depend on site.exp. Run dejagnu. |
168 | (site.exp): New target. | |
169 | (cgen): New target. | |
170 | * configure.in: Call AC_CHECK_PROG(SCHEME) if using cgen. | |
171 | (arch): Define from target_cpu. | |
172 | * configure: Regenerate. | |
173 | ||
1a6eb36b AC |
174 | Wed Sep 17 10:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com> |
175 | ||
176 | * common/bits-gen.c (gen_bit): Pass in the full name of the macro. | |
177 | (gen_mask): Ditto. | |
178 | ||
179 | * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT. | |
180 | (calc): Add support for 8 bit version of macros. | |
181 | (main): Add tests for 8 bit versions of macros. | |
182 | (check_sext): Check SEXT of zero clears bits. | |
183 | ||
184 | * common/bits-gen.c (main): Generate tests for 8 bit versions of | |
185 | macros. | |
186 | ||
a2ab5e65 AC |
187 | Thu Sep 11 13:04:40 1997 Andrew Cagney <cagney@b1.cygnus.com> |
188 | ||
189 | * common/Make-common.in: New file, provide generic rules for | |
190 | running checks. | |
191 | ||
52352d38 AC |
192 | Mon Sep 1 16:43:55 1997 Andrew Cagney <cagney@b1.cygnus.com> |
193 | ||
194 | * configure.in (configdirs): Test for the target directory instead | |
195 | of matching on a target. | |
196 | ||
ed063d52 | 197 | start-sanitize-r5900 |
52352d38 AC |
198 | Tue Jul 15 13:43:20 1997 Andrew Cagney <cagney@sendai.cygnus.com> |
199 | ||
ed063d52 | 200 | * configure.in (configdirs): Configure mips64vr5900el |
52352d38 AC |
201 | directory. |
202 | * configure: Regenerate. | |
203 | ||
ed063d52 | 204 | end-sanitize-r5900 |