projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 1d7b4a70 MF |
1 | //Original:/proj/frio/dv/testcases/core/c_compi2opd_flags/c_compi2opd_flags.dsp |
| 2 | // Spec Reference: compi2opd dregs += imm7 flags (az, an, ac, av0) | |
| 3 | # mach: bfin | |
| 4 | ||
| 5 | #include "test.h" | |
| 6 | .include "testutils.inc" | |
| 7 | start | |
| 8 | ||
| 9 | INIT_R_REGS 0; | |
| 10 | ASTAT = R0; // initialize astat | |
| 11 | ||
| 12 | // AZ for R0 | |
| 13 | imm32 r0, 0x00000000; | |
| 14 | R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 15 | R7 = ASTAT; | |
| 16 | R0 += 1; // az = 0 an = 0 ac = 0 av0 = 0 | |
| 17 | R6 = ASTAT; | |
| 18 | R0 += -1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 19 | R5 = ASTAT; | |
| 20 | R1 = R0; | |
| 21 | R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 22 | R4 = ASTAT; | |
| 23 | R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 24 | R3 = ASTAT; | |
| 25 | CHECKREG r0, 0x00000000; | |
| 26 | CHECKREG r1, 0x00000000; | |
| 27 | CHECKREG r3, (_AC0|_AC0_COPY|_AZ); | |
| 28 | CHECKREG r4, (_AN); | |
| 29 | CHECKREG r5, (_AC0|_AC0_COPY|_AZ); | |
| 30 | CHECKREG r6, 0x00000000; | |
| 31 | CHECKREG r7, (_AZ); | |
| 32 | ||
| 33 | // AN, AC for R0 | |
| 34 | imm32 r0, 0xffffffff; | |
| 35 | R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 36 | R7 = ASTAT; | |
| 37 | R1 = R0; | |
| 38 | R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 39 | R6 = ASTAT; | |
| 40 | R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 41 | R5 = ASTAT; | |
| 42 | CHECKREG r0, 0xFFFFFFFF; | |
| 43 | CHECKREG r1, 0x00000000; | |
| 44 | CHECKREG r5, (_AN); | |
| 45 | CHECKREG r6, (_AZ); | |
| 46 | CHECKREG r7, (_AC0|_AC0_COPY|_AZ); | |
| 47 | ||
| 48 | // AC, AV0 for R0 | |
| 49 | imm32 r0, 0x7fffffff; | |
| 50 | R0 += 1; // az = 0 an = 1 ac = 0 av0 = 1 | |
| 51 | R7 = ASTAT; | |
| 52 | R1 = R0; | |
| 53 | R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 54 | R6 = ASTAT; | |
| 55 | R2 = R0; | |
| 56 | R0 += -1; // az = 0 an = 0 ac = 1 av0 = 0 | |
| 57 | R5 = ASTAT; | |
| 58 | CHECKREG r0, 0x7FFFFFFE; | |
| 59 | CHECKREG r1, 0x80000000; | |
| 60 | CHECKREG r2, 0x7FFFFFFF; | |
| 61 | CHECKREG r5, (_VS|_AC0|_AC0_COPY); | |
| 62 | CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); //C | |
| 63 | CHECKREG r7, (_VS|_V|_V_COPY|_AN); // A | |
| 64 | ||
| 65 | // AZ, AN, AC, AV0 for R0 | |
| 66 | R0 = 0; | |
| 67 | ASTAT = R0; | |
| 68 | imm32 r0, 0x80000000; | |
| 69 | R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 70 | R7 = ASTAT; | |
| 71 | R1 = R0; | |
| 72 | R0 += 1; // az = 1 an = 1 ac = 0 av0 = 1 | |
| 73 | R6 = ASTAT; | |
| 74 | R2 = R0; | |
| 75 | R0 += 1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 76 | R5 = ASTAT; | |
| 77 | CHECKREG r0, 0x80000001; | |
| 78 | CHECKREG r1, 0x7FFFFFFF; | |
| 79 | CHECKREG r2, 0x80000000; | |
| 80 | CHECKREG r5, (_VS|_AN); | |
| 81 | CHECKREG r6, (_VS|_V|_V_COPY|_AN); | |
| 82 | CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 83 | ||
| 84 | // AZ for R0 | |
| 85 | R1 = 0; | |
| 86 | ASTAT = R1; | |
| 87 | imm32 r1, 0x00000000; | |
| 88 | R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 89 | R7 = ASTAT; | |
| 90 | R1 += 1; // az = 0 an = 0 ac = 0 av0 = 0 | |
| 91 | R6 = ASTAT; | |
| 92 | R1 += -1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 93 | R5 = ASTAT; | |
| 94 | R0 = R1; | |
| 95 | R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 96 | R4 = ASTAT; | |
| 97 | R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 98 | R3 = ASTAT; | |
| 99 | CHECKREG r0, 0x00000000; | |
| 100 | CHECKREG r1, 0x00000000; | |
| 101 | CHECKREG r3, (_AC0|_AC0_COPY|_AZ); | |
| 102 | CHECKREG r4, (_AN); | |
| 103 | CHECKREG r5, (_AC0|_AC0_COPY|_AZ); | |
| 104 | CHECKREG r6, 0x00000000; | |
| 105 | CHECKREG r7, (_AZ); | |
| 106 | ||
| 107 | // AN, AC for R1 | |
| 108 | imm32 r1, 0xffffffff; | |
| 109 | R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 110 | R7 = ASTAT; | |
| 111 | R0 = R1; | |
| 112 | R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 113 | R6 = ASTAT; | |
| 114 | R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 115 | R5 = ASTAT; | |
| 116 | CHECKREG r0, 0x00000000; | |
| 117 | CHECKREG r1, 0xFFFFFFFF; | |
| 118 | CHECKREG r5, (_AN); | |
| 119 | CHECKREG r6, (_AZ); | |
| 120 | CHECKREG r7, (_AC0|_AC0_COPY|_AZ); | |
| 121 | ||
| 122 | // AC, AV0 for R1 | |
| 123 | imm32 r1, 0x7fffffff; | |
| 124 | R1 += 1; // az = 0 an = 1 ac = 0 av0 = 1 | |
| 125 | R7 = ASTAT; | |
| 126 | R0 = R1; | |
| 127 | R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 128 | R6 = ASTAT; | |
| 129 | R2 = R1; | |
| 130 | R1 += -1; // az = 0 an = 0 ac = 1 av0 = 0 | |
| 131 | R5 = ASTAT; | |
| 132 | CHECKREG r0, 0x80000000; | |
| 133 | CHECKREG r1, 0x7FFFFFFE; | |
| 134 | CHECKREG r2, 0x7FFFFFFF; | |
| 135 | CHECKREG r5, (_VS|_AC0|_AC0_COPY); | |
| 136 | CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 137 | CHECKREG r7, (_VS|_V|_V_COPY|_AN); | |
| 138 | ||
| 139 | // AZ, AN, AC, AV0 for R1 | |
| 140 | R1 = 0; | |
| 141 | ASTAT = R1; | |
| 142 | imm32 r1, 0x80000000; | |
| 143 | R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 144 | R7 = ASTAT; | |
| 145 | R0 = R1; | |
| 146 | R1 += 1; // az = 1 an = 1 ac = 0 av0 = 1 | |
| 147 | R6 = ASTAT; | |
| 148 | R2 = R1; | |
| 149 | R1 += 1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 150 | R5 = ASTAT; | |
| 151 | CHECKREG r0, 0x7FFFFFFF; | |
| 152 | CHECKREG r1, 0x80000001; | |
| 153 | CHECKREG r2, 0x80000000; | |
| 154 | CHECKREG r5, (_VS|_AN); | |
| 155 | CHECKREG r6, (_VS|_V|_V_COPY|_AN); | |
| 156 | CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 157 | ||
| 158 | // AZ for R2 | |
| 159 | imm32 r2, 0x00000000; | |
| 160 | ASTAT = R2; | |
| 161 | R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 162 | R7 = ASTAT; | |
| 163 | R2 += 1; // az = 0 an = 0 ac = 0 av0 = 0 | |
| 164 | R6 = ASTAT; | |
| 165 | R2 += -1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 166 | R5 = ASTAT; | |
| 167 | R1 = R2; | |
| 168 | R2 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 169 | R4 = ASTAT; | |
| 170 | R2 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 171 | R3 = ASTAT; | |
| 172 | CHECKREG r1, 0x00000000; | |
| 173 | CHECKREG r2, 0x00000000; | |
| 174 | CHECKREG r3, (_AC0|_AC0_COPY|_AZ); | |
| 175 | CHECKREG r4, (_AN); | |
| 176 | CHECKREG r5, (_AC0|_AC0_COPY|_AZ); | |
| 177 | CHECKREG r6, 0x00000000; | |
| 178 | CHECKREG r7, (_AZ); | |
| 179 | ||
| 180 | // AN, AC for R2 | |
| 181 | imm32 r2, 0xffffffff; | |
| 182 | R2 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 183 | R7 = ASTAT; | |
| 184 | R1 = R2; | |
| 185 | R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 186 | R6 = ASTAT; | |
| 187 | R2 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 188 | R5 = ASTAT; | |
| 189 | CHECKREG r2, 0xFFFFFFFF; | |
| 190 | CHECKREG r1, 0x00000000; | |
| 191 | CHECKREG r5, (_AN); | |
| 192 | CHECKREG r6, (_AZ); | |
| 193 | CHECKREG r7, (_AC0|_AC0_COPY|_AZ); | |
| 194 | ||
| 195 | // AC, AV0 for R2 | |
| 196 | imm32 r2, 0x7fffffff; | |
| 197 | R2 += 1; // az = 0 an = 1 ac = 0 av0 = 1 | |
| 198 | R7 = ASTAT; | |
| 199 | R0 = R2; | |
| 200 | R2 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 201 | R6 = ASTAT; | |
| 202 | R1 = R2; | |
| 203 | R2 += -1; // az = 0 an = 0 ac = 1 av0 = 0 | |
| 204 | R5 = ASTAT; | |
| 205 | CHECKREG r0, 0x80000000; | |
| 206 | CHECKREG r1, 0x7FFFFFFF; | |
| 207 | CHECKREG r2, 0x7FFFFFFE; | |
| 208 | CHECKREG r5, (_VS|_AC0|_AC0_COPY); | |
| 209 | CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 210 | CHECKREG r7, (_VS|_V|_V_COPY|_AN); | |
| 211 | ||
| 212 | // AZ, AN, AC, AV0 for R2 | |
| 213 | R2 = 0; | |
| 214 | ASTAT = R2; | |
| 215 | imm32 r2, 0x80000000; | |
| 216 | R2 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 217 | R7 = ASTAT; | |
| 218 | R0 = R2; | |
| 219 | R2 += 1; // az = 1 an = 1 ac = 0 av0 = 1 | |
| 220 | R6 = ASTAT; | |
| 221 | R1 = R2; | |
| 222 | R2 += 1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 223 | R5 = ASTAT; | |
| 224 | CHECKREG r0, 0x7FFFFFFF; | |
| 225 | CHECKREG r1, 0x80000000; | |
| 226 | CHECKREG r2, 0x80000001; | |
| 227 | CHECKREG r5, (_VS|_AN); | |
| 228 | CHECKREG r6, (_VS|_V|_V_COPY|_AN); | |
| 229 | CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 230 | ||
| 231 | // AZ for R3 | |
| 232 | imm32 r3, 0x00000000; | |
| 233 | ASTAT = R3; | |
| 234 | R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 235 | R7 = ASTAT; | |
| 236 | R3 += 1; // az = 0 an = 0 ac = 0 av0 = 0 | |
| 237 | R6 = ASTAT; | |
| 238 | R3 += -1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 239 | R5 = ASTAT; | |
| 240 | R0 = R3; | |
| 241 | R3 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 242 | R4 = ASTAT; | |
| 243 | R3 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 244 | R2 = ASTAT; | |
| 245 | CHECKREG r0, 0x00000000; | |
| 246 | CHECKREG r2, (_AC0|_AC0_COPY|_AZ); | |
| 247 | CHECKREG r3, 0x00000000; | |
| 248 | CHECKREG r4, (_AN); | |
| 249 | CHECKREG r5, (_AC0|_AC0_COPY|_AZ); | |
| 250 | CHECKREG r6, 0x00000000; | |
| 251 | CHECKREG r7, (_AZ); | |
| 252 | ||
| 253 | // AN, AC for R3 | |
| 254 | imm32 r3, 0xffffffff; | |
| 255 | R3 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 256 | R7 = ASTAT; | |
| 257 | R0 = R3; | |
| 258 | R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 259 | R6 = ASTAT; | |
| 260 | R3 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 261 | R5 = ASTAT; | |
| 262 | CHECKREG r0, 0x00000000; | |
| 263 | CHECKREG r3, 0xFFFFFFFF; | |
| 264 | CHECKREG r5, (_AN); | |
| 265 | CHECKREG r6, (_AZ); | |
| 266 | CHECKREG r7, (_AC0|_AC0_COPY|_AZ); | |
| 267 | ||
| 268 | // AC, AV0 for R3 | |
| 269 | imm32 r3, 0x7fffffff; | |
| 270 | R3 += 1; // az = 0 an = 1 ac = 0 av0 = 1 | |
| 271 | R7 = ASTAT; | |
| 272 | R0 = R3; | |
| 273 | R3 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 274 | R6 = ASTAT; | |
| 275 | R1 = R3; | |
| 276 | R3 += -1; // az = 0 an = 0 ac = 1 av0 = 0 | |
| 277 | R5 = ASTAT; | |
| 278 | CHECKREG r0, 0x80000000; | |
| 279 | CHECKREG r1, 0x7FFFFFFF; | |
| 280 | CHECKREG r3, 0x7FFFFFFE; | |
| 281 | CHECKREG r5, (_VS|_AC0|_AC0_COPY); | |
| 282 | CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 283 | CHECKREG r7, (_VS|_V|_V_COPY|_AN); | |
| 284 | ||
| 285 | // AZ, AN, AC, AV0 for R3 | |
| 286 | R3 = 0; | |
| 287 | ASTAT = R3; | |
| 288 | imm32 r3, 0x80000000; | |
| 289 | R3 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 290 | R7 = ASTAT; | |
| 291 | R0 = R3; | |
| 292 | R3 += 1; // az = 1 an = 1 ac = 0 av0 = 1 | |
| 293 | R6 = ASTAT; | |
| 294 | R1 = R3; | |
| 295 | R3 += 1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 296 | R5 = ASTAT; | |
| 297 | CHECKREG r0, 0x7FFFFFFF; | |
| 298 | CHECKREG r1, 0x80000000; | |
| 299 | CHECKREG r3, 0x80000001; | |
| 300 | CHECKREG r5, (_VS|_AN); | |
| 301 | CHECKREG r6, (_VS|_V|_V_COPY|_AN); | |
| 302 | CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 303 | ||
| 304 | // AZ for R4 | |
| 305 | imm32 r4, 0x00000000; | |
| 306 | ASTAT = R4; | |
| 307 | R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 308 | R7 = ASTAT; | |
| 309 | R4 += 1; // az = 0 an = 0 ac = 0 av0 = 0 | |
| 310 | R6 = ASTAT; | |
| 311 | R4 += -1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 312 | R5 = ASTAT; | |
| 313 | R1 = R4; | |
| 314 | R4 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 315 | R3 = ASTAT; | |
| 316 | R4 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 317 | R2 = ASTAT; | |
| 318 | CHECKREG r1, 0x00000000; | |
| 319 | CHECKREG r2, (_AC0|_AC0_COPY|_AZ); | |
| 320 | CHECKREG r3, (_AN); | |
| 321 | CHECKREG r4, 0x00000000; | |
| 322 | CHECKREG r5, (_AC0|_AC0_COPY|_AZ); | |
| 323 | CHECKREG r6, 0x00000000; | |
| 324 | CHECKREG r7, (_AZ); | |
| 325 | ||
| 326 | // AN, AC for R4 | |
| 327 | imm32 r4, 0xffffffff; | |
| 328 | R4 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 329 | R7 = ASTAT; | |
| 330 | R1 = R4; | |
| 331 | R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 332 | R6 = ASTAT; | |
| 333 | R4 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 334 | R5 = ASTAT; | |
| 335 | CHECKREG r1, 0x00000000; | |
| 336 | CHECKREG r4, 0xFFFFFFFF; | |
| 337 | CHECKREG r5, (_AN); | |
| 338 | CHECKREG r6, (_AZ); | |
| 339 | CHECKREG r7, (_AC0|_AC0_COPY|_AZ); | |
| 340 | ||
| 341 | // AC, AV0 for R4 | |
| 342 | imm32 r4, 0x7fffffff; | |
| 343 | R4 += 1; // az = 0 an = 1 ac = 0 av0 = 1 | |
| 344 | R7 = ASTAT; | |
| 345 | R1 = R4; | |
| 346 | R4 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 347 | R6 = ASTAT; | |
| 348 | R2 = R4; | |
| 349 | R4 += -1; // az = 0 an = 0 ac = 1 av0 = 0 | |
| 350 | R5 = ASTAT; | |
| 351 | CHECKREG r1, 0x80000000; | |
| 352 | CHECKREG r2, 0x7FFFFFFF; | |
| 353 | CHECKREG r4, 0x7FFFFFFE; | |
| 354 | CHECKREG r5, (_VS|_AC0|_AC0_COPY); | |
| 355 | CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 356 | CHECKREG r7, (_VS|_V|_V_COPY|_AN); | |
| 357 | ||
| 358 | // AZ, AN, AC, AV0 for R4 | |
| 359 | R4 = 0; | |
| 360 | ASTAT = R4; | |
| 361 | imm32 r4, 0x80000000; | |
| 362 | R4 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 363 | R7 = ASTAT; | |
| 364 | R1 = R4; | |
| 365 | R4 += 1; // az = 1 an = 1 ac = 0 av0 = 1 | |
| 366 | R6 = ASTAT; | |
| 367 | R2 = R4; | |
| 368 | R4 += 1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 369 | R5 = ASTAT; | |
| 370 | CHECKREG r1, 0x7FFFFFFF; | |
| 371 | CHECKREG r2, 0x80000000; | |
| 372 | CHECKREG r4, 0x80000001; | |
| 373 | CHECKREG r5, (_VS|_AN); | |
| 374 | CHECKREG r6, (_VS|_V|_V_COPY|_AN); | |
| 375 | CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 376 | ||
| 377 | // AZ for R5 | |
| 378 | imm32 r5, 0x00000000; | |
| 379 | ASTAT = R5; | |
| 380 | R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 381 | R7 = ASTAT; | |
| 382 | R5 += 1; // az = 0 an = 0 ac = 0 av0 = 0 | |
| 383 | R6 = ASTAT; | |
| 384 | R5 += -1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 385 | R2 = ASTAT; | |
| 386 | R0 = R5; | |
| 387 | R5 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 388 | R4 = ASTAT; | |
| 389 | R5 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 390 | R3 = ASTAT; | |
| 391 | CHECKREG r0, 0x00000000; | |
| 392 | CHECKREG r2, (_AC0|_AC0_COPY|_AZ); | |
| 393 | CHECKREG r3, (_AC0|_AC0_COPY|_AZ); | |
| 394 | CHECKREG r4, (_AN); | |
| 395 | CHECKREG r5, 0x00000000; | |
| 396 | CHECKREG r6, 0x00000000; | |
| 397 | CHECKREG r7, (_AZ); | |
| 398 | ||
| 399 | // AN, AC for R5 | |
| 400 | imm32 r5, 0xffffffff; | |
| 401 | R5 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 402 | R7 = ASTAT; | |
| 403 | R0 = R5; | |
| 404 | R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 405 | R6 = ASTAT; | |
| 406 | R5 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 407 | R4 = ASTAT; | |
| 408 | CHECKREG r0, 0x00000000; | |
| 409 | CHECKREG r4, (_AN); | |
| 410 | CHECKREG r5, 0xFFFFFFFF; | |
| 411 | CHECKREG r6, (_AZ); | |
| 412 | CHECKREG r7, (_AC0|_AC0_COPY|_AZ); | |
| 413 | ||
| 414 | // AC, AV0 for R5 | |
| 415 | imm32 r5, 0x7fffffff; | |
| 416 | R5 += 1; // az = 0 an = 1 ac = 0 av0 = 1 | |
| 417 | R7 = ASTAT; | |
| 418 | R0 = R5; | |
| 419 | R5 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 420 | R6 = ASTAT; | |
| 421 | R2 = R5; | |
| 422 | R5 += -1; // az = 0 an = 0 ac = 1 av0 = 0 | |
| 423 | R4 = ASTAT; | |
| 424 | CHECKREG r0, 0x80000000; | |
| 425 | CHECKREG r2, 0x7FFFFFFF; | |
| 426 | CHECKREG r4, (_VS|_AC0|_AC0_COPY); | |
| 427 | CHECKREG r5, 0x7FFFFFFE; | |
| 428 | CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 429 | CHECKREG r7, (_VS|_V|_V_COPY|_AN); | |
| 430 | ||
| 431 | // AZ, AN, AC, AV0 for R5 | |
| 432 | R5 = 0; | |
| 433 | ASTAT = R5; | |
| 434 | imm32 r5, 0x80000000; | |
| 435 | R5 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 436 | R7 = ASTAT; | |
| 437 | R0 = R5; | |
| 438 | R5 += 1; // az = 1 an = 1 ac = 0 av0 = 1 | |
| 439 | R6 = ASTAT; | |
| 440 | R2 = R5; | |
| 441 | R5 += 1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 442 | R4 = ASTAT; | |
| 443 | CHECKREG r0, 0x7FFFFFFF; | |
| 444 | CHECKREG r2, 0x80000000; | |
| 445 | CHECKREG r4, (_VS|_AN); | |
| 446 | CHECKREG r5, 0x80000001; | |
| 447 | CHECKREG r6, (_VS|_V|_V_COPY|_AN); | |
| 448 | CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 449 | ||
| 450 | // AZ for R6 | |
| 451 | imm32 r6, 0x00000000; | |
| 452 | ASTAT = R6; | |
| 453 | R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 454 | R7 = ASTAT; | |
| 455 | R6 += 1; // az = 0 an = 0 ac = 0 av0 = 0 | |
| 456 | R0 = ASTAT; | |
| 457 | R6 += -1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 458 | R5 = ASTAT; | |
| 459 | R1 = R6; | |
| 460 | R6 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 461 | R4 = ASTAT; | |
| 462 | R6 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 463 | R3 = ASTAT; | |
| 464 | CHECKREG r0, 0x00000000; | |
| 465 | CHECKREG r1, 0x00000000; | |
| 466 | CHECKREG r3, (_AC0|_AC0_COPY|_AZ); | |
| 467 | CHECKREG r4, (_AN); | |
| 468 | CHECKREG r5, (_AC0|_AC0_COPY|_AZ); | |
| 469 | CHECKREG r6, 0x00000000; | |
| 470 | CHECKREG r7, (_AZ); | |
| 471 | ||
| 472 | // AN, AC for R6 | |
| 473 | imm32 r6, 0xffffffff; | |
| 474 | R6 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 475 | R7 = ASTAT; | |
| 476 | R1 = R6; | |
| 477 | R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 478 | R4 = ASTAT; | |
| 479 | R6 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 480 | R5 = ASTAT; | |
| 481 | CHECKREG r1, 0x00000000; | |
| 482 | CHECKREG r4, (_AZ); | |
| 483 | CHECKREG r5, (_AN); | |
| 484 | CHECKREG r6, 0xFFFFFFFF; | |
| 485 | CHECKREG r7, (_AC0|_AC0_COPY|_AZ); | |
| 486 | ||
| 487 | // AC, AV0 for R6 | |
| 488 | R6 = 0; | |
| 489 | ASTAT = R6; | |
| 490 | imm32 r6, 0x7fffffff; | |
| 491 | R6 += 1; // az = 0 an = 1 ac = 0 av0 = 1 | |
| 492 | R7 = ASTAT; | |
| 493 | R0 = R6; | |
| 494 | R6 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 495 | R4 = ASTAT; | |
| 496 | R1 = R6; | |
| 497 | R6 += -1; // az = 0 an = 0 ac = 1 av0 = 0 | |
| 498 | R5 = ASTAT; | |
| 499 | CHECKREG r0, 0x80000000; | |
| 500 | CHECKREG r1, 0x7FFFFFFF; | |
| 501 | CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 502 | CHECKREG r5, (_VS|_AC0|_AC0_COPY); | |
| 503 | CHECKREG r6, 0x7FFFFFFE; | |
| 504 | CHECKREG r7, (_VS|_V|_V_COPY|_AN); | |
| 505 | ||
| 506 | // AZ, AN, AC, AV0 for R6 | |
| 507 | R6 = 0; | |
| 508 | ASTAT = R6; | |
| 509 | imm32 r6, 0x80000000; | |
| 510 | R6 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 511 | R7 = ASTAT; | |
| 512 | R0 = R6; | |
| 513 | R6 += 1; // az = 1 an = 1 ac = 0 av0 = 1 | |
| 514 | R4 = ASTAT; | |
| 515 | R1 = R6; | |
| 516 | R6 += 1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 517 | R5 = ASTAT; | |
| 518 | CHECKREG r0, 0x7FFFFFFF; | |
| 519 | CHECKREG r1, 0x80000000; | |
| 520 | CHECKREG r4, (_VS|_V|_V_COPY|_AN); | |
| 521 | CHECKREG r5, (_VS|_AN); | |
| 522 | CHECKREG r6, 0x80000001; | |
| 523 | CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 524 | ||
| 525 | // AZ for R7 | |
| 526 | imm32 r7, 0x00000000; | |
| 527 | ASTAT = R7; | |
| 528 | R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 529 | R1 = ASTAT; | |
| 530 | R7 += 1; // az = 0 an = 0 ac = 0 av0 = 0 | |
| 531 | R6 = ASTAT; | |
| 532 | R7 += -1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 533 | R5 = ASTAT; | |
| 534 | R0 = R7; | |
| 535 | R7 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 536 | R4 = ASTAT; | |
| 537 | R7 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 538 | R2 = ASTAT; | |
| 539 | CHECKREG r0, 0x00000000; | |
| 540 | CHECKREG r1, (_AZ); | |
| 541 | CHECKREG r2, (_AC0|_AC0_COPY|_AZ); | |
| 542 | CHECKREG r4, (_AN); | |
| 543 | CHECKREG r5, (_AC0|_AC0_COPY|_AZ); | |
| 544 | CHECKREG r6, 0x00000000; | |
| 545 | CHECKREG r7, 0x00000000; | |
| 546 | ||
| 547 | // AN, AC for R7 | |
| 548 | imm32 r7, 0xffffffff; | |
| 549 | R7 += 1; // az = 1 an = 0 ac = 1 av0 = 0 | |
| 550 | R4 = ASTAT; | |
| 551 | R0 = R7; | |
| 552 | R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 | |
| 553 | R6 = ASTAT; | |
| 554 | R7 += -1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 555 | R5 = ASTAT; | |
| 556 | CHECKREG r0, 0x00000000; | |
| 557 | CHECKREG r4, (_AC0|_AC0_COPY|_AZ); | |
| 558 | CHECKREG r5, (_AN); | |
| 559 | CHECKREG r6, (_AZ); | |
| 560 | CHECKREG r7, 0xFFFFFFFF; | |
| 561 | ||
| 562 | // AC, AV0 for R7 | |
| 563 | R7 = 0; | |
| 564 | ASTAT = R7; | |
| 565 | imm32 r7, 0x7fffffff; | |
| 566 | R7 += 1; // az = 0 an = 1 ac = 0 av0 = 1 | |
| 567 | R4 = ASTAT; | |
| 568 | R0 = R7; | |
| 569 | R7 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 570 | R6 = ASTAT; | |
| 571 | R1 = R7; | |
| 572 | R7 += -1; // az = 0 an = 0 ac = 1 av0 = 0 | |
| 573 | R5 = ASTAT; | |
| 574 | CHECKREG r0, 0x80000000; | |
| 575 | CHECKREG r1, 0x7FFFFFFF; | |
| 576 | CHECKREG r4, (_VS|_V|_V_COPY|_AN); | |
| 577 | CHECKREG r5, (_VS|_AC0|_AC0_COPY); | |
| 578 | CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 579 | CHECKREG r7, 0x7FFFFFFE; | |
| 580 | ||
| 581 | // AZ, AN, AC, AV0 for R7 | |
| 582 | R7 = 0; | |
| 583 | ASTAT = R7; | |
| 584 | imm32 r7, 0x80000000; | |
| 585 | R7 += -1; // az = 0 an = 0 ac = 1 av0 = 1 | |
| 586 | R4 = ASTAT; | |
| 587 | R0 = R7; | |
| 588 | R7 += 1; // az = 1 an = 1 ac = 0 av0 = 1 | |
| 589 | R6 = ASTAT; | |
| 590 | R1 = R7; | |
| 591 | R7 += 1; // az = 0 an = 1 ac = 0 av0 = 0 | |
| 592 | R5 = ASTAT; | |
| 593 | CHECKREG r0, 0x7FFFFFFF; | |
| 594 | CHECKREG r1, 0x80000000; | |
| 595 | CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); | |
| 596 | CHECKREG r5, (_VS|_AN); | |
| 597 | CHECKREG r6, (_VS|_V|_V_COPY|_AN); | |
| 598 | CHECKREG r7, 0x80000001; | |
| 599 | ||
| 600 | pass |