[deliverable/binutils-gdb.git] / sim / testsuite / sim / bfin / c_dsp32shift_a0alr.s

//Original:/proj/frio/dv/testcases/core/c_dsp32shift_a0alr/c_dsp32shift_a0alr.dsp
// Spec Reference: dsp32shift a0 ashift, lshift, rot
# mach: bfin

.include "testutils.inc"
	start

	R0 = 0;
	ASTAT = R0;

	imm32 r0, 0x11140000;
	imm32 r1, 0x012C003E;
	imm32 r2, 0x81359E24;
	imm32 r3, 0x81459E24;
	imm32 r4, 0xD159E268;
	imm32 r5, 0x51626AF2;
	imm32 r6, 0x9176AF36;
	imm32 r7, 0xE18BFF86;

	R0.L = 0;
	A0 = 0;
	A0.L = R1.L;
	A0.H = R1.H;
	A0 = ASHIFT A0 BY R0.L;	/* a0 = 0x00000000 */
	R2 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r2, 0x012C003E;

	R1.L = 1;
	A0.L = R2.L;
	A0.H = R2.H;
	A0 = ASHIFT A0 BY R1.L;	/* a0 = 0x00000000 */
	R3 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r3, 0x0258007C;

	R2.L = 15;
	A0.L = R3.L;
	A0.H = R3.H;
	A0 = ASHIFT A0 BY R2.L;	/* a0 = 0x00000000 */
	R4 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r4, 0x003E0000;

	R3.L = 31;
	A0.L = R4.L;
	A0.H = R4.H;
	A0 = ASHIFT A0 BY R3.L;	/* a0 = 0x00000000 */
	R5 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r5, 0x00000000;

	R4.L = -1;
	A0.L = R5.L;
	A0.H = R5.H;
	A0 = ASHIFT A0 BY R4.L;	/* a0 = 0x00000000 */
	R6 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r6, 0x00000000;

	R5.L = -16;
	A0 = 0;
	A0.L = R6.L;
	A0.H = R6.H;
	A0 = ASHIFT A0 BY R5.L;	/* a0 = 0x00000000 */
	R7 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r7, 0x00000000;

	R6.L = -31;
	A0.L = R7.L;
	A0.H = R7.H;
	A0 = ASHIFT A0 BY R6.L;	/* a0 = 0x00000000 */
	R0 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r0, 0x00000000;

	R7.L = -32;
	A0.L = R0.L;
	A0.H = R0.H;
	A0 = ASHIFT A0 BY R7.L;	/* a0 = 0x00000000 */
	R1 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r1, 0x00000000;

	imm32 r0, 0x12340000;
	imm32 r1, 0x028C003E;
	imm32 r2, 0x82159E24;
	imm32 r3, 0x82159E24;
	imm32 r4, 0xD259E268;
	imm32 r5, 0x52E26AF2;
	imm32 r6, 0x9226AF36;
	imm32 r7, 0xE26BFF86;

	R0.L = 0;
	A0 = 0;
	A0.L = R1.L;
	A0.H = R1.H;
	A0 = LSHIFT A0 BY R0.L;	/* a0 = 0x00000000 */
	R2 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r2, 0x028C003E;

	R1.L = 1;
	A0.L = R2.L;
	A0.H = R2.H;
	A0 = LSHIFT A0 BY R1.L;	/* a0 = 0x00000000 */
	R3 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r3, 0x0518007C;

	R2.L = 15;
	A0.L = R3.L;
	A0.H = R3.H;
	A0 = LSHIFT A0 BY R2.L;	/* a0 = 0x00000000 */
	R4 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r4, 0x003E0000;

	R3.L = 31;
	A0.L = R4.L;
	A0.H = R4.H;
	A0 = LSHIFT A0 BY R3.L;	/* a0 = 0x00000000 */
	R5 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r5, 0x00000000;

	R4.L = -1;
	A0.L = R5.L;
	A0.H = R5.H;
	A0 = LSHIFT A0 BY R4.L;	/* a0 = 0x00000000 */
	R6 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r6, 0x00000000;

	R5.L = -16;
	A0 = 0;
	A0.L = R6.L;
	A0.H = R6.H;
	A0 = LSHIFT A0 BY R5.L;	/* a0 = 0x00000000 */
	R7 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r7, 0x00000000;

	R6.L = -31;
	A0.L = R7.L;
	A0.H = R7.H;
	A0 = LSHIFT A0 BY R6.L;	/* a0 = 0x00000000 */
	R0 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r0, 0x00000000;

	R7.L = -32;
	A0.L = R0.L;
	A0.H = R0.H;
	A0 = LSHIFT A0 BY R7.L;	/* a0 = 0x00000000 */
	R1 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r1, 0x00000000;

	imm32 r0, 0x13340000;
	imm32 r1, 0x038C003E;
	imm32 r2, 0x83159E24;
	imm32 r3, 0x83159E24;
	imm32 r4, 0xD359E268;
	imm32 r5, 0x53E26AF2;
	imm32 r6, 0x9326AF36;
	imm32 r7, 0xE36BFF86;

	R0.L = 0;
	A0 = 0;
	A0.L = R1.L;
	A0.H = R1.H;
	A0 = ROT A0 BY R0.L;	/* a0 = 0x00000000 */
	R2 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r2, 0x038C003E;

	R1.L = 1;
	A0.L = R2.L;
	A0.H = R2.H;
	A0 = ROT A0 BY R1.L;	/* a0 = 0x00000000 */
	R3 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r3, 0x0718007C;

	R2.L = 15;
	A0.L = R3.L;
	A0.H = R3.H;
	A0 = ROT A0 BY R2.L;	/* a0 = 0x00000000 */
	R4 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r4, 0x003E0001;

	R3.L = 31;
	A0.L = R4.L;
	A0.H = R4.H;
	A0 = ROT A0 BY R3.L;	/* a0 = 0x00000000 */
	R5 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r5, 0xE3000F80;

	R4.L = -1;
	A0.L = R5.L;
	A0.H = R5.H;
	A0 = ROT A0 BY R4.L;	/* a0 = 0x00000000 */
	R6 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r6, 0x718007C0;

	R5.L = -16;
	A0.L = R6.L;
	A0.H = R6.H;
	A0 = ROT A0 BY R5.L;	/* a0 = 0x00000000 */
	R7 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r7, 0x80007180;

	R6.L = -31;
	A0.L = R7.L;
	A0.H = R7.H;
	A0 = ROT A0 BY R6.L;	/* a0 = 0x00000000 */
	R0 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r0, 0x01C6001F;

	R7.L = -32;
	A0.L = R0.L;
	A0.H = R0.H;
	A0 = ROT A0 BY R7.L;	/* a0 = 0x00000000 */
	R1 = A0.w;	/* r5 = 0x00000000 */
	CHECKREG r1, 0x8C003E00;

	pass
Commit	Line	Data
1d7b4a70 MF	1	//Original:/proj/frio/dv/testcases/core/c_dsp32shift_a0alr/c_dsp32shift_a0alr.dsp
	2	// Spec Reference: dsp32shift a0 ashift, lshift, rot
	3	# mach: bfin
	4
	5	.include "testutils.inc"
	6	start
	7
	8	R0 = 0;
	9	ASTAT = R0;
	10
	11	imm32 r0, 0x11140000;
	12	imm32 r1, 0x012C003E;
	13	imm32 r2, 0x81359E24;
	14	imm32 r3, 0x81459E24;
	15	imm32 r4, 0xD159E268;
	16	imm32 r5, 0x51626AF2;
	17	imm32 r6, 0x9176AF36;
	18	imm32 r7, 0xE18BFF86;
	19
	20	R0.L = 0;
	21	A0 = 0;
	22	A0.L = R1.L;
	23	A0.H = R1.H;
	24	A0 = ASHIFT A0 BY R0.L; /* a0 = 0x00000000 */
	25	R2 = A0.w; /* r5 = 0x00000000 */
	26	CHECKREG r2, 0x012C003E;
	27
	28	R1.L = 1;
	29	A0.L = R2.L;
	30	A0.H = R2.H;
	31	A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00000000 */
	32	R3 = A0.w; /* r5 = 0x00000000 */
	33	CHECKREG r3, 0x0258007C;
	34
	35	R2.L = 15;
	36	A0.L = R3.L;
	37	A0.H = R3.H;
	38	A0 = ASHIFT A0 BY R2.L; /* a0 = 0x00000000 */
	39	R4 = A0.w; /* r5 = 0x00000000 */
	40	CHECKREG r4, 0x003E0000;
	41
	42	R3.L = 31;
	43	A0.L = R4.L;
	44	A0.H = R4.H;
	45	A0 = ASHIFT A0 BY R3.L; /* a0 = 0x00000000 */
	46	R5 = A0.w; /* r5 = 0x00000000 */
	47	CHECKREG r5, 0x00000000;
	48
	49	R4.L = -1;
	50	A0.L = R5.L;
	51	A0.H = R5.H;
	52	A0 = ASHIFT A0 BY R4.L; /* a0 = 0x00000000 */
	53	R6 = A0.w; /* r5 = 0x00000000 */
	54	CHECKREG r6, 0x00000000;
	55
	56	R5.L = -16;
	57	A0 = 0;
	58	A0.L = R6.L;
	59	A0.H = R6.H;
	60	A0 = ASHIFT A0 BY R5.L; /* a0 = 0x00000000 */
	61	R7 = A0.w; /* r5 = 0x00000000 */
	62	CHECKREG r7, 0x00000000;
	63
	64	R6.L = -31;
65	A0.L = R7.L;
66	A0.H = R7.H;
67	A0 = ASHIFT A0 BY R6.L; /* a0 = 0x00000000 */
68	R0 = A0.w; /* r5 = 0x00000000 */
69	CHECKREG r0, 0x00000000;
70
71	R7.L = -32;
72	A0.L = R0.L;
73	A0.H = R0.H;
74	A0 = ASHIFT A0 BY R7.L; /* a0 = 0x00000000 */
75	R1 = A0.w; /* r5 = 0x00000000 */
76	CHECKREG r1, 0x00000000;
77
78	imm32 r0, 0x12340000;
79	imm32 r1, 0x028C003E;
80	imm32 r2, 0x82159E24;
81	imm32 r3, 0x82159E24;
82	imm32 r4, 0xD259E268;
83	imm32 r5, 0x52E26AF2;
84	imm32 r6, 0x9226AF36;
85	imm32 r7, 0xE26BFF86;
86
87	R0.L = 0;
88	A0 = 0;
89	A0.L = R1.L;
90	A0.H = R1.H;
91	A0 = LSHIFT A0 BY R0.L; /* a0 = 0x00000000 */
92	R2 = A0.w; /* r5 = 0x00000000 */
93	CHECKREG r2, 0x028C003E;
94
95	R1.L = 1;
96	A0.L = R2.L;
97	A0.H = R2.H;
98	A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00000000 */
99	R3 = A0.w; /* r5 = 0x00000000 */
100	CHECKREG r3, 0x0518007C;
101
102	R2.L = 15;
103	A0.L = R3.L;
104	A0.H = R3.H;
105	A0 = LSHIFT A0 BY R2.L; /* a0 = 0x00000000 */
106	R4 = A0.w; /* r5 = 0x00000000 */
107	CHECKREG r4, 0x003E0000;
108
109	R3.L = 31;
110	A0.L = R4.L;
111	A0.H = R4.H;
112	A0 = LSHIFT A0 BY R3.L; /* a0 = 0x00000000 */
113	R5 = A0.w; /* r5 = 0x00000000 */
114	CHECKREG r5, 0x00000000;
115
116	R4.L = -1;
117	A0.L = R5.L;
118	A0.H = R5.H;
119	A0 = LSHIFT A0 BY R4.L; /* a0 = 0x00000000 */
120	R6 = A0.w; /* r5 = 0x00000000 */
121	CHECKREG r6, 0x00000000;
122
123	R5.L = -16;
124	A0 = 0;
125	A0.L = R6.L;
126	A0.H = R6.H;
127	A0 = LSHIFT A0 BY R5.L; /* a0 = 0x00000000 */
128	R7 = A0.w; /* r5 = 0x00000000 */
129	CHECKREG r7, 0x00000000;
130
131	R6.L = -31;
132	A0.L = R7.L;
133	A0.H = R7.H;
134	A0 = LSHIFT A0 BY R6.L; /* a0 = 0x00000000 */
135	R0 = A0.w; /* r5 = 0x00000000 */
136	CHECKREG r0, 0x00000000;
137
138	R7.L = -32;
139	A0.L = R0.L;
140	A0.H = R0.H;
141	A0 = LSHIFT A0 BY R7.L; /* a0 = 0x00000000 */
142	R1 = A0.w; /* r5 = 0x00000000 */
143	CHECKREG r1, 0x00000000;
144
145	imm32 r0, 0x13340000;
146	imm32 r1, 0x038C003E;
147	imm32 r2, 0x83159E24;
148	imm32 r3, 0x83159E24;
149	imm32 r4, 0xD359E268;
150	imm32 r5, 0x53E26AF2;
151	imm32 r6, 0x9326AF36;
152	imm32 r7, 0xE36BFF86;
153
154	R0.L = 0;
155	A0 = 0;
156	A0.L = R1.L;
157	A0.H = R1.H;
158	A0 = ROT A0 BY R0.L; /* a0 = 0x00000000 */
159	R2 = A0.w; /* r5 = 0x00000000 */
160	CHECKREG r2, 0x038C003E;
161
162	R1.L = 1;
163	A0.L = R2.L;
164	A0.H = R2.H;
165	A0 = ROT A0 BY R1.L; /* a0 = 0x00000000 */
166	R3 = A0.w; /* r5 = 0x00000000 */
167	CHECKREG r3, 0x0718007C;
168
169	R2.L = 15;
170	A0.L = R3.L;
171	A0.H = R3.H;
172	A0 = ROT A0 BY R2.L; /* a0 = 0x00000000 */
173	R4 = A0.w; /* r5 = 0x00000000 */
174	CHECKREG r4, 0x003E0001;
175
176	R3.L = 31;
177	A0.L = R4.L;
178	A0.H = R4.H;
179	A0 = ROT A0 BY R3.L; /* a0 = 0x00000000 */
180	R5 = A0.w; /* r5 = 0x00000000 */
181	CHECKREG r5, 0xE3000F80;
182
183	R4.L = -1;
184	A0.L = R5.L;
185	A0.H = R5.H;
186	A0 = ROT A0 BY R4.L; /* a0 = 0x00000000 */
187	R6 = A0.w; /* r5 = 0x00000000 */
188	CHECKREG r6, 0x718007C0;
189
190	R5.L = -16;
191	A0.L = R6.L;
192	A0.H = R6.H;
193	A0 = ROT A0 BY R5.L; /* a0 = 0x00000000 */
194	R7 = A0.w; /* r5 = 0x00000000 */
195	CHECKREG r7, 0x80007180;
196
197	R6.L = -31;
198	A0.L = R7.L;
199	A0.H = R7.H;
200	A0 = ROT A0 BY R6.L; /* a0 = 0x00000000 */
201	R0 = A0.w; /* r5 = 0x00000000 */
202	CHECKREG r0, 0x01C6001F;
203
204	R7.L = -32;
205	A0.L = R0.L;
206	A0.H = R0.H;
207	A0 = ROT A0 BY R7.L; /* a0 = 0x00000000 */
208	R1 = A0.w; /* r5 = 0x00000000 */
209	CHECKREG r1, 0x8C003E00;
210
211	pass