Commit | Line | Data |
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1d7b4a70 MF |
1 | //Original:/testcases/core/c_dsp32shiftim_lhalf_rn/c_dsp32shiftim_lhalf_rn.dsp |
2 | // Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) | |
3 | # mach: bfin | |
4 | ||
5 | .include "testutils.inc" | |
6 | start | |
7 | ||
8 | ||
9 | ||
10 | // lshift : neg data, count (+)=left (half reg) | |
11 | // d_lo = lshift (d_lo BY d_lo) | |
12 | // RLx by RLx | |
13 | imm32 r0, 0x00000000; | |
14 | R0.L = -1; | |
15 | imm32 r1, 0x00008001; | |
16 | imm32 r2, 0x00008002; | |
17 | imm32 r3, 0x00008003; | |
18 | imm32 r4, 0x00008004; | |
19 | imm32 r5, 0x00008005; | |
20 | imm32 r6, 0x00008006; | |
21 | imm32 r7, 0x00008007; | |
22 | R0.L = R0.L >> 1; | |
23 | R1.L = R1.L >> 2; | |
24 | R2.L = R2.L >> 3; | |
25 | R3.L = R3.L >> 4; | |
26 | R4.L = R4.L >> 5; | |
27 | R5.L = R5.L >> 6; | |
28 | R6.L = R6.L >> 7; | |
29 | R7.L = R7.L >> 8; | |
30 | CHECKREG r0, 0x00007FFF; | |
31 | CHECKREG r1, 0x00002000; | |
32 | CHECKREG r2, 0x00001000; | |
33 | CHECKREG r3, 0x00000800; | |
34 | CHECKREG r4, 0x00000400; | |
35 | CHECKREG r5, 0x00000200; | |
36 | CHECKREG r6, 0x00000100; | |
37 | CHECKREG r7, 0x00000080; | |
38 | ||
39 | imm32 r0, 0x00008001; | |
40 | R1.L = -1; | |
41 | imm32 r2, 0x00008002; | |
42 | imm32 r3, 0x00008003; | |
43 | imm32 r4, 0x00008004; | |
44 | imm32 r5, 0x00008005; | |
45 | imm32 r6, 0x00008006; | |
46 | imm32 r7, 0x00008007; | |
47 | R0.L = R0.L >> 9; | |
48 | R1.L = R1.L >> 10; | |
49 | R2.L = R2.L >> 11; | |
50 | R3.L = R3.L >> 12; | |
51 | R4.L = R4.L >> 13; | |
52 | R5.L = R5.L >> 14; | |
53 | R6.L = R6.L >> 15; | |
54 | R7.L = R7.L >> 10; | |
55 | CHECKREG r0, 0x00000040; | |
56 | CHECKREG r1, 0x0000003F; | |
57 | CHECKREG r2, 0x00000010; | |
58 | CHECKREG r3, 0x00000008; | |
59 | CHECKREG r4, 0x00000004; | |
60 | CHECKREG r5, 0x00000002; | |
61 | CHECKREG r6, 0x00000001; | |
62 | CHECKREG r7, 0x00000020; | |
63 | ||
64 | ||
65 | imm32 r0, 0x30008001; | |
66 | imm32 r1, 0x30008001; | |
67 | R2.L = -15; | |
68 | imm32 r3, 0x30008003; | |
69 | imm32 r4, 0x30008004; | |
70 | imm32 r5, 0x30008005; | |
71 | imm32 r6, 0x30008006; | |
72 | imm32 r7, 0x30008007; | |
73 | R7.L = R0.L >> 1; | |
74 | R6.L = R1.L >> 2; | |
75 | R5.L = R2.L >> 3; | |
76 | R4.L = R3.L >> 4; | |
77 | R3.L = R4.L >> 5; | |
78 | R2.L = R5.L >> 6; | |
79 | R0.L = R7.L >> 8; | |
80 | R1.L = R6.L >> 7; | |
81 | CHECKREG r0, 0x30000040; | |
82 | CHECKREG r1, 0x30000040; | |
83 | CHECKREG r2, 0x0000007F; | |
84 | CHECKREG r3, 0x30000040; | |
85 | CHECKREG r4, 0x30000800; | |
86 | CHECKREG r5, 0x30001FFE; | |
87 | CHECKREG r6, 0x30002000; | |
88 | CHECKREG r7, 0x30004000; | |
89 | ||
90 | imm32 r0, 0x00008001; | |
91 | imm32 r1, 0x00008001; | |
92 | imm32 r2, 0x00008002; | |
93 | R3.L = -16; | |
94 | imm32 r4, 0x00008004; | |
95 | imm32 r5, 0x00008005; | |
96 | imm32 r6, 0x00008006; | |
97 | imm32 r7, 0x00008007; | |
98 | R6.L = R0.L >> 13; | |
99 | R5.L = R1.L >> 13; | |
100 | R4.L = R2.L >> 13; | |
101 | R3.L = R3.L >> 13; | |
102 | R2.L = R4.L >> 13; | |
103 | R1.L = R5.L >> 13; | |
104 | R0.L = R6.L >> 13; | |
105 | R7.L = R7.L >> 13; | |
106 | CHECKREG r0, 0x00000000; | |
107 | CHECKREG r1, 0x00000000; | |
108 | CHECKREG r2, 0x00000000; | |
109 | CHECKREG r3, 0x30000007; | |
110 | CHECKREG r4, 0x00000004; | |
111 | CHECKREG r5, 0x00000004; | |
112 | CHECKREG r6, 0x00000004; | |
113 | CHECKREG r7, 0x00000004; | |
114 | ||
115 | // d_lo = lshift (d_hi BY d_lo) | |
116 | // RHx by RLx | |
117 | imm32 r0, 0x00000000; | |
118 | imm32 r1, 0x80010000; | |
119 | imm32 r2, 0x80020000; | |
120 | imm32 r3, 0x80030000; | |
121 | imm32 r4, 0x80040000; | |
122 | imm32 r5, 0x80050000; | |
123 | imm32 r6, 0x80060000; | |
124 | imm32 r7, 0x80070000; | |
125 | R0.L = R0.H >> 1; | |
126 | R1.L = R1.H >> 1; | |
127 | R2.L = R2.H >> 1; | |
128 | R3.L = R3.H >> 1; | |
129 | R4.L = R4.H >> 1; | |
130 | R5.L = R5.H >> 1; | |
131 | R6.L = R6.H >> 1; | |
132 | R7.L = R7.H >> 1; | |
133 | CHECKREG r0, 0x00000000; | |
134 | CHECKREG r1, 0x80014000; | |
135 | CHECKREG r2, 0x80024001; | |
136 | CHECKREG r3, 0x80034001; | |
137 | CHECKREG r4, 0x80044002; | |
138 | CHECKREG r5, 0x80054002; | |
139 | CHECKREG r6, 0x80064003; | |
140 | CHECKREG r7, 0x80074003; | |
141 | ||
142 | imm32 r0, 0x80010000; | |
143 | R1.L = -1; | |
144 | imm32 r2, 0x80020000; | |
145 | imm32 r3, 0x80030000; | |
146 | imm32 r4, 0x80040000; | |
147 | imm32 r5, 0x80050000; | |
148 | imm32 r6, 0x80060000; | |
149 | imm32 r7, 0x80070000; | |
150 | R1.L = R0.H >> 10; | |
151 | R2.L = R1.H >> 11; | |
152 | R3.L = R2.H >> 12; | |
153 | R4.L = R3.H >> 13; | |
154 | R5.L = R4.H >> 14; | |
155 | R6.L = R5.H >> 15; | |
156 | R0.L = R7.H >> 15; | |
157 | R7.L = R6.H >> 15; | |
158 | CHECKREG r0, 0x80010001; | |
159 | CHECKREG r1, 0x80010020; | |
160 | CHECKREG r2, 0x80020010; | |
161 | CHECKREG r3, 0x80030008; | |
162 | CHECKREG r4, 0x80040004; | |
163 | CHECKREG r5, 0x80050002; | |
164 | CHECKREG r6, 0x80060001; | |
165 | CHECKREG r7, 0x80070001; | |
166 | ||
167 | ||
168 | imm32 r0, 0xa0010000; | |
169 | imm32 r1, 0xa0010000; | |
170 | R2.L = -15; | |
171 | imm32 r3, 0xa0030000; | |
172 | imm32 r4, 0xa0040000; | |
173 | imm32 r5, 0xa0050000; | |
174 | imm32 r6, 0xa0060000; | |
175 | imm32 r7, 0xa0070000; | |
176 | R2.L = R0.H >> 2; | |
177 | R3.L = R1.H >> 2; | |
178 | R4.L = R2.H >> 2; | |
179 | R5.L = R3.H >> 2; | |
180 | R6.L = R4.H >> 2; | |
181 | R7.L = R5.H >> 2; | |
182 | R0.L = R6.H >> 2; | |
183 | R1.L = R7.H >> 2; | |
184 | CHECKREG r0, 0xA0012801; | |
185 | CHECKREG r1, 0xA0012801; | |
186 | CHECKREG r2, 0x80022800; | |
187 | CHECKREG r3, 0xA0032800; | |
188 | CHECKREG r4, 0xA0042000; | |
189 | CHECKREG r5, 0xA0052800; | |
190 | CHECKREG r6, 0xA0062801; | |
191 | CHECKREG r7, 0xA0072801; | |
192 | ||
193 | imm32 r0, 0xb0010001; | |
194 | imm32 r1, 0xb0010001; | |
195 | imm32 r2, 0xb0020002; | |
196 | R3.L = -16; | |
197 | imm32 r4, 0xb0040004; | |
198 | imm32 r5, 0xb0050005; | |
199 | imm32 r6, 0xb0060006; | |
200 | imm32 r7, 0xb0070007; | |
201 | R3.L = R0.H >> 13; | |
202 | R4.L = R1.H >> 13; | |
203 | R5.L = R2.H >> 13; | |
204 | R6.L = R3.H >> 13; | |
205 | R7.L = R4.H >> 13; | |
206 | R0.L = R5.H >> 13; | |
207 | R1.L = R6.H >> 13; | |
208 | R2.L = R7.H >> 13; | |
209 | CHECKREG r0, 0xB0010005; | |
210 | CHECKREG r1, 0xB0010005; | |
211 | CHECKREG r2, 0xB0020005; | |
212 | CHECKREG r3, 0xA0030005; | |
213 | CHECKREG r4, 0xB0040005; | |
214 | CHECKREG r5, 0xB0050005; | |
215 | CHECKREG r6, 0xB0060005; | |
216 | CHECKREG r7, 0xB0070005; | |
217 | ||
218 | // d_hi = lshift (d_lo BY d_lo) | |
219 | // RLx by RLx | |
220 | imm32 r0, 0x00000001; | |
221 | imm32 r1, 0x00000001; | |
222 | imm32 r2, 0x00000002; | |
223 | imm32 r3, 0x00000003; | |
224 | imm32 r4, 0x00000004; | |
225 | imm32 r5, 0x00000005; | |
226 | imm32 r6, 0x00000006; | |
227 | imm32 r7, 0x00000007; | |
228 | R0.H = R0.L >> 14; | |
229 | R1.H = R1.L >> 14; | |
230 | R2.H = R2.L >> 14; | |
231 | R3.H = R3.L >> 14; | |
232 | R4.H = R4.L >> 14; | |
233 | R5.H = R5.L >> 14; | |
234 | R6.H = R6.L >> 14; | |
235 | R7.H = R7.L >> 14; | |
236 | CHECKREG r0, 0x00000001; | |
237 | CHECKREG r1, 0x00000001; | |
238 | CHECKREG r2, 0x00000002; | |
239 | CHECKREG r3, 0x00000003; | |
240 | CHECKREG r4, 0x00000004; | |
241 | CHECKREG r5, 0x00000005; | |
242 | CHECKREG r6, 0x00000006; | |
243 | CHECKREG r7, 0x00000007; | |
244 | ||
245 | imm32 r0, 0x00008001; | |
246 | imm32 r1, 0x00008001; | |
247 | imm32 r2, 0x00008002; | |
248 | imm32 r3, 0x00008003; | |
249 | imm32 r4, 0x00008004; | |
250 | R5.L = -1; | |
251 | imm32 r6, 0x00008006; | |
252 | imm32 r7, 0x00008007; | |
253 | R1.H = R0.L >> 5; | |
254 | R0.H = R7.L >> 5; | |
255 | R2.H = R1.L >> 5; | |
256 | R3.H = R2.L >> 5; | |
257 | R4.H = R3.L >> 5; | |
258 | R5.H = R4.L >> 5; | |
259 | R6.H = R5.L >> 5; | |
260 | R7.H = R6.L >> 5; | |
261 | CHECKREG r0, 0x04008001; | |
262 | CHECKREG r1, 0x04008001; | |
263 | CHECKREG r2, 0x04008002; | |
264 | CHECKREG r3, 0x04008003; | |
265 | CHECKREG r4, 0x04008004; | |
266 | CHECKREG r5, 0x0400FFFF; | |
267 | CHECKREG r6, 0x07FF8006; | |
268 | CHECKREG r7, 0x04008007; | |
269 | ||
270 | ||
271 | imm32 r0, 0x00009001; | |
272 | imm32 r1, 0x00009001; | |
273 | imm32 r2, 0x00009002; | |
274 | imm32 r3, 0x00009003; | |
275 | imm32 r4, 0x00009004; | |
276 | imm32 r5, 0x00009005; | |
277 | R6.L = -15; | |
278 | imm32 r7, 0x00009007; | |
279 | R3.H = R0.L >> 14; | |
280 | R4.H = R1.L >> 14; | |
281 | R5.H = R2.L >> 14; | |
282 | R6.H = R3.L >> 14; | |
283 | R7.H = R4.L >> 14; | |
284 | R0.H = R5.L >> 14; | |
285 | R1.H = R6.L >> 14; | |
286 | R2.H = R7.L >> 14; | |
287 | CHECKREG r0, 0x00029001; | |
288 | CHECKREG r1, 0x00039001; | |
289 | CHECKREG r2, 0x00029002; | |
290 | CHECKREG r3, 0x00029003; | |
291 | CHECKREG r4, 0x00029004; | |
292 | CHECKREG r5, 0x00029005; | |
293 | CHECKREG r6, 0x0002FFF1; | |
294 | CHECKREG r7, 0x00029007; | |
295 | ||
296 | imm32 r0, 0x0000a001; | |
297 | imm32 r1, 0x0000a001; | |
298 | imm32 r2, 0x0000a002; | |
299 | imm32 r3, 0x0000a003; | |
300 | imm32 r4, 0x0000a004; | |
301 | imm32 r5, 0x0000a005; | |
302 | imm32 r6, 0x0000a006; | |
303 | R7.L = -16; | |
304 | R4.H = R0.L >> 15; | |
305 | R5.H = R1.L >> 15; | |
306 | R6.H = R2.L >> 15; | |
307 | R7.H = R3.L >> 15; | |
308 | R0.H = R4.L >> 15; | |
309 | R1.H = R5.L >> 15; | |
310 | R2.H = R6.L >> 15; | |
311 | R3.H = R7.L >> 15; | |
312 | CHECKREG r0, 0x0001A001; | |
313 | CHECKREG r1, 0x0001A001; | |
314 | CHECKREG r2, 0x0001A002; | |
315 | CHECKREG r3, 0x0001A003; | |
316 | CHECKREG r4, 0x0001A004; | |
317 | CHECKREG r5, 0x0001A005; | |
318 | CHECKREG r6, 0x0001A006; | |
319 | CHECKREG r7, 0x0001FFF0; | |
320 | ||
321 | // d_lo = lshft (d_hi BY d_lo) | |
322 | // RHx by RLx | |
323 | imm32 r0, 0x80010000; | |
324 | imm32 r1, 0x80010000; | |
325 | imm32 r2, 0x80020000; | |
326 | imm32 r3, 0x80030000; | |
327 | R4.L = -1; | |
328 | imm32 r5, 0x80050000; | |
329 | imm32 r6, 0x80060000; | |
330 | imm32 r7, 0x80070000; | |
331 | R0.H = R0.H >> 4; | |
332 | R1.H = R1.H >> 4; | |
333 | R2.H = R2.H >> 4; | |
334 | R3.H = R3.H >> 4; | |
335 | R4.H = R4.H >> 4; | |
336 | R5.H = R5.H >> 4; | |
337 | R6.H = R6.H >> 4; | |
338 | R7.H = R7.H >> 4; | |
339 | CHECKREG r0, 0x08000000; | |
340 | CHECKREG r1, 0x08000000; | |
341 | CHECKREG r2, 0x08000000; | |
342 | CHECKREG r3, 0x08000000; | |
343 | CHECKREG r4, 0x0000FFFF; | |
344 | CHECKREG r5, 0x08000000; | |
345 | CHECKREG r6, 0x08000000; | |
346 | CHECKREG r7, 0x08000000; | |
347 | ||
348 | imm32 r0, 0x80010000; | |
349 | imm32 r1, 0x80010000; | |
350 | imm32 r2, 0x80020000; | |
351 | imm32 r3, 0x80030000; | |
352 | imm32 r4, 0x80040000; | |
353 | R5.L = -1; | |
354 | imm32 r6, 0x80060000; | |
355 | imm32 r7, 0x80070000; | |
356 | R1.H = R0.H >> 15; | |
357 | R2.H = R1.H >> 15; | |
358 | R3.H = R2.H >> 15; | |
359 | R4.H = R3.H >> 15; | |
360 | R5.H = R4.H >> 15; | |
361 | R6.H = R5.H >> 15; | |
362 | R0.H = R7.H >> 15; | |
363 | R7.H = R6.H >> 15; | |
364 | CHECKREG r0, 0x00010000; | |
365 | CHECKREG r1, 0x00010000; | |
366 | CHECKREG r2, 0x00000000; | |
367 | CHECKREG r3, 0x00000000; | |
368 | CHECKREG r4, 0x00000000; | |
369 | CHECKREG r5, 0x0000FFFF; | |
370 | CHECKREG r6, 0x00000000; | |
371 | CHECKREG r7, 0x00000000; | |
372 | ||
373 | ||
374 | imm32 r0, 0xd0010000; | |
375 | imm32 r1, 0xd0010000; | |
376 | imm32 r2, 0xd0020000; | |
377 | imm32 r3, 0xd0030000; | |
378 | imm32 r4, 0xd0040000; | |
379 | imm32 r5, 0xd0050000; | |
380 | R6.L = -15; | |
381 | imm32 r7, 0xd0070000; | |
382 | R3.H = R0.H >> 6; | |
383 | R4.H = R1.H >> 6; | |
384 | R5.H = R2.H >> 6; | |
385 | R6.H = R3.H >> 6; | |
386 | R7.H = R4.H >> 6; | |
387 | R0.H = R5.H >> 6; | |
388 | R1.H = R6.H >> 6; | |
389 | R2.H = R7.H >> 6; | |
390 | CHECKREG r0, 0x000D0000; | |
391 | CHECKREG r1, 0x00000000; | |
392 | CHECKREG r2, 0x00000000; | |
393 | CHECKREG r3, 0x03400000; | |
394 | CHECKREG r4, 0x03400000; | |
395 | CHECKREG r5, 0x03400000; | |
396 | CHECKREG r6, 0x000DFFF1; | |
397 | CHECKREG r7, 0x000D0000; | |
398 | ||
399 | imm32 r0, 0xe0010000; | |
400 | imm32 r1, 0xe0010000; | |
401 | imm32 r2, 0xe0020000; | |
402 | imm32 r3, 0xe0030000; | |
403 | imm32 r4, 0xe0040000; | |
404 | imm32 r5, 0xe0050000; | |
405 | imm32 r6, 0xe0060000; | |
406 | R7.L = -16; | |
407 | R4.H = R0.H >> 7; | |
408 | R5.H = R1.H >> 7; | |
409 | R6.H = R2.H >> 7; | |
410 | R7.H = R3.H >> 7; | |
411 | R0.H = R4.H >> 7; | |
412 | R1.H = R5.H >> 7; | |
413 | R2.H = R6.H >> 7; | |
414 | R3.H = R7.H >> 7; | |
415 | CHECKREG r0, 0x00030000; | |
416 | CHECKREG r1, 0x00030000; | |
417 | CHECKREG r2, 0x00030000; | |
418 | CHECKREG r3, 0x00030000; | |
419 | CHECKREG r4, 0x01C00000; | |
420 | CHECKREG r5, 0x01C00000; | |
421 | CHECKREG r6, 0x01C00000; | |
422 | CHECKREG r7, 0x01C0FFF0; | |
423 | ||
424 | pass |