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1d7b4a70 MF |
1 | //Original:/proj/frio/dv/testcases/core/c_mmr_loop_user_except/c_mmr_loop_user_except.dsp |
2 | // Spec Reference: c_mmr_loop_user_except | |
3 | # mach: bfin | |
4 | # sim: --environment operating | |
5 | ||
6 | #include "test.h" | |
7 | .include "testutils.inc" | |
8 | start | |
9 | ||
10 | include(gen_int.inc) | |
11 | include(selfcheck.inc) | |
12 | include(std.inc) | |
13 | include(mmrs.inc) | |
14 | ||
15 | #ifndef STACKSIZE | |
16 | #define STACKSIZE 0x10 | |
17 | #endif | |
18 | #ifndef ITABLE | |
19 | #define ITABLE 0xF0000000 | |
20 | #endif | |
21 | ||
22 | GEN_INT_INIT(ITABLE) // set location for interrupt table | |
23 | ||
24 | // | |
25 | // Reset/Bootstrap Code | |
26 | // (Here we set the processor operating modes, initialize registers | |
27 | // etc.) | |
28 | // | |
29 | ||
30 | BOOT: | |
31 | ||
32 | INIT_R_REGS(0); | |
33 | INIT_P_REGS(0); | |
34 | INIT_I_REGS(0); // initialize the dsp address regs | |
35 | INIT_M_REGS(0); | |
36 | INIT_L_REGS(0); | |
37 | INIT_B_REGS(0); | |
38 | //CHECK_INIT(p5, 0xe0000000); | |
39 | include(symtable.inc) | |
40 | CHECK_INIT_DEF(p5); | |
41 | ||
42 | ||
43 | ||
44 | CLI R1; // inhibit events during MMR writes | |
45 | ||
46 | LD32_LABEL(sp, USTACK); // setup the user stack pointer | |
47 | USP = SP; // and frame pointer | |
48 | ||
49 | LD32_LABEL(sp, KSTACK); // setup the stack pointer | |
50 | FP = SP; // and frame pointer | |
51 | ||
52 | LD32(p0, EVT0); // Setup Event Vectors and Handlers | |
53 | LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) | |
54 | [ P0 ++ ] = R0; | |
55 | ||
56 | LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) | |
57 | [ P0 ++ ] = R0; | |
58 | ||
59 | LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) | |
60 | [ P0 ++ ] = R0; | |
61 | ||
62 | LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) | |
63 | [ P0 ++ ] = R0; | |
64 | ||
65 | [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) | |
66 | ||
67 | ||
68 | LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) | |
69 | [ P0 ++ ] = R0; | |
70 | ||
71 | LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) | |
72 | [ P0 ++ ] = R0; | |
73 | ||
74 | LD32_LABEL(r0, I7HANDLE); // IVG7 Handler | |
75 | [ P0 ++ ] = R0; | |
76 | ||
77 | LD32_LABEL(r0, I8HANDLE); // IVG8 Handler | |
78 | [ P0 ++ ] = R0; | |
79 | ||
80 | LD32_LABEL(r0, I9HANDLE); // IVG9 Handler | |
81 | [ P0 ++ ] = R0; | |
82 | ||
83 | LD32_LABEL(r0, I10HANDLE);// IVG10 Handler | |
84 | [ P0 ++ ] = R0; | |
85 | ||
86 | LD32_LABEL(r0, I11HANDLE);// IVG11 Handler | |
87 | [ P0 ++ ] = R0; | |
88 | ||
89 | LD32_LABEL(r0, I12HANDLE);// IVG12 Handler | |
90 | [ P0 ++ ] = R0; | |
91 | ||
92 | // LD32_LABEL(r0, I13HANDLE);// IVG13 Handler | |
93 | // [p0++] = r0; | |
94 | ||
95 | // LD32_LABEL(r0, I14HANDLE);// IVG14 Handler | |
96 | // [p0++] = r0; | |
97 | ||
98 | //***************** | |
99 | // wrt-rd EVT13 = 0xFFE02034 | |
100 | LD32(p0, 0xFFE02034); | |
101 | LD32(r0, 0xDDDDABC6); | |
102 | [ P0 ] = R0; | |
103 | ||
104 | // wrt-rd EVT14 = 0xFFE02038 | |
105 | LD32(p0, 0xFFE02038); | |
106 | LD32(r0, 0xEEEEABC6); | |
107 | [ P0 ] = R0; | |
108 | //***************** | |
109 | LD32_LABEL(r0, I15HANDLE);// IVG15 Handler | |
110 | [ P0 ++ ] = R0; | |
111 | ||
112 | LD32(p0, EVT_OVERRIDE); | |
113 | R0 = 0; | |
114 | [ P0 ++ ] = R0; | |
115 | ||
116 | R1 = -1; // Change this to mask interrupts (*) | |
117 | CSYNC; // wait for MMR writes to finish | |
118 | STI R1; // sync and reenable events (implicit write to IMASK) | |
119 | ||
120 | DUMMY: | |
121 | ||
122 | R0 = 0 (Z); | |
123 | ||
124 | LT0 = r0; // set loop counters to something deterministic | |
125 | LB0 = r0; | |
126 | LC0 = r0; | |
127 | LT1 = r0; | |
128 | LB1 = r0; | |
129 | LC1 = r0; | |
130 | ||
131 | ASTAT = r0; // reset other internal regs | |
132 | SYSCFG = r0; | |
133 | RETS = r0; // prevent X's breaking LINK instruction | |
134 | ||
135 | ||
136 | // The following code sets up the test for running in USER mode | |
137 | ||
138 | LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a | |
139 | // ReturnFromInterrupt (RTI) | |
140 | RETI = r0; // We need to load the return address | |
141 | ||
142 | // Comment the following line for a USER Mode test | |
143 | ||
144 | // JUMP STARTSUP; // jump to code start for SUPERVISOR mode | |
145 | ||
146 | RTI; // execute this instr put us in USER mode | |
147 | ||
148 | STARTSUP: | |
149 | LD32_LABEL(p1, BEGIN); | |
150 | ||
151 | LD32(p0, EVT15); | |
152 | ||
153 | CLI R1; // inhibit events during write to MMR | |
154 | [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start | |
155 | CSYNC; // wait for it | |
156 | STI R1; // reenable events with proper imask | |
157 | ||
158 | RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in | |
159 | // USER MODE & go to different RAISE in USER mode | |
160 | // until the end of the test. | |
161 | ||
162 | RTI; | |
163 | ||
164 | // | |
165 | // The Main Program | |
166 | // | |
167 | STARTUSER: | |
168 | LD32_LABEL(sp, USTACK); // setup the stack pointer | |
169 | FP = SP; // set frame pointer | |
170 | // LINK 0; // change for how much stack frame space you need. | |
171 | ||
172 | JUMP BEGIN; | |
173 | ||
174 | //********************************************************************* | |
175 | ||
176 | BEGIN: | |
177 | ||
178 | // COMMENT the following line for USER MODE tests | |
179 | [ -- SP ] = RETI; // enable interrupts in supervisor mode | |
180 | ||
181 | // **** YOUR CODE GOES HERE **** | |
182 | ||
183 | ||
184 | ||
185 | // PUT YOUR TEST HERE! | |
186 | // Can't Raise 0, 3, or 4 | |
187 | // Raise 1 requires some intelligence so the test | |
188 | // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) | |
189 | // RAISE 2; // RTN // exception because we execute this in USER mode | |
190 | R0 = 0; | |
191 | LD32(p0, 0xFFE02034); | |
192 | P2 = 2; | |
193 | LSETUP ( start1 , end1 ) LC0 = P2; | |
194 | start1: | |
195 | R0 = [ P0 ++ ]; // 16 bit instr | |
196 | end1: R1 = R0; | |
197 | ||
198 | CHECKREG(r0, 0x00000000); | |
199 | CHECKREG(r1, 0x00000000); | |
200 | CHECKREG(r2, 0x00000000); | |
201 | //CHECKREG(r3, 0x00000030); | |
202 | CHECKREG(r4, 0x0000000F); | |
203 | CHECKREG(r5, 0x00000012); | |
204 | CHECKREG(r6, 0x00000015); | |
205 | CHECKREG(r7, 0x00000018); | |
206 | ||
207 | ||
208 | END: | |
209 | dbg_pass; // End the test | |
210 | ||
211 | //********************************************************************* | |
212 | ||
213 | // | |
214 | // Handlers for Events | |
215 | // | |
216 | ||
217 | EHANDLE: // Emulation Handler 0 | |
218 | RTE; | |
219 | ||
220 | RHANDLE: // Reset Handler 1 | |
221 | RTI; | |
222 | ||
223 | NHANDLE: // NMI Handler 2 | |
224 | R0 = RETN; | |
225 | R0 += 2; | |
226 | RETN = r0; | |
227 | RTN; | |
228 | ||
229 | XHANDLE: // Exception Handler 3 | |
230 | R3 = RETX; | |
231 | R4 += 5; | |
232 | R5 += 6; | |
233 | R6 += 7; | |
234 | R7 += 8; | |
235 | R3 += 2; // for resturn address | |
236 | RETX = r3; | |
237 | RTX; | |
238 | ||
239 | HWHANDLE: // HW Error Handler 5 | |
240 | R2 = RETI; | |
241 | R2 += 2; | |
242 | RETI = r2; | |
243 | RTI; | |
244 | ||
245 | THANDLE: // Timer Handler 6 | |
246 | R3 = RETI; | |
247 | R3 += 2; | |
248 | RETI = r3; | |
249 | RTI; | |
250 | ||
251 | I7HANDLE: // IVG 7 Handler | |
252 | R4 = RETI; | |
253 | R4 += 2; | |
254 | RETI = r4; | |
255 | RTI; | |
256 | ||
257 | I8HANDLE: // IVG 8 Handler | |
258 | R5 = RETI; | |
259 | R5 += 2; | |
260 | RETI = r5; | |
261 | RTI; | |
262 | ||
263 | I9HANDLE: // IVG 9 Handler | |
264 | R6 = RETI; | |
265 | R6 += 2; | |
266 | RETI = r6; | |
267 | RTI; | |
268 | ||
269 | I10HANDLE: // IVG 10 Handler | |
270 | R7 = RETI; | |
271 | R7 += 2; | |
272 | RETI = r7; | |
273 | RTI; | |
274 | ||
275 | I11HANDLE: // IVG 11 Handler | |
276 | I0 = R0; | |
277 | I1 = R1; | |
278 | I2 = R2; | |
279 | I3 = R3; | |
280 | M0 = R4; | |
281 | R0 = RETI; | |
282 | R0 += 2; | |
283 | RETI = r0; | |
284 | RTI; | |
285 | ||
286 | I12HANDLE: // IVG 12 Handler | |
287 | R1 = RETI; | |
288 | R1 += 2; | |
289 | RETI = r1; | |
290 | RTI; | |
291 | ||
292 | I13HANDLE: // IVG 13 Handler | |
293 | R2 = RETI; | |
294 | R2 += 2; | |
295 | RETI = r2; | |
296 | RTI; | |
297 | ||
298 | I14HANDLE: // IVG 14 Handler | |
299 | R3 = RETI; | |
300 | R3 += 2; | |
301 | RETI = r3; | |
302 | RTI; | |
303 | ||
304 | I15HANDLE: // IVG 15 Handler | |
305 | R4 = 15; | |
306 | RTI; | |
307 | ||
308 | NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug | |
309 | ||
310 | // | |
311 | // Data Segment | |
312 | // | |
313 | ||
314 | .data | |
315 | DATA: | |
316 | .space (0x10); | |
317 | ||
318 | // Stack Segments (Both Kernel and User) | |
319 | ||
320 | .space (STACKSIZE); | |
321 | KSTACK: | |
322 | ||
323 | .space (STACKSIZE); | |
324 | USTACK: | |
325 | // .space (STACKSIZE); // adding this may solve the problem |