Commit | Line | Data |
---|---|---|
1d7b4a70 MF |
1 | //Original:/proj/frio/dv/testcases/core/c_regmv_imlb_imlb/c_regmv_imlb_imlb.dsp |
2 | // Spec Reference: regmv imlb-imlb | |
3 | # mach: bfin | |
4 | ||
5 | .include "testutils.inc" | |
6 | start | |
7 | ||
8 | // initialize source regs | |
9 | imm32 i0, 0x11111111; | |
10 | imm32 i1, 0x22222222; | |
11 | imm32 i2, 0x33333333; | |
12 | imm32 i3, 0x44444444; | |
13 | imm32 m0, 0x55555555; | |
14 | imm32 m1, 0x66666666; | |
15 | imm32 m2, 0x77777777; | |
16 | imm32 m3, 0x88888888; | |
17 | imm32 l0, 0x99999999; | |
18 | imm32 l1, 0xAAAAAAAA; | |
19 | imm32 l2, 0xBBBBBBBB; | |
20 | imm32 l3, 0xCCCCCCCC; | |
21 | imm32 b0, 0xDDDDDDDD; | |
22 | imm32 b1, 0xEEEEEEEE; | |
23 | imm32 b2, 0xFFFFFFFF; | |
24 | imm32 b3, 0x12345667; | |
25 | ||
26 | //*******************i-i & m-m, i-m & m-i, l-l & b-b, l-b & b-l | |
27 | // i to i & m to m | |
28 | I0 = I0; | |
29 | I1 = I1; | |
30 | I2 = I2; | |
31 | I3 = I3; | |
32 | M0 = M0; | |
33 | M1 = M1; | |
34 | M2 = M2; | |
35 | M3 = M3; | |
36 | ||
37 | I0 = I1; | |
38 | I1 = I2; | |
39 | I2 = I3; | |
40 | I3 = I0; | |
41 | M0 = M1; | |
42 | M1 = M2; | |
43 | M2 = M3; | |
44 | M3 = M0; | |
45 | ||
46 | R0 = I0; | |
47 | R1 = I1; | |
48 | R2 = I2; | |
49 | R3 = I3; | |
50 | R4 = M0; | |
51 | R5 = M1; | |
52 | R6 = M2; | |
53 | R7 = M3; | |
54 | ||
55 | CHECKREG r0, 0x22222222; | |
56 | CHECKREG r1, 0x33333333; | |
57 | CHECKREG r2, 0x44444444; | |
58 | CHECKREG r3, 0x22222222; | |
59 | CHECKREG r4, 0x66666666; | |
60 | CHECKREG r5, 0x77777777; | |
61 | CHECKREG r6, 0x88888888; | |
62 | CHECKREG r7, 0x66666666; | |
63 | ||
64 | I0 = I2; | |
65 | I1 = I3; | |
66 | I2 = I0; | |
67 | I3 = I1; | |
68 | M0 = M2; | |
69 | M1 = M3; | |
70 | M2 = M0; | |
71 | M3 = M1; | |
72 | ||
73 | R0 = I0; | |
74 | R1 = I1; | |
75 | R2 = I2; | |
76 | R3 = I3; | |
77 | R4 = M0; | |
78 | R5 = M1; | |
79 | R6 = M2; | |
80 | R7 = M3; | |
81 | ||
82 | CHECKREG r0, 0x44444444; | |
83 | CHECKREG r1, 0x22222222; | |
84 | CHECKREG r2, 0x44444444; | |
85 | CHECKREG r3, 0x22222222; | |
86 | CHECKREG r4, 0x88888888; | |
87 | CHECKREG r5, 0x66666666; | |
88 | CHECKREG r6, 0x88888888; | |
89 | CHECKREG r7, 0x66666666; | |
90 | ||
91 | I0 = I3; | |
92 | I1 = I0; | |
93 | I2 = I1; | |
94 | I3 = I2; | |
95 | M0 = M3; | |
96 | M1 = M0; | |
97 | M2 = M1; | |
98 | M3 = M2; | |
99 | ||
100 | R0 = I0; | |
101 | R1 = I1; | |
102 | R2 = I2; | |
103 | R3 = I3; | |
104 | R4 = M0; | |
105 | R5 = M1; | |
106 | R6 = M2; | |
107 | R7 = M3; | |
108 | ||
109 | CHECKREG r0, 0x22222222; | |
110 | CHECKREG r1, 0x22222222; | |
111 | CHECKREG r2, 0x22222222; | |
112 | CHECKREG r3, 0x22222222; | |
113 | CHECKREG r4, 0x66666666; | |
114 | CHECKREG r5, 0x66666666; | |
115 | CHECKREG r6, 0x66666666; | |
116 | CHECKREG r7, 0x66666666; | |
117 | ||
118 | imm32 i0, 0xa1111110; | |
119 | imm32 i1, 0xb2222220; | |
120 | imm32 i2, 0xc3333330; | |
121 | imm32 i3, 0xd4444440; | |
122 | imm32 m0, 0xe5555550; | |
123 | imm32 m1, 0xf6666660; | |
124 | imm32 m2, 0x17777770; | |
125 | imm32 m3, 0x28888888; | |
126 | ||
127 | // m to i & i to m | |
128 | I0 = M0; | |
129 | I1 = M1; | |
130 | I2 = M2; | |
131 | I3 = M3; | |
132 | M0 = I0; | |
133 | M1 = I1; | |
134 | M2 = I2; | |
135 | M3 = I3; | |
136 | ||
137 | R0 = I0; | |
138 | R1 = I1; | |
139 | R2 = I2; | |
140 | R3 = I3; | |
141 | R4 = M0; | |
142 | R5 = M1; | |
143 | R6 = M2; | |
144 | R7 = M3; | |
145 | ||
146 | CHECKREG r0, 0xE5555550; | |
147 | CHECKREG r1, 0xF6666660; | |
148 | CHECKREG r2, 0x17777770; | |
149 | CHECKREG r3, 0x28888888; | |
150 | CHECKREG r4, 0xE5555550; | |
151 | CHECKREG r5, 0xF6666660; | |
152 | CHECKREG r6, 0x17777770; | |
153 | CHECKREG r7, 0x28888888; | |
154 | ||
155 | I0 = M1; | |
156 | I1 = M2; | |
157 | I2 = M3; | |
158 | I3 = M0; | |
159 | M0 = I1; | |
160 | M1 = I2; | |
161 | M2 = I3; | |
162 | M3 = I0; | |
163 | ||
164 | R0 = I0; | |
165 | R1 = I1; | |
166 | R2 = I2; | |
167 | R3 = I3; | |
168 | R4 = M0; | |
169 | R5 = M1; | |
170 | R6 = M2; | |
171 | R7 = M3; | |
172 | ||
173 | CHECKREG r0, 0xF6666660; | |
174 | CHECKREG r1, 0x17777770; | |
175 | CHECKREG r2, 0x28888888; | |
176 | CHECKREG r3, 0xE5555550; | |
177 | CHECKREG r4, 0x17777770; | |
178 | CHECKREG r5, 0x28888888; | |
179 | CHECKREG r6, 0xE5555550; | |
180 | CHECKREG r7, 0xF6666660; | |
181 | ||
182 | I0 = M2; | |
183 | I1 = M3; | |
184 | I2 = M0; | |
185 | I3 = M1; | |
186 | M0 = I2; | |
187 | M1 = I3; | |
188 | M2 = I0; | |
189 | M3 = I1; | |
190 | ||
191 | R0 = I0; | |
192 | R1 = I1; | |
193 | R2 = I2; | |
194 | R3 = I3; | |
195 | R4 = M0; | |
196 | R5 = M1; | |
197 | R6 = M2; | |
198 | R7 = M3; | |
199 | ||
200 | CHECKREG r0, 0xE5555550; | |
201 | CHECKREG r1, 0xF6666660; | |
202 | CHECKREG r2, 0x17777770; | |
203 | CHECKREG r3, 0x28888888; | |
204 | CHECKREG r4, 0x17777770; | |
205 | CHECKREG r5, 0x28888888; | |
206 | CHECKREG r6, 0xE5555550; | |
207 | CHECKREG r7, 0xF6666660; | |
208 | ||
209 | I0 = M3; | |
210 | I1 = M0; | |
211 | I2 = M1; | |
212 | I3 = M2; | |
213 | M0 = I3; | |
214 | M1 = I0; | |
215 | M2 = I1; | |
216 | M3 = I2; | |
217 | ||
218 | R0 = I0; | |
219 | R1 = I1; | |
220 | R2 = I2; | |
221 | R3 = I3; | |
222 | R4 = M0; | |
223 | R5 = M1; | |
224 | R6 = M2; | |
225 | R7 = M3; | |
226 | ||
227 | CHECKREG r0, 0xF6666660; | |
228 | CHECKREG r1, 0x17777770; | |
229 | CHECKREG r2, 0x28888888; | |
230 | CHECKREG r3, 0xE5555550; | |
231 | CHECKREG r4, 0xE5555550; | |
232 | CHECKREG r5, 0xF6666660; | |
233 | CHECKREG r6, 0x17777770; | |
234 | CHECKREG r7, 0x28888888; | |
235 | ||
236 | // l to l & b to b | |
237 | L0 = L0; | |
238 | L1 = L1; | |
239 | L2 = L2; | |
240 | L3 = L3; | |
241 | B0 = B0; | |
242 | B1 = B1; | |
243 | B2 = B2; | |
244 | B3 = B3; | |
245 | ||
246 | L0 = L1; | |
247 | L1 = L2; | |
248 | L2 = L3; | |
249 | L3 = L0; | |
250 | B0 = B1; | |
251 | B1 = B2; | |
252 | B2 = B3; | |
253 | B3 = B0; | |
254 | ||
255 | R0 = L0; | |
256 | R1 = L1; | |
257 | R2 = L2; | |
258 | R3 = L3; | |
259 | R4 = B0; | |
260 | R5 = B1; | |
261 | R6 = B2; | |
262 | R7 = B3; | |
263 | ||
264 | CHECKREG r0, 0xAAAAAAAA; | |
265 | CHECKREG r1, 0xBBBBBBBB; | |
266 | CHECKREG r2, 0xCCCCCCCC; | |
267 | CHECKREG r3, 0xAAAAAAAA; | |
268 | CHECKREG r4, 0xEEEEEEEE; | |
269 | CHECKREG r5, 0xFFFFFFFF; | |
270 | CHECKREG r6, 0x12345667; | |
271 | CHECKREG r7, 0xEEEEEEEE; | |
272 | ||
273 | L0 = L2; | |
274 | L1 = L3; | |
275 | L2 = L0; | |
276 | L3 = L1; | |
277 | B0 = B2; | |
278 | B1 = B3; | |
279 | B2 = B0; | |
280 | B3 = B1; | |
281 | ||
282 | R0 = L0; | |
283 | R1 = L1; | |
284 | R2 = L2; | |
285 | R3 = L3; | |
286 | R4 = B0; | |
287 | R5 = B1; | |
288 | R6 = B2; | |
289 | R7 = B3; | |
290 | ||
291 | CHECKREG r0, 0xCCCCCCCC; | |
292 | CHECKREG r1, 0xAAAAAAAA; | |
293 | CHECKREG r2, 0xCCCCCCCC; | |
294 | CHECKREG r3, 0xAAAAAAAA; | |
295 | CHECKREG r4, 0x12345667; | |
296 | CHECKREG r5, 0xEEEEEEEE; | |
297 | CHECKREG r6, 0x12345667; | |
298 | CHECKREG r7, 0xEEEEEEEE; | |
299 | ||
300 | imm32 l0, 0x09499091; | |
301 | imm32 l1, 0x0A55A0A2; | |
302 | imm32 l2, 0x0B6BB0B3; | |
303 | imm32 l3, 0x0C7CC0C4; | |
304 | imm32 b0, 0x0D8DD0D5; | |
305 | imm32 b1, 0x0E9EE0E6; | |
306 | imm32 b2, 0x0F0FF0F7; | |
307 | imm32 b3, 0x12145068; | |
308 | ||
309 | L0 = L3; | |
310 | L1 = L0; | |
311 | L2 = L1; | |
312 | L3 = L2; | |
313 | B0 = B3; | |
314 | B1 = B0; | |
315 | B2 = B1; | |
316 | B3 = B2; | |
317 | ||
318 | R0 = L0; | |
319 | R1 = L1; | |
320 | R2 = L2; | |
321 | R3 = L3; | |
322 | R4 = B0; | |
323 | R5 = B1; | |
324 | R6 = B2; | |
325 | R7 = B3; | |
326 | ||
327 | CHECKREG r0, 0x0C7CC0C4; | |
328 | CHECKREG r1, 0x0C7CC0C4; | |
329 | CHECKREG r2, 0x0C7CC0C4; | |
330 | CHECKREG r3, 0x0C7CC0C4; | |
331 | CHECKREG r4, 0x12145068; | |
332 | CHECKREG r5, 0x12145068; | |
333 | CHECKREG r6, 0x12145068; | |
334 | CHECKREG r7, 0x12145068; | |
335 | ||
336 | // b to l & l to b | |
337 | L0 = B0; | |
338 | L1 = B1; | |
339 | L2 = B2; | |
340 | L3 = B3; | |
341 | B0 = L0; | |
342 | B1 = L1; | |
343 | B2 = L2; | |
344 | B3 = L3; | |
345 | ||
346 | R0 = I0; | |
347 | R1 = I1; | |
348 | R2 = I2; | |
349 | R3 = I3; | |
350 | R4 = M0; | |
351 | R5 = M1; | |
352 | R6 = M2; | |
353 | R7 = M3; | |
354 | ||
355 | CHECKREG r0, 0xF6666660; | |
356 | CHECKREG r1, 0x17777770; | |
357 | CHECKREG r2, 0x28888888; | |
358 | CHECKREG r3, 0xE5555550; | |
359 | CHECKREG r4, 0xE5555550; | |
360 | CHECKREG r5, 0xF6666660; | |
361 | CHECKREG r6, 0x17777770; | |
362 | CHECKREG r7, 0x28888888; | |
363 | ||
364 | imm32 l0, 0x01909910; | |
365 | imm32 l1, 0x12A11220; | |
366 | imm32 l2, 0x23B25530; | |
367 | imm32 l3, 0x34C36640; | |
368 | imm32 b0, 0x45D47750; | |
369 | imm32 b1, 0x56E58860; | |
370 | imm32 b2, 0x67F66676; | |
371 | imm32 b3, 0x78375680; | |
372 | ||
373 | L0 = B1; | |
374 | L1 = B2; | |
375 | L2 = B3; | |
376 | L3 = B0; | |
377 | B0 = L1; | |
378 | B1 = L2; | |
379 | B2 = L3; | |
380 | B3 = L0; | |
381 | ||
382 | R0 = L0; | |
383 | R1 = L1; | |
384 | R2 = L2; | |
385 | R3 = L3; | |
386 | R4 = B0; | |
387 | R5 = B1; | |
388 | R6 = B2; | |
389 | R7 = B3; | |
390 | ||
391 | CHECKREG r0, 0x56E58860; | |
392 | CHECKREG r1, 0x67F66676; | |
393 | CHECKREG r2, 0x78375680; | |
394 | CHECKREG r3, 0x45D47750; | |
395 | CHECKREG r4, 0x67F66676; | |
396 | CHECKREG r5, 0x78375680; | |
397 | CHECKREG r6, 0x45D47750; | |
398 | CHECKREG r7, 0x56E58860; | |
399 | ||
400 | imm32 l0, 0x09909990; | |
401 | imm32 l1, 0x1AA11230; | |
402 | imm32 l2, 0x2BB25550; | |
403 | imm32 l3, 0x3CC36660; | |
404 | imm32 b0, 0x4DD47770; | |
405 | imm32 b1, 0x5EE58880; | |
406 | imm32 b2, 0x6FF66666; | |
407 | imm32 b3, 0x72375660; | |
408 | ||
409 | L0 = B2; | |
410 | L1 = B3; | |
411 | L2 = B0; | |
412 | L3 = B1; | |
413 | B0 = L2; | |
414 | B1 = L3; | |
415 | B2 = L0; | |
416 | B3 = L1; | |
417 | ||
418 | R0 = L0; | |
419 | R1 = L1; | |
420 | R2 = L2; | |
421 | R3 = L3; | |
422 | R4 = B0; | |
423 | R5 = B1; | |
424 | R6 = B2; | |
425 | R7 = B3; | |
426 | ||
427 | CHECKREG r0, 0x6FF66666; | |
428 | CHECKREG r1, 0x72375660; | |
429 | CHECKREG r2, 0x4DD47770; | |
430 | CHECKREG r3, 0x5EE58880; | |
431 | CHECKREG r4, 0x4DD47770; | |
432 | CHECKREG r5, 0x5EE58880; | |
433 | CHECKREG r6, 0x6FF66666; | |
434 | CHECKREG r7, 0x72375660; | |
435 | ||
436 | L0 = B3; | |
437 | L1 = B0; | |
438 | L2 = B1; | |
439 | L3 = B2; | |
440 | B0 = L3; | |
441 | B1 = L0; | |
442 | B2 = L1; | |
443 | B3 = L2; | |
444 | ||
445 | R0 = L0; | |
446 | R1 = L1; | |
447 | R2 = L2; | |
448 | R3 = L3; | |
449 | R4 = B0; | |
450 | R5 = B1; | |
451 | R6 = B2; | |
452 | R7 = B3; | |
453 | ||
454 | CHECKREG r0, 0x72375660; | |
455 | CHECKREG r1, 0x4DD47770; | |
456 | CHECKREG r2, 0x5EE58880; | |
457 | CHECKREG r3, 0x6FF66666; | |
458 | CHECKREG r4, 0x6FF66666; | |
459 | CHECKREG r5, 0x72375660; | |
460 | CHECKREG r6, 0x4DD47770; | |
461 | CHECKREG r7, 0x5EE58880; | |
462 | ||
463 | imm32 l0, 0x09999990; | |
464 | imm32 l1, 0x1AAAAAA0; | |
465 | imm32 l2, 0x2BBBBBB0; | |
466 | imm32 l3, 0x3CCCCCC0; | |
467 | imm32 b0, 0x4DDDDDD0; | |
468 | imm32 b1, 0x5EEEEEE0; | |
469 | imm32 b2, 0x6FFFFFF0; | |
470 | imm32 b3, 0x72345660; | |
471 | ||
472 | //*******************l-i & l-m, b-i & b-m, i-l & i-b, m-l & m-b | |
473 | // l to i & l to m | |
474 | I0 = L0; | |
475 | I1 = L1; | |
476 | I2 = L2; | |
477 | I3 = L3; | |
478 | M0 = L0; | |
479 | M1 = L1; | |
480 | M2 = L2; | |
481 | M3 = L3; | |
482 | ||
483 | R0 = I0; | |
484 | R1 = I1; | |
485 | R2 = I2; | |
486 | R3 = I3; | |
487 | R4 = M0; | |
488 | R5 = M1; | |
489 | R6 = M2; | |
490 | R7 = M3; | |
491 | ||
492 | CHECKREG r0, 0x09999990; | |
493 | CHECKREG r1, 0x1AAAAAA0; | |
494 | CHECKREG r2, 0x2BBBBBB0; | |
495 | CHECKREG r3, 0x3CCCCCC0; | |
496 | CHECKREG r4, 0x09999990; | |
497 | CHECKREG r5, 0x1AAAAAA0; | |
498 | CHECKREG r6, 0x2BBBBBB0; | |
499 | CHECKREG r7, 0x3CCCCCC0; | |
500 | ||
501 | I0 = L1; | |
502 | I1 = L2; | |
503 | I2 = L3; | |
504 | I3 = L0; | |
505 | M0 = L1; | |
506 | M1 = L2; | |
507 | M2 = L3; | |
508 | M3 = L0; | |
509 | ||
510 | R0 = I0; | |
511 | R1 = I1; | |
512 | R2 = I2; | |
513 | R3 = I3; | |
514 | R4 = M0; | |
515 | R5 = M1; | |
516 | R6 = M2; | |
517 | R7 = M3; | |
518 | ||
519 | CHECKREG r0, 0x1AAAAAA0; | |
520 | CHECKREG r1, 0x2BBBBBB0; | |
521 | CHECKREG r2, 0x3CCCCCC0; | |
522 | CHECKREG r3, 0x09999990; | |
523 | CHECKREG r4, 0x1AAAAAA0; | |
524 | CHECKREG r5, 0x2BBBBBB0; | |
525 | CHECKREG r6, 0x3CCCCCC0; | |
526 | CHECKREG r7, 0x09999990; | |
527 | ||
528 | I0 = L2; | |
529 | I1 = L3; | |
530 | I2 = L0; | |
531 | I3 = L1; | |
532 | M0 = L2; | |
533 | M1 = L3; | |
534 | M2 = L0; | |
535 | M3 = L1; | |
536 | ||
537 | R4 = I0; | |
538 | R5 = I1; | |
539 | R6 = I2; | |
540 | R7 = I3; | |
541 | R4 = M0; | |
542 | R5 = M1; | |
543 | R6 = M2; | |
544 | R7 = M3; | |
545 | ||
546 | CHECKREG r0, 0x1AAAAAA0; | |
547 | CHECKREG r1, 0x2BBBBBB0; | |
548 | CHECKREG r2, 0x3CCCCCC0; | |
549 | CHECKREG r3, 0x09999990; | |
550 | CHECKREG r4, 0x2BBBBBB0; | |
551 | CHECKREG r5, 0x3CCCCCC0; | |
552 | CHECKREG r6, 0x09999990; | |
553 | CHECKREG r7, 0x1AAAAAA0; | |
554 | ||
555 | I0 = L3; | |
556 | I1 = L0; | |
557 | I2 = L1; | |
558 | I3 = L2; | |
559 | M0 = L3; | |
560 | M1 = L0; | |
561 | M2 = L1; | |
562 | M3 = L2; | |
563 | ||
564 | R0 = I0; | |
565 | R1 = I1; | |
566 | R2 = I2; | |
567 | R3 = I3; | |
568 | R4 = M0; | |
569 | R5 = M1; | |
570 | R6 = M2; | |
571 | R7 = M3; | |
572 | ||
573 | CHECKREG r0, 0x3CCCCCC0; | |
574 | CHECKREG r1, 0x09999990; | |
575 | CHECKREG r2, 0x1AAAAAA0; | |
576 | CHECKREG r3, 0x2BBBBBB0; | |
577 | CHECKREG r4, 0x3CCCCCC0; | |
578 | CHECKREG r5, 0x09999990; | |
579 | CHECKREG r6, 0x1AAAAAA0; | |
580 | CHECKREG r7, 0x2BBBBBB0; | |
581 | ||
582 | // b to i & b to m | |
583 | I0 = B0; | |
584 | I1 = B1; | |
585 | I2 = B2; | |
586 | I3 = B3; | |
587 | M0 = B0; | |
588 | M1 = B1; | |
589 | M2 = B2; | |
590 | M3 = B3; | |
591 | ||
592 | R0 = I0; | |
593 | R1 = I1; | |
594 | R2 = I2; | |
595 | R3 = I3; | |
596 | R4 = M0; | |
597 | R5 = M1; | |
598 | R6 = M2; | |
599 | R7 = M3; | |
600 | ||
601 | CHECKREG r0, 0x4DDDDDD0; | |
602 | CHECKREG r1, 0x5EEEEEE0; | |
603 | CHECKREG r2, 0x6FFFFFF0; | |
604 | CHECKREG r3, 0x72345660; | |
605 | CHECKREG r4, 0x4DDDDDD0; | |
606 | CHECKREG r5, 0x5EEEEEE0; | |
607 | CHECKREG r6, 0x6FFFFFF0; | |
608 | CHECKREG r7, 0x72345660; | |
609 | ||
610 | I0 = B1; | |
611 | I1 = B2; | |
612 | I2 = B3; | |
613 | I3 = B0; | |
614 | M0 = B1; | |
615 | M1 = B2; | |
616 | M2 = B3; | |
617 | M3 = B0; | |
618 | ||
619 | R0 = I0; | |
620 | R1 = I1; | |
621 | R2 = I2; | |
622 | R3 = I3; | |
623 | R4 = M0; | |
624 | R5 = M1; | |
625 | R6 = M2; | |
626 | R7 = M3; | |
627 | ||
628 | CHECKREG r0, 0x5EEEEEE0; | |
629 | CHECKREG r1, 0x6FFFFFF0; | |
630 | CHECKREG r2, 0x72345660; | |
631 | CHECKREG r3, 0x4DDDDDD0; | |
632 | CHECKREG r4, 0x5EEEEEE0; | |
633 | CHECKREG r5, 0x6FFFFFF0; | |
634 | CHECKREG r6, 0x72345660; | |
635 | CHECKREG r7, 0x4DDDDDD0; | |
636 | ||
637 | I0 = B2; | |
638 | I1 = B3; | |
639 | I2 = B0; | |
640 | I3 = B1; | |
641 | M0 = B2; | |
642 | M1 = B3; | |
643 | M2 = B0; | |
644 | M3 = B1; | |
645 | ||
646 | R0 = I0; | |
647 | R1 = I1; | |
648 | R2 = I2; | |
649 | R3 = I3; | |
650 | R4 = M0; | |
651 | R5 = M1; | |
652 | R6 = M2; | |
653 | R7 = M3; | |
654 | ||
655 | CHECKREG r0, 0x6FFFFFF0; | |
656 | CHECKREG r1, 0x72345660; | |
657 | CHECKREG r2, 0x4DDDDDD0; | |
658 | CHECKREG r3, 0x5EEEEEE0; | |
659 | CHECKREG r4, 0x6FFFFFF0; | |
660 | CHECKREG r5, 0x72345660; | |
661 | CHECKREG r6, 0x4DDDDDD0; | |
662 | CHECKREG r7, 0x5EEEEEE0; | |
663 | ||
664 | I0 = B3; | |
665 | I1 = B0; | |
666 | I2 = B1; | |
667 | I3 = B2; | |
668 | M0 = B3; | |
669 | M1 = B0; | |
670 | M2 = B1; | |
671 | M3 = B2; | |
672 | ||
673 | P1 = I1; | |
674 | P2 = I2; | |
675 | P3 = I3; | |
676 | P4 = M0; | |
677 | P5 = M1; | |
678 | FP = M2; | |
679 | SP = M3; | |
680 | ||
681 | CHECKREG p1, 0x4DDDDDD0; | |
682 | CHECKREG p2, 0x5EEEEEE0; | |
683 | CHECKREG p3, 0x6FFFFFF0; | |
684 | CHECKREG p4, 0x72345660; | |
685 | CHECKREG p5, 0x4DDDDDD0; | |
686 | CHECKREG fp, 0x5EEEEEE0; | |
687 | CHECKREG sp, 0x6FFFFFF0; | |
688 | ||
689 | // i to l & i to b | |
690 | imm32 i0, 0x09999990; | |
691 | imm32 i1, 0x1AAAAAA0; | |
692 | imm32 i2, 0x2BBBBBB0; | |
693 | imm32 i3, 0x3CCCCCC0; | |
694 | ||
695 | L0 = I0; | |
696 | L1 = I1; | |
697 | L2 = I2; | |
698 | L3 = I3; | |
699 | B0 = I0; | |
700 | B1 = I1; | |
701 | B2 = I2; | |
702 | B3 = I3; | |
703 | ||
704 | L0 = I1; | |
705 | L1 = I2; | |
706 | L2 = I3; | |
707 | L3 = I0; | |
708 | B0 = I1; | |
709 | B1 = I2; | |
710 | B2 = I3; | |
711 | B3 = I0; | |
712 | ||
713 | R0 = L0; | |
714 | R1 = L1; | |
715 | R2 = L2; | |
716 | R3 = L3; | |
717 | R4 = B0; | |
718 | R5 = B1; | |
719 | R6 = B2; | |
720 | R7 = B3; | |
721 | ||
722 | CHECKREG r0, 0x1AAAAAA0; | |
723 | CHECKREG r1, 0x2BBBBBB0; | |
724 | CHECKREG r2, 0x3CCCCCC0; | |
725 | CHECKREG r3, 0x09999990; | |
726 | CHECKREG r4, 0x1AAAAAA0; | |
727 | CHECKREG r5, 0x2BBBBBB0; | |
728 | CHECKREG r6, 0x3CCCCCC0; | |
729 | CHECKREG r7, 0x09999990; | |
730 | ||
731 | L0 = I2; | |
732 | L1 = I3; | |
733 | L2 = I0; | |
734 | L3 = I1; | |
735 | B0 = I2; | |
736 | B1 = I3; | |
737 | B2 = I0; | |
738 | B3 = I1; | |
739 | ||
740 | R0 = L0; | |
741 | R1 = L1; | |
742 | R2 = L2; | |
743 | R3 = L3; | |
744 | R4 = B0; | |
745 | R5 = B1; | |
746 | R6 = B2; | |
747 | R7 = B3; | |
748 | ||
749 | CHECKREG r0, 0x2BBBBBB0; | |
750 | CHECKREG r1, 0x3CCCCCC0; | |
751 | CHECKREG r2, 0x09999990; | |
752 | CHECKREG r3, 0x1AAAAAA0; | |
753 | CHECKREG r4, 0x2BBBBBB0; | |
754 | CHECKREG r5, 0x3CCCCCC0; | |
755 | CHECKREG r6, 0x09999990; | |
756 | CHECKREG r7, 0x1AAAAAA0; | |
757 | ||
758 | imm32 l0, 0x09499091; | |
759 | imm32 l1, 0x0A55A0A2; | |
760 | imm32 l2, 0x0B6BB0B3; | |
761 | imm32 l3, 0x0C7CC0C4; | |
762 | imm32 b0, 0x0D8DD0D5; | |
763 | imm32 b1, 0x0E9EE0E6; | |
764 | imm32 b2, 0x0F0FF0F7; | |
765 | imm32 b3, 0x12145068; | |
766 | ||
767 | L0 = I3; | |
768 | L1 = I0; | |
769 | L2 = I1; | |
770 | L3 = I2; | |
771 | B0 = I3; | |
772 | B1 = I0; | |
773 | B2 = I1; | |
774 | B3 = I2; | |
775 | ||
776 | R0 = L0; | |
777 | R1 = L1; | |
778 | R2 = L2; | |
779 | R3 = L3; | |
780 | R4 = B0; | |
781 | R5 = B1; | |
782 | R6 = B2; | |
783 | R7 = B3; | |
784 | ||
785 | CHECKREG r0, 0x3CCCCCC0; | |
786 | CHECKREG r1, 0x09999990; | |
787 | CHECKREG r2, 0x1AAAAAA0; | |
788 | CHECKREG r3, 0x2BBBBBB0; | |
789 | CHECKREG r4, 0x3CCCCCC0; | |
790 | CHECKREG r5, 0x09999990; | |
791 | CHECKREG r6, 0x1AAAAAA0; | |
792 | CHECKREG r7, 0x2BBBBBB0; | |
793 | ||
794 | // m to l & m to b | |
795 | imm32 m0, 0x4DDDDDD0; | |
796 | imm32 m1, 0x5EEEEEE0; | |
797 | imm32 m2, 0x6FFFFFF0; | |
798 | imm32 m3, 0x72345660; | |
799 | L0 = M0; | |
800 | L1 = M1; | |
801 | L2 = M2; | |
802 | L3 = M3; | |
803 | B0 = M0; | |
804 | B1 = M1; | |
805 | B2 = M2; | |
806 | B3 = M3; | |
807 | ||
808 | R0 = I0; | |
809 | R1 = I1; | |
810 | R2 = I2; | |
811 | R3 = I3; | |
812 | R4 = M0; | |
813 | R5 = M1; | |
814 | R6 = M2; | |
815 | R7 = M3; | |
816 | ||
817 | CHECKREG r0, 0x09999990; | |
818 | CHECKREG r1, 0x1AAAAAA0; | |
819 | CHECKREG r2, 0x2BBBBBB0; | |
820 | CHECKREG r3, 0x3CCCCCC0; | |
821 | CHECKREG r4, 0x4DDDDDD0; | |
822 | CHECKREG r5, 0x5EEEEEE0; | |
823 | CHECKREG r6, 0x6FFFFFF0; | |
824 | CHECKREG r7, 0x72345660; | |
825 | ||
826 | imm32 l0, 0x01909910; | |
827 | imm32 l1, 0x12A11220; | |
828 | imm32 l2, 0x23B25530; | |
829 | imm32 l3, 0x34C36640; | |
830 | imm32 b0, 0x45D47750; | |
831 | imm32 b1, 0x56E58860; | |
832 | imm32 b2, 0x67F66676; | |
833 | imm32 b3, 0x78375680; | |
834 | ||
835 | L0 = M1; | |
836 | L1 = M2; | |
837 | L2 = M3; | |
838 | L3 = M0; | |
839 | B0 = M1; | |
840 | B1 = M2; | |
841 | B2 = M3; | |
842 | B3 = M0; | |
843 | ||
844 | R0 = L0; | |
845 | R1 = L1; | |
846 | R2 = L2; | |
847 | R3 = L3; | |
848 | R4 = B0; | |
849 | R5 = B1; | |
850 | R6 = B2; | |
851 | R7 = B3; | |
852 | ||
853 | CHECKREG r0, 0x5EEEEEE0; | |
854 | CHECKREG r1, 0x6FFFFFF0; | |
855 | CHECKREG r2, 0x72345660; | |
856 | CHECKREG r3, 0x4DDDDDD0; | |
857 | CHECKREG r4, 0x5EEEEEE0; | |
858 | CHECKREG r5, 0x6FFFFFF0; | |
859 | CHECKREG r6, 0x72345660; | |
860 | CHECKREG r7, 0x4DDDDDD0; | |
861 | ||
862 | imm32 l0, 0x09909990; | |
863 | imm32 l1, 0x1AA11230; | |
864 | imm32 l2, 0x2BB25550; | |
865 | imm32 l3, 0x3CC36660; | |
866 | imm32 b0, 0x4DD47770; | |
867 | imm32 b1, 0x5EE58880; | |
868 | imm32 b2, 0x6FF66666; | |
869 | imm32 b3, 0x72375660; | |
870 | ||
871 | L0 = M2; | |
872 | L1 = M3; | |
873 | L2 = M0; | |
874 | L3 = M1; | |
875 | B0 = M2; | |
876 | B1 = M3; | |
877 | B2 = M0; | |
878 | B3 = M1; | |
879 | ||
880 | R0 = L0; | |
881 | R1 = L1; | |
882 | R2 = L2; | |
883 | R3 = L3; | |
884 | R4 = B0; | |
885 | R5 = B1; | |
886 | R6 = B2; | |
887 | R7 = B3; | |
888 | ||
889 | CHECKREG r0, 0x6FFFFFF0; | |
890 | CHECKREG r1, 0x72345660; | |
891 | CHECKREG r2, 0x4DDDDDD0; | |
892 | CHECKREG r3, 0x5EEEEEE0; | |
893 | CHECKREG r4, 0x6FFFFFF0; | |
894 | CHECKREG r5, 0x72345660; | |
895 | CHECKREG r6, 0x4DDDDDD0; | |
896 | CHECKREG r7, 0x5EEEEEE0; | |
897 | ||
898 | L0 = M3; | |
899 | L1 = M0; | |
900 | L2 = M1; | |
901 | L3 = M2; | |
902 | B0 = M3; | |
903 | B1 = M0; | |
904 | B2 = M1; | |
905 | B3 = M2; | |
906 | ||
907 | R0 = L0; | |
908 | R1 = L1; | |
909 | R2 = L2; | |
910 | R3 = L3; | |
911 | R4 = B0; | |
912 | R5 = B1; | |
913 | R6 = B2; | |
914 | R7 = B3; | |
915 | ||
916 | CHECKREG r0, 0x72345660; | |
917 | CHECKREG r1, 0x4DDDDDD0; | |
918 | CHECKREG r2, 0x5EEEEEE0; | |
919 | CHECKREG r3, 0x6FFFFFF0; | |
920 | CHECKREG r4, 0x72345660; | |
921 | CHECKREG r5, 0x4DDDDDD0; | |
922 | CHECKREG r6, 0x5EEEEEE0; | |
923 | CHECKREG r7, 0x6FFFFFF0; | |
924 | ||
925 | pass |