Commit | Line | Data |
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4a306116 DB |
1 | # frv testcase to generate fp_exception |
2 | # mach: fr500 | |
3 | .include "testutils.inc" | |
4 | ||
5 | float_constants | |
6 | start | |
7 | load_float_constants | |
8 | ||
9 | .global align | |
10 | align: | |
11 | ; clear the packing bit if the insn at 'pack:'. We can't simply use | |
12 | ; '.p' because the assembler will catch the error. | |
13 | set_gr_mem pack,gr10 | |
14 | and_gr_immed 0x7fffffff,gr10 | |
15 | set_mem_gr gr10,pack | |
16 | set_gr_addr pack,gr10 | |
17 | flush_data_cache gr10 | |
18 | ||
5ca353c3 DB |
19 | ; Make the the source register number odd at badst. We can't simply |
20 | ; code an odd register number because the assembler will catch the | |
21 | ; error. | |
22 | set_gr_mem badst,gr10 | |
23 | or_gr_immed 0x02000000,gr10 | |
24 | set_mem_gr gr10,badst | |
25 | set_gr_addr badst,gr10 | |
26 | flush_data_cache gr10 | |
27 | ||
28 | ; Make the the dest register number odd at ld. We can't simply | |
29 | ; code an odd register number because the assembler will catch the | |
30 | ; error. | |
31 | set_gr_mem badld,gr10 | |
32 | or_gr_immed 0x02000000,gr10 | |
33 | set_mem_gr gr10,badld | |
34 | set_gr_addr badld,gr10 | |
35 | flush_data_cache gr10 | |
36 | ||
4a306116 DB |
37 | and_spr_immed -4081,tbr ; clear tbr.tt |
38 | set_gr_spr tbr,gr17 | |
39 | inc_gr_immed 0x070,gr17 ; address of exception handler | |
40 | set_bctrlr_0_0 gr17 | |
41 | inc_gr_immed 0x060,gr17 ; address of exception handler | |
42 | set_bctrlr_0_0 gr17 | |
43 | set_spr_immed 128,lcr | |
44 | set_spr_addr ok1,lr | |
45 | set_psr_et 1 | |
46 | inc_gr_immed -4,sp ; for alignment | |
47 | ||
48 | set_gr_immed 0,gr20 ; PC increment | |
49 | set_gr_immed 0,gr15 | |
50 | ||
51 | set_spr_addr ok3,lr | |
5ca353c3 | 52 | badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0 |
4a306116 DB |
53 | test_gr_immed 1,gr15 |
54 | ||
55 | set_spr_addr ok4,lr | |
56 | nop.p | |
5ca353c3 | 57 | badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1 |
4a306116 DB |
58 | test_gr_immed 2,gr15 |
59 | ||
60 | set_spr_addr ok5,lr | |
61 | fnegs.p fr9,fr9 | |
62 | pack: fnegs fr10,fr10 | |
63 | fnegs fr10,fr11 ; packing violation | |
64 | test_gr_immed 3,gr15 | |
65 | ||
66 | set_spr_addr ok1,lr | |
67 | set_gr_immed 4,gr20 ; PC increment | |
676a64f4 | 68 | bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented) |
4a306116 DB |
69 | test_gr_immed 4,gr15 |
70 | ||
71 | and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception | |
72 | set_fr_iimmed 0x7f7f,0xffff,fr0 | |
73 | set_fr_iimmed 0x0000,0x0000,fr1 | |
74 | fdivs fr0,fr1,fr2 ; div/0 -- no exception | |
75 | test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set | |
76 | test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set | |
77 | test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear | |
78 | and_spr_immed 0xffefffff,fsr0 ; Clear fsr0.qne | |
79 | ||
80 | set_spr_addr ok2,lr | |
81 | set_gr_immed 0,gr20 ; PC increment | |
82 | or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception | |
83 | set_fr_iimmed 0xdead,0xbeef,fr2 | |
84 | fdivs fr0,fr1,fr2 ; fp_exception - div/0 | |
85 | test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated | |
86 | test_gr_immed 5,gr15 | |
87 | ||
88 | and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception | |
89 | fsqrts fr32,fr2 ; inexact -- no exception | |
90 | test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set | |
91 | test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set | |
92 | test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear | |
93 | ||
94 | set_fr_fr fr2,fr3 ; sqrt 2 | |
95 | set_fr_iimmed 0xdead,0xbeef,fr2 | |
96 | set_spr_addr ok6,lr | |
97 | or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception | |
98 | fsqrts fr32,fr2 ; fp_exception - inexact | |
99 | test_gr_immed 6,gr15 ; handler called | |
100 | test_fr_fr fr2,fr3 ; fr2 updated | |
101 | ||
102 | set_fr_iimmed 0xdead,0xbeef,fr2 | |
103 | set_spr_addr ok7,lr | |
104 | fsqrts fr32,fr2 ; fp_exception - inexact again | |
105 | test_gr_immed 7,gr15 ; handler called | |
106 | test_fr_fr fr2,fr3 ; fr2 updated | |
107 | ||
108 | pass | |
109 | ||
110 | ; exception handler 1 -- bad insn | |
111 | ok1: | |
112 | test_spr_immed 1,esfr1 ; esr0 active | |
113 | test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set | |
114 | test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set | |
115 | test_spr_addr bad,epcr0 | |
116 | bra ret | |
117 | ||
118 | ; exception handler 2 - fp_exception: divide by 0 | |
119 | ok2: | |
120 | test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set | |
121 | test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set | |
122 | test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set | |
123 | ||
124 | test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set | |
125 | test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set | |
126 | test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set | |
127 | test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set | |
128 | test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set | |
129 | test_spr_immed 0x85e40241,fqop2 ; fq2.opc | |
130 | bra ret | |
131 | ||
132 | ; exception handler 3 - fp_exception: register exception | |
133 | ok3: | |
134 | test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set | |
135 | test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set | |
136 | test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear | |
137 | ||
138 | test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set | |
139 | test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set | |
140 | test_spr_bits 0x380,7,0x6,fqst2 ; fq2.ftt is set | |
141 | test_spr_bits 0x7e,1,0x0,fqst2 ; fq2.cexc is set | |
142 | test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set | |
143 | test_spr_immed 0x83581000,fqop2 ; fq2.opc | |
144 | bra ret | |
145 | ||
146 | ; exception handler 4 - fp_exception: another register exception | |
147 | ok4: | |
148 | test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set | |
149 | test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set | |
150 | test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear | |
151 | ||
152 | test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set | |
153 | test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set | |
154 | test_spr_bits 0x380,7,0x6,fqst3 ; fq3.ftt is set | |
155 | test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set | |
156 | test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set | |
157 | test_spr_immed 0x92ec1000,fqop3 ; fq3.opc | |
158 | bra ret | |
159 | ||
160 | ; exception handler 5 - fp_exception: sequence violation | |
161 | ok5: | |
162 | test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set | |
163 | test_spr_bits 0xe0000,17,0x4,fsr0 ; fsr0.ftt is set | |
164 | test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear | |
165 | ||
166 | test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set | |
167 | test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set | |
168 | test_spr_bits 0x380,7,0x4,fqst3 ; fq3.ftt is set | |
169 | test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set | |
170 | test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set | |
171 | test_spr_immed 0x97e400ca,fqop3 ; fq3.opc | |
172 | bra ret | |
173 | ||
174 | ; exception handler 6 - fp_exception: inexact | |
175 | ok6: | |
176 | test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set | |
177 | test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set | |
178 | test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set | |
179 | ||
180 | test_spr_bits 0x80000000,31,0x0,fqst0 ; fq0.miv is set | |
181 | test_spr_bits 0x18000,15,0x0,fqst0 ; fq0.sie is set | |
182 | test_spr_bits 0x380,7,0x1,fqst0 ; fq0.ftt is set | |
183 | test_spr_bits 0x7e,1,0x2,fqst0 ; fq0.cexc is set | |
184 | test_spr_bits 0x1,0,0x1,fqst0 ; fq0.valid is set | |
185 | test_spr_immed 0x85e40160,fqop0 ; fq0.opc | |
186 | bra ret | |
187 | ||
188 | ; exception handler 7 - fp_exception: inexact again | |
189 | ok7: | |
190 | test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set | |
191 | test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set | |
192 | test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set | |
193 | ||
194 | test_spr_bits 0x80000000,31,0x0,fqst1 ; fq1.miv is set | |
195 | test_spr_bits 0x18000,15,0x0,fqst1 ; fq1.sie is set | |
196 | test_spr_bits 0x380,7,0x1,fqst1 ; fq1.ftt is set | |
197 | test_spr_bits 0x7e,1,0x2,fqst1 ; fq1.cexc is set | |
198 | test_spr_bits 0x1,0,0x1,fqst1 ; fq1.valid is set | |
199 | test_spr_immed 0x85e40160,fqop1 ; fq1.opc | |
200 | bra ret | |
201 | ||
202 | ret: | |
203 | inc_gr_immed 1,gr15 | |
204 | movsg pcsr,gr60 | |
205 | add gr60,gr20,gr60 | |
206 | movgs gr60,pcsr | |
207 | rett 0 | |
208 | fail | |
209 |