projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 4a306116 | 1 | # frv testcase for mqmachu $GRi,$GRj,$GRk |
| 086419a8 | 2 | # mach: frv fr500 fr400 |
| 4a306116 DB |
3 | |
| 4 | .include "testutils.inc" | |
| 5 | ||
| 6 | start | |
| 7 | ||
| 8 | .global mqmachu | |
| 9 | mqmachu: | |
| 10 | set_fr_iimmed 3,2,fr8 ; multiply small numbers | |
| 11 | set_fr_iimmed 2,3,fr10 | |
| 12 | set_fr_iimmed 1,2,fr9 ; multiply by 1 | |
| 13 | set_fr_iimmed 2,1,fr11 | |
| 14 | mqmachu fr8,fr10,acc0 | |
| 15 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
| 16 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
| 17 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
| 18 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
| 19 | test_accg_immed 0,accg0 | |
| 20 | test_acc_immed 6,acc0 | |
| 21 | test_accg_immed 0,accg1 | |
| 22 | test_acc_immed 6,acc1 | |
| 23 | test_accg_immed 0,accg2 | |
| 24 | test_acc_immed 2,acc2 | |
| 25 | test_accg_immed 0,accg3 | |
| 26 | test_acc_immed 2,acc3 | |
| 27 | ||
| 28 | set_fr_iimmed 0,2,fr8 ; multiply by 0 | |
| 29 | set_fr_iimmed 2,0,fr10 | |
| 30 | set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result | |
| 31 | set_fr_iimmed 2,0x3fff,fr11 | |
| 32 | mqmachu fr8,fr10,acc0 | |
| 33 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
| 34 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
| 35 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
| 36 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
| 37 | test_accg_immed 0,accg0 | |
| 38 | test_acc_immed 6,acc0 | |
| 39 | test_accg_immed 0,accg1 | |
| 40 | test_acc_immed 6,acc1 | |
| 41 | test_accg_immed 0,accg2 | |
| 42 | test_acc_limmed 0x0000,0x8000,acc2 | |
| 43 | test_accg_immed 0,accg3 | |
| 44 | test_acc_limmed 0x0000,0x8000,acc3 | |
| 45 | ||
| 46 | set_fr_iimmed 0x4000,2,fr8 ; 16 bit result | |
| 47 | set_fr_iimmed 2,0x4000,fr10 | |
| 48 | set_fr_iimmed 0x8000,2,fr9 ; 17 bit result | |
| 49 | set_fr_iimmed 2,0x8000,fr11 | |
| 50 | mqmachu fr8,fr10,acc0 | |
| 51 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
| 52 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
| 53 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
| 54 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
| 55 | test_accg_immed 0,accg0 | |
| 56 | test_acc_limmed 0x0000,0x8006,acc0 | |
| 57 | test_accg_immed 0,accg1 | |
| 58 | test_acc_limmed 0x0000,0x8006,acc1 | |
| 59 | test_accg_immed 0,accg2 | |
| 60 | test_acc_immed 0x00018000,acc2 | |
| 61 | test_accg_immed 0,accg3 | |
| 62 | test_acc_immed 0x00018000,acc3 | |
| 63 | ||
| 64 | set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result | |
| 65 | set_fr_iimmed 0x7fff,0x7fff,fr10 | |
| 66 | set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result | |
| 67 | set_fr_iimmed 0x8000,0x8000,fr11 | |
| 68 | mqmachu fr8,fr10,acc0 | |
| 69 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
| 70 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
| 71 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
| 72 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
| 73 | test_accg_immed 0,accg0 | |
| 74 | test_acc_immed 0x3fff8007,acc0 | |
| 75 | test_accg_immed 0,accg1 | |
| 76 | test_acc_immed 0x3fff8007,acc1 | |
| 77 | test_accg_immed 0,accg2 | |
| 78 | test_acc_limmed 0x4001,0x8000,acc2 | |
| 79 | test_accg_immed 0,accg3 | |
| 80 | test_acc_limmed 0x4001,0x8000,acc3 | |
| 81 | ||
| 82 | set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result | |
| 83 | set_fr_iimmed 0xffff,0xffff,fr10 | |
| 84 | set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result | |
| 85 | set_fr_iimmed 0xffff,0xffff,fr11 | |
| 86 | mqmachu fr8,fr10,acc0 | |
| 87 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
| 88 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
| 89 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
| 90 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
| 91 | test_accg_immed 1,accg0 | |
| 92 | test_acc_limmed 0x3ffd,0x8008,acc0 | |
| 93 | test_accg_immed 1,accg1 | |
| 94 | test_acc_limmed 0x3ffd,0x8008,acc1 | |
| 95 | test_accg_immed 1,accg2 | |
| 96 | test_acc_limmed 0x3fff,0x8001,acc2 | |
| 97 | test_accg_immed 1,accg3 | |
| 98 | test_acc_limmed 0x3fff,0x8001,acc3 | |
| 99 | ||
| 100 | set_accg_immed 0xff,accg0 ; saturation | |
| 101 | set_acc_immed 0xffffffff,acc0 | |
| 102 | set_accg_immed 0xff,accg1 | |
| 103 | set_acc_immed 0xffffffff,acc1 | |
| 104 | set_accg_immed 0xff,accg2 ; saturation | |
| 105 | set_acc_immed 0xffffffff,acc2 | |
| 106 | set_accg_immed 0xff,accg3 | |
| 107 | set_acc_immed 0xffffffff,acc3 | |
| 108 | set_fr_iimmed 1,1,fr8 | |
| 109 | set_fr_iimmed 1,1,fr10 | |
| 110 | set_fr_iimmed 1,1,fr9 | |
| 111 | set_fr_iimmed 1,1,fr11 | |
| 112 | mqmachu fr8,fr10,acc0 | |
| 113 | test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set | |
| 114 | test_spr_bits 2,1,1,msr0 ; msr0.ovf is set | |
| 115 | test_spr_bits 1,0,1,msr0 ; msr0.aovf is set | |
| 116 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set | |
| 117 | test_accg_immed 0xff,accg0 | |
| 118 | test_acc_limmed 0xffff,0xffff,acc0 | |
| 119 | test_accg_immed 0xff,accg1 | |
| 120 | test_acc_limmed 0xffff,0xffff,acc1 | |
| 121 | test_accg_immed 0xff,accg2 | |
| 122 | test_acc_limmed 0xffff,0xffff,acc2 | |
| 123 | test_accg_immed 0xff,accg3 | |
| 124 | test_acc_limmed 0xffff,0xffff,acc3 | |
| 125 | ||
| 126 | set_fr_iimmed 0xffff,0x0000,fr8 | |
| 127 | set_fr_iimmed 0xffff,0xffff,fr10 | |
| 128 | set_fr_iimmed 0x0000,0xffff,fr9 | |
| 129 | set_fr_iimmed 0xffff,0xffff,fr11 | |
| 130 | mqmachu fr8,fr10,acc0 | |
| 131 | test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set | |
| 132 | test_spr_bits 2,1,1,msr0 ; msr0.ovf is set | |
| 133 | test_spr_bits 1,0,1,msr0 ; msr0.aovf is set | |
| 134 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set | |
| 135 | test_accg_immed 0xff,accg0 | |
| 136 | test_acc_limmed 0xffff,0xffff,acc0 | |
| 137 | test_accg_immed 0xff,accg1 | |
| 138 | test_acc_limmed 0xffff,0xffff,acc1 | |
| 139 | test_accg_immed 0xff,accg2 | |
| 140 | test_acc_limmed 0xffff,0xffff,acc2 | |
| 141 | test_accg_immed 0xff,accg3 | |
| 142 | test_acc_limmed 0xffff,0xffff,acc3 | |
| 143 | ||
| 144 | pass |