[deliverable/binutils-gdb.git] / sim / testsuite / sky / sce_main.c


/****************************************************/
/* This is a (Toronto created) wrapper program      */
/* to drive the sce_tests                           */
/*                                                  */
/* Copyright (C) 1998, Cygnus Solutions             */
/****************************************************/ 

extern int printf(const char *, ...);

extern char My_dma_start[];
extern char gpu_refresh;


/* ------------- VU defines --------------*/

#define VPU_STAT		(volatile int *)0x110073d0
#define VPU_STAT_VBS1_MASK	0x00000100

/* ----------end of VU defines -----------*/

                                
/* ------------- VIF defines -------------*/
#define VIF1_STAT		(volatile int *) 0x10003C00
#define VIF1_STAT_FQC_MASK 0x1F000000
#define VIF1_STAT_PPS_MASK 0x00000003
                                                 
/* ----------end of VIF defines -----------*/


/* -------------- DMA defines -------------*/
#define DMA_D0_CHCR	(volatile int*)0x10008000
#define DMA_D0_MADR	(volatile int*)0x10008010
#define DMA_D0_QWC	(volatile int*)0x10008020
#define DMA_D0_TADR	(volatile int*)0x10008030
#define DMA_D0_ASR0	(volatile int*)0x10008040
#define DMA_D0_ASR1	(volatile int*)0x10008050
#define DMA_D0_PKTFLAG	(volatile int*)0x10008060	/* virtual reg to indicate presence of tag in data */

#define DMA_D1_CHCR	(volatile int*)0x10009000
#define DMA_D1_MADR	(volatile int*)0x10009010
#define DMA_D1_QWC	(volatile int*)0x10009020
#define DMA_D1_TADR	(volatile int*)0x10009030
#define DMA_D1_ASR0	(volatile int*)0x10009040
#define DMA_D1_ASR1	(volatile int*)0x10009050
#define DMA_D1_PKTFLAG	(volatile int*)0x10009060	/* virtual reg to indicate presence of tag in data */ 

#define DMA_D2_CHCR	(volatile int*)0x1000a000
#define DMA_D2_MADR	(volatile int*)0x1000a010
#define DMA_D2_QWC	(volatile int*)0x1000a020
#define DMA_D2_TADR	(volatile int*)0x1000a030
#define DMA_D2_ASR0	(volatile int*)0x1000a040
#define DMA_D2_ASR1	(volatile int*)0x1000a050
#define DMA_D2_PKTFLAG	(volatile int*)0x1000a060	/* virtual reg to indicate presence of tag in data */ 

#define DMA_D_CTRL	(volatile int*)0x1000e000
#define DMA_D_CTRL__DMAE	0x00000001
#define DMA_D_STAT	(volatile int*)0x1000e010
#define DMA_D_STAT__TOGGLE	0x63ff0000
#define DMA_D_STAT__CLEAR	0x0000e3ff
#define DMA_D_PCR	(volatile int*)0x1000e020
#define DMA_D_PCR__PCE		0x80000000
#define DMA_D_PCR__CDE		0x03ff0000
#define DMA_D_SQWC	(volatile int*)0x1000e030
#define DMA_D_RBSR	(volatile int*)0x1000e040
#define DMA_D_RBOR	(volatile int*)0x1000e050
#define DMA_D_STADR	(volatile int*)0x1000e060

/* Defines for DMA tag fields. */    
#define DMA_TAG_ID	0x70000000
#define DMA_TAG_ID__REFE	0
#define DMA_TAG_ID__CNT		1
#define DMA_TAG_ID__NEXT	2
#define DMA_TAG_ID__REF		3
#define DMA_TAG_ID__REFS	4
#define DMA_TAG_ID__CALL	5
#define DMA_TAG_ID__RET		6
#define DMA_TAG_ID__END		7

/* Dn_CHCR definition values */
#define MODE_NORM       0
#define MODE_CHAIN      (1 << 2)
#define MODE_INTR       (2 << 2)
#define DMA_START       (1 << 8)
#define DMA_Dn_CHCR__TTE  0x00000040


/* ----------end of VIF defines -----------*/


void DMA_enable(void) {
    *DMA_D_CTRL = 0x01; /* DMA enable */
}

/* If DMA mode is source chain */ 
void start_DMA_ch1_source_chain(void* data) {
    *DMA_D_CTRL  = 0x01; /* DMA enable */
    *DMA_D1_QWC  = 0x00;
    *DMA_D1_TADR = (int)data; 
    *DMA_D1_CHCR = MODE_CHAIN | DMA_START | DMA_Dn_CHCR__TTE;

}

/* If DMA mode is normal */
void start_DMA_ch1_normal(void* data, int qwc) {
    *DMA_D_CTRL  = 0x01; /* DMA enable */
    *DMA_D1_QWC  = qwc; /* 8 is sample */
    *DMA_D1_MADR = (int)data; 
    *DMA_D1_CHCR = MODE_NORM | DMA_START | DMA_Dn_CHCR__TTE;

}

void wait_until_idle() {
    /* Hmmm... Not sure exactly what the right code is for this.  I'll look for
     * VIF_STAT.PPS = 0 && VIF_STAT.FQC == 0 && VPU_STAT.VBS1 == 0 */

    int vif1_stat, vpu_stat;
    do {
	vif1_stat = *VIF1_STAT;
	vpu_stat = *VPU_STAT;
    } while (!(   (vif1_stat & VIF1_STAT_PPS_MASK) == 0
	       && (vif1_stat & VIF1_STAT_FQC_MASK) == 0
	       && (vpu_stat  & VPU_STAT_VBS1_MASK) == 0));
}

void wait_a_while() {
    int i;
    for (i = 0; i<200000; i++) {}
}

int main() {
    start_DMA_ch1_source_chain(&My_dma_start);
    wait_until_idle();
    start_DMA_ch1_source_chain(&gpu_refresh);
    wait_a_while();

    return 0;
}
Commit	Line	Data
5087a605 JY	1
	2	/****************************************************/
	3	/* This is a (Toronto created) wrapper program */
	4	/* to drive the sce_tests */
	5	/* */
	6	/* Copyright (C) 1998, Cygnus Solutions */
	7	/****************************************************/
	8
	9	extern int printf(const char *, ...);
	10
	11	extern char My_dma_start[];
	12	extern char gpu_refresh;
	13
	14
	15	/* ------------- VU defines --------------*/
	16
	17	#define VPU_STAT (volatile int *)0x110073d0
	18	#define VPU_STAT_VBS1_MASK 0x00000100
	19
	20	/* ----------end of VU defines -----------*/
	21
	22
	23	/* ------------- VIF defines -------------*/
	24	#define VIF1_STAT (volatile int *) 0x10003C00
	25	#define VIF1_STAT_FQC_MASK 0x1F000000
	26	#define VIF1_STAT_PPS_MASK 0x00000003
	27
	28	/* ----------end of VIF defines -----------*/
	29
	30
	31	/* -------------- DMA defines -------------*/
	32	#define DMA_D0_CHCR (volatile int*)0x10008000
	33	#define DMA_D0_MADR (volatile int*)0x10008010
	34	#define DMA_D0_QWC (volatile int*)0x10008020
	35	#define DMA_D0_TADR (volatile int*)0x10008030
	36	#define DMA_D0_ASR0 (volatile int*)0x10008040
	37	#define DMA_D0_ASR1 (volatile int*)0x10008050
	38	#define DMA_D0_PKTFLAG (volatile int)0x10008060 / virtual reg to indicate presence of tag in data */
	39
	40	#define DMA_D1_CHCR (volatile int*)0x10009000
	41	#define DMA_D1_MADR (volatile int*)0x10009010
	42	#define DMA_D1_QWC (volatile int*)0x10009020
	43	#define DMA_D1_TADR (volatile int*)0x10009030
	44	#define DMA_D1_ASR0 (volatile int*)0x10009040
	45	#define DMA_D1_ASR1 (volatile int*)0x10009050
	46	#define DMA_D1_PKTFLAG (volatile int)0x10009060 / virtual reg to indicate presence of tag in data */
	47
	48	#define DMA_D2_CHCR (volatile int*)0x1000a000
	49	#define DMA_D2_MADR (volatile int*)0x1000a010
	50	#define DMA_D2_QWC (volatile int*)0x1000a020
	51	#define DMA_D2_TADR (volatile int*)0x1000a030
	52	#define DMA_D2_ASR0 (volatile int*)0x1000a040
	53	#define DMA_D2_ASR1 (volatile int*)0x1000a050
	54	#define DMA_D2_PKTFLAG (volatile int)0x1000a060 / virtual reg to indicate presence of tag in data */
	55
	56	#define DMA_D_CTRL (volatile int*)0x1000e000
	57	#define DMA_D_CTRL__DMAE 0x00000001
	58	#define DMA_D_STAT (volatile int*)0x1000e010
	59	#define DMA_D_STAT__TOGGLE 0x63ff0000
	60	#define DMA_D_STAT__CLEAR 0x0000e3ff
	61	#define DMA_D_PCR (volatile int*)0x1000e020
	62	#define DMA_D_PCR__PCE 0x80000000
	63	#define DMA_D_PCR__CDE 0x03ff0000
	64	#define DMA_D_SQWC (volatile int*)0x1000e030
65	#define DMA_D_RBSR (volatile int*)0x1000e040
66	#define DMA_D_RBOR (volatile int*)0x1000e050
67	#define DMA_D_STADR (volatile int*)0x1000e060
68
69	/* Defines for DMA tag fields. */
70	#define DMA_TAG_ID 0x70000000
71	#define DMA_TAG_ID__REFE 0
72	#define DMA_TAG_ID__CNT 1
73	#define DMA_TAG_ID__NEXT 2
74	#define DMA_TAG_ID__REF 3
75	#define DMA_TAG_ID__REFS 4
76	#define DMA_TAG_ID__CALL 5
77	#define DMA_TAG_ID__RET 6
78	#define DMA_TAG_ID__END 7
79
80	/* Dn_CHCR definition values */
81	#define MODE_NORM 0
82	#define MODE_CHAIN (1 << 2)
83	#define MODE_INTR (2 << 2)
84	#define DMA_START (1 << 8)
85	#define DMA_Dn_CHCR__TTE 0x00000040
86
87
88	/* ----------end of VIF defines -----------*/
89
90
91
92	void DMA_enable(void) {
93	DMA_D_CTRL = 0x01; / DMA enable */
94	}
95
96	/* If DMA mode is source chain */
97	void start_DMA_ch1_source_chain(void* data) {
98	DMA_D_CTRL = 0x01; / DMA enable */
99	*DMA_D1_QWC = 0x00;
1430343e	100	*DMA_D1_TADR = (int)data;
5087a605 JY	101	*DMA_D1_CHCR = MODE_CHAIN \| DMA_START \| DMA_Dn_CHCR__TTE;
	102
	103	}
	104
	105	/* If DMA mode is normal */
	106	void start_DMA_ch1_normal(void* data, int qwc) {
	107	DMA_D_CTRL = 0x01; / DMA enable */
	108	DMA_D1_QWC = qwc; / 8 is sample */
	109	*DMA_D1_MADR = (int)data;
	110	*DMA_D1_CHCR = MODE_NORM \| DMA_START \| DMA_Dn_CHCR__TTE;
	111
	112	}
	113
	114	void wait_until_idle() {
	115	/* Hmmm... Not sure exactly what the right code is for this. I'll look for
	116	* VIF_STAT.PPS = 0 && VIF_STAT.FQC == 0 && VPU_STAT.VBS1 == 0 */
	117
	118	int vif1_stat, vpu_stat;
	119	do {
	120	vif1_stat = *VIF1_STAT;
	121	vpu_stat = *VPU_STAT;
	122	} while (!( (vif1_stat & VIF1_STAT_PPS_MASK) == 0
	123	&& (vif1_stat & VIF1_STAT_FQC_MASK) == 0
	124	&& (vpu_stat & VPU_STAT_VBS1_MASK) == 0));
	125	}
	126
	127	void wait_a_while() {
	128	int i;
	129	for (i = 0; i<200000; i++) {}
	130	}
	131
	132	int main() {
	133	start_DMA_ch1_source_chain(&My_dma_start);
	134	wait_until_idle();
	135	start_DMA_ch1_source_chain(&gpu_refresh);
	136	wait_a_while();
f8c732a1 JY	137
f8c732a1 JY	138	return 0;
5087a605	139	}